Power device and method for manufacturing the same

Abstract

The present application discloses a power device and a preparation method thereof, wherein the power device comprises: a substrate, the substrate having a first surface; a first epitaxial layer arranged on the first surface, the first epitaxial layer comprising a plurality of epitaxial regions distributed along a first direction, each epitaxial region having a second surface away from the substrate, the second surfaces of the plurality of epitaxial regions having different distances from the first surface in the second direction, the first direction being parallel to the first surface, the second direction being perpendicular to the first surface, the first epitaxial layer having a first doping type; a plurality of injection regions, the injection regions being arranged in the epitaxial regions, and the surfaces of the injection regions away from the substrate being located in the second surface, at least one injection region being arranged in each epitaxial region; a second epitaxial layer, the second epitaxial layer being located on the side of the first epitaxial layer away from the substrate, the second epitaxial layer being in contact with the injection region, and the second epitaxial layer and the injection region having a second doping type. The invention solves the problem of low breakdown voltage of power devices with a field confinement ring structure in the related art.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power device and a method for preparing the same. Background Art

[0002] The most important performance of power devices is to block high voltage. The devices are designed to withstand high voltage on the depletion layer of the PN junction, metal-semiconductor contact, and MOS interface. As the applied voltage increases, the electric field strength of the depletion layer will also increase, and eventually exceed the material limit to cause avalanche breakdown. The increase in the curvature of the electric field in the depletion region at the edge of the device will cause the electric field strength to be greater than that inside the die. During the voltage increase process, the edge of the die will experience avalanche breakdown earlier than the inside of the die. In order to maximize the performance of the device, it is necessary to design a voltage divider structure at the edge of the device to reduce the curvature of the PN junction at the edge of the active area (cell area), extend the depletion layer laterally, enhance the horizontal withstand voltage, and cause the edge and inside of the device to break down simultaneously. The cutoff ring is distributed at the outermost edge of the chip between the voltage divider structure and the scribe groove area, and is indispensable for devices with high reliability requirements and module packaging.

[0003] Field limiting ring technology is one of the most commonly used voltage divider structures in power devices. Its process is very simple and can be formed by diffusion with the active area without adding process steps. The spacing between the main junction and the field limiting ring, the junction depth, the width of the ring and the number of rings will affect the size of the breakdown voltage. If the spacing is selected appropriately so that the electric field strength of the main junction and the ring junction reaches the critical breakdown field strength at the same time, the highest breakdown voltage can be obtained. In general, the breakdown voltage increases with the increase in the number of rings, but it does not increase linearly. The more rings there are, the larger the chip area occupied. The number of rings and the size of the breakdown voltage should be considered during design.

[0004] At present, in the prior art, the interface charge of the surface oxide layer in the field confinement ring structure will have a great influence on the surface potential of the device, affecting the voltage division effect and reducing the breakdown voltage. Summary of the invention

[0005] The present application provides a power device and a preparation method thereof, so as to solve the problem of low breakdown voltage of a power device with a field confinement ring structure in the related art.

[0006] According to one aspect of the present application, a power device is provided, comprising: a substrate, the substrate having a first surface; a first epitaxial layer, the first epitaxial layer is arranged on the first surface, and the first epitaxial layer includes a plurality of epitaxial regions distributed along a first direction, each of the epitaxial regions having a second surface away from the substrate, and the second surfaces of the plurality of epitaxial regions have different distances from the first surface in the second direction, the first direction is parallel to the first surface, the second direction is perpendicular to the first surface, and the first epitaxial layer has a first doping type; a plurality of injection regions, the injection regions are arranged in the epitaxial regions, and the surfaces of the injection regions away from the substrate are located in the second surface, and at least one injection region is arranged in each of the epitaxial regions; a second epitaxial layer, the second epitaxial layer is located on a side of the first epitaxial layer away from the substrate, the second epitaxial layer is in contact with the injection region, and the second epitaxial layer and the injection region have a second doping type.

[0007] Optionally, the distance between the second surface of the plurality of epitaxial regions and the first surface in the second direction increases gradually along the first direction.

[0008] Optionally, the depth of the implantation region in any one of the epitaxial regions decreases along the first direction.

[0009] Optionally, the doping concentration of the implanted region in any one of the epitaxial regions decreases along the first direction.

[0010] Optionally, the width of the epitaxial region decreases along the first direction.

[0011] Optionally, the power device further includes: an active region and a cut-off region, the active region and the cut-off region being located on different sides of the first epitaxial layer away from the substrate, wherein the first direction is the direction from the active region to the cut-off region, the cut-off region has the first doping type, and the active region has the second doping type.

[0012] Optionally, the doping concentration of the cut-off region is lower than the doping concentration of the second epitaxial layer, and the doping concentration of the active region is higher than the doping concentration of the second epitaxial layer.

[0013] According to one aspect of the present application, a method for preparing a power device is provided, which is used to prepare any one of the power devices described above, and the preparation method includes: providing a substrate, the substrate having a first surface; forming a first epitaxial layer on the first surface, the first epitaxial layer including a plurality of epitaxial regions distributed along a first direction, each of the epitaxial regions having a plurality of second surfaces facing away from the substrate, the second surfaces of the plurality of epitaxial regions having different distances from the first surface in the second direction, the first direction being parallel to the first surface, the second direction being perpendicular to the first surface, and the first epitaxial layer having a first doping type; forming a plurality of injection regions in the epitaxial regions, the surfaces of the injection regions facing away from the substrate being located in the second surface, and at least one injection region is provided in each of the epitaxial regions; forming a second epitaxial layer on a side of the first epitaxial layer facing away from the substrate, the second epitaxial layer and the injection regions having a second doping type.

[0014] Optionally, the step of forming the first epitaxial layer includes: forming a first epitaxial material layer on the substrate using an epitaxial growth process; etching the first epitaxial material layer multiple times to form a plurality of second surfaces on the side of the first epitaxial material layer facing away from the substrate, the plurality of second surfaces having different distances from the first surface in the second direction, and the remaining first epitaxial material layer constituting the first epitaxial layer.

[0015] Optionally, the step of forming the injection region includes: forming a mask layer on the first epitaxial layer by a deposition process; patterning the mask layer to form an injection region pattern, wherein the injection region pattern exposes the first epitaxial layer; forming the injection region in the exposed first epitaxial layer by an ion implantation process; and removing the remaining mask layer.

[0016] Through the technical solution of the present application, a power device is provided, wherein the device comprises a double-layer structure of a first epitaxial layer and a second epitaxial layer, and a plurality of epitaxial regions have different heights in the second direction, thereby improving the high-voltage resistance of the power device. At the same time, an injection region is provided in the first epitaxial layer and contacts the second epitaxial layer, so that on the basis of the terminal structure of the traditional power device, the second epitaxial layer and the injection region are combined, thereby greatly reducing the leakage current of the device and reducing the production cost of the device. In addition, after the high-low structure is formed on the surface of the first epitaxial layer, an injection region is formed on the surface of the first epitaxial layer, thereby simplifying the process and reducing the production cost. Therefore, the device improves the high-voltage resistance of the field limiting ring structure, improves the breakdown voltage of the power device, and reduces the production cost of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0018] Figure 1 A top view of a power device in the prior art is shown;

[0019] Figure 2 A schematic cross-sectional structure diagram of a power device in the prior art is shown;

[0020] Figure 3 A schematic diagram of the cross-sectional structure of a voltage divider structure and a cut-off ring of a power device in the prior art is shown;

[0021] Figure 4 is a schematic cross-sectional structure diagram of a power device according to an embodiment of the present application;

[0022] Figure 5 is a schematic diagram of a cross-sectional structure of a depletion region of a power device according to an embodiment of the present application;

[0023] Figure 6 is a schematic cross-sectional structure diagram of a depletion region of another power device according to an embodiment of the present application;

[0024] Figure 7 is a schematic cross-sectional structure diagram of another power device according to an embodiment of the present application;

[0025] Figure 8 is a schematic cross-sectional structure diagram of another power device according to an embodiment of the present application;

[0026] Fig. 9 A flow chart of a method for preparing a power device provided in accordance with an embodiment of the present application is shown;

[0027] Fig.10 A schematic diagram of the cross-sectional structure of a substrate obtained in each step in a method for preparing a power device provided in an embodiment of the present application is shown;

[0028] Fig.11 A schematic diagram of the cross-sectional structure of a substrate obtained in each step in another method for preparing a power device provided in an embodiment of the present application is shown.

[0029] The above drawings include the following reference numerals:

[0030] 1. Active area; 2. Voltage divider structure; 3. Cut-off ring; 4. Slice road; 5. Oxide layer; 10. Substrate; 101. First surface; 102. Epitaxial layer; 20. First epitaxial layer; 201. Second surface; 202. N-type epitaxial layer; 21. First epitaxial material layer; 30. P-type ring; 31. Injection region; 33. First groove; 34. Second groove; 40. Cut-off region; 50. Second epitaxial layer; 51. Second P-type doped region; 61. First P-type doped region; 62. First doped region; 63. Gate; 631. First trench; 64. Gate oxide layer; 65. Second doped region; 66. Third doped region; 70. Depletion region; 81. First conductive layer; 82. Second conductive layer. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] As described in the background art, a power device in the prior art, Figure 1 is a schematic diagram of a cellular composite structure of a power device in the prior art, Figure 2 for Figure 1 The cross-sectional view along the X direction is shown in Figure 1 and Figure 2As shown, the power device in the prior art includes: an active area 1, a voltage divider structure 2, a cut-off ring 3 and a scribe line 4, wherein the voltage divider structure 2 is located outside the active area 1 to reduce the curvature effect of the PN junction at the edge of the active area and enhance the horizontal withstand voltage capability, the cut-off ring 3 is located outside the voltage divider structure 2 to improve the electric field distribution at the edge of the device, and the scribe line 4 is located outside the cut-off ring 3 to cut the device to separate the device. The structures of the voltage divider structure 2 and the cut-off ring 3 are as shown in FIG. Figure 3 As shown, the voltage-dividing structure 2 includes a substrate 10, an epitaxial layer 102 is provided on the substrate 10, and a plurality of P-type rings 30 are provided on the side of the epitaxial layer 102 facing away from the substrate 10, and the cut-off ring 3 includes a cut-off region 40, and the cut-off region 40 is located on the side facing away from the substrate 10 and in contact with the voltage-dividing structure 2, and the oxide layer 5 is located on the side of the epitaxial layer 102, the P-type ring 30 and the cut-off region 40 facing away from the bottom, that is, the oxide layer 5 is located on the surface of the power device and has the function of controlling the current. In this structure, the interface charge of the oxide layer 5 located on the surface of the device will have a great influence on the surface potential of the device, affecting the voltage-dividing effect and reducing the breakdown voltage. In order to solve the above problems, the present application provides a power device and a method for preparing the same.

[0035] According to one aspect of the present application, a power device is provided, such as Figure 4As shown, the device includes: a substrate 10, the substrate 10 has a first surface 101; a first epitaxial layer 20, the first epitaxial layer 20 is arranged on the first surface 101, and the first epitaxial layer 20 includes a plurality of epitaxial regions distributed along a first direction A, each epitaxial region has a second surface 201 away from the substrate, and in a second direction B, the second surfaces 201 of the plurality of epitaxial regions have different distances from the first surface 101, the first direction A is parallel to the first surface 101, the second direction B is perpendicular to the first surface 101, and the first epitaxial layer 20 has a first doping type; a plurality of injection regions 31, the injection regions 31 are arranged in the epitaxial regions, and the surface of the injection regions 31 away from the substrate 10 is located in the second surface 201, and at least one injection region 31 is arranged in each epitaxial region; a second epitaxial layer 50, the second epitaxial layer 50 is located on a side of the first epitaxial layer 20 away from the substrate 10, the second epitaxial layer 50 is in contact with the injection region 31, and the second epitaxial layer 50 and the injection region 31 have a second doping type. The device includes a double-layer structure of a first epitaxial layer 20 and a second epitaxial layer 50, and a plurality of epitaxial regions have different heights in the second direction B, which improves the high-voltage resistance of the power device. At the same time, the first epitaxial layer has an injection region and contacts the second epitaxial layer, so that on the basis of the terminal structure of the traditional power device, the second epitaxial layer and the injection region are combined, which greatly reduces the leakage current of the device and reduces the production cost of the device. In addition, after the high-low structure is formed on the surface of the first epitaxial layer, an injection region is formed on the surface of the first epitaxial layer, which simplifies the process and reduces the production cost. Therefore, the device improves the high-voltage resistance of the field limiting ring structure and the breakdown voltage of the power device while reducing the production cost of the device.

[0036] In some optional embodiments, the distance between the second surface and the first surface of the plurality of epitaxial regions in the second direction increases gradually along the first direction.

[0037] For example, Figure 5 As shown, in the semiconductor power device, the N-type epitaxial layer 202 is located on the N-type substrate 10, wherein the first P-type doped region 61 in the active region 1 and the N-type epitaxial layer 202 form a main PN junction structure with the N-type epitaxial layer 202 to enable the device to achieve unidirectional current conduction. When the device is in reverse bias, the main PN junction structure forms a depletion region 70 with a wider width, and the breakdown voltage at the corner of the first P-type doped region 61 is lower, causing the device to break down prematurely, wherein the first conductive layer 81 and the second conductive layer 82 are used to transmit current. Therefore, the active region 1 needs to alleviate the curvature effect of the depletion region of the main PN junction structure in the active region through the terminal voltage divider structure 2, reduce the electric field concentration at the corner, and increase the main PN junction breakdown voltage of the device, wherein the oxide layer 5 is used to control the direction of the current. As shown Figure 6As shown, in the semiconductor power device, the N-type epitaxial layer 202 is located on the N-type substrate 10, and a voltage-dividing structure 2 is provided on one side of the active area 1. The second P-type doping region 51 in the voltage-dividing structure 2 has different doping types from the N-type epitaxial layer 202, and a slowed depletion region 70 is formed at the junction of the second P-type doping region 51 and the N-type epitaxial layer 202, and the curvature effect of the depletion region 70 formed by the first P-type doping region 61 and the N-type epitaxial layer 202 in the device is changed, and the outer electric field of the PN junction is reduced, and the breakdown voltage is increased, thereby increasing the breakdown voltage of the device and enhancing the withstand voltage of the device. The height of the epitaxial region increases along the first direction A, the depth of the depletion region formed in the voltage-dividing structure decreases along the first direction A, and the width of the formed depletion layer gradually decreases along the first direction A, and the device is voltage-divided to prevent the device from being broken down, thereby improving the withstand voltage capability of the device.

[0038] In some optional implementations, the depth of the implantation region in any one epitaxial region decreases along the first direction.

[0039] Specifically, Figure 7 As shown, an injection region 31 is formed in the first epitaxial layer 20, and the doping concentration of the injection region 31 is different from the doping concentration of the first epitaxial layer 20, so a PN junction structure is formed, which further increases the depth of the depletion region in the voltage-dividing structure. The depth of the injection region 31 located in any epitaxial region decreases along the first direction A, and the width of the depletion region formed by the injection region 31 and the first epitaxial layer 20 gradually decreases along the first direction, further slowing down the curvature effect of the depletion region of the voltage-dividing structure, increasing the voltage-dividing capability of the voltage-dividing structure for the device, increasing the breakdown voltage of the device, and improving the high-voltage resistance of the device. Figure 7 The other structural positions shown in Figure 4 The structural position relationship is the same as in , and will not be repeated here.

[0040] In some optional implementations, the doping concentration of the implantation region in any one epitaxial region decreases along the first direction.

[0041] Specifically, in an epitaxial region, multiple implantation regions can share the electric field in the voltage-dividing structure to improve the reverse blocking capability of the device and improve the breakdown voltage of the device. The doping concentration of the implantation region located in an epitaxial region decreases along the first direction, which can effectively reduce the peak electric field formed by each implantation region and improve the blocking capability of the terminal.

[0042] In some optional embodiments, the width of the epitaxial region decreases along the first direction.

[0043] Specifically, the width of the epitaxial region decreases along the first direction, which reduces the curvature effect of the depletion region of the voltage divider structure and can reduce the size of the voltage divider structure, thereby increasing the cost of the product.

[0044] In some optional embodiments, such as Figure 4 , Figure 7 and Figure 8 As shown, the power device further includes: an active region 1 and a cut-off region 40, the active region 1 and the cut-off region 40 are located on different sides of the second epitaxial layer 50 away from the substrate 10, wherein the first direction A is the direction from the active region 1 to the cut-off region 40, the cut-off region 40 has a first doping type, and the active region 1 has a second doping type, Figure 7 and Figure 8 The other structural positions shown in Figure 4 The structural position relationship is the same as in , and will not be repeated here.

[0045] Specifically, the function of the cut-off region is to make the device enter the cut-off state under certain voltage or current conditions, block the current path, put the device in the cut-off state, and reduce the conduction capacity of the device. In this way, the switch control of the power device can be achieved, while protecting the device from hazards such as overload and short circuit. The cut-off ring can also play the role of current limiting and overheating protection. In addition, the cut-off region is between the voltage-dividing area and the dicing road and the voltage-dividing structure to achieve grounding of the device, prevent charge accumulation from damaging the device, and then protect the device. Specifically, the cut-off region is a doping region, and the cut-off region and the second epitaxial layer have different doping concentrations.

[0046] Among them, the cut-off region is a doped region of the first type formed on the side of the voltage-dividing structure away from the active region. When the device is reverse biased, since the cut-off region and the voltage-dividing structure have the same doping type, the flow of breakdown electrons can be limited to protect the device from damage.

[0047] In an optional embodiment, the above variable voltage dividing structure is applied to a diode device, such as Figure 4 As shown, the diode device includes: a first doped region 62, the first doped region 62 is located on the side of the first epitaxial layer 20 away from the substrate 10 and in contact with the second epitaxial layer 50, the first doped region 62 has the same doping type as the second epitaxial layer 50 and a different doping type from the first epitaxial layer 20, then a PN junction is formed between the first doped region 62 and the first epitaxial layer 20 located below the first doped region 62, thereby forming a diode device.

[0048] In another specific embodiment, the voltage dividing structure is applied to a trench gate MOSFET device, such as Figure 8As shown, the active region 1 of the device includes a source region and a gate trench structure, the gate trench structure includes a gate 63 and a gate oxide layer 64, the gate 63 penetrates the first epitaxial layer 20 and is located on one side of the second epitaxial layer 50, the gate oxide layer 64 is coated on the surface of the gate 63 and contacts the first epitaxial layer 20, the second epitaxial layer 50 and the source region, the source region is located on the side of the gate trench structure away from the voltage divider structure, the source region includes a second doping region 65 and a third doping region 66, the second doping region 65 is located on the first epitaxial layer 20 away from the substrate 1 0, the third doping region 66 is located on the side of the second doping region 65 away from the bottom, the second doping region 65 and the third doping region 66 are both in contact with the gate oxide layer 64 of the gate trench structure, wherein the doping type of the second doping region 65 is the same as the doping type of the second epitaxial layer 50, the doping type of the third doping region 66 is the same as the doping type of the first epitaxial layer 20, and the doping concentration of the second doping region 65 is greater than the doping concentration of the third doping region 66, forming a trench gate MOSFET device.

[0049] In some optional embodiments, the doping concentration of the cut-off region 40 is greater than the doping concentration of the second epitaxial layer 50 , and the doping concentration of the third doping region 66 in the active region is greater than the doping concentration of the second epitaxial layer 50 .

[0050] Specifically, the cut-off region 40 has the same doping type as the first epitaxial layer 20 and the doping concentration of the cut-off region 40 is greater than the doping concentration of the second epitaxial layer 50, which can effectively cut off the leakage current generated by the leakage channel, help reduce the occurrence of large leakage at the edge of the device, reduce the barrier height during forward conduction, and significantly reduce the forward turn-on voltage of the power device, thereby reducing the turn-on loss of the diode and improving system reliability.

[0051] Furthermore, in the above-mentioned trench gate MOSFET device and diode device, the doping type of the active region is greater than the doping concentration of the second epitaxial layer, which can realize the opening of large current and increase the conduction capability of the device.

[0052] In such Figure 4 , Figures 7 and 8 The structure of the power device shown also includes a first conductive layer 81, a second conductive layer 82 and an oxide layer 5. The first conductive layer 81 is located on the side of the active area away from the substrate 10, and the second conductive layer 82 is located on the side of the substrate 10 away from the first epitaxial layer 20. The first conductive layer 81 constitutes a drain, and the second conductive layer 82 constitutes a source, and their main function is to input and output current; the side of the oxide layer 5 away from the substrate 10 in the voltage divider structure has the function of isolating the current and controlling the direction of the current.

[0053] Specifically, the first conductive layer 81 and the second conductive layer 82 both include conductive materials, wherein the conductive materials include but are not limited to alloy materials composed of any one or more of silver, copper, aluminum, gold, titanium, platinum and palladium metals. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0054] Specifically, the material of the oxide layer 5 includes insulating materials, wherein the insulating materials include but are not limited to any one or more of aluminum oxide, silicon oxide, aluminum nitride, titanium oxide, germanium oxide, gallium oxide, and indium tin oxide. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0055] According to another aspect of the present application, a preparation method is provided, such as Fig. 9 As shown, for preparing any of the above power devices, the preparation method includes:

[0056] Step S401: providing a substrate, wherein the substrate has a first surface;

[0057] Step S402: forming a first epitaxial layer on the first surface, the first epitaxial layer comprising a plurality of epitaxial regions distributed along a first direction, each epitaxial region having a second surface facing away from the substrate, the second surfaces of the plurality of epitaxial regions having different distances from the first surface in the second direction, the first direction being parallel to the first surface, the second direction being perpendicular to the first surface, and the first epitaxial layer having a first doping type;

[0058] Step S403: forming a plurality of implantation regions in the epitaxial region, wherein surfaces of the implantation regions facing away from the substrate are located in the second surface, and at least one implantation region is disposed in each epitaxial region;

[0059] Step S404: forming a second epitaxial layer on a side of the first epitaxial layer facing away from the substrate, wherein the second epitaxial layer and the implanted region have a second doping type.

[0060] The above-mentioned preparation method of the embodiment of the present application adopts a mature etching process, an ion implantation process and an epitaxial process, and has epitaxial regions with different heights. Only one ion implantation process is used to form an implantation region on the second surface of the epitaxial region, which reduces the process difficulty. Only one epitaxial process is required to form a second epitaxial layer with different doping types on the first epitaxial layer, simplifying the process and reducing the production cost. The formed device includes a double-layer structure of a first epitaxial layer and a second epitaxial layer, and multiple epitaxial regions have different heights in the second direction, which improves the high-voltage resistance of the power device. At the same time, there is an implantation region in the first epitaxial layer and it contacts the second epitaxial layer, so that on the basis of the terminal structure of the traditional power device, the second epitaxial layer and the implantation region are combined, which greatly reduces the leakage current of the device and reduces the production cost of the device. In addition, after the surface of the first epitaxial layer forms a high-low structure, an implantation region is formed on the surface of the first epitaxial layer, which simplifies the process and reduces the production cost. Therefore, the above-mentioned device improves the high-voltage resistance of the field limiting ring structure and the breakdown voltage of the power device while reducing the production cost of the device.

[0061] The following will describe in more detail the exemplary embodiments of the method for preparing a power device provided by the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0062] First, proceed to step S401: Fig.10 (a) to Fig.11 As shown in (a), a substrate 10 is provided.

[0063] Specifically, the substrate material includes but is not limited to silicon, silicon nitride, silicon carbide, gallium nitride, gallium oxide, aluminum oxide and aluminum nitride and other materials. Personnel in this field can make reasonable selections based on actual needs and no specific limitation is made without application.

[0064] After the step of providing the substrate, step S402 is performed; Fig.10 (b) to Fig.10 (d) and Fig.11 (b) to Fig.11 As shown in (f), a first epitaxial layer 20 is formed on the substrate 10.

[0065] Specifically, the steps of forming the first epitaxial layer include: Fig.10 (b) and Fig.11 As shown in (b), a first epitaxial material layer 21 is formed on the substrate by an epitaxial growth process; then, as shown in Fig.10 (d) and Fig.11As shown in (f), the first epitaxial material layer 21 is etched multiple times to form multiple second surfaces on the side of the first epitaxial material layer 21 facing away from the substrate. The multiple second surfaces have different heights in the second direction B, that is, multiple grooves with different depths are formed in the first epitaxial material layer 21, and the remaining first epitaxial material layer constitutes the first epitaxial layer 20.

[0066] Before etching to form the groove, the preparation method further comprises the following steps: Fig.10 (c) and Fig.11 (c) to Fig.11 As shown in (e), an active region is formed.

[0067] In a specific implementation method, the voltage division structure is applied to a trench gate MOSFET device, such as Fig.11 (c) to Fig.11 As shown in (e), the steps of forming the trench gate active region include: first, as shown in Fig.11 As shown in (c), a second doping region 65 and a third doping region 66 are formed in the second epitaxial layer 50, wherein the second doping region 65 and the third doping region 66 are both of the second doping type, and the doping concentration of the third doping region 66 is greater than the doping concentration of the first doping region; then, as shown in Fig.11 As shown in (d), a first trench 631 is formed that penetrates the second doping region 65 and the third doping region 66 and extends into the first epitaxial layer 20; then, as shown in Fig.11 As shown in (e), a gate oxide layer 64 is formed on the inner wall of the first trench, and a gate material is filled in the remaining area of ​​the first trench to form a gate 63.

[0068] In another specific implementation method, the above voltage dividing structure is applied to a diode device, and the steps of forming a diode active region include: Fig.10 As shown in (c), a first doping region 62 having a second doping type is formed in the first epitaxial layer 20 , wherein the doping concentration of the first doping region 62 is greater than the doping concentration of the first epitaxial layer 20 .

[0069] Specifically, the first epitaxial layer 20 may include materials such as silicon carbide, silicon, quartz, silicon nitride, gallium nitride, gallium oxide, aluminum oxide, and aluminum nitride. Personnel in the art may make reasonable selections based on actual needs, and no specific limitation is made without application. Exemplarily, the first epitaxial layer 20 is made of silicon carbide material to solve the problem that the product performance advantage of SiC diode devices is not obvious in some parameters.

[0070] Among them, the process of forming the first epitaxial layer includes but is not limited to a deposition process and an epitaxial growth process. In the epitaxial growth process, the doping concentration of impurities is relatively easy to control, and the activation rate is relatively fixed, and it is easy to achieve the target doping distribution. It is not only suitable for silicon-based power devices, but also can avoid the difficulty of injection doping of silicon carbide power devices and improve the efficiency of its terminal structure. The deposition process is relatively mature, simple to operate, and has a low cost. Among them, the deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). Among them, physical vapor deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, chemical vapor deposition (CVD) includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), metal organic compound chemical vapor deposition (MOCVD), laser induced chemical vapor deposition (LCVD), and those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0071] Among them, the etching process includes but is not limited to dry etching (Dry Etching), wet etching (Wet Etching), deep etching (Deep Etching), ion beam etching (IBE) and electrolytic etching, among which dry etching includes physical etching, chemical vapor etching and plasma etching, and deep etching includes deep reactive ion etching and laser etching. Technical personnel in this field can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0072] After etching the first epitaxial layer, step S403 is performed: Fig.10 (e) and Fig.11 As shown in (g), a plurality of implantation regions 31 are formed in the epitaxial region.

[0073] Specifically, the step of forming the injection region includes: forming a mask layer on the first epitaxial layer by a deposition process; patterning the mask layer to form an injection region pattern, wherein the injection region pattern exposes the first epitaxial layer; forming an injection region in the exposed first epitaxial layer by an ion implantation process, and then removing the remaining mask layer.

[0074] Specifically, the ion implantation process does not require high temperature treatment, that is, it can achieve precise control of the ion concentration and depth of the implantation, and while achieving precise doping, it can avoid damage and deformation of the material structure. In addition, the doping concentration of the implantation region is greater than the doping concentration of the second sub-epitaxial portion, and the depth of the implantation region is less than the depth of the first sub-epitaxial portion. The ion implantation process can accurately control the doping concentration and depth of the implantation region. In addition, for the carbon-silicon bond energy in the silicon carbide material is high, it is difficult for impurity atoms to diffuse in the silicon carbide material. The ion implantation process is a method of adding a certain amount and type of impurities to the semiconductor material to change the electrical properties. The ion implantation process has a low injection temperature, and can flexibly and accurately control the doping distribution, which can reduce the damage of high temperature to the silicon carbide material and improve the doping efficiency. However, the ion implantation cost is relatively expensive and the cost is high. The diode structure of the present application uses a double-layer epitaxial material to form the first epitaxial layer and the second epitaxial layer, which can reduce the number of ion implantations, simplify the process, and reduce the production cost.

[0075] After the implantation region is formed, step S404 is performed: Fig.10 (f) and Fig.11 As shown in (h), a second epitaxial layer 50 is formed on the first epitaxial layer.

[0076] Specifically, the process for forming the first epitaxial layer includes but is not limited to a deposition process and an epitaxial growth process, wherein the deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD), wherein physical vapor deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, chemical vapor deposition (CVD) includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), metal organic compound chemical vapor deposition (MOCVD), laser induced chemical vapor deposition (LCVD), and those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0077] The doping type of the second epitaxial layer is different from the doping type of the first epitaxial layer.

[0078] In some optional embodiments, after step S404, the preparation method further comprises: first, Fig.10 As shown in (g) and 11 (i), a cut-off region 40 is formed. Specifically, an N-type doped cut-off region 40 is formed on the side of the second epitaxial layer 50 away from the active region, and the cut-off region 40 is in contact with the second epitaxial layer 50; then, as shown in Fig.10 As shown in (h) and 11 (j), an oxide layer 5 is formed on the above structure; then, as shown in Fig.10 As shown in (i) and 11 (k), a through hole is formed on the active area by an etching process; then, as shown in Fig.10 As shown in (j) and 11 (l), a first conductive layer 81 and a second conductive layer 82 are formed by a deposition process to transmit current to the semiconductor.

[0079] In the above specific implementation method, Fig.11 As shown in (k), in the above trench gate MOSFET device, an etching process is used to form a through hole penetrating to the third doping region 66 in the oxide layer 5; then, as shown in Fig.11 As shown in (l), a first conductive layer 81 is formed above the third doped region 66 and the gate trench structure, and then a second conductive layer 82 is formed on a side of the substrate 10 away from the first epitaxial layer 20 by a deposition process.

[0080] In another specific implementation method above, Fig.10 As shown in (i), in the above diode device, an etching process is used to form a through hole penetrating to the first doping region 62 in the oxide layer 5; then, as shown in Fig.10 As shown in (j), a first conductive layer 81 is formed above the first doped region 62 , and then a second conductive layer 82 is formed on a side of the substrate 10 away from the first epitaxial layer 20 by a deposition process.

[0081] Specifically, the material of the first conductive layer and the material of the second conductive layer include but are not limited to alloy materials composed of any one or more of silver, copper, aluminum, gold, titanium, platinum and palladium metals. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0082] The power device formed by the method for preparing the power device of the present application will be further described below in conjunction with embodiments.

[0083] Example 1

[0084] The method for preparing a diode power device provided in this embodiment comprises the following steps: Fig.10 As shown:

[0085] Provide an N-shaped silicon carbide substrate 10, such as Fig.10 (a) as shown;

[0086] An N-type first epitaxial material layer 21 is formed on the N-type silicon carbide substrate 10 by using an epitaxial growth process. Fig.10 (b) as shown;

[0087] An ion doping process is used to form a P-type first doped region 62 on the side of the N-type first epitaxial material layer 21 away from the substrate. Fig.10 (c) as shown;

[0088] A first groove 33 is formed in the N-type first epitaxial material layer on one side of the P-type first doping region 62 by using an etching process, and a second groove 34 is formed in the N-type first epitaxial material layer on the side of the first groove 33 away from the P-type first doping region 62 by using an etching process, wherein one side of the second groove 34 is coplanar with one side of the first groove, and the remaining N-type first epitaxial material layer constitutes the first epitaxial layer 20, as shown in FIG. Fig.10 (d) as shown;

[0089] A mask layer is formed on the first epitaxial layer by a deposition process, and the mask layer is patterned to form an implantation region pattern, wherein the implantation region pattern exposes the first epitaxial layer 20, and P ions are implanted into the exposed first epitaxial layer 20 by an ion implantation process to form an implantation region 31, and the remaining mask layer is removed to form four P-type implantation regions 31 on the bottom surface of the first groove 33, and three P-type implantation regions 31 are formed on the bottom surface of the second groove 34, as shown in FIG. Fig.10 (e) as shown;

[0090] The P-type second epitaxial layer 50 is formed in the first groove 33 and the second groove 34 by using an epitaxial growth process. Fig.10 (f) as shown;

[0091] An N-type cut-off region 40 is formed on the side of the second epitaxial layer 50 away from the P-type first doping region 62 by an ion implantation process. Fig.10 (g) as shown;

[0092] A silicon oxide layer is deposited on the above structure by a deposition process to form an oxide layer 5, such as Fig.10 (h) as shown;

[0093] The oxide layer on the P-type first doping region 62 is removed by etching to form a through hole penetrating the first doping region 62. Fig.10 (i) as shown;

[0094] A first conductive layer 81 is formed in the through hole on the surface of the P-type first doped region 62 by a deposition process, and a second conductive layer 82 is formed on the side of the N-type silicon carbide substrate 10 away from the P-type first epitaxial layer 20. Fig.10 (j) shown.

[0095] Example 2

[0096] The method for preparing a trench gate MOSFET power device provided in this embodiment comprises the following steps: Fig.11 As shown:

[0097] Provide an N-shaped silicon carbide substrate 10, such as Fig.11 (a) as shown;

[0098] An N-type first epitaxial material layer 21 is formed on the N-type silicon carbide substrate 10 by using an epitaxial growth process. Fig.11 (b) as shown;

[0099] An ion doping process is used to form a P-type second doping region 65 on the side of the N-type first epitaxial material layer 21 away from the substrate, and a P-type third doping region 66 is formed on the side of the P-type second doping region 65 away from the substrate, wherein the doping concentration of the P-type third doping region 66 is greater than the doping concentration of the P-type second doping region 65, such as Fig.11 (c) as shown;

[0100] A first trench 631 is formed in the P-type third doping region 66 and the N-type first epitaxial material layer 21 on one side adjacent to the P-type third doping region 66 by an etching process. Fig.11 (d) as shown;

[0101] An oxidation process is used to form a gate oxide layer 64 on the inner wall of the first trench, and a deposition process is used to deposit polysilicon material on the remaining area of ​​the first trench to form a gate 63. The gate 63 and the gate oxide layer 64 constitute a gate trench structure, such as Fig.11 (e) as shown;

[0102] A first groove 33 is formed in the N-type first epitaxial material layer on the side of the gate trench structure away from the P-type third doping region 66 by an etching process, and a second groove 34 is formed in the N-type first epitaxial material layer on the side of the first groove 33 away from the P-type third doping region 66 by an etching process, wherein one side of the second groove 34 is coplanar with one side of the first groove 33, and the first groove 33 is greater than the depth of the second groove 34, and the remaining N-type first epitaxial material layer constitutes the first epitaxial layer 20, as shown in FIG. Fig.11 (f) as shown;

[0103] A mask layer is formed on the first epitaxial layer 20 by a deposition process, and the mask layer is patterned to form an implantation region pattern, wherein the implantation region pattern exposes the first epitaxial layer 20, and P ions are implanted into the exposed first epitaxial layer 20 by an ion implantation process to form an implantation region 31, and the remaining mask layer is removed, that is, four P-type implantation regions 31 are formed on the bottom surface of the first groove 33, and three P-type implantation regions 31 are formed on the bottom surface of the second groove 34, as shown in FIG. Fig.11 (g) as shown;

[0104] The P-type second epitaxial layer 50 is formed in the first groove 33 and the second groove 34 by using an epitaxial growth process. Fig.11 (h) as shown;

[0105] An N-type cut-off region 40 is formed on the side of the second epitaxial layer 50 away from the gate trench structure by an ion implantation process. Fig.11 (i) as shown;

[0106] A silicon oxide layer is deposited on the above structure by a deposition process to form an oxide layer 5, such as Fig.11 (j) as shown;

[0107] The oxide layer 5 located on the P-type third doping region 66 is removed by etching to form a through hole penetrating to the first doping region 62, such as Fig.11 (k) as shown;

[0108] A first conductive layer 81 is formed in the through hole on the P-type third doping region 66 by a deposition process, and a second conductive layer 82 is formed on the side of the N-type silicon carbide substrate 10 away from the P-type first epitaxial layer 20. Fig.11 (l) shown.

[0109] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0110] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A power device, characterized in that: include: a substrate having a first surface; a first epitaxial layer, the first epitaxial layer is arranged on the first surface, and the first epitaxial layer includes a plurality of epitaxial regions distributed along a first direction, each of the epitaxial regions has a second surface facing away from the substrate, the second surfaces of the plurality of epitaxial regions have different distances from the first surface in the second direction, the first direction is parallel to the first surface, the second direction is perpendicular to the first surface, and the first epitaxial layer has a first doping type; A plurality of implantation regions, wherein the implantation regions are arranged in the epitaxial region, and the surfaces of the implantation regions facing away from the substrate are located in the second surface, and at least one implantation region is arranged in each epitaxial region; A second epitaxial layer, wherein the second epitaxial layer is located on a side of the first epitaxial layer away from the substrate, the second epitaxial layer is in contact with the implantation region, and the second epitaxial layer and the implantation region have a second doping type.

2. The power device according to claim 1, characterized in that: The distance between the second surface of the plurality of epitaxial regions and the first surface in the second direction increases gradually along the first direction.

3. The power device according to claim 1, characterized in that: The depth of the implanted region in any one of the epitaxial regions decreases along the first direction.

4. The power device according to claim 1, characterized in that: The doping concentration of the implanted region in any one of the epitaxial regions decreases along the first direction.

5. The power device according to claim 1, characterized in that: The width of the epitaxial region decreases along the first direction.

6. The power device according to any one of claims 1 to 5, characterized in that: The power device also includes: an active region and a cut-off region, wherein the active region and the cut-off region are located on different sides of the first epitaxial layer away from the substrate, wherein the first direction is the direction from the active region to the cut-off region, the cut-off region has the first doping type, and the active region has the second doping type.

7. The power device according to claim 6, characterized in that: The doping concentration of the cut-off region is lower than the doping concentration of the second epitaxial layer, and the doping concentration of the active region is higher than the doping concentration of the second epitaxial layer.

8. A method for preparing a power device, characterized in that: Used to prepare the power device according to any one of claims 1 to 7, the preparation method comprising: providing a substrate having a first surface; forming a first epitaxial layer on the first surface, the first epitaxial layer comprising a plurality of epitaxial regions distributed along a first direction, each of the epitaxial regions having a second surface facing away from the substrate, the second surfaces of the plurality of epitaxial regions having different distances from the first surface in the second direction, the first direction being parallel to the first surface, the second direction being perpendicular to the first surface, and the first epitaxial layer having a first doping type; forming a plurality of implantation regions in the epitaxial region, wherein the implantation regions are located in the second surface away from the surface of the substrate, and at least one implantation region is disposed in each epitaxial region; A second epitaxial layer is formed on a side of the first epitaxial layer facing away from the substrate, and the second epitaxial layer and the implantation region have a second doping type.

9. The preparation method according to claim 8, characterized in that: The step of forming the first epitaxial layer comprises: forming a first epitaxial material layer on the substrate by using an epitaxial growth process; The first epitaxial material layer is etched multiple times to form a plurality of second surfaces on a side of the first epitaxial material layer away from the substrate, wherein the plurality of second surfaces have different distances from the first surface in the second direction, and the remaining first epitaxial material layer constitutes the first epitaxial layer.

10. The preparation method according to claim 8, characterized in that: The step of forming the implantation region comprises: forming a mask layer on the first epitaxial layer by a deposition process; Performing patterning on the mask layer to form an implantation region pattern, wherein the implantation region pattern exposes the first epitaxial layer; forming the implantation region in the exposed first epitaxial layer by an ion implantation process; The remaining mask layer is removed.

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