A SiC trench power device, a manufacturing method, a power module, a conversion circuit, and a vehicle

Abstract

The application discloses a SiC gate trench type power device, which comprises a substrate layer provided with a first conductive type; an epitaxial layer provided with the first conductive type and located on one side of the substrate layer; the epitaxial layer is provided with a gate trench on a side far from the substrate layer; the gate trench comprises at least one arc segment; the epitaxial layer comprises a well region provided with a second conductive type; and a first region provided with the first conductive type and located on a side of the well region far from the substrate layer; a gate structure located in the gate trench; the gate structure comprises a gate; the gate is in contact with the well region; a source electrode located on a side of the epitaxial layer far from the substrate layer; and a drain electrode located on a side of the substrate layer far from the epitaxial layer. The SiC gate trench type power device has the gate trench provided with a circular arc shape, so that the electric field distribution at the bottom of the gate trench is uniform, the electric field at the corner of the trench is not intensified, and the oxide layer is not easy to be broken down. The application further discloses a preparation method of the SiC gate trench type power device, a power module, a conversion circuit and a vehicle.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology. Specifically, the present invention relates to a SiC trench power device, a preparation method, a power module, a conversion circuit and a vehicle. Background Art

[0002] In the prior art, such as Figure 7 As shown, the power device adopts an asymmetric gate trench structure, and the left side wall of the gate trench contains a MOS channel (metal oxide semiconductor channel), which is aligned to the (11-20) plane to achieve optimal channel mobility.

[0003] The p-type region below the bottom of the gate trench increases the body diode area by embedding a p+ region at the bottom of the gate trench, thereby increasing the maximum current of the device in the dead zone at the switching moment and improving the reliability of the device.

[0004] In existing gate trench power devices, the high electric field in the SiC (silicon carbide) drift region leads to a very high electric field on the gate oxide layer. The right-angle (or obtuse) structure of the trench corner and the bottom intensifies the electric field, making the oxide layer prone to breakdown. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention provides a SiC gate trench power device, the purpose of which is to ensure that the oxide layer is not easily broken down.

[0006] In order to achieve the above-mentioned object, the technical solution adopted by the present invention is: a SiC gate trench power device, comprising:

[0007] A substrate layer configured as a first conductivity type;

[0008] An epitaxial layer of the first conductivity type is located on one side of the substrate layer, a gate trench is provided on a side of the epitaxial layer away from the substrate layer, and the gate trench includes at least one arc-shaped segment; the epitaxial layer includes a well region of the second conductivity type; and a first region of the first conductivity type is located on a side of the well region away from the substrate layer;

[0009] a gate structure located in the gate trench, the gate structure comprising a gate, the gate being in contact with the well region;

[0010] a source electrode, located on a side of the epitaxial layer away from the substrate layer;

[0011] The drain is located on a side of the substrate layer away from the epitaxial layer.

[0012] The gate structure further includes a gate oxide layer, which is located between the gate and the gate trench. The gate oxide layer covers the gate trench and extends to a side of the epitaxial layer away from the substrate layer.

[0013] The epitaxial layer further includes a second region of a second conductivity type, the second region being located on a side of the well region away from the substrate layer and in contact with the first region.

[0014] The epitaxial layer further includes a third region of the second conductivity type, and the third region is located at the bottom of the gate trench.

[0015] The gate, the well region, the first region, and the second region are all symmetrically arranged in two with respect to the gate trench.

[0016] The present invention also provides a method for manufacturing a SiC gate trench power device, comprising:

[0017] providing a substrate layer configured as a first conductivity type;

[0018] forming an epitaxial layer of a first conductivity type on one side of the substrate layer;

[0019] forming a well region of the second conductivity type in the epitaxial layer, the second conductivity type being opposite to the first conductivity type;

[0020] forming a first region having the first conductivity type on a side of the well region away from the substrate layer;

[0021] forming a gate trench on a side of the epitaxial layer away from the substrate layer, wherein the gate trench contacts the well region and includes at least one arc-shaped segment;

[0022] forming a gate in the gate trench;

[0023] forming a dielectric isolation layer on a side of the gate trench away from the epitaxial layer;

[0024] forming a source electrode on a side of the dielectric isolation layer away from the epitaxial layer, wherein the source electrode is in contact with the first region;

[0025] A drain is formed on a side of the substrate layer away from the epitaxial layer.

[0026] The gate trench is formed on a side of the epitaxial layer away from the substrate layer, the gate trench is in contact with the well region and the gate trench includes at least one arc segment.

[0027] forming a first mask layer on a side of the epitaxial layer away from the substrate layer;

[0028] forming a first photoresist on a side of the first mask layer away from the epitaxial layer, wherein the first photoresist has a first groove on a side away from the first mask layer, and the first groove includes at least one arc segment;

[0029] forming a second groove on a side of the first mask layer away from the epitaxial layer, wherein the second groove has the same morphology as the first groove;

[0030] The gate trench is formed on a side of the epitaxial layer away from the substrate layer, and the gate trench and the second groove have the same morphology.

[0031] A first photoresist is formed on a side of the first mask layer away from the epitaxial layer, wherein the first photoresist has a first groove on a side away from the first mask layer, wherein the first groove includes at least one arc segment.

[0032] The first photoresist is formed by using a gradient transmittance photolithography technique or a weak exposure technique, and the first photoresist has a first groove on a side away from the first mask layer, and the first groove includes at least one arc segment;

[0033] And / or, forming a second groove on a side of the first mask layer away from the epitaxial layer, wherein the second groove has the same morphology as the first groove comprises:

[0034] forming the second groove by dry etching technology, wherein the second groove and the first groove have the same morphology;

[0035] And / or, forming the gate trench on a side of the epitaxial layer away from the substrate layer, wherein the gate trench and the second groove have the same morphology comprises:

[0036] The gate trench is formed by dry etching technology, and the gate trench and the second groove have the same morphology.

[0037] Forming a gate in the gate trench includes:

[0038] forming a gate oxide layer on a side of the epitaxial layer away from the substrate layer, the gate oxide layer covering a side of the epitaxial layer away from the substrate layer and the gate trench, and a third groove being provided on the side of the gate oxide layer away from the epitaxial layer, the third groove and the gate trench having the same morphology;

[0039] A polysilicon layer is formed on a side of the gate oxide layer away from the epitaxial layer, and a fourth groove is formed on a side of the polysilicon layer away from the gate oxide layer, and the fourth groove and the gate trench have the same morphology;

[0040] forming a second mask layer on a side of the polysilicon layer away from the gate oxide layer, wherein the second mask layer has a fifth groove on a side away from the polysilicon layer, and the fifth groove and the gate trench have the same morphology;

[0041] Filling the fifth groove with a second photoresist;

[0042] removing a portion of the second mask layer to form a sub-mask, wherein the sub-mask is located in the fourth groove;

[0043] forming a sidewall spacer on at least one side of the sub-mask, wherein the sidewall spacer is located in the fourth groove;

[0044] removing the sub-mask;

[0045] Using the sidewall as a mask, a portion of the polysilicon layer is removed to form the gate, wherein the gate contacts the well region;

[0046] The side walls are removed.

[0047] The method for manufacturing the SiC trench power device further includes:

[0048] forming a third region of the second conductivity type at the bottom of the gate trench;

[0049] sputtered carbon film;

[0050] Passivation was performed with argon;

[0051] After high temperature annealing, the carbon film is removed.

[0052] The present invention also provides a power module, characterized in that it includes a substrate and at least one SiC trench-type power device, wherein the substrate is used to support the SiC trench-type power device.

[0053] The present invention also provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction;

[0054] The power conversion circuit includes a circuit board and at least one SiC trench power device, and the SiC trench power device is electrically connected to the circuit board.

[0055] The present invention also provides a vehicle, comprising a load and the power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0056] In the SiC trench power device of the present invention, the gate trench is arranged in an arc shape, so that the electric field at the bottom of the gate trench is evenly distributed, the electric field at the trench corner is prevented from being aggravated, and the oxide layer is not easily broken down. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] This manual includes the following drawings, which show the following contents:

[0058] Figure 1 It is a schematic structural diagram of a gate trench power device of the present invention;

[0059] Figures 2 to 6 This is a schematic diagram of the preparation process of a gate trench power device;

[0060] Figure 7 It is a schematic structural diagram of a gate trench power device in the prior art;

[0061] The markings in the figure are: 1. substrate layer; 2. first region; 3. epitaxial layer; 4. p-type region; 5. p+ region; 6. gate oxide layer; 7. gate trench; 8. dielectric isolation layer; 9. source; 10. gate; 11. n-type region; 12. second region; 13. third region; 14. well region; 15. drain; 16. polysilicon layer; 17. first photoresist; 18. sidewall; 19. second mask layer; 20. first mask layer; 21. second photoresist. DETAILED DESCRIPTION

[0062] The following is a further detailed description of the specific implementation methods of the present invention through the description of embodiments with reference to the accompanying drawings, with the aim of helping those skilled in the art to have a more complete, accurate and in-depth understanding of the concept and technical solution of the present invention and to facilitate its implementation.

[0063] It should be noted that in the following embodiments, the "first", "second" and "third" do not represent an absolute distinction in structure and / or function, nor do they represent a sequence of execution, but are merely for the convenience of description.

[0064] First, as Figure 1 As shown, the present invention provides a SiC gate trench power device, comprising:

[0065] A substrate layer 1 of a first conductivity type is provided, and the material of the substrate layer 1 is silicon carbide;

[0066] An epitaxial layer 3 of the first conductivity type is located on one side of the substrate layer 1. A gate trench 7 is provided on the side of the epitaxial layer 3 away from the substrate layer 1. The gate trench 7 includes at least one arc-shaped segment. The epitaxial layer 3 includes a well region 14 of the second conductivity type. A first region 2 of the first conductivity type is located on the side of the well region 14 away from the substrate layer 1.

[0067] A gate 10 structure is located in the gate trench 7 , and the gate 10 structure includes a gate 10 , and the gate 10 is in contact with the well region 14 ;

[0068] The source electrode 9 is located on a side of the epitaxial layer 3 away from the substrate layer 1;

[0069] The drain 15 is located on a side of the substrate layer 1 away from the epitaxial layer 3 .

[0070] Specifically, if Figure 1 As shown, the gate 10 structure further includes a gate oxide layer 6, which is located between the gate 10 and the gate trench 7. The gate oxide layer 6 covers the gate trench 7 and extends to the side of the epitaxial layer 3 away from the substrate layer 1. Two gates 10 are provided, and the well regions 14 distributed on both sides of the gate trench 7 are aligned with the two gates 10 provided in the gate trench 7.

[0071] like Figure 1 As shown, the epitaxial layer 3 also includes a second region 12 set to the second conductivity type (for example, P type) and a third region 13 set to the second conductivity type (for example, P type), the second region 12 is located on the side of the well region 14 away from the substrate layer 1 and in contact with the first region 2, and the third region 13 is located at the bottom of the gate trench 7.

[0072] like Figure 1 As shown, the gate oxide layer 6 completely covers the inner circular surface of the arcuate segment of the gate trench 7. The gate 10 is connected to the inner circular surface of the gate oxide layer 6. The inner circular surface of the gate oxide layer 6 and the inner circular surface of the arcuate segment of the gate trench 7 are coaxially arranged arc surfaces. Two gates 10, well regions 14, first regions 2, and second regions 12 are each symmetrically arranged about the gate trench 7. The two gates 10 are distributed along the circumferential direction on the inner circular surface of the gate oxide layer 6, and the two gates 10 are aligned with the two well regions 14 respectively. The two first regions 2 are distributed on both sides of the gate trench 7. The gate oxide layer 6 is in contact with the first regions 2 and well regions 14 on both sides. The gates 10 are polycrystalline silicon.

[0073] like Figure 1 As shown, the arc section of the gate trench 7 is set to be an arc shape, so that the electric field at the bottom of the arc is evenly distributed, avoiding the aggravation of the electric field at the groove corner, and the oxide layer is not easily broken down. The gate 10 in the gate trench 7 is split into two parts, which are respectively aligned with the well regions 14 on the left and right sides of the gate trench 7, thereby greatly reducing the coupling capacitance between the gate 10 and the first region 2.

[0074] like Figure 1As shown, the second region 12 contacts the first region 2 and the well region 14. The second region 12 is distributed on both sides of the first region 2. The first region 2 is located between the gate trench 7 and the second region 12. The third region 13 is located at the bottom of the gate trench 7, and the well region 14 is distributed on both sides of the third region 13. The second region 12 plays a role in maintaining potential, and the third region 13 plays a role in shielding the electric field and protecting the bottom of the gate trench 7.

[0075] like Figure 1 As shown, the SiC gate trench power device of the present invention further includes a drain 15, a dielectric isolation layer 8 and a source 9. The source 9 is located on the side of the epitaxial layer 3 away from the substrate layer 1, and the drain 15 is located on the side of the substrate layer 1 away from the epitaxial layer. The dielectric isolation layer 8 covers the gate oxide layer 6 and the two gates 10. The dielectric isolation layer 8 is located between the source 9 and the gate oxide layer 6. The source 9 covers the dielectric isolation layer 8, the second region 12 and the first region 2, and the source 9 is in contact with the second region 12 and the first region 2.

[0076] In a second aspect, the present invention further provides a method for manufacturing a SiC gate trench power device, comprising the following steps:

[0077] S1, providing a substrate layer 1 set to a first conductivity type;

[0078] S2, forming an epitaxial layer 3 of a first conductivity type on one side of the substrate layer 1;

[0079] S3, forming a well region 14 of a second conductivity type in the epitaxial layer 3, where the second conductivity type is opposite to the first conductivity type;

[0080] S4, forming a first region 2 having a first conductivity type on a side of the well region 14 away from the substrate layer 1;

[0081] S5. Forming a gate trench 7 on a side of the epitaxial layer 3 away from the substrate layer 1, wherein the gate trench 7 contacts the well region 14 and includes at least one arc-shaped segment;

[0082] S6, forming a gate 10 in the gate trench 7;

[0083] S7, forming a dielectric isolation layer 8 on a side of the gate trench 7 away from the epitaxial layer 3;

[0084] S8. Forming a source electrode 9 on a side of the dielectric isolation layer 8 away from the epitaxial layer 3, wherein the source electrode 9 is in contact with the first region 2;

[0085] S9 . Form a drain 15 on a side of the substrate layer 1 away from the epitaxial layer 3 .

[0086] Specifically, if Figure 2As shown, in the above method, on the substrate layer 1, PECVD (plasma enhanced chemical vapor deposition) and photolithography process are used to transfer the pattern of the mask to the SiO2 mask, and then P-, N+, and P+ ions are injected in sequence to form a channel switch path. Finally, the mask is removed to form a well region 14, a second region 12, and a first region 2. The second region 12 is distributed on both sides of the first region 2, and the second region 12 is connected to the first region 2 and the well region 14.

[0087] In the above step S5, forming a gate trench 7 on a side of the epitaxial layer 3 away from the substrate layer 1, wherein the gate trench 7 contacts the well region 14 and includes at least one arc-shaped segment, comprises the following steps:

[0088] S501, forming a first mask layer 20 on a side of the epitaxial layer 3 away from the substrate layer 1;

[0089] S502, forming a first photoresist 17 on a side of the first mask layer 20 away from the epitaxial layer 3, wherein the first photoresist 17 has a first groove on a side away from the first mask layer 20, and the first groove includes at least one arc segment;

[0090] S503, forming a second groove on a side of the first mask layer 20 away from the epitaxial layer 3, wherein the second groove has the same morphology as the first groove;

[0091] S504 , forming a gate trench 7 on a side of the epitaxial layer 3 away from the substrate layer 1 , wherein the gate trench 7 and the second groove have the same morphology.

[0092] In this embodiment, the material of the first mask layer 20 may be silicon nitride, silicon oxide, silicon oxynitride, or amorphous carbon, preferably silicon oxide.

[0093] like Figure 3.2 As shown, in the above step S502, a first photoresist 17 is formed on the side of the first mask layer 20 away from the epitaxial layer 3. The first photoresist 17 has a first groove on the side away from the first mask layer 20. The first groove includes at least one arc segment including:

[0094] The first photoresist 17 is formed by using a gradient transmittance photolithography technique or a weak exposure technique. The first photoresist 17 has a first groove on a side away from the first mask layer 20 . The first groove includes at least one arc segment.

[0095] like Figure 3.3 As shown, in the above step S503, a second groove is formed on the side of the first mask layer 20 away from the epitaxial layer 3, and the second groove and the first groove have the same morphology including:

[0096] The second groove is formed by adopting dry etching technology, and the second groove has the same morphology as the first groove.

[0097] In the above step S504, a gate trench 7 is formed on the side of the epitaxial layer 3 away from the substrate layer 1. The gate trench 7 and the second groove have the same morphology including:

[0098] The gate trench 7 is formed by dry etching technology, and the gate trench 7 and the second groove have the same morphology.

[0099] In the above step S6, forming the gate 10 in the gate trench 7 includes:

[0100] S601, forming a gate oxide layer 6 on a side of the epitaxial layer 3 away from the substrate layer 1, the gate oxide layer 6 covering the side of the epitaxial layer 3 away from the substrate layer 1 and the gate trench 7, and a third groove is formed on the side of the gate oxide layer 6 away from the epitaxial layer 3, and the third groove and the gate trench 7 have the same morphology;

[0101] S602, forming a polysilicon layer on a side of the gate oxide layer 6 away from the epitaxial layer 3, and a fourth groove is formed on the side of the polysilicon layer away from the gate oxide layer 6, and the fourth groove and the gate trench 7 have the same morphology;

[0102] S603, forming a second mask layer 19 on a side of the polysilicon layer away from the gate oxide layer 6, wherein the second mask layer 19 has a fifth groove on a side away from the polysilicon layer, and the fifth groove has the same morphology as the gate trench 7;

[0103] S604, filling the fifth groove with a second photoresist 21;

[0104] S605, removing a portion of the second mask layer 19 to form a sub-mask, where the sub-mask is located in the fourth groove;

[0105] S606, forming a sidewall spacer 18 on at least one side of the sub-mask, wherein the sidewall spacer 18 is located in the fourth groove;

[0106] S607, removing the sub-mask;

[0107] S608 , using the sidewall 18 as a mask, removing part of the polysilicon layer to form the gate 10 , where the gate 10 is in contact with the well region 14 ;

[0108] S609 , remove the side wall 18 .

[0109] like Figure 5.1 As shown, in the above step S601 , a gate oxide layer 6 is formed by high-temperature dry oxygen. The gate oxide layer 6 covers the side of the epitaxial layer 3 away from the substrate layer 1 and the gate trench 7 . The gate oxide layer 6 contacts the second region 12 and the first region 2 .

[0110] like Figure 5.1 As shown, in the above step S602 , after the gate oxide layer 6 is prepared, a polysilicon layer 16 is formed on a side of the gate oxide layer 6 away from the epitaxial layer 3 .

[0111] like Figure 5.1 As shown, in the above step S603 , a second mask layer 19 is prepared on the polysilicon layer 16 , and the polysilicon layer 16 completely covers the gate oxide layer 6 . The second mask layer 19 completely covers the polysilicon layer 16 .

[0112] In this embodiment, the material of the second mask layer 19 may be silicon nitride, silicon oxide, silicon oxynitride or amorphous carbon, preferably silicon oxide.

[0113] like Figure 5.3 As shown, in the above step S605, the second mask layer 19 outside the arc-shaped groove on the polysilicon layer 16 is wet-etched, and then the etching time is controlled so that the second mask layer 19 inside the arc-shaped groove on the polysilicon layer 16 remains located at a part of the bottom of the arc-shaped groove to form a sub-mask in the fourth groove of the sub-mask.

[0114] like Figure 5.4 As shown, in the above step S606 , a spacer 18 is formed on at least one side of the sub-mask. The spacer 18 is located in the fourth groove, and the spacer 18 is in contact with the polysilicon layer 16 .

[0115] like Figure 5.5 As shown, in the above step S608 , the sub-mask located between the two sidewall spacers 18 is removed.

[0116] like Figure 5.6 As shown, in the above step S609 , the two sidewalls 18 are used as masks to etch the polysilicon layer 16 and remove a portion of the polysilicon layer 16 to form the gate 10 .

[0117] like Figure 5.6 As shown, in the above step S609 , after the spacers 18 are removed, two gates 10 are formed.

[0118] In this embodiment, the material of the second mask layer 19 may be silicon nitride, silicon oxide, silicon oxynitride, or amorphous carbon, preferably silicon nitride.

[0119] like Figure 1 As shown, the method for manufacturing a SiC gate trench power device of the present invention further includes the following steps between forming the first region 2 having the first conductivity type on the side of the well region 14 away from the substrate layer 1 and forming the gate trench 7 on the side of the epitaxial layer 3 away from the substrate layer 1:

[0120] A third region 13 of the second conductivity type is formed at the bottom of the gate trench 7. Figure 4 As shown;

[0121] sputtered carbon film;

[0122] Passivation was performed with argon;

[0123] After high temperature annealing, the carbon film is removed.

[0124] Through the above process steps, two polycrystalline gates can be formed in the arc gate trench, and the gates are self-aligned with the well region. The overlapping area between the gates and the third region 13 and the first region 2 is small, and the parasitic capacitance is small.

[0125] In a third aspect, the present invention further provides a power module comprising a substrate and at least one SiC trench power device according to any embodiment of the present invention, wherein the substrate is configured to support the SiC trench power device. The present invention has the same technical effects and is not further described here.

[0126] In a fourth aspect, the present invention further provides a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0127] The power conversion circuit includes a circuit board and at least one SiC trench power device according to any embodiment of the present invention, wherein the SiC trench power device is electrically connected to the circuit board. The same technical effects are achieved and are not described in detail here.

[0128] In a fifth aspect, the present invention further provides a vehicle comprising a load and a power conversion circuit, wherein the power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. The aforementioned embodiments have the same technical effects and are not further described herein.

[0129] The present invention has been described above with reference to the accompanying drawings. Obviously, the specific implementation of the present invention is not limited to the above-described method. Any non-substantial improvements made using the method concepts and technical solutions of the present invention, or any direct application of the above-described concepts and technical solutions to other situations without modification, fall within the scope of protection of the present invention.

Claims

1. A method for manufacturing a SiC gate trench power device, characterized in that: include: providing a substrate layer configured as a first conductivity type; forming an epitaxial layer of a first conductivity type on one side of the substrate layer; forming a well region of a second conductivity type in the epitaxial layer, the second conductivity type being opposite to the first conductivity type; forming a first region having the first conductivity type on a side of the well region away from the substrate layer; forming a gate trench on a side of the epitaxial layer away from the substrate layer, wherein the gate trench contacts the well region and includes at least one arc-shaped segment; forming a gate in the gate trench; forming a dielectric isolation layer on a side of the gate trench away from the epitaxial layer; forming a source electrode on a side of the dielectric isolation layer away from the epitaxial layer, wherein the source electrode is in contact with the first region; forming a drain electrode on a side of the substrate layer away from the epitaxial layer; Wherein, forming a gate in the gate trench comprises: forming a gate oxide layer on a side of the epitaxial layer away from the substrate layer, the gate oxide layer covering a side of the epitaxial layer away from the substrate layer and the gate trench, and a third groove being provided on the side of the gate oxide layer away from the epitaxial layer, the third groove and the gate trench having the same morphology; A polysilicon layer is formed on a side of the gate oxide layer away from the epitaxial layer, and a fourth groove is formed on a side of the polysilicon layer away from the gate oxide layer, and the fourth groove and the gate trench have the same morphology; forming a second mask layer on a side of the polysilicon layer away from the gate oxide layer, wherein the second mask layer has a fifth groove on a side away from the polysilicon layer, and the fifth groove and the gate trench have the same morphology; Filling the fifth groove with a second photoresist; removing a portion of the second mask layer to form a sub-mask, wherein the sub-mask is located in the fourth groove; forming a sidewall spacer on at least one side of the sub-mask, wherein the sidewall spacer is located in the fourth groove; removing the sub-mask; Using the sidewall as a mask, a portion of the polysilicon layer is removed to form the gate, wherein the gate contacts the well region; The side walls are removed.

2. The method for manufacturing a SiC gate trench power device according to claim 1, wherein: The gate trench is formed on a side of the epitaxial layer away from the substrate layer, the gate trench is in contact with the well region and the gate trench includes at least one arc segment. forming a first mask layer on a side of the epitaxial layer away from the substrate layer; forming a first photoresist on a side of the first mask layer away from the epitaxial layer, wherein the first photoresist has a first groove on a side away from the first mask layer, and the first groove includes at least one arc segment; forming a second groove on a side of the first mask layer away from the epitaxial layer, wherein the second groove has the same morphology as the first groove; The gate trench is formed on a side of the epitaxial layer away from the substrate layer, and the gate trench and the second groove have the same morphology.

3. The method for manufacturing a SiC gate trench power device according to claim 2, wherein: A first photoresist is formed on a side of the first mask layer away from the epitaxial layer, wherein the first photoresist has a first groove on a side away from the first mask layer, wherein the first groove includes at least one arc segment. The first photoresist is formed by using a gradient transmittance photolithography technique or a weak exposure technique, and the first photoresist has a first groove on a side away from the first mask layer, and the first groove includes at least one arc segment; And / or, forming a second groove on a side of the first mask layer away from the epitaxial layer, wherein the second groove has the same morphology as the first groove comprises: forming the second groove by dry etching technology, wherein the second groove and the first groove have the same morphology; And / or, forming the gate trench on a side of the epitaxial layer away from the substrate layer, wherein the gate trench and the second groove have the same morphology comprises: The gate trench is formed by dry etching technology, and the gate trench and the second groove have the same morphology.

4. The method for manufacturing a SiC gate trench power device according to claim 1, wherein: Also includes: forming a third region of the second conductivity type at the bottom of the gate trench; sputtered carbon film; Passivation was performed with argon; After high temperature annealing, the carbon film is removed.

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