A Micro-LED Chip and Its Fabrication Method

Abstract

This invention discloses a Micro-LED chip and its fabrication method. The method includes: providing an epitaxial wafer; fabricating a transparent conductive layer on a P-type semiconductor layer; placing the epitaxial wafer with the transparent conductive layer in an annealing apparatus for annealing; etching the P-type semiconductor layer and the multiple quantum well layer to expose the surface of the N-type semiconductor layer to form a MESA mesa; fabricating an N-type electrode layer and a P-type electrode layer on the MESA mesa and the transparent conductive layer, respectively; fabricating a protective layer on the N-type electrode layer and the P-type electrode layer; grinding and polishing the protective layer, the N-type electrode layer, and the P-type electrode layer to change the thickness of the epitaxial wafer from an initial thickness to a target thickness; and fabricating an N-type pad layer connected to the N-type electrode layer and a P-type pad layer connected to the P-type electrode layer on the protective layer. This invention aims to solve the technical problem that in the prior art, Micro-LED chips can only rely on metal bonding, and the unevenness of the pad surface leads to low bonding yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a Micro-LED chip and its fabrication method. Background Technology

[0002] Conventional LED chips are die bonded using solder, but Micro-LED chips have very small pad areas, usually less than 10um, making it difficult to use solder for die bonding. Therefore, metal bonding or ACF film (anisotropic conductive film) is usually used for die bonding.

[0003] During soldering, the solder paste is fluid and can fill the unevenness of the chip pad surface. However, for Micro-LED chips, bonding can only be done by metal bonding (Au-Au, Au-In, Au-Cu, Cu-In, etc.). The unevenness of the pad surface will lead to a low yield during bonding. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a Micro-LED chip and its preparation method, which aims to solve the technical problem that Micro-LED chips in the prior art can only rely on metal bonding, and the unevenness of the pad surface will lead to low bonding yield.

[0005] A first aspect of the present invention is to provide a method for fabricating a Micro-LED chip, the method comprising:

[0006] An epitaxial wafer is provided, the epitaxial wafer including a substrate and an epitaxial layer, the epitaxial layer including an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer;

[0007] The epitaxial layer is etched to expose the surface of the substrate to form an isolation trench;

[0008] A transparent conductive layer is fabricated on the surface of the P-type semiconductor layer away from the multi-quantum-well layer;

[0009] The epitaxial wafer after the transparent conductive layer is fabricated is placed in an annealing equipment for annealing treatment;

[0010] The P-type semiconductor layer and the multiple quantum well layer are etched to expose the surface of the N-type semiconductor layer to form a MESA mesa.

[0011] An N-type electrode layer and a P-type electrode layer are respectively fabricated on the MESA mesa and the transparent conductive layer;

[0012] A protective layer is formed on the N-type electrode layer and the P-type electrode layer so that the protective layer covers the N-type electrode layer and the P-type electrode layer;

[0013] The protective layer, the N-type electrode layer, and the P-type electrode layer are ground and polished to change the thickness of the epitaxial wafer from an initial thickness to a target thickness.

[0014] An N-type pad layer connected to the N-type electrode layer and a P-type pad layer connected to the P-type electrode layer are formed on the protective layer.

[0015] According to one aspect of the above technical solution, the step of fabricating a transparent conductive layer on the surface of the P-type semiconductor layer away from the multi-quantum-well layer specifically includes:

[0016] A material for fabricating a transparent conductive layer is deposited on the P-type semiconductor layer to form an initial transparent conductive layer;

[0017] Photoresist is coated on the surface of the initial transparent conductive layer, and photolithography is performed on the initial transparent conductive layer to form a transparent conductive layer layer on the initial transparent conductive layer;

[0018] Using the transparent conductive layer as a barrier layer, the transparent conductive layer is immersed in a transparent conductive layer etching solution to remove the transparent conductive layer material outside the transparent conductive layer, thereby obtaining the target transparent conductive layer.

[0019] According to one aspect of the above technical solution, in the step of immersing the initial transparent conductive layer with a transparent conductive layer etching solution, the immersion time is 3 min to 15 min.

[0020] According to one aspect of the above technical solution, the material used to make the transparent conductive layer is any one of GIO, ZITO, ITO or other inorganic materials or organic materials with the same properties, such as silver nanowires. The transparency of the material is greater than 80%, and the resistivity is lower than that of the P-type semiconductor layer.

[0021] According to one aspect of the above technical solution, the step of placing the epitaxial wafer after the transparent conductive layer is fabricated in an annealing apparatus for annealing specifically includes:

[0022] The epitaxial wafer after the transparent conductive layer is fabricated is placed in an annealing equipment for annealing treatment, and the substrate and the transparent conductive layer are annealed.

[0023] The annealing temperature for the annealing process is 450℃-650℃.

[0024] According to one aspect of the above technical solution, the step of fabricating an N-type electrode layer and a P-type electrode layer on the MESA mesa and the transparent conductive layer respectively specifically includes:

[0025] A negative photoresist is coated on the surface of the epitaxial wafer after the MESA mesa and the transparent conductive layer are fabricated, followed by exposure and development;

[0026] Metal electrode layers were deposited on the surfaces of the MESA mesa and the transparent conductive layer using an electron beam evaporation process.

[0027] A lift-off process is used to remove part of the metal electrode material and photoresist to obtain an N-type electrode layer and a P-type electrode layer.

[0028] According to one aspect of the above technical solution, the thickness of both the N-type electrode layer and the P-type electrode layer is 1μm-3μm.

[0029] According to one aspect of the above technical solution, the protective layer includes a DBR structure reflective sublayer and an insulating layer stacked on the surfaces of the N-type electrode layer and the P-type electrode layer;

[0030] The DBR structure reflective layer is a single-layer structure of one of SiO2, Al2O3, and Ti3O5 or any stacked structure of multiple materials, and the thickness of the DBR structure reflective layer is 1μm-2μm.

[0031] The insulating layer is a single-layer structure of one of SiO2, Al2O3, and Ti3O5, and the thickness of the insulating layer is less than 2μm.

[0032] According to one aspect of the above technical solution, after grinding and polishing the protective layer, the N-type electrode layer and the P-type electrode layer, the thickness of the protective layer is 2μm-3μm.

[0033] A second aspect of the present invention is to provide a Micro-LED chip, wherein the Micro-LED chip is prepared by the preparation method described in the above technical solution.

[0034] Compared with existing technologies, the advantages of using the Micro-LED chip and its fabrication method shown in this invention are as follows:

[0035] After fabricating a protective layer on the surface of the N-type electrode layer and the P-type electrode layer, the protective layer includes a DBR structure reflective layer and an insulating layer. The protective layer is then ground and polished, replacing the existing photolithography process. The protective layer can fill the grooves and protrusions in the chip front-end process. Combined with the grinding and polishing process, the surface of the protective layer is flattened to facilitate the fabrication of a flatter metal pad layer. This makes the chip's pads flat, which is beneficial to improving the yield of the chip in mass transfer and subsequent bonding. Attached Figure Description

[0036] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0037] Figure 1 This is a schematic flowchart of a Micro-LED chip fabrication method according to an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the structure of a Micro-LED chip shown in an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of the protective layer in a Micro-LED chip according to an embodiment of the present invention;

[0040] Explanation of symbols in the attached drawings:

[0041] Substrate 10, N-type semiconductor layer 21, MESA mesa 210, multiple quantum well layer 22, P-type semiconductor layer 23, transparent conductive layer 30, P-type electrode layer 41, N-type electrode layer 42, protective layer 50, DBR structure reflective layer 51, insulating layer 52, P-type pad layer 61, N-type pad layer 62. Detailed Implementation

[0042] To make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Several embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be more thorough and complete.

[0043] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0045] A first aspect of the present invention provides a method for fabricating a Micro-LED chip, the method comprising steps S1-S9:

[0046] Step S1: Provide an epitaxial wafer, the epitaxial wafer including a substrate and an epitaxial layer, the epitaxial layer including an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer;

[0047] Step S2: Etch the epitaxial layer to expose the surface of the substrate to form an isolation trench;

[0048] Step S3: A transparent conductive layer is fabricated on the surface of the P-type semiconductor layer away from the multi-quantum-well layer;

[0049] Step S4: Place the epitaxial wafer after the transparent conductive layer is fabricated in an annealing apparatus for annealing treatment;

[0050] Step S5: Etch the P-type semiconductor layer and the multiple quantum well layer to expose the surface of the N-type semiconductor layer to form a MESA mesa.

[0051] Step S6: An N-type electrode layer and a P-type electrode layer are fabricated on the MESA mesa and the transparent conductive layer, respectively.

[0052] Step S7: A protective layer is formed on the N-type electrode layer and the P-type electrode layer so that the protective layer covers the N-type electrode layer and the P-type electrode layer;

[0053] Step S8: Grind and polish the protective layer, the N-type electrode layer and the P-type electrode layer to change the thickness of the epitaxial wafer from an initial thickness to a target thickness.

[0054] Step S9: On the protective layer, an N-type pad layer connected to the N-type electrode layer and a P-type pad layer connected to the P-type electrode layer are formed.

[0055] Furthermore, the step of fabricating a transparent conductive layer on the surface of the P-type semiconductor layer away from the multi-quantum-well layer specifically includes:

[0056] A material for fabricating a transparent conductive layer is deposited on the P-type semiconductor layer to form an initial transparent conductive layer;

[0057] Photoresist is coated on the surface of the initial transparent conductive layer, and photolithography is performed on the initial transparent conductive layer to form a transparent conductive layer layer on the initial transparent conductive layer;

[0058] Using the transparent conductive layer as a barrier layer, the transparent conductive layer is immersed in a transparent conductive layer etching solution to remove the transparent conductive layer material outside the transparent conductive layer, thereby obtaining the target transparent conductive layer.

[0059] Furthermore, in the step of immersing the initial transparent conductive layer with a transparent conductive layer etching solution, the immersion time is 3 min to 15 min.

[0060] Furthermore, the material used to fabricate the transparent conductive layer is any one of GIO, ZITO, ITO, or other inorganic materials or organic materials with the same properties, such as silver nanowires. The material has a transparency greater than 80% and a resistivity lower than that of the P-type semiconductor layer.

[0061] Furthermore, the step of placing the epitaxial wafer after the transparent conductive layer is fabricated into an annealing apparatus for annealing specifically includes:

[0062] The epitaxial wafer after the transparent conductive layer is fabricated is placed in an annealing equipment for annealing treatment, and the substrate and the transparent conductive layer are annealed.

[0063] The annealing temperature for the annealing process is 450℃-650℃.

[0064] Furthermore, the steps of fabricating N-type electrode layers and P-type electrode layers on the MESA mesa and the transparent conductive layer respectively specifically include:

[0065] A negative photoresist is coated on the surface of the epitaxial wafer after the MESA mesa and the transparent conductive layer are fabricated, followed by exposure and development;

[0066] Metal electrode layers were deposited on the surfaces of the MESA mesa and the transparent conductive layer using an electron beam evaporation process.

[0067] A lift-off process is used to remove part of the metal electrode material and photoresist to obtain an N-type electrode layer and a P-type electrode layer.

[0068] Furthermore, the thickness of both the N-type electrode layer and the P-type electrode layer is 1μm-3μm.

[0069] Furthermore, the protective layer includes a DBR structure reflective sublayer and an insulating layer stacked on the surfaces of the N-type electrode layer and the P-type electrode layer;

[0070] The DBR structure reflective layer is a single-layer structure of one of SiO2, Al2O3, and Ti3O5 or any stacked structure of multiple materials, and the thickness of the DBR structure reflective layer is 1μm-2μm.

[0071] The insulating layer is a single-layer structure of one of SiO2, Al2O3, and Ti3O5, and the thickness of the insulating layer is less than 2μm.

[0072] Furthermore, after grinding and polishing the protective layer, the N-type electrode layer, and the P-type electrode layer, the thickness of the protective layer is 2μm-3μm.

[0073] Please see Figure 2-3A second aspect of the present invention provides a Micro-LED chip, which is prepared by the preparation method described in the above technical solution.

[0074] Compared with existing technologies, the advantages of using the Micro-LED chip and its fabrication method shown in this invention are as follows:

[0075] After fabricating a protective layer on the surface of the N-type electrode layer and the P-type electrode layer, the protective layer includes a DBR structure reflective layer and an insulating layer. The protective layer is then ground and polished, replacing the existing photolithography process. The protective layer can fill the grooves and protrusions in the chip front-end process. Combined with the grinding and polishing process, the surface of the protective layer is flattened to facilitate the fabrication of a flatter metal pad layer. This makes the chip's pads flat, which is beneficial to improving the yield of the chip in mass transfer and subsequent bonding.

[0076] Example 1

[0077] Please see Figure 1 The first embodiment of the present invention provides a method for fabricating a Micro-LED chip. In this embodiment, the fabrication method includes steps S1-S9:

[0078] Step S1: Provide an epitaxial wafer, the epitaxial wafer including a substrate and an epitaxial layer, the epitaxial layer including an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer.

[0079] The substrate 10 is a Si substrate 10, and an epitaxial layer is stacked on the Si substrate 10. The N-type semiconductor layer 21, the multiple quantum well layer 22 and the P-type semiconductor layer 23 of the epitaxial layer are stacked sequentially on the Si substrate 10.

[0080] In some other feasible embodiments, the substrate 10 may also be a SiC substrate 10, a ZnO substrate 10, or a sapphire substrate 10.

[0081] Step S2: Etch the epitaxial layer to expose the surface of the substrate to form an isolation trench.

[0082] Specifically, etching the epitaxial wafer requires exposing the surface of the substrate 10 to form isolation trenches, also known as isolation channels, between multiple epitaxial layers.

[0083] In this embodiment, etching the epitaxial wafer actually involves etching the multi-quantum well layer 22 and the P-type semiconductor layer 23 stacked on the N-type semiconductor layer 21, thereby disconnecting the multi-quantum well layer 22 and the P-type semiconductor layer 23 to form the aforementioned isolation trench.

[0084] Specifically, an ISO layer is fabricated on top of the P-type semiconductor layer 23. The ISO layer is used as a mask for photoresist coating and photolithography. Then, the epitaxial layer is etched by ICP to form isolation trenches between chips.

[0085] Step S3: A transparent conductive layer is fabricated on the surface of the P-type semiconductor layer away from the multi-quantum-well layer.

[0086] In this embodiment, the step of fabricating the transparent conductive layer 30 specifically includes steps S31-S33:

[0087] Step S31: Deposit material for fabricating transparent conductive layer 30 on the P-type semiconductor layer 23 to form initial transparent conductive layer 30.

[0088] The material used to make the transparent conductive layer 30 is ITO material, namely indium tin oxide. After depositing the ITO material on the P-type semiconductor layer 23, an initial transparent conductive layer 30 is formed.

[0089] Step S32: Photoresist is coated on the surface of the initial transparent conductive layer 30, and photolithography is performed on the initial transparent conductive layer 30 to form a transparent conductive layer 30 layer on the initial transparent conductive layer 30.

[0090] After obtaining the initial transparent conductive layer 30, photoresist is coated on the surface of the initial transparent conductive layer 30, and photolithography is performed on the initial transparent conductive layer 30 to form a transparent conductive layer 30 layer on the initial transparent conductive layer 30.

[0091] Step S33: Using the transparent conductive layer 30 as a barrier layer, immerse the transparent conductive layer 30 in an etching solution to remove the transparent conductive layer 30 material outside the transparent conductive layer 30, thereby obtaining the target transparent conductive layer 30.

[0092] In this process, the transparent conductive layer 30 is used as a barrier layer. The transparent conductive layer 30 is immersed in the transparent conductive layer 30 etching solution to etch and remove the ITO material outside the transparent conductive layer 30, thereby obtaining the target transparent conductive layer 30, which is the final form of the transparent conductive layer 30 that participates in the later chip fabrication.

[0093] Specifically, when the initial transparent conductive layer 30 is immersed in the transparent conductive layer etching solution, the immersion time is 5 minutes.

[0094] It should be noted that the material used to make the transparent conductive layer 30 is required to have a transparency greater than 80% and be able to conduct electricity, and have a resistivity lower than that of the P-type semiconductor layer 23. Therefore, the material used to make the transparent conductive layer 30 shown in this embodiment is ITO material, which has high transparency, good conductivity, and a resistivity lower than that of the P-type semiconductor layer 23.

[0095] Step S4: Place the epitaxial wafer after the transparent conductive layer is fabricated in an annealing apparatus for annealing.

[0096] The transparent conductive layer 30 is annealed by placing the entire epitaxial wafer in an annealing apparatus, specifically in an annealing furnace, and maintaining the annealing temperature in the furnace at 500°C to anneal the substrate 10 and the transparent conductive layer 30 on the epitaxial wafer.

[0097] Step S5: Etch the P-type semiconductor layer and the multiple quantum well layer to expose the surface of the N-type semiconductor layer to form a MESA mesa.

[0098] In the process of etching the P-type semiconductor layer 23 and the multiple quantum well layer 22 to form the MESA mesa 210, a MESA layer is first fabricated on the P-type semiconductor layer 23. Using the MESA layer as a mask, photoresist is applied and photolithography is performed. The P-type semiconductor layer 23 and the multiple quantum well layer 22 of the epitaxial layer are etched, that is, part of the material of the P-type semiconductor layer 23 and the multiple quantum well layer 22 is removed to expose the surface of the N-type semiconductor layer 21, so as to obtain the MESA mesa 210, also known as the MESA step. Later, a metal electrode layer connected to the N-type semiconductor layer 21 is fabricated on the MESA mesa 210.

[0099] Step S6: An N-type electrode layer and a P-type electrode layer are fabricated on the MESA mesa and the transparent conductive layer, respectively.

[0100] In this embodiment, the steps of fabricating the N-type electrode layer 42 and the P-type electrode layer 41 on the ESA mesa and the transparent conductive layer 30 respectively specifically include steps S61-S63:

[0101] Step S61: Coat the surface of the epitaxial wafer on which the MESA mesa 210 and the transparent conductive layer 30 are fabricated with negative photoresist, and expose and develop it.

[0102] Step S62: Electron beam evaporation is used to deposit metal electrode layers on the surfaces of the MESA mesa 210 and the transparent conductive layer 30, respectively.

[0103] In step S63, a lift-off process is used to remove part of the metal electrode material and photoresist to obtain the N-type electrode layer 42 and the P-type electrode layer 41.

[0104] The thickness of both the N-type electrode layer 42 and the P-type electrode layer 41 is 2 μm.

[0105] Step S7: A protective layer is formed on the N-type electrode layer and the P-type electrode layer so that the protective layer covers the N-type electrode layer and the P-type electrode layer.

[0106] The protective layer 50 covering the N-type electrode layer 42 and the P-type electrode layer 41 includes a stacked DBR structure reflective sublayer and an insulating layer 52. The DBR structure reflective layer 51 is a stacked structure formed by overlapping SiO2 and Ti3O5, and the thickness of the DBR structure reflective layer 51 is 2μm; while the insulating layer 52 is a stacked structure formed by overlapping SiO2, Al2O3, and Ti3O5, and the thickness of the insulating layer 52 is less than 2μm, preferably 1.5μm in this embodiment.

[0107] Step S8: Grind and polish the protective layer, the N-type electrode layer and the P-type electrode layer to change the thickness of the epitaxial wafer from an initial thickness to a target thickness.

[0108] When grinding and polishing the protective layer 50, the N-type electrode layer 42 and the P-type electrode layer 41, the protective layer 50 is mainly ground and polished, while the N-type electrode layer 42 and the P-type electrode layer 41 encased in the protective layer 50 will be ground and polished at the same time. The first purpose of grinding and polishing is to reduce the thickness of the protective layer 50, keep the thickness of the protective layer 50 at 3μm, and control the total thickness of the chip.

[0109] The second purpose of grinding and polishing the protective layer 50, the N-type semiconductor layer 21 and the P-type semiconductor layer 23 is to improve the flatness of the protective layer 50, thereby improving the flatness of the pads, which can effectively improve the bonding yield of the chip to the target substrate.

[0110] Step S9: On the protective layer, an N-type pad layer connected to the N-type electrode layer and a P-type pad layer connected to the P-type electrode layer are formed.

[0111] Finally, after grinding and polishing the protective layer 50, the N-type electrode layer 42 and the P-type electrode layer 41, a metal pad layer is deposited on the surface of the protective layer 50, including an N-type pad layer 62 attached to the surface of the protective layer 50 and connected to the N-type electrode layer 42, and a P-type pad layer 61 attached to the surface of the protective layer 50 and connected to the P-type electrode layer 41, thus obtaining the Micro-LED chip.

[0112] Please see Figure 2-3 The Micro-LED chip prepared using the method shown in this embodiment includes:

[0113] Substrate 10, epitaxial layer disposed on substrate 10;

[0114] The N-type electrode layer 42 and the P-type electrode layer 41 are disposed on the epitaxial layer;

[0115] The protective layer 50 includes a DBR structure reflective layer 51 and an insulating layer 52, which are disposed on the surface of the epitaxial layer and cover the N-type electrode layer 42 and the P-type electrode layer 41.

[0116] And an N-type pad layer 62 and a P-type pad layer 61, wherein the N-type pad layer 62 is attached to the surface of the protective layer 50 and connected to the N-type electrode layer 42, and the P-type pad layer 61 is attached to the surface of the protective layer 50 and connected to the P-type electrode layer 41.

[0117] It should be noted that the protective layer 50, the N-type electrode layer 42, and the P-type electrode layer 41 are ground and polished, which can effectively improve the flatness of the protective layer 50, thereby improving the flatness of the pads and effectively improving the bonding yield of the chip to the target substrate.

[0118] Compared with existing technologies, the advantages of using the fabrication method shown in this embodiment to fabricate Micro-LED chips are as follows:

[0119] In this embodiment, after a protective layer 50 is fabricated on the surface of the N-type electrode layer 42 and the P-type electrode layer 41, the protective layer 50 includes a DBR structure reflective layer 51 and an insulating layer 52. The protective layer 50 is then ground and polished, replacing the existing photolithography process. The protective layer 50 can fill the grooves and protrusions in the chip front-end process. Combined with the grinding and polishing process, the surface of the protective layer 50 is flattened to facilitate the fabrication of a flatter metal pad layer. This makes the chip's pads flat, which is beneficial for improving the yield of the chip in mass transfer and subsequent bonding.

[0120] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0121] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a Micro-LED chip, characterized in that, The preparation method includes: An epitaxial wafer is provided, the epitaxial wafer including a substrate and an epitaxial layer, the epitaxial layer including an N-type semiconductor layer, a multiple quantum well layer and a P-type semiconductor layer; The epitaxial layer is etched to expose the surface of the substrate to form an isolation trench; A transparent conductive layer is fabricated on the surface of the P-type semiconductor layer away from the multi-quantum-well layer; The epitaxial wafer after the transparent conductive layer is fabricated is placed in an annealing equipment for annealing treatment; The P-type semiconductor layer and the multiple quantum well layer are etched to expose the surface of the N-type semiconductor layer to form a MESA mesa. An N-type electrode layer and a P-type electrode layer are respectively fabricated on the MESA mesa and the transparent conductive layer; A protective layer is formed on the N-type electrode layer and the P-type electrode layer so that the protective layer covers the N-type electrode layer and the P-type electrode layer; The protective layer, the N-type electrode layer, and the P-type electrode layer are ground and polished to change the thickness of the epitaxial wafer from an initial thickness to a target thickness. An N-type pad layer connected to the N-type electrode layer and a P-type pad layer connected to the P-type electrode layer are formed on the protective layer.

2. The method for fabricating a Micro-LED chip according to claim 1, characterized in that, The step of fabricating a transparent conductive layer on the surface of the P-type semiconductor layer away from the multi-quantum-well layer specifically includes: A material for fabricating a transparent conductive layer is deposited on the P-type semiconductor layer to form an initial transparent conductive layer; Photoresist is coated on the surface of the initial transparent conductive layer, and photolithography is performed on the initial transparent conductive layer to form a transparent conductive layer layer on the initial transparent conductive layer; Using the transparent conductive layer as a barrier layer, the transparent conductive layer is immersed in a transparent conductive layer etching solution to remove the transparent conductive layer material outside the transparent conductive layer, thereby obtaining the target transparent conductive layer.

3. The method for fabricating a Micro-LED chip according to claim 2, characterized in that, In the step of immersing the initial transparent conductive layer with a transparent conductive layer etching solution, the immersion time is 3 min to 15 min.

4. The method for fabricating a Micro-LED chip according to claim 2, characterized in that, The material used to fabricate the transparent conductive layer is any one of GIO, ZITO, ITO, or silver nanowire organic material, with a transparency greater than 80% and a resistivity lower than that of the P-type semiconductor layer.

5. The method for fabricating a Micro-LED chip according to claim 1, characterized in that, The step of placing the epitaxial wafer after the transparent conductive layer is fabricated into an annealing apparatus for annealing specifically includes: The epitaxial wafer after the transparent conductive layer is fabricated is placed in an annealing equipment for annealing treatment, and the substrate and the transparent conductive layer are annealed. The annealing temperature for the annealing process is 450℃-650℃.

6. The method for fabricating a Micro-LED chip according to claim 1, characterized in that, The steps of fabricating N-type electrode layers and P-type electrode layers on the MESA mesa and the transparent conductive layer respectively specifically include: A negative photoresist is coated on the surface of the epitaxial wafer after the MESA mesa and the transparent conductive layer are fabricated, followed by exposure and development; Metal electrode layers were deposited on the surfaces of the MESA mesa and the transparent conductive layer using an electron beam evaporation process. A partial stripping process is used to remove the metal electrode material and photoresist to obtain an N-type electrode layer and a P-type electrode layer.

7. The method for fabricating a Micro-LED chip according to claim 1, characterized in that, The thickness of both the N-type electrode layer and the P-type electrode layer is 1μm-3μm.

8. The method for fabricating a Micro-LED chip according to claim 1, characterized in that, The protective layer includes a DBR structure reflective layer and an insulating layer stacked on the surfaces of the N-type electrode layer and the P-type electrode layer; The DBR structure reflective layer is a stacked structure of any combination of SiO2, Al2O3, and Ti3O5, and the thickness of the DBR structure reflective layer is 1μm-2μm. The insulating layer is a single-layer structure of one of SiO2, Al2O3, and Ti3O5, and the thickness of the insulating layer is less than 2μm.

9. The method for fabricating a Micro-LED chip according to any one of claims 1-8, characterized in that, After grinding and polishing the protective layer, the N-type electrode layer and the P-type electrode layer, the thickness of the protective layer is 2μm-3μm.

10. A Micro-LED chip, characterized in that, The Micro-LED chip is prepared by the preparation method according to any one of claims 1-9.

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