A fast shutdown circuit based on output instantaneous power-off load switch

Abstract

The invention discloses a fast shut-off circuit based on an output instantaneous power-off load switch, comprising: a fast discharge module, a power-off detection module and an N-type power tube; the N-type power tube MN1 is used for load current, and transmits the current to an output signal VOUT; when the output of the N-type power tube is powered off, the power-off detection module is used to quickly detect the power-off state of the output signal VOUT, and generate a logic signal to output to the fast discharge module; the fast discharge module receives the logic signal of the power-off detection module, and quickly discharges and shuts off the gate terminal potential of the N-type power tube, thereby reducing the instantaneous current transmitted to the output signal VOUT. The invention can quickly shut down the N-type power tube when the output signal VOUT is powered off or short-circuited, so that the N-type power tube will not generate excessive instantaneous current to burn the circuit, and the invention has a fast response speed, basically consumes no static power consumption, and has a small area, and has a good effect of suppressing instantaneous current.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuits and semiconductor integrated circuits, and in particular to a fast shut-down circuit based on an output instantaneous power-off load switch. Background Art

[0002] Load switches are widely used in various systems that consume large amounts of power in standby mode or need to control power sequencing, such as mobile phones, tablet computers and other consumer electronics and automotive systems, due to their advantages of space saving, high integration and high efficiency. For load switches, low on-resistance is a significant feature, and when the output loses power instantly, even with functional modules such as current limiting protection, it is not enough to respond to such a fast process. Therefore, this part of the voltage difference will inevitably act on the low on-resistance, generating a very large current and burning circuit components. Therefore, it is particularly important to eliminate the instantaneous large current, so as to protect the circuit and increase the life of the chip.

[0003] The Chinese patent with publication number CN106209041A proposes an overcurrent protection circuit. For a load switch with low on-resistance, an NMOS tube is usually sampled as a power tube, and a charge pump is used to raise the gate terminal potential of the power tube. The width and length of the power tube are relatively large to ensure low on-resistance. When the output end is instantly powered off or short-circuited, the circuit has no time to respond, and there is a large parasitic capacitance at the gate end of the power tube. The gate terminal potential remains unchanged, and the source terminal potential drops instantly, that is, a large current is generated. After the gate terminal potential of the power tube drops, the current can return to normal. At this time, the time that has passed is enough to burn out the device.

[0004] The idea of ​​the traditional protection circuit is to sample the output current or voltage signal and compare it with the set current signal or voltage signal through a comparator, and use the output result to perform open-loop control on the power tube, or use an op amp to perform closed-loop control on the power tube. For example, the Chinese patent with publication number CN105577152A proposes an open-loop control overcurrent protection circuit idea. Figure 1As shown, the current on the power tube MN1 is sampled by the power tube MN2 in proportion, and the current flows through the resistor R1 to form a voltage drop. When the voltage drop is greater than the product of the set current source 104 current IB and the resistor R2, the comparator 105 outputs a logic low. After three inversion logics, the output is instantly powered off to a high level. At this time, the discharge tube MN4 is turned on, and the gate terminal potential of the power tube MN1 is discharged through the discharge tube MN4 to reduce the output current. This structure has two disadvantages. First, the comparison response time of the comparator is relatively demanding, requiring a large static power consumption. Second, the discharge speed of the gate terminal potential of the power tube MN1 is relatively high, and the device area is large. The comparison response time of the comparator and the discharge time of the gate terminal potential of the power tube MN1 are not easy to reduce. Therefore, when the output is instantly powered off, it is necessary to wait for the comparator 105 to respond. After the comparator 105 responds, the gate terminal of the power tube MN1 begins to discharge. At this time, a long time has passed, and the power tube MN1 will still generate a large current and continue for a period of time, and there is still a risk of burning the circuit. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a fast shutdown circuit based on an instantaneous power-off load switch, which can quickly shut down the N-type power tube when the output signal VOUT is instantly powered off or instantly short-circuited, so that the N-type power tube will not generate excessive instantaneous current and thus burn the circuit. In addition, the fast shutdown circuit of the present invention has a faster response speed, basically consumes no static power consumption, has a small area, and has a good effect in suppressing instantaneous current.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solutions: a fast shutdown circuit based on an output instantaneous power-off load switch, comprising: a fast discharge module, a power-off detection module and an N-type power tube MN1;

[0007] The N-type power tube MN1 is used for load current and transmits the current to the output signal VOUT;

[0008] When the output of the N-type power tube MN1 loses power, the power-off detection module is used to quickly detect the power-off state of the output signal VOUT and generate a logic signal to output to the fast discharge module;

[0009] The fast discharge module receives the logic signal from the power-off detection module, quickly discharges the gate terminal potential of the N-type power tube MN1 and turns it off, thereby reducing the instantaneous current transmitted to the output signal VOUT.

[0010] Furthermore, the power-off detection module includes: a power-off sampling module and a logic trigger module, wherein the power-off sampling module is used to sample the power-off state of the output signal VOUT; the logic trigger module converts the power-off state sampled by the power-off sampling module into a logic signal output for controlling the fast discharge module.

[0011] Further, the power-off sampling module includes: a first capacitor C1, a first current source, a second current source, a first P-type current mirror MP1, a second P-type current mirror MP2, an inverter and a D flip-flop, wherein the positive electrode of the first current source is respectively connected to the gate of the first P-type current mirror MP1, the drain of the first P-type current mirror MP1, the gate of the second P-type current mirror MP2, and the upper plate of the first capacitor C1, the lower plate of the first capacitor C1 is connected to the output signal VOUT, the source of the first P-type current mirror MP1 and the source of the second P-type current mirror MP2 are both connected to the power supply voltage VIN, the drain of the second P-type current mirror MP2 is respectively connected to the positive electrode of the second current source, the D terminal of the D flip-flop, and the input terminal of the inverter, the output terminal of the inverter is connected to the CLK terminal of the D flip-flop, the negative electrode of the first current source and the negative electrode of the second current source are both grounded, and the inverting output terminal of the D flip-flop is connected to the ground. Connect with logic trigger module.

[0012] Furthermore, the logic trigger module includes: a first N-type switch tube MN5, a first P-type switch tube MP3, a third current source, a second capacitor C2 and an NOR gate, the source of the first P-type switch tube MP3 is connected to the negative electrode of the third current source, the positive electrode of the third current source is connected to the power supply voltage VIN, the drain of the first P-type switch tube MP3, the drain of the first N-type switch tube MN5, and the upper plate of the second capacitor C2 are all connected to the first input end of the NOR gate, the source of the first N-type switch tube MN5 and the lower plate of the second capacitor C2 are all grounded, and the output end of the NOR gate is connected to the fast discharge module.

[0013] Furthermore, the gate of the first P-type switch tube MP3, the gate of the first N-type switch tube MN5, and the second input terminal of the NOR gate are all connected to the inverting output terminal of the D trigger. connect.

[0014] Furthermore, the fast discharge module includes: a fourth current source, a first N-type field effect transistor MN6, a second N-type field effect transistor MN7, a first P-type field effect transistor MP4 and a second P-type field effect transistor MP5, the positive electrode of the fourth current source is connected to the source of the first N-type field effect transistor MN6, the drain of the first N-type field effect transistor MN6 is respectively connected to the gate of the first P-type field effect transistor MP4 and the gate of the second P-type field effect transistor MP5, the source of the first P-type field effect transistor MP4 is connected to the source of the second P-type field effect transistor MP5, and the drain of the second P-type field effect transistor MP5 is connected to the output VOUT; the source of the second N-type field effect transistor MN7 and the negative electrode of the fourth current source are both grounded.

[0015] Furthermore, the drain of the first P-type field effect transistor MP4 and the drain of the second N-type field effect transistor MN7 are both connected to the gate of the N-type power transistor MN1.

[0016] Furthermore, the gate of the first N-type field effect transistor MN6 and the gate of the second N-type field effect transistor MN7 are both connected to the output end of the NOR gate.

[0017] Compared with the prior art, the present invention has the following beneficial effects: the power-off detection module of the fast shutdown circuit of the instantaneous power-off load switch of the present invention samples the output signal VOUT through the first capacitor, avoids the use of a large-area operational amplifier, and only requires a small current to achieve fast sampling of the output power-off signal. Compared with the traditional structure, in order to speed up the sampling and triggering speed, a larger static power consumption is required. The present invention realizes the output instantaneous power-off fast shutdown function while increasing the smaller static power consumption and chip area; at the same time, the present invention quickly converts the voltage signal collected by the first capacitor into a current signal through the P-type current mirror in the power-off sampling module, and generates a logic signal through the logic trigger module, so that the fast discharge module can discharge the gate potential of the N-type power tube to the ground potential, and at the same time, the gate of the gate of the N-type power tube is connected to the source through the current path, so as to speed up the discharge of its gate potential, thereby suppressing the instantaneous large current. Compared with the traditional structure, the circuit response speed is faster and the suppression effect of the instantaneous large current is more significant. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of a conventional fast shut-off circuit suitable for a load switch;

[0019] Figure 2 The schematic diagram of the fast shutdown circuit of the instantaneous power-off load switch of the present invention is as follows;

[0020] Figure 3 This is a circuit diagram of a power failure detection module in the present invention;

[0021] Figure 4 This is a circuit diagram of the fast discharge module in the present invention. DETAILED DESCRIPTION

[0022] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0023] like Figure 2The present invention is a schematic diagram of a fast shutdown circuit based on an instantaneous power-off load switch, the fast shutdown circuit comprising: a fast discharge module 201, a power-off detection module 202, an N-type power tube MN1, a load resistor Rload and a load capacitor Cload, the drain of the N-type power tube MN1 is connected to the power supply voltage VIN, the gate of the N-type power tube MN1 is connected to the output end of the fast discharge module 201, the source of the N-type power tube MN1 is respectively connected to the input end of the power-off detection module 202, the fast discharge module 201, one end of the load resistor Rload, one end of the load capacitor Cload, and the output signal VOUT, the other end of the load resistor Rload and the other end of the load capacitor Cload are both grounded, and the output end of the power-off detection module 202 is connected to the input end of the fast discharge module 201. In the present invention, the load resistor Rload and the load capacitor Cload are external load devices, and the N-type power tube MN1 is used for load current, and transmits the current to the output signal VOUT; when the output of the N-type power tube MN1 is powered off, the power-off detection module 202 is used to quickly detect the power-off state of the output signal VOUT, and generate a logic signal to output to the fast discharge module 201; the fast discharge module 201 receives the logic signal of the power-off detection module 202, and quickly discharges and shuts off the gate terminal potential of the N-type power tube MN1, thereby reducing the instantaneous current transmitted to the output signal VOUT. The present invention can reduce the large current caused by the instantaneous power-off of the output signal VOUT when the output VOUT is instantly powered off or short-circuited, so that the N-type power tube MN1 will not generate excessive instantaneous current to burn the circuit, and the fast shutdown circuit of the present invention has a faster response speed, basically consumes no static power consumption, has a small area, and has a better effect of suppressing instantaneous current.

[0024] like Figure 3 In the present invention, the power-off detection module 202 includes: a power-off sampling module 307 and a logic trigger module 308. The power-off sampling module 307 is used to sample the power-off state of the output signal VOUT; the logic trigger module 308 converts the power-off state sampled by the power-off sampling module 307 into a logic signal output, which is used to control the fast discharge module 201 to quickly discharge and shut down the gate terminal potential of the N-type power tube MN1 to suppress the instantaneous current.

[0025] The power-off sampling module 307 of the present invention includes: a first capacitor C1, a first current source 301, a second current source 302, a first P-type current mirror MP1, a second P-type current mirror MP2, an inverter 303 and a D trigger 304, wherein the positive electrode of the first current source 301 is respectively connected to the gate of the first P-type current mirror MP1, the drain of the first P-type current mirror MP1, the gate of the second P-type current mirror MP2, and the upper plate of the first capacitor C1, the lower plate of the first capacitor C1 is connected to the output signal VOUT, the source of the first P-type current mirror MP1 and the source of the second P-type current mirror MP2 are both connected to the power supply voltage VIN, and the drain of the second P-type current mirror MP2 is respectively connected to the second current The positive electrode of the first current source 302, the D terminal of the D flip-flop 304, and the input terminal of the inverter 303 are connected, and the output terminal of the inverter 303 is connected to the CLK terminal of the D flip-flop 304. The output terminal of the inverter 303 can output a level signal opposite to the input terminal of the inverter 303. Therefore, the inverter 303 can make the CLK terminal of the D flip-flop 304 receive a signal that jumps from a high level to a low level when the output signal VOUT is instantly powered off, thereby triggering the D flip-flop 304. At the same time, the delay of the inverter 303 can ensure the establishment time of the D flip-flop 304; the negative electrode of the first current source 301 and the negative electrode of the second current source 302 are both grounded, and the inverting output terminal of the D flip-flop 304 The first current source 301 provides a bias for the first P-type current mirror MP1, so that the first P-type current mirror MP1 maintains a weak on state when the output signal VOUT is not instantly powered off or short-circuited, and this state is not enough to make the pull-up current of the second P-type current mirror MP2 greater than the pull-down current of the second current source 302. In addition, the D flip-flop 304 in the present invention can be triggered when the falling edge of the clock at the CLK terminal comes, sample the signal at the D terminal, and transmit the D terminal signal to the in-phase output terminal Q and the inverting output terminal Q of the D flip-flop 304. Inverting output terminal Output TRIG signal. The present invention utilizes the characteristic that the voltage across the capacitor cannot change suddenly to sample the output signal VOUT, and samples the instantaneous fluctuation of the output signal VOUT through the first capacitor C1 in the power-off sampling module 307, avoiding the use of a large-area operational amplifier while only requiring a small current to achieve fast sampling of the output power-off signal. Compared with the traditional structure, which requires a larger static power consumption in order to speed up the sampling and triggering speed, the present invention realizes the output instantaneous power-off fast shutdown function while increasing the smaller static power consumption and chip area. The voltage signal collected by the first capacitor C1 is quickly converted into a current signal through the first P-type current mirror MP1 or the second P-type current mirror MP2. In the present invention, the first P-type current mirror MP1 and the second P-type current mirror MP2 can be a common-source and common-gate current mirror structure. The ratio of the number of the first P-type current mirror MP1 and the second P-type current mirror MP2 is 1:n, wherein n is an integer greater than 1. The first current source 301 provides a bias current for the first P-type current mirror MP1. By adjusting the number n of the second P-type current mirror MP2, it is ensured that when the output VOUT is powered off, the current generated by the decrease in the gate potential of the second P-type current mirror MP2 can be greater than the current generated by the second current source 302, thereby ensuring smooth sampling of the power-off signal of the output VOUT.

[0026] The logic trigger module 308 in the present invention includes: a first N-type switch tube MN5, a first P-type switch tube MP3, a third current source 305, a second capacitor C2 and a NOR gate 306. The source of the first P-type switch tube MP3 is connected to the negative electrode of the third current source 305, the positive electrode of the third current source 305 is connected to the power supply voltage VIN, the drain of the first P-type switch tube MP3, the drain of the first N-type switch tube MN5, and the upper plate of the second capacitor C2 are all connected to the first input end of the NOR gate 306, the source of the first N-type switch tube MN5 and the lower plate of the second capacitor C2 are all grounded, and the output end of the NOR gate 306 is connected to the fast discharge module 201. The gate of the first P-type switch tube MP3, the gate of the first N-type switch tube MN5, and the second input end of the NOR gate 306 are all connected to the inverting output end of the D trigger 304. The first P-type switch tube MP3 can be turned on when the output signal VOUT is powered off instantly due to the TRIG signal becoming a low level. At this time, the third current source 305 can inject current into the second capacitor C2 through the turned-on first P-type switch tube MP3 to charge it, thereby controlling the output level SD duration of the NOR gate 306. Specifically, when the output signal VOUT is powered off instantly, the TRIG signal at the second input end of the NOR gate 306 is a low level, and the first input end is controlled by the second capacitor C2. Since the charging of the second capacitor C2 takes time, This is low level for a period of time when the output signal VOUT is powered off instantly, and the NOR gate 306 outputs a high level, which is used to control the operation of the fast discharge module 201 and quickly turn off the N-type power tube MN1; when the second capacitor C2 is charged, the second input terminal of the NOR gate 306 is high level, and the output is low level at this time, ending the fast shutdown process; at the same time, the first N-type switch tube MN5 can be turned off when the output signal VOUT is powered off instantly because the TRIG signal becomes a low level, and the upper plate of the second capacitor C2 will not discharge to the ground through the first N-type switch tube MN5 at this time. When the output signal VOUT is not powered off, the TRIG signal is high level, the first N-type switch tube MN5 is turned on, and the second capacitor C2 is discharged through the first N-type switch tube MN5.

[0027] The fast discharge module 201 in the present invention includes: a fourth current source 401, a first N-type field effect transistor MN6, a second N-type field effect transistor MN7, a first P-type field effect transistor MP4 and a second P-type field effect transistor MP5. The positive electrode of the fourth current source 401 is connected to the source of the first N-type field effect transistor MN6, the drain of the first N-type field effect transistor MN6 is respectively connected to the gate of the first P-type field effect transistor MP4 and the gate of the second P-type field effect transistor MP5, the source of the first P-type field effect transistor MP4 is connected to the source of the second P-type field effect transistor MP5, and the drain of the second P-type field effect transistor MP5 is connected to the output VOUT; the source of the second N-type field effect transistor MN7 and the negative electrode of the fourth current source 401 are both grounded. The drain of the first P-type field effect transistor MP4 and the drain of the second N-type field effect transistor MN7 are both connected to the gate of the N-type power transistor MN1. The gate of the first N-type field effect transistor MN6 and the gate of the second N-type field effect transistor MN7 are both connected to the output end of the NOR gate 306 . When the output signal VOUT loses power quickly, at this time, the SD signal 203 output by the power-off detection module 202 is at a high level, the first N-type field effect transistor MN6 and the second N-type field effect transistor MN7 are turned on because the gate SD signal 203 is at a high level, the second N-type field effect transistor MN7 provides a path to the ground for the gate of the N-type power tube MN1, and discharges the gate potential of the N-type power tube MN1 to the ground potential, the first N-type field effect transistor MN6 is turned on, and at this time the fourth current source 401 pulls down the gate potential of the first P-type field effect transistor MP4 and the second P-type field effect transistor MP5 to the ground potential through the first N-type field effect transistor MN6, the first P-type field effect transistor MP4 and the second P-type field effect transistor MP5 are turned on, the first P-type field effect transistor MP4 and the second P-type field effect transistor MP5 provide a path for the gate of the N-type power tube MN1 to the output signal VOUT, and can quickly pull the gate of the N-type power tube MN1 and the output signal VOUT to the same potential, accelerate the shutdown of the N-type power tube MN1, and suppress the generation of instantaneous large current.

[0028] The specific working process of the fast shutdown circuit of the instantaneous power-off load switch of the present invention is as follows: the first current source 301 provides a bias for the first P-type current mirror MP1, so that the first P-type current mirror MP1 maintains a weak conduction state when the output signal VOUT is not instantly powered off or instantly short-circuited, and this state is not enough to make the pull-up current of the second P-type current mirror MP2 greater than the pull-down current of the second current source 302. The bias provided by the first current source 301 for the first P-type current mirror MP1 can improve the conduction degree and speed up the conduction speed of the first P-type current mirror MP1 when VOUT is instantly powered off or instantly short-circuited. When the output VOUT is instantly powered off or instantly short-circuited, since the voltage across the capacitor cannot suddenly change, the upper plate of the first capacitor C1 loses power due to the instantaneous power off of the lower plate. At this time, the conduction degree of the first P-type current mirror MP1 is improved, so that the pull-up current of the second P-type current mirror MP2 is greater than the pull-down current of the second current source 302, and a high-level signal is output. When the input signal of the inverter 303 is high level, the inverter 303 outputs a low level signal. The level flip at this time causes the CLK terminal of the D flip-flop 304 to receive the logic level flipped downward, the D flip-flop 304 is triggered, and the D terminal of the D flip-flop 304 samples the high level signal. When the output signal VOUT is at a low level, the first P-type switch tube MP3 can be turned on due to the TRIG signal becoming a low level. At this time, the third current source 305 can inject current into the second capacitor C2 through the turned-on first P-type switch tube MP3 to charge it and control the duration of the output level SD. The first N-type switch tube MN5 is turned off due to the TRIG signal becoming a low level. At this time, the upper plate of the second capacitor C2 will not discharge to the ground through the first N-type switch tube MN5; when the output signal VOUT is powered off instantly, the TRIG signal at the second input end of the NOR gate 306 is at a low level, and the first input end is controlled by the second capacitor C2. Since the charging of the second capacitor C2 takes time, it is at a low level for a period of time when the output signal VOUT is powered off instantly. The NOR gate 306 outputs a high level. At this time, the logic trigger module 308 outputs a high level, and the fast discharge module 201 starts to work. The first N-type field effect transistor MN6 is turned on due to the high level output by the logic trigger module 308, and the fourth current source 401 pulls down the gate potentials of the first P-type field effect transistor MP4 and the second P-type field effect transistor MP5 through the first N-type field effect transistor MN6, so that the gate of the N-type power tube MN1 and the output VOUT are quickly pulled to the same potential, and at the same time, the second N-type field effect transistor MN7 is turned on to pull down the gate potential of the N-type power tube MN1 to 0. At this time, the gate and output VOUT of the N-type power tube MN1 are both pulled down to 0, further improving the effect of suppressing instantaneous large current.

[0029] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A fast shutdown circuit based on an output instantaneous power-off load switch, characterized in that: include: A fast discharge module (201), a power failure detection module (202) and an N-type power tube MN1; The N-type power tube MN1 is used for load current and transmits the current to the output signal VOUT; When the output of the N-type power tube MN1 loses power, the power-off detection module (202) is used to quickly detect the power-off state of the output signal VOUT and generate a logic signal to output to the fast discharge module (201); The fast discharge module (201) receives the logic signal of the power-off detection module (202), quickly discharges the gate terminal potential of the N-type power tube MN1 and turns it off, thereby reducing the instantaneous current transmitted to the output signal VOUT; The power-off detection module (202) comprises: a power-off sampling module (307) and a logic trigger module (308), wherein the power-off sampling module (307) is used to sample the power-off state of the output signal VOUT; and the logic trigger module (308) converts the power-off state sampled by the power-off sampling module (307) into a logic signal output for controlling the fast discharge module (201); The power-off sampling module (307) comprises: a first capacitor C1, a first current source (301), a second current source (302), a first P-type current mirror MP1, a second P-type current mirror MP2, an inverter (303) and a D trigger (304), wherein the positive electrode of the first current source (301) is respectively connected to the gate of the first P-type current mirror MP1, the drain of the first P-type current mirror MP1, the gate of the second P-type current mirror MP2 and the upper plate of the first capacitor C1, and the lower plate of the first capacitor C1 is connected to the output signal VOUT. The source of the first P-type current mirror MP1 and the source of the second P-type current mirror MP2 are both connected to the power supply voltage VIN; the drain of the second P-type current mirror MP2 is respectively connected to the positive electrode of the second current source (302), the D terminal of the D flip-flop (304), and the input terminal of the inverter (303); the output terminal of the inverter (303) is connected to the CLK terminal of the D flip-flop (304); the negative electrode of the first current source (301) and the negative electrode of the second current source (302) are both grounded; the inverting output terminal of the D flip-flop (304) is connected to the ground. Connected to a logic trigger module (308); The logic trigger module (308) comprises: a first N-type switch tube MN5, a first P-type switch tube MP3, a third current source (305), a second capacitor C2 and a NOR gate (306), wherein the source of the first P-type switch tube MP3 is connected to the negative electrode of the third current source (305), the positive electrode of the third current source (305) is connected to the power supply voltage VIN, the drain of the first P-type switch tube MP3, the drain of the first N-type switch tube MN5 and the upper plate of the second capacitor C2 are all connected to the first input end of the NOR gate (306), the source of the first N-type switch tube MN5 and the lower plate of the second capacitor C2 are all grounded, and the output end of the NOR gate (306) is connected to the fast discharge module (201); The gate of the first P-type switch tube MP3, the gate of the first N-type switch tube MN5, and the second input terminal of the NOR gate (306) are all connected to the inverting output terminal of the D flip-flop (304). connect; The fast discharge module (201) comprises: a fourth current source (401), a first N-type field effect transistor MN6, a second N-type field effect transistor MN7, a first P-type field effect transistor MP4 and a second P-type field effect transistor MP5; the positive electrode of the fourth current source (401) is connected to the source of the first N-type field effect transistor MN6; the drain of the first N-type field effect transistor MN6 is respectively connected to the gate of the first P-type field effect transistor MP4 and the gate of the second P-type field effect transistor MP5; the source of the first P-type field effect transistor MP4 is connected to the source of the second P-type field effect transistor MP5; the drain of the second P-type field effect transistor MP5 is connected to the output VOUT; the source of the second N-type field effect transistor MN7 and the negative electrode of the fourth current source (401) are both grounded.

2. A fast shutdown circuit based on an output instantaneous power-off load switch according to claim 1, characterized in that: The drain of the first P-type field effect transistor MP4 and the drain of the second N-type field effect transistor MN7 are both connected to the gate of the N-type power transistor MN1.

3. A fast shutdown circuit based on an output instantaneous power-off load switch according to claim 2, characterized in that: The gate of the first N-type field effect transistor MN6 and the gate of the second N-type field effect transistor MN7 are both connected to the output end of the NOR gate (306).

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