A nonlinear system correction method based on nonlinear equalization filter

Abstract

The invention relates to a nonlinear system correction method based on a nonlinear equalization filter. The method comprises the following steps: constructing a dual-tone sinusoidal baseband signal based on an FPGA, transmitting the dual-tone sinusoidal baseband signal as a training signal through an antenna after passing through a nonlinear transmission system; receiving the transmitted signal through an antenna, and transforming it into a baseband signal with nonlinear characteristics through a nonlinear receiving system; performing single-point FFT transformation on both the baseband signal with nonlinear characteristics and the dual-tone sinusoidal baseband signal constructed by the FPGA, and inputting the transformed signal into an ARM end, and obtaining an optimal filter coefficient vector and a corresponding combination of multiple delay items through calculation by the ARM; constructing a nonlinear signal by using a nonlinear equalization filter according to the optimal filter coefficient vector and the corresponding combination of multiple delay items of the dual-tone sinusoidal baseband signal constructed by the FPGA, and obtaining a signal after the nonlinear characteristics are corrected by subtracting the constructed nonlinear signal from the baseband signal with nonlinear characteristics.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a nonlinear system correction method based on a nonlinear equalization filter. Background Art

[0002] Almost all natural or artificial systems exhibit some degree of nonlinear phenomena. Such systems whose input and output do not satisfy a linear relationship are called nonlinear systems. Typical examples include fluid systems, optical systems, radio frequency transceiver systems, analog circuit systems, etc. The concept of signal is used to represent the mathematical change relationship of one or more measurable physical parameters in a nonlinear system, such as pressure, light intensity, voltage, etc. Then the output signal of a nonlinear system will contain various nonlinear components, which can be further decomposed into distortion items such as harmonics, intermodulation, spurious, quantization noise, etc. The existence of these nonlinear distortions will significantly limit the ability of the signal processing system to separate the desired linear signal from the output signal, thereby limiting the overall performance of the system.

[0003] Analog-to-digital converters, power amplifiers and other devices widely used in the communication field can easily cause nonlinear distortion of communication signals, and the existence of these nonlinear distortions will significantly affect the performance of communication equipment. Nonlinear signals are generated after the input signal passes through a nonlinear system, which is related to both the characteristics of the input signal and the nonlinear response of the system.

[0004] Nonlinear correction algorithms inevitably consume a large amount of multiplication resources, which limits their use and makes them incapable of being embedded in other large-scale signal processing algorithms. Summary of the invention

[0005] In view of the above analysis, an embodiment of the present invention aims to provide a nonlinear system correction method based on a nonlinear equalization filter, so as to solve the problem that analog-to-digital converters, power amplifiers and other devices widely used in the existing communication field can easily cause nonlinear distortion of communication signals, and the existence of these nonlinear distortions will significantly affect the performance of communication equipment.

[0006] The embodiment of the present invention provides a nonlinear system correction method based on a nonlinear equalization filter. A two-tone sinusoidal baseband signal is constructed based on an FPGA. The two-tone sinusoidal baseband signal is used as a training signal and then transmitted through an antenna after passing through a nonlinear transmission system. The transmitted signal is then received by an antenna and transformed into a baseband signal with nonlinear characteristics through a nonlinear receiving system. The baseband signal with nonlinear characteristics and the two-tone sinusoidal baseband signal constructed by the FPGA are both subjected to single-point FFT transformation and then input into an ARM end, and an optimal filter coefficient vector and a corresponding combination of multiple delay items are calculated by the ARM. The FPGA constructs a nonlinear signal using a nonlinear equalization filter according to the filter coefficient vector and the corresponding combination of multiple delay items of the two-tone sinusoidal baseband signal constructed by the FPGA, and the constructed nonlinear signal is subtracted from the baseband signal with nonlinear characteristics to obtain a signal after the nonlinear characteristics are corrected.

[0007] Furthermore, the baseband signal with nonlinear characteristics and the two-tone sinusoidal baseband signal constructed by FPGA are both subjected to single-point FFT transformation, including: constructing the transformation function The expression is:

[0008] ,

[0009] Where N is the number of points of FFT transformation, n=0,1,2,...N-1;

[0010] At frequency Single-point FFT transform at The formula is:

[0011] ,

[0012] The frequency built with FPGA is , Two-tone sinusoidal baseband signal or baseband signal with nonlinear characteristics, for , , , Four frequencies.

[0013] Further, the FPGA constructs a nonlinear signal using a nonlinear equalization filter according to the filter coefficient vector and the corresponding multiple delay items of the dual-tone sinusoidal baseband signal constructed by the FPGA, including:

[0014] For two-tone sinusoidal baseband signal According to each delay item combination Separately , , The delay of each delay item combination is obtained. ; Before passing through the nonlinear equalization filter, each delayed signal needs to be combined with the third delayed signal Take the conjugate and combine it with the other two signals , Multiply them together to get the product result corresponding to each delay item combination ;in, is the delay item combination calculated by ARM, , , The delay range is an integer from 0 to 15, i=0, 1, 2, ..., (M-1), M is the order of the nonlinear equalization filter, and the number of the delay term combinations is the same as the order of the nonlinear equalization filter;

[0015] The product result corresponding to each delay item combination is The corresponding coefficients in the M-order filter Multiplication operations are performed respectively, and M multiplication operation results are summed to obtain the constructed nonlinear signal.

[0016] Further, the FPGA constructs a nonlinear signal using a nonlinear equalization filter according to the filter coefficient vector and the corresponding multiple delay items of the dual-tone sinusoidal baseband signal constructed by the FPGA, and further includes:

[0017] The product result corresponding to each delay item combination is The corresponding coefficients in the M-order filter Before multiplication, the coefficients of the M-order filter are The enlargement and rounding process is performed to obtain m-bit binary data; after the multiplication operation is performed, the result is correspondingly reduced.

[0018] Furthermore, the coefficients of the M-order filter are Performing a magnification and rounding process to obtain m-bit data includes: before the magnification and rounding process, firstly converting the coefficients of the filter It is represented as a binary integer part and a binary decimal part, connected by a decimal point; A magnification and rounding process is performed to obtain a magnified m-bit data; wherein m is an integer ranging from 8 to 16; after the multiplication operation, the decimal point of the result is shifted left, and the number of bits shifted left is the same as the number of bits shifted right in the magnification and rounding process.

[0019] Furthermore, the nonlinear transmitting system includes a digital up-conversion module, a DA converter, and a power amplifier; the nonlinear receiving system includes a low-noise operational amplifier, an AD converter, and a down-conversion module.

[0020] Further, calculate the M-way product result In the process, the multiplication in the calculation is converted into addition operation by taking the logarithm with base 2.

[0021] Furthermore, by taking the logarithm, before converting the multiplication in the operation into an addition operation, it is also necessary to convert , , By moving the decimal point to the right, we can enlarge and round it to get bits of binary data; is an integer in the range of 8 to 16; after the multiplication operation, the decimal point of the result is shifted left by the same number of digits as the number of digits right-shifted in the enlargement and rounding process.

[0022] Furthermore, before converting the multiplication in the operation into the addition operation, the logarithmic results of each multiplier are amplified and rounded, and then stored in the ROM in the form of a LUT table. When performing the addition operation, the corresponding values ​​are directly obtained from the LUT table for addition.

[0023] Furthermore, we construct a computation 2 N to obtain the final product result.

[0024] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0025] 1. The FPGA of the present invention constructs a nonlinear signal by combining the filter coefficients calculated by the ARM end and the multiple delay terms of the constructed dual-tone sinusoidal baseband signal using a nonlinear equalization filter, and subtracts the constructed nonlinear signal from the baseband signal with nonlinear characteristics to obtain a signal after the nonlinear characteristics are corrected, which can effectively remove the nonlinear components of the dual-tone signal after passing through the nonlinear system.

[0026] 2. The single-point FFT transformation of the present invention constructs a transformation function , The multiplication and addition with the two-tone sinusoidal baseband signal or the baseband signal with nonlinear characteristics realizes the single-point FFT transformation, which only needs to calculate the FFT of 4 frequency points, greatly reducing the amount of calculation.

[0027] 3. The present invention performs the following operations on the two-tone sinusoidal baseband signal constructed by FPGA: , , The delay of the two-tone sine baseband signal constructed by FPGA is obtained by combining multiple delay terms. ; Before passing through the nonlinear equalization filter, the third delayed signal in each combination item needs to be Take the conjugate and combine it with the other two signals , Multiply them together to get the M-way product result y i (n); The product result y corresponding to each delay item combination i (n) corresponds to the coefficient h in the M-order filter i (n) Perform multiplication operation, sum the multiplication results, and obtain the constructed nonlinear signal. The process of constructing the nonlinear signal is relatively simple, and the nonlinear component of the signal is removed.

[0028] 4. The present invention is used in computing in the process and The corresponding coefficients in the M-order filter In the multiplication process, the multiplication in the operation is converted into addition operation by taking the logarithm with base 2. This greatly reduces the amount of calculation, improves the calculation speed, and reduces the signal delay.

[0029] 5. In the data processing process of the FPGA of the present invention, the decimal point is shifted right to enlarge and round up to obtain bits of binary data; is an integer in the range of 8 to 16; after the multiplication operation, the decimal point of the result is shifted left by the same number of digits as the number of digits shifted right in the enlargement and rounding process; the problem of decimal operation is cleverly handled, and in the process of rounding the filter coefficients, due to the The integer range is set to 8 to 16, so that the calculation result has higher accuracy.

[0030] 6. The present invention constructs a logarithm with base 2 and 2 N The LUT table is stored in ROM, and data is read directly through the corresponding address during use, which greatly reduces the amount of calculation.

[0031] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are only used for the purpose of illustrating specific embodiments and are not to be considered as limiting the present invention. In the entire drawings, the same reference symbols represent the same components;

[0033] Figure 1 It is a flow chart of the internal working principle of the FPGA end of a nonlinear system correction method based on a nonlinear equalization filter;

[0034] Figure 2It is an overall structural block diagram of a nonlinear system correction method based on a nonlinear equalization filter;

[0035] Figure 3 A flowchart for the algorithm implementation of a nonlinear system correction method based on a nonlinear equalization filter that only contains nonlinear component signals;

[0036] Figure 4 The figure is a schematic diagram of the internal interface of the ARM side of a nonlinear system correction method based on a nonlinear equalization filter. DETAILED DESCRIPTION

[0037] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0038] A specific embodiment of the present invention discloses a nonlinear system correction method based on a nonlinear equalization filter, such as Figure 1 Specifically including steps S1-S4.

[0039] Step S1, constructing a two-tone sinusoidal baseband signal based on FPGA, transmitting the two-tone sinusoidal baseband signal as a training signal through an antenna after passing through a nonlinear transmitting system; then receiving the transmitted signal through an antenna, and transforming it into a baseband signal with nonlinear characteristics through a nonlinear receiving system.

[0040] The nonlinear transmitting system comprises a digital up-conversion module, a DA converter, and a power amplifier; the nonlinear receiving system comprises a low-noise operational amplifier, an AD converter, and a down-conversion module.

[0041] The nonlinear system includes a nonlinear transmitting system and a nonlinear receiving system. Figure 1 shown.

[0042] The overall structure diagram of the nonlinear system correction method of the nonlinear equalization filter is as follows: Figure 2 shown.

[0043] Specifically, the frequency is , The single-tone signal is synthesized into a dual-tone sinusoidal baseband signal by a fully digital frequency synthesizer DDS. The dual-tone sinusoidal baseband signal is used as a training signal and converted to the required frequency band by a digital up-conversion module, and then transmitted through a transmitting antenna Tx after digital-to-analog conversion and power amplifier processing; after being received by a receiving antenna Rx, it is collected by an AD after a low-noise amplifier and down-converted to obtain a baseband signal with nonlinear characteristics.

[0044] A specific embodiment of the present invention, =10M, =20M, mixed with 1G local oscillator signal to 1010M, 1020M.

[0045] Step S2: Perform single-point FFT transformation on the baseband signal with nonlinear characteristics and the two-tone sinusoidal baseband signal constructed by FPGA and input them into the ARM end.

[0046] Perform single-point FFT transformation on both the baseband signal with nonlinear characteristics and the two-tone sinusoidal baseband signal constructed by FPGA, including: constructing the transformation function The expression is:

[0047] (1)

[0048] Where N is the number of points of FFT transformation, n=0,1,2,...N-1;

[0049] At frequency Single-point FFT transform at The formula is:

[0050] (2)

[0051] The frequency built with FPGA is , Two-tone sinusoidal baseband signal or baseband signal with nonlinear characteristics, for , , , Four frequencies.

[0052] Specifically, the higher the FFT accuracy, the better the nonlinear correction effect. Because only four frequency domain values ​​are needed, it is too wasteful to directly perform FFT on the collected data. The number of FFT points in FPGA is limited by the IP core, with a maximum of 65536, and the accuracy cannot be improved. The more points there are, the more RAM and DSP resources are consumed.

[0053] Using FPGA to build transformation functions and the frequency is , The two-tone sinusoidal baseband signal is then calculated by formula (2) to obtain The single-point FFT transform result at . In (2) The frequency built using FPGA is , A two-tone sinusoidal baseband signal, Selection , , , The data of four frequency points can be used to obtain the frequency constructed by FPGA: , The two-tone sinusoidal baseband signal is , , , Frequency domain data at . In (2) Using a baseband signal with nonlinear characteristics (i.e., the signal obtained after passing through a nonlinear system), Selection , , , The data of four frequency points can be used to obtain the baseband signal with nonlinear characteristics. , , , The frequency domain data at . The frequency constructed by the FPGA is , The two-tone sinusoidal baseband signal is , , , The frequency domain data at and the baseband signal with nonlinear characteristics are , , , The frequency domain data at the locations is packaged and sent from the FPGA to the ARM through the DMA interface.

[0054] Step S3: ARM calculates and obtains an optimal filter coefficient vector and corresponding combinations of multiple delay items.

[0055] On the ARM side, the frequency of the FPGA built received by the DMA interface is , The two-tone sinusoidal baseband signal is , , , Frequency domain data at , to construct nonlinear frequency components , The product vector Y of the delayed combination terms at .

[0056] Said , is the product of the delay term y i The frequency domain value of (n), , is the product of the delay term y i (n) corresponds to a set of delays, is a two-tone sinusoidal baseband signal constructed by FPGA, conj is a conjugate operation, where , , The delay range is an integer from 0 to 15, i=0,1,2,......,(M-1), n=0,1,2,...N-1; N is the number of FFT transformation points.

[0057] The following operations research optimization model is established to solve the filter coefficients:

[0058] , (3)

[0059] ,

[0060] ,

[0061] Where Z is the baseband signal with nonlinear characteristics received by the DMA interface at the ARM end. , Frequency domain data at, Y is the nonlinear frequency component , The delayed combination product vector Y at , h is the filter coefficient vector, and Y and h are dotted. For the frequency , At , the error between the baseband signal frequency domain data Z with nonlinear characteristics and the output signal corresponding to the nonlinear filter sets a threshold. In order to make the obtained nonlinear filter as simple as possible and thus easy to implement in hardware, the number of non-zero items in the vector h needs to be as small as possible. The second-order cone optimization method can be used to obtain a sparse solution for the vector h.

[0062] ARM side according to the transmitted , , , The amplitude and phase of the frequency domain data at (the Q component of the frequency domain data is divided by the I component and the inverse tangent function is calculated to obtain the phase), constructing the delay combination term , after traversing according to (3), the optimal filter coefficient vector and the corresponding multiple delay term combinations are obtained.

[0063] Delay combination item From [0, 0, 0] to [15, 15, 15], each delay combination item can calculate a set of filter coefficients h, and finally obtain the delay combination items and filter coefficients whose filter coefficients h are not all 0 as the corresponding output results. The optimal filter coefficient vector and the corresponding multiple delay item combinations are transmitted to the FPGA through the DMA interface.

[0064] The internal interface schematic diagram of the ARM side is as follows Figure 4 shown.

[0065] Step S4, FPGA constructs a nonlinear signal using a nonlinear equalization filter according to the filter coefficient vector and the corresponding multiple delay items of the dual-tone sinusoidal baseband signal constructed by the FPGA, and subtracts the constructed nonlinear signal from the baseband signal with nonlinear characteristics to obtain a signal after the nonlinear characteristics are corrected.

[0066] The algorithm implementation flowchart for constructing a signal containing only nonlinear components is as follows Figure 3 shown.

[0067] The FPGA constructs a nonlinear signal using a nonlinear equalization filter according to the filter coefficient vector and the corresponding multiple delay items of the dual-tone sinusoidal baseband signal constructed by the FPGA, including:

[0068] For two-tone sinusoidal baseband signal According to each delay item combination Separately , , The delay of each delay item combination is obtained. ; Before passing through the nonlinear equalization filter, each delayed signal needs to be combined with the third delayed signal Take the conjugate and combine it with the other two signals , Multiply them together to get the product result y corresponding to each delay item combination i (n); among which, is the delay item combination calculated by ARM, , , The delay range is an integer from 0 to 15, i=0, 1, 2, ..., (M-1), M is the order of the nonlinear equalization filter, and the number of the delay term combinations is the same as the order of the nonlinear equalization filter;

[0069] The product result y corresponding to each delay item combination i (n) corresponds to the coefficient h in the M-order filter i (n) perform multiplication operations respectively, and sum the M multiplication results to obtain the constructed nonlinear signal.

[0070] Specifically, , , , The delay term combination calculated by ARM. is a two-tone sinusoidal baseband signal constructed by FPGA, conj is a conjugate operation, n=0,1,2,...N-1; N is the number of points of FFT transformation. The coefficient h corresponding to the M-order filter i (n) Perform multiplication operations respectively, sum the multiplication results of each channel, and obtain the constructed nonlinear signal, thus realizing the delay term product Convolution operation with the filter coefficients obtains a signal containing only nonlinear components.

[0071] Calculate the M-way product result In the process, the multiplication in the calculation is converted into addition operation by taking the logarithm with base 2.

[0072] Before converting the multiplication in the operation into addition operation by taking logarithm, it is necessary to , , By moving the decimal point to the right, we can enlarge and round it to get bits of binary data; is an integer in the range of 8 to 16; after the convolution operation, the decimal point of the result is shifted left, and the number of bits shifted left is the same as the number of bits shifted right in the enlargement and rounding process.

[0073] Specifically, when constructing a signal that contains only nonlinear components, a large number of multiplication operations are required. When implementing the multiplication of three delayed signals on the FPGA side, it is necessary to first calculate In order to ensure the accuracy of the entire calculation process, no truncation operation is performed, resulting in the result width being twice the original. When the multiplication resource required is calculated In this nonlinear correction system, the calculated filter coefficients are on the order of 10 -13 Therefore, before performing the multiplication operation with the filter coefficient, the filter coefficient needs to be enlarged and rounded; after the convolution operation, the result is scaled. In the process of rounding the filter coefficient, the calculation accuracy may be reduced:

[0074] ,

[0075] Among them, A is the multiplier in the multiplication operation, round(A) is the integer operation, and || is the absolute value operation. In order to reduce this effect, it is only necessary to infinitely enlarge A. However, the larger the value of A, the larger the bit width required on the FPGA side, and the more resources are required for subsequent multiplication operations.

[0076] At the same time, in order to ensure a good correction effect, the filter order will also be very high. The higher the filter order, the more multiplication resources will be used.

[0077] Therefore, in order to ensure the effect of the nonlinear correction system, the multiplication in the operation can be converted into addition by taking the logarithm to reduce the multiplication resources.

[0078] Before converting the multiplication in the operation into an addition operation, the logarithmic results of each multiplier are amplified and rounded, and then stored in the ROM in the form of a LUT table. When performing an addition operation, the corresponding values ​​are directly obtained from the LUT table for addition.

[0079] Build a Compute 2 N to obtain the final product result.

[0080] The product result y corresponding to each delay item combination i (n) corresponds to the coefficient h in the M-order filter i (n) Before multiplication, the coefficient h of the M-order filter is i (n) Perform enlargement and rounding processing to obtain m-bit binary data; after the multiplication operation, perform corresponding reduction processing on the result.

[0081] Specifically, subtracting the constructed nonlinear signal from the baseband signal with nonlinear characteristics to obtain a signal after the nonlinear characteristics are corrected is an operation in the time domain.

[0082] Since there is a delay between the baseband signal with nonlinear characteristics (i.e. the signal obtained after passing through the nonlinear system) and the constructed signal, this delay is the inherent delay introduced by the FPGA during the operation. Therefore, alignment processing is required when performing subtraction to remove nonlinearity. Finally, the actual signal without nonlinearity can be obtained.

[0083] Compared with the prior art, the method provided in this embodiment is that the FPGA uses a nonlinear equalization filter to construct a nonlinear signal based on the filter coefficients calculated by the ARM end and the multiple delay terms of the constructed dual-tone sinusoidal baseband signal, and subtracts the constructed nonlinear signal from the baseband signal with nonlinear characteristics to obtain a signal after the nonlinear characteristics are corrected, which can effectively remove the nonlinear components of the dual-tone signal after passing through the nonlinear system. The single-point FFT transformation provided in this embodiment realizes the single-point FFT transformation by constructing a transformation function p(n,f), and multiplying and adding p(n,f) with the dual-tone sinusoidal baseband signal or the baseband signal with nonlinear characteristics. It only needs to calculate the FFT of 4 frequency points, which greatly reduces the amount of calculation. The method provided in this embodiment performs the following operations on the dual-tone sinusoidal baseband signal constructed by FPGA: , , The delay of the two-tone sine baseband signal constructed by FPGA is obtained by combining multiple delay terms. ; Before passing through the nonlinear equalization filter, the third delayed signal in each combination item needs to be Take the conjugate and combine it with the other two signals , Multiply them together to get the M-way product result y i (n); The multiplication result y of each path i (n) corresponds to the coefficient h in the M-order filter i (n) performs a multiplication operation, and sums the multiplication results of each path to obtain the constructed nonlinear signal. The process of constructing a nonlinear signal is relatively simple, and the nonlinear component of the signal is removed. The method provided in this embodiment calculates y i (n) process and y i (n) corresponds to the coefficient h in the M-order filter i (n), the multiplication in the operation is converted into an addition operation by taking the logarithm with base 2. This greatly reduces the amount of calculation, improves the calculation speed, and reduces the signal delay. In the data processing process of the method provided in this embodiment, the FPGA is enlarged and rounded by shifting the decimal point to the right to obtain bits of binary data; is an integer in the range of 8 to 16; after the multiplication operation, the decimal point of the result is shifted left by the same number of digits as the number of digits shifted right in the enlargement and rounding process; the problem of decimal operation is cleverly handled, and in the process of rounding the filter coefficients, due to the The range is set to an integer between 8 and 16, so that the calculation result has a higher accuracy. N The LUT table is stored in ROM, and data is read directly through the corresponding address during use, which greatly reduces the amount of calculation.

[0084] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0085] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A nonlinear system correction method based on a nonlinear equalization filter, characterized in that: A two-tone sinusoidal baseband signal is constructed based on FPGA, and the two-tone sinusoidal baseband signal is used as a training signal and then transmitted through an antenna after passing through a nonlinear transmission system; the transmitted signal is then received through an antenna and converted into a baseband signal with nonlinear characteristics through a nonlinear receiving system; The baseband signal with nonlinear characteristics and the two-tone sine baseband signal constructed by FPGA are both subjected to single-point FFT transformation and then input to the ARM end. The baseband signal with nonlinear characteristics and the two-tone sine baseband signal constructed by FPGA are both subjected to single-point FFT transformation, including: constructing the transformation function The expression is: ， Where N is the number of points of FFT transformation, n=0,1,2,...N-1; At frequency Single-point FFT transform at The formula is: ， The frequency built with FPGA is , Two-tone sinusoidal baseband signal or baseband signal with nonlinear characteristics, for , , , Four frequencies; The ARM calculates the optimal filter coefficient vector and the corresponding multiple delay item combinations; the FPGA uses a nonlinear equalization filter to construct a nonlinear signal according to the filter coefficient vector and the corresponding multiple delay item combinations of the dual-tone sinusoidal baseband signal constructed by the FPGA, including: According to each delay item combination Separately , , The delay of each delay item combination is obtained. ; Before passing through the nonlinear equalization filter, each delayed signal needs to be combined with the third delayed signal Take the conjugate and combine it with the other two signals , Multiply them together to get the product result corresponding to each delay item combination ;in, is the delay item combination calculated by ARM, , , The delay range is an integer from 0 to 15, i=0, 1, 2, ..., (M-1), M is the order of the nonlinear equalization filter, and the number of the delay term combinations is the same as the order of the nonlinear equalization filter; The product result corresponding to each delay item combination is The corresponding coefficients in the M-order filter Perform multiplication operations respectively, and sum the M multiplication results to obtain the constructed nonlinear signal; The product result corresponding to each delay item combination is The corresponding coefficients in the M-order filter Before multiplication, the coefficients of the M-order filter are Performing a magnification and rounding process to obtain m-bit binary data includes: before the magnification and rounding process, firstly convert the coefficients of the filter It is represented as a binary integer part and a binary decimal part, connected by a decimal point; Performing an enlarged rounding process to obtain an enlarged m-bit data; wherein m is an integer ranging from 8 to 16; after performing the multiplication operation, the decimal point of the result is shifted to the left, and the number of bits shifted to the left is the same as the number of bits shifted to the right in the enlargement rounding process; after performing the multiplication operation, the result is correspondingly reduced; The constructed nonlinear signal is subtracted from the baseband signal with nonlinear characteristics to obtain a signal after the nonlinear characteristics are corrected.

2. The nonlinear system correction method according to claim 1, characterized in that: The nonlinear transmitting system comprises a digital up-conversion module, a DA converter, and a power amplifier; the nonlinear receiving system comprises a low-noise operational amplifier, an AD converter, and a down-conversion module.

3. The nonlinear system correction method according to claim 1, characterized in that: Calculate the M-way product result In the process, the multiplication in the calculation is converted into addition operation by taking the logarithm with base 2.

4. The nonlinear system correction method according to claim 3, characterized in that: Before converting the multiplication operation into addition operation by taking logarithm, , , By moving the decimal point to the right, we can enlarge and round it to get bit binary data; in is an integer in the range of 8 to 16; after the multiplication operation, the decimal point of the result is shifted left by the same number of digits as the number of digits right-shifted in the enlargement and rounding process.

5. The nonlinear system correction method according to claim 1 or 4, characterized in that: Before converting the multiplication in the operation into an addition operation, the logarithmic results of each multiplier are amplified and rounded, and then stored in the ROM in the form of a LUT table. When performing an addition operation, the corresponding values ​​are directly obtained from the LUT table for addition.

6. The nonlinear system correction method according to claim 5, characterized in that: Build a Compute 2 N to obtain the final product result.

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