A chip testing method, device, system and medium

Abstract

A chip testing method, device, system and medium provided by the embodiments of the present invention have the following beneficial effects: by configuring the designated general input and output port as an input mode and enabling the interrupt mode; configuring the received data length of the designated general input and output port to be a preset length; synchronizing the data acquisition clock of the designated general input and output port to be consistent with the clock of the host computer; setting the data sampling point; parsing the instruction information sent by the host computer, the instruction information is used to configure the function of the chip to be tested; and sending the test data related to the function of the chip to be tested to the host computer through the universal serial port printing interface, so that the host computer verifies the test data. The present invention realizes the interaction between the chip to be tested and the host computer, thereby realizing automated testing, reducing the dependence on testers, and effectively improving the test efficiency.

Description

Technical Field

[0001] The present invention relates to the field of chip verification, and in particular to a chip testing method, device, system and medium. Background Art

[0002] During the post-silicon verification process of the chip, the MCU (Micro Computing Unit) chip needs to configure registers to implement specified functions in order to perform subsequent function and performance verification.

[0003] In order to implement chip testing, testers need to use related software such as Keil to burn the code of specified functions into the chip to be tested. After each test case is completed, the next code is burned again to test the next test case. When there are many test cases, there will be a lot of code, and testers need to burn it multiple times, resulting in low testing efficiency.

[0004] It can be seen from the above description that how to improve chip testing efficiency is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0005] In order to overcome the inefficiency of the existing chip testing method, the present invention proposes a chip testing method, device, system and medium.

[0006] In order to achieve the above object, according to a first aspect of the present invention, an embodiment of the present invention provides a chip testing method, the method comprising the following steps:

[0007] Configure a designated general input / output port as an input mode and enable an interrupt mode, wherein the designated general input / output port is any general input / output port in the chip to be tested;

[0008] Configuring the received data length of the designated general input / output port to be a preset length, wherein the preset length is proportional to the number of test cases;

[0009] Synchronize the data acquisition clock of the designated general purpose input and output port to be consistent with the clock of the host computer;

[0010] A plurality of data sampling points are set according to the preset length, wherein the first sampling point is a sampling point delayed by a preset time after the interrupt mode is triggered, and the other sampling points other than the first sampling point are separated from the adjacent sampling points by one data acquisition clock;

[0011] Parsing the instruction information sent by the host computer, wherein the instruction information is used to configure the function of the chip to be tested;

[0012] The test data related to the function of the chip to be tested is sent to the host computer through the universal serial port printing interface, so that the host computer can verify the test data.

[0013] Optionally, configuring the received data length of the designated general input / output port to be a preset length includes:

[0014] When the number of test cases is greater than (n-1)×128 and less than or equal to n×128, the preset length is set to n bytes.

[0015] Optionally, the preset time is 1 / m times the data acquisition clock, where m is a natural number greater than or equal to 2.

[0016] Optionally, the parsing of the instruction information sent by the host computer includes:

[0017] Read n bytes of instruction information;

[0018] Store the read instruction information into the receiving variable;

[0019] Matching the function of the chip to be tested according to the received variable;

[0020] Configure the chip under test to the matched function;

[0021] The maximum number of functions of the chip to be tested is n×128.

[0022] According to a second aspect of the present invention, an embodiment of the present invention further provides a chip testing device, comprising:

[0023] A port configuration module, used to configure a designated general input / output port to an input mode and enable an interrupt mode, wherein the designated general input / output port is any general input / output port in the chip to be tested;

[0024] A data configuration module, used to configure the length of received data of the designated general input and output port to be a preset length, wherein the preset length is proportional to the number of test cases;

[0025] A clock synchronization module, used to synchronize the data acquisition clock of the designated general input and output port with the clock of the host computer;

[0026] A data sampling module, used to set a plurality of data sampling points according to the preset length, wherein the first sampling point is a sampling point delayed by a preset time after the interrupt mode is triggered, and the other sampling points other than the first sampling point are separated from the adjacent sampling points by a data acquisition clock;

[0027] A parsing module, used to parse the instruction information sent by the host computer, wherein the instruction information is used to configure the function of the chip to be tested;

[0028] The sending module is used to send test data related to the function of the chip to be tested to the host computer through the universal serial port printing interface, so that the host computer can verify the test data.

[0029] Optionally, the data configuration module is further used to:

[0030] When the number of test cases is greater than (n-1)×128 and less than or equal to n×128, the preset length is set to n bytes.

[0031] Optionally, the preset time is 1 / m times the data acquisition clock, where m is a natural number greater than or equal to 2.

[0032] Optionally, the parsing module is further used to:

[0033] Read n bytes of instruction information;

[0034] Store the read instruction information into the receiving variable;

[0035] Match the function of the chip under test according to the above received variables;

[0036] Configure the chip under test to the matched function;

[0037] The maximum number of functions of the chip to be tested is n×128.

[0038] According to the third aspect of the present invention, an embodiment of the present invention also provides a test system, including a host computer and a universal asynchronous receiver and transmitter, wherein the host computer is connected to a designated universal input and output port of a chip to be tested through the universal asynchronous receiver and transmitter, for sending instruction information to the chip to be tested; the chip to be tested is also connected to the host computer through a universal serial port printing interface, for sending test data to the host computer; the chip to be tested implements the steps of a chip testing method as in any of the above embodiments.

[0039] According to the fourth aspect of the present invention, an embodiment of the present invention also provides a storage medium, in which at least one instruction, at least one program, code set or instruction set is stored, and the at least one instruction, the at least one program, the code set or instruction set is loaded and executed by a processor to implement the steps of the chip testing method in any of the above embodiments.

[0040] As described above, a chip testing method, device, system and medium provided by an embodiment of the present invention have the following beneficial effects: by configuring a designated general input and output port as an input mode and enabling an interrupt mode, the designated general input and output port is any general input and output port in the chip to be tested; configuring the received data length of the designated general input and output port to be a preset length, the preset length is proportional to the number of test cases; synchronizing the data acquisition clock of the designated general input and output port to be consistent with the clock of the host computer; setting multiple data sampling points according to the preset length, wherein the first sampling point is a sampling point delayed by a preset time after triggering the interrupt mode, and other sampling points other than the first sampling point are one data acquisition clock away from the adjacent sampling points; parsing the instruction information sent by the host computer, the instruction information is used to configure the function of the chip to be tested; sending test data related to the function of the chip to be tested to the host computer through the universal serial port printing interface, so that the host computer verifies the test data. The present invention realizes the interaction between the chip to be tested and the host computer, thereby realizing automated testing, reducing the dependence on testers, and effectively improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a flow chart of a chip testing method provided by an embodiment of the present invention;

[0042] Figure 2 is a schematic diagram of a data sampling point provided by an embodiment of the present invention;

[0043] Figure 3 It is a flow chart of a method for configuring the function of a chip under test provided by an embodiment of the present invention;

[0044] Figure 4 is a schematic structural diagram of a chip testing device provided by an embodiment of the present invention;

[0045] Figure 5 It is a schematic diagram of the structure of a test system for executing a chip test method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0047] See also Figures 1 to 5It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] In the present invention, the chip to be tested may be a microprocessor unit MCU, and the chip to be tested MCU is usually configured with a plurality of GPIO ports (General Purpose Input Output in English and General Purpose Input Output in Chinese). The embodiment of the present invention configures any one of the general purpose input and output ports in the chip to be tested to realize the interaction between the host computer and the chip to be tested, thereby completing the test of the chip to be tested.

[0049] Of course, it should be noted that the chip testing method of the present invention is not limited to MCU, but can also be other chips with computing and data processing functions, which is not limited here.

[0050] See also Figure 1 , is a flow chart of a chip testing method provided by an embodiment of the present invention, such as Figure 1 As shown, the embodiment of the present invention shows the process of configuring the chip to be tested and executing the test method.

[0051] Step S101: configuring a designated general purpose input / output port as an input mode and enabling an interrupt mode, wherein the designated general purpose input / output port is any general purpose input / output port in the chip to be tested.

[0052] In specific implementation, the chip under test may have any number of general purpose input and output ports according to the chip design architecture. The present invention selects any one of all the general purpose input and output ports of the chip under test as the designated general purpose input and output port for configuration.

[0053] Specifically, the designated general purpose input / output port is configured as input mode, and the interrupt mode of the designated general purpose input / output port is enabled. In an exemplary embodiment, the interrupt mode may be a Falling mode, i.e., an interrupt is triggered at the falling edge of a signal, so that data connected to the designated general purpose input / output port can be read.

[0054] Step S102: configuring the length of received data of the designated general purpose input / output port to be a preset length, wherein the preset length is proportional to the number of test cases.

[0055] Configure the receive data length of the specified general input and output port, so as to receive the command information from the host computer through this port.

[0056] In specific implementation, the preset length can be flexibly configured according to the number of test cases. Specifically, when the number of test cases is greater than (n-1)×128 and less than or equal to n×128, the preset length is set to n bytes.

[0057] In an exemplary embodiment, the preset length can be configured as 1 byte, the maximum data is 7F, and the highest bit is 0, in order to trigger the Falling interrupt mode of the specified general input and output port, and receive valid data according to the configured receive data length. By configuring the receive data length, 128 test cases can be supported to test the chip under test. Of course, in the specific implementation, it can be flexibly configured according to the actual use situation. The specific rules are as described above and will not be repeated here.

[0058] Step S103: Synchronize the data acquisition clock of the designated general input / output port to be consistent with the clock of the host computer.

[0059] In order to receive data from the host computer, the data acquisition clock needs to be synchronized. In an exemplary implementation, if the baud rate sent by the host computer is 9600 (T1=104us), the data acquisition clock of the designated general input and output port of the chip under test is also configured to be 9600 (T1=104us).

[0060] Step S104: setting a plurality of data sampling points according to the preset length, wherein the first sampling point is a sampling point delayed by a preset time after the interrupt mode is triggered, and the other sampling points other than the first sampling point are one data acquisition clock away from the adjacent sampling points.

[0061] In an exemplary embodiment, after the data acquisition clock is configured according to the above steps, during the data reading process, since the highest bit of the data obtained is 0, the Falling interrupt mode of the specified general input and output port is triggered, and data of a preset length of bits is continuously read after the interruption. The implementation of the present invention takes the reading of 8 bits (1 byte) as an example to describe the data reading process in detail.

[0062] In order to ensure the reliability of the read data, in an embodiment of the present invention, the first sampling point is delayed by a preset time, and the preset time can be configured as 1 / m times the data acquisition clock, where m is a natural number approximately or equal to 2. In a preferred embodiment, m is equal to 2, so that the data of the first sampling point is collected after half a clock acquisition clock (delay=T1 / 2).

[0063] See also Figure 2, is a schematic diagram of a data sampling point provided by an embodiment of the present invention. As shown in the figure, the signal of the designated general input / output port is low level, that is, data 0, triggering the falling edge. In the figure, F1 represents the point where the interrupt signal is generated. P1 is the first sampling point. Compared with F1, P1 is delayed by T1 / 2, that is, delayed by half of the data acquisition clock; P2 is the second sampling point. Compared with the first sampling point P1, P2-P1=T1, that is, the second sampling point is delayed by 1 data acquisition clock than the first sampling point; similarly, P3-P8 are the third to eighth sampling points respectively. Except for the first sampling point, the interval between each sampling point is 1 data acquisition clock, which will not be repeated here.

[0064] Step S105: parsing the instruction information sent by the host computer, wherein the instruction information is used to configure the function of the chip to be tested.

[0065] According to the data sampling points determined in the above steps, after the interrupt mode is triggered, the general input and output ports are designated to collect the data sent by the host computer at the corresponding sampling points.

[0066] Further, the data is parsed to configure the function of the chip under test. In the specific implementation, see Figure 3 , is a flow chart of a method for configuring the function of a chip under test provided by an embodiment of the present invention, such as Figure 3 As shown, the method comprises the following steps:

[0067] Step S1051: Read n bytes of instruction information.

[0068] In the above embodiment, according to the preset length (n bytes) configured in the above embodiment and the matching sampling points, n bytes of instruction information are read.

[0069] Specifically, in a specific implementation, when the preset length is 1 byte, 8 bits of instruction information are read at 8 sampling points P1-P8.

[0070] Step S1052: Store the read instruction information into the receiving variable.

[0071] The read instruction information is stored in the receiving variable RX_DATA, so as to continue the subsequent steps.

[0072] In an exemplary embodiment, according to the read instruction information, the data stored in the receiving variable RX_DATA may be 0x01, 0x02, 0x03, etc.

[0073] Step S1053: Match the function of the chip to be tested according to the received variables described above.

[0074] The data stored in the received variable is matched. In specific implementation, a corresponding mapping table can be set to establish a relationship between the received variable and the function, which will not be described in detail here.

[0075] In an exemplary embodiment, 0x01 may correspond to the PCLK (Peripheral Bus Clock) related functions of the timer in the chip under test, 0x02 may correspond to the FCLK (Free Running Clock) related functions of the timer in the chip under test, and 0x03 may correspond to the prescale related functions of the frequency division number of the timer in the chip under test.

[0076] In this way, the function of the chip under test can be determined by matching the received variables, so that the chip under test is configured to the corresponding function, and the chip under test executes the action corresponding to the corresponding function.

[0077] In the present invention, the maximum number of functions of the chip to be tested is n×128, which is freely configured according to the preset length n of the received data. In the above embodiment, when the preset length is 1 byte, that is, n=1, 128 functions of the chip to be tested can be configured. The host computer sends different instruction information, and the chip to be tested is parsed into corresponding functions, thereby realizing automatic switching of functions during the test process and completing the functional test of the chip to be tested.

[0078] Step S1054: configure the chip to be tested to a matched function.

[0079] The chip under test is configured with corresponding functions according to the functions matched in the above steps and performs corresponding actions.

[0080] Step S106: Sending test data related to the function of the chip to be tested to the host computer through the universal serial port printing interface, so that the host computer can verify the test data.

[0081] The chip under test is usually equipped with a serial printing interface for debugging. After the chip under test executes the matching function, the generated test data is sent to the host computer through the universal serial printing interface. In this way, one function of the chip under test is tested. The host computer obtains the corresponding test data and can further verify whether the corresponding function test passes; then, the host computer continues to send corresponding instruction information, and the chip under test automatically parses and executes the next function test item.

[0082] In order to ensure the test coverage and accuracy of the chip to be tested, in the present invention, the host computer periphery can be further connected with test instruments such as an oscilloscope, a power supply, and a multimeter to meet different test requirements.

[0083] In the first implementation, taking the measurement of the input capture of the timer of a chip under test as an example, the matching equipment includes a DC power supply and a signal generator. First, the host computer initializes the test system, then controls the DC power supply to output 12V, sends instruction information to the MCU of the chip under test to configure the relevant timer input capture function, controls the signal generator to output a signal of a specified frequency to the test port of the MCU of the chip under test, and after the MCU of the chip under test detects the input signal, it sends the measured test data to the host computer, and finally the host computer displays the test results for the tester to verify.

[0084] In the second implementation, taking the measurement of the power consumption of the MCU under test in low power consumption mode as an example, the equipment includes a DC power supply and a digital multimeter. The host computer controls the DC power supply to output 12V, configures the gear of the digital multimeter to the current gear and sends data to the MCU under test to configure it to sleep or sleepwalk mode. At this time, the host computer reads the current value of the digital multimeter, thereby completing the test function item.

[0085] In the third implementation, taking the measurement of the pulse modulation width PWM signal of the chip MCU under test as an example: the equipment has a DC power supply and an oscilloscope. The host computer controls the DC power supply to output 12V and sends data to the chip MCU under test, so that the designated port of the chip MCU under test outputs a pulse modulation width PWM signal. At this time, the host computer controls the oscilloscope to read the PWM signal and takes a screenshot to save the relevant data for the tester to verify.

[0086] As can be seen from the description of the above embodiments, a chip testing method provided by an embodiment of the present invention is configured by configuring a designated general input / output port as an input mode and enabling an interrupt mode, wherein the designated general input / output port is any general input / output port in the chip to be tested; configuring the length of received data of the designated general input / output port to be a preset length, wherein the preset length is proportional to the number of test cases; synchronizing the data acquisition clock of the designated general input / output port to be consistent with the clock of the host computer; setting multiple data sampling points according to the preset length, wherein the first sampling point is a sampling point delayed by a preset time after triggering the interrupt mode, and other sampling points other than the first sampling point are one data acquisition clock away from the adjacent sampling points; parsing the instruction information sent by the host computer, wherein the instruction information is used to configure the function of the chip to be tested; and sending test data related to the function of the chip to be tested to the host computer through a universal serial port printing interface, so that the host computer verifies the test data. The present invention realizes information interaction between the chip to be tested and the host computer, thereby realizing automated testing, reducing dependence on testers, and effectively improving test efficiency.

[0087] Through the description of the above method embodiments, the technicians in the relevant field can clearly understand that the present invention can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk.

[0088] An embodiment of the present invention provides a non-volatile computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions can execute the chip testing method in any of the above method embodiments.

[0089] Corresponding to the chip testing method embodiment provided by the present invention, the present invention also provides a chip testing device.

[0090] See also Figure 4 , is a schematic diagram of the structure of a chip testing device provided by an embodiment of the present invention. As shown in the figure, the device includes:

[0091] A port configuration module 11, configured to configure a designated general input / output port to an input mode and enable an interrupt mode, wherein the designated general input / output port is any general input / output port in the chip to be tested;

[0092] A data configuration module 12, used to configure the length of received data of the designated general input and output port to be a preset length, wherein the preset length is proportional to the number of test cases;

[0093] A clock synchronization module 13, used to synchronize the data acquisition clock of the designated general input and output port with the clock of the host computer;

[0094] The data sampling module 14 is used to set a plurality of data sampling points according to a preset length, wherein the first sampling point is a sampling point delayed by a preset time after the interrupt mode is triggered, and the other sampling points other than the first sampling point are separated from the adjacent sampling points by a data acquisition clock;

[0095] The parsing module 15 is used to parse the instruction information sent by the host computer, and the instruction information is used to configure the function of the chip to be tested;

[0096] The sending module 16 is used to send test data related to the function of the chip to be tested to the host computer through the universal serial port printing interface, so that the host computer can verify the test data.

[0097] Optionally, the data configuration module 12 is further configured to set the preset length to n bytes when the number of test cases is greater than (n-1)×128 and less than or equal to n×128.

[0098] Optionally, the preset time of the first sampling point configured by the data sampling module 14 is 1 / m times the data acquisition clock, where m is a natural number greater than or equal to 2.

[0099] Optionally, the parsing module 15 is further used for:

[0100] Also used for

[0101] Read n bytes of instruction information;

[0102] Store the read instruction information into the receiving variable;

[0103] Match the function of the chip under test according to the above received variables;

[0104] Configure the chip under test to the matched function;

[0105] The maximum number of functions of the chip to be tested is n×128.

[0106] Figure 5 FIG. 1 is a schematic diagram of the structure of a test system for executing a chip test method provided by an embodiment of the present invention. Figure 5 As shown, the system includes a host computer 21 and a universal asynchronous receiver / transmitter (UART) 22. The host computer 21 is connected to the receiving end of the designated general purpose input / output port GPIO (RX) of the chip to be tested 23 through the transmitting end (TX) of the universal asynchronous receiver / transmitter 22, and is used to send instruction information to the chip to be tested 23. In specific implementation, the host computer 21 and the universal asynchronous receiver / transmitter 22 are connected via USB, and the transmitting end TX of the universal asynchronous receiver / transmitter 22 is connected to the receiving end RX of the designated general purpose input / output port of the chip to be tested 23. The above method is used to realize the software configuration of the host computer 21 to specify the function of the chip to be tested 23. The chip to be tested 23 is also connected to the host computer through a universal serial port printing interface (not shown), which is used to send test data to the host computer 21 to complete the function verification.

[0107] In addition, the test system may further include test instruments such as an oscilloscope, a power supply and a multimeter, which can be found in the description of the above embodiment and will not be described in detail here.

[0108] The above product can execute the method provided by the embodiment of the present invention, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not described in detail in this embodiment, please refer to the method provided by the embodiment of the present invention.

[0109] The electronic device of the embodiment of the present invention exists in various forms, including but not limited to:

[0110] (1) Mobile communication devices: These devices are characterized by their mobile communication functions and their main purpose is to provide voice and data communications. These terminals include: smart phones (such as iPhone), multimedia phones, functional phones, and low-end phones;

[0111] (2) Ultra-mobile personal computer devices: These devices belong to the category of personal computers, have computing and processing functions, and generally also have mobile Internet access features. These terminals include: PDA, MID and UMPC devices, such as iPad;

[0112] (3) Portable entertainment devices: These devices can display and play multimedia content. They include audio and video players (such as iPods), handheld game consoles, e-books, smart toys, and portable car navigation devices;

[0113] (4) Server: A device that provides computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server is similar to a general computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0114] (5) Other electronic devices with data interaction functions;

[0115] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0116] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The device and system embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0117] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0118] The above description is only a specific embodiment of the present invention, so that those skilled in the art can understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A chip testing method, characterized in that: Applied to the chip side, including: Configure a designated general input / output port as an input mode and enable an interrupt mode, wherein the designated general input / output port is any general input / output port in the chip to be tested; Configuring the received data length of the designated general input / output port to be a preset length, wherein the preset length is proportional to the number of test cases; Synchronize the data acquisition clock of the designated general purpose input and output port to be consistent with the clock of the host computer; A plurality of data sampling points are set according to the preset length, wherein the first sampling point is a sampling point delayed by a preset time after the interrupt mode is triggered, and the other sampling points other than the first sampling point are separated from the adjacent sampling points by one data acquisition clock; Parsing the instruction information sent by the host computer, wherein the instruction information is used to configure the function of the chip to be tested; The test data related to the function of the chip to be tested is sent to the host computer through the universal serial port printing interface, so that the host computer can verify the test data.

2. The chip testing method according to claim 1, characterized in that: The step of configuring the received data length of the designated general purpose input / output port to be a preset length includes: When the number of test cases is greater than (n-1)×128 and less than or equal to n×128, the preset length is set to n bytes.

3. The chip testing method according to claim 1, characterized in that: The preset time is 1 / m times the data acquisition clock, where m is a natural number greater than or equal to 2.

4. The chip testing method according to claim 2, characterized in that: The parsing of the instruction information sent by the host computer includes: Read n bytes of instruction information; Store the read instruction information into the receiving variable; Matching the function of the chip to be tested according to the received variable; Configure the chip under test to the matching function; The maximum number of functions of the chip to be tested is n×128.

5. A chip testing device, characterized in that: include: A port configuration module, used to configure a designated general input / output port to an input mode and enable an interrupt mode, wherein the designated general input / output port is any general input / output port in the chip to be tested; A data configuration module, used to configure the length of received data of the designated general input and output port to be a preset length, wherein the preset length is proportional to the number of test cases; A clock synchronization module, used to synchronize the data acquisition clock of the designated general input and output port with the clock of the host computer; A data sampling module, used to set a plurality of data sampling points according to the preset length, wherein the first sampling point is a sampling point delayed by a preset time after the interrupt mode is triggered, and the other sampling points other than the first sampling point are separated from the adjacent sampling points by a data acquisition clock; A parsing module, used to parse the instruction information sent by the host computer, wherein the instruction information is used to configure the function of the chip to be tested; The sending module is used to send test data related to the function of the chip to be tested to the host computer through the universal serial port printing interface, so that the host computer can verify the test data.

6. The chip testing device according to claim 5, characterized in that: The data configuration module is also used to: When the number of test cases is greater than (n-1)×128 and less than or equal to n×128, the preset length is set to n bytes.

7. The chip testing device according to claim 5, characterized in that: The preset time is 1 / m times the data acquisition clock, where m is a natural number greater than or equal to 2.

8. The chip testing device according to claim 6, characterized in that: The parsing module is also used to: Read n bytes of instruction information; Store the read instruction information into the receiving variable; Match the function of the chip under test according to the above received variables; Configure the chip under test to the matching function; The maximum number of functions of the chip to be tested is n×128.

9. A testing system, characterized in that: It includes a host computer and a universal asynchronous receiver and transmitter, wherein the host computer is connected to a designated universal input and output port of a chip to be tested through the universal asynchronous receiver and transmitter, and is used to send instruction information to the chip to be tested; the chip to be tested is also connected to the host computer through a universal serial port printing interface, and is used to send test data to the host computer; the chip to be tested implements the chip testing method as described in any one of claims 1 to 4.

10. A computer-readable storage medium, characterized in that: The storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the steps of the chip testing method as described in any one of claims 1 to 4.

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