A PLC ladder diagram detection method and terminal

Abstract

The present invention discloses a PLC ladder diagram detection method and terminal, the method comprising: obtaining a data structure of a ladder diagram, the data structure comprising a plurality of elements to be tested and a connection relationship; determining the input element and output element of each element to be tested according to the connection relationship, and detecting whether the ladder diagram has a circuit break; if not, associating the plurality of elements to be tested according to the connection relationship to obtain a node diagram; filling the plurality of elements to be tested into a binary tree structure according to the input element, the output element and the node diagram; detecting whether the plurality of elements to be tested are all filled into the nodes of the binary tree structure, if not, the ladder diagram has a path abnormality. The present invention can cover complex logical structures and accurately describe the data structure of the ladder diagram, thereby improving the detection accuracy.

Description

Technical Field

[0001] The present invention relates to the technical field of graphic compilation detection, and in particular to a PLC ladder diagram detection method and a terminal. Background Art

[0002] PLC ladder diagram is a graphical programming language widely used in PLC (Programmable Logic Controller) programming. At present, most ladder diagram compilation modules usually check whether the input ladder diagram logic has path errors or parameter errors. When checking the ladder diagram, the compilation module usually needs to analyze each path in the ladder diagram. Therefore, for each element of the ladder diagram, it is necessary to analyze the adjacent elements in eight directions: up, down, left, right, upper left, lower left, upper right, and lower right. However, this detection method is difficult to cover some special cases with more complex code logic, and it cannot describe the data structure of the operation block in the ladder diagram, so the detection accuracy is poor. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a PLC ladder diagram detection method and terminal, which can cover complex logical structures and accurately describe the data structure of the ladder diagram, thereby improving the detection accuracy.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0005] A PLC ladder diagram detection method, comprising:

[0006] Acquire a data structure of a ladder diagram, wherein the data structure includes a plurality of elements to be tested and connection relationships;

[0007] Determine the input element and the output element of each of the elements to be tested according to the connection relationship, and detect whether there is a circuit break in the ladder diagram;

[0008] If not, the plurality of elements to be tested are associated according to the connection relationship to obtain a node graph;

[0009] Filling the plurality of elements to be tested into a binary tree structure according to the input elements, the output elements and the node graph;

[0010] It is detected whether the multiple elements to be tested are all filled into the nodes of the binary tree structure. If not, there is a path abnormality in the ladder diagram.

[0011] In order to solve the above technical problems, another technical solution adopted by the present invention is:

[0012] A PLC ladder diagram detection terminal comprises a memory, a processor and a computer program stored in the memory and running on the processor. When the processor executes the computer program, each step in the above-mentioned PLC ladder diagram detection method is implemented.

[0013] The beneficial effects of the present invention are: firstly, the elements to be tested and the connection relationship of the ladder diagram are obtained, and at the same time, the input elements and output elements of each element to be tested are determined based on the connection relationship, and whether there is a circuit break in the current ladder diagram is detected, that is, the characteristics of the circuit break data structure are used to complete the detection of the circuit break problem when the elements to be tested are in a discrete state. If there is no circuit break in the ladder diagram, the elements to be tested are associated through the connection relationship to form a node diagram, so that the elements to be tested that are originally in a discrete state are filled into the binary tree structure based on the node diagram and the input and output elements. Since the ladder diagram with normal paths can be completely converted into a binary tree structure, based on this characteristic, by detecting whether the elements to be tested are all filled into the binary tree structure, it is verified whether the binary tree covers the paths of all discrete points, thereby determining whether there is an abnormality in the path of the current ladder diagram. By converting discrete ladder diagram elements into a structure with input and output information through a binary tree structure, it is not only possible to cover complex logical structures, but also to accurately describe the data structure of the ladder diagram, thereby improving the detection accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A flow chart of a PLC ladder diagram detection method provided by an embodiment of the present invention;

[0015] Figure 2 Another flow chart of a PLC ladder diagram detection method provided by an embodiment of the present invention;

[0016] Figure 3 A schematic diagram of storage of a two-dimensional array provided by an embodiment of the present invention;

[0017] Figure 4 A ladder diagram with a circuit break provided by an embodiment of the present invention;

[0018] Figure 5 A node graph provided by an embodiment of the present invention;

[0019] Figure 6 A schematic diagram of a node graph provided by an embodiment of the present invention after parallel merging;

[0020] Figure 7 A ladder diagram with a short circuit provided by an embodiment of the present invention;

[0021] Figure 8 A schematic diagram of the structure of a binary tree provided by an embodiment of the present invention;

[0022] Fig. 9 A schematic diagram of a structure of a binary tree after parallel merging provided by an embodiment of the present invention;

[0023] Fig.10 A schematic diagram of a binary tree structure after serial merging provided by an embodiment of the present invention;

[0024] Fig.11 A ladder diagram with abnormal path provided by an embodiment of the present invention;

[0025] Fig.12 Another node graph provided by an embodiment of the present invention;

[0026] Fig.13 for Fig.12 The node graph after parallel merging;

[0027] Fig.14 for Fig.13 The node graph after parallel merging;

[0028] Fig.15 A schematic diagram of the structure of a PLC ladder diagram detection terminal provided by an embodiment of the present invention;

[0029] Description of labels:

[0030] 100. A PLC ladder diagram detection terminal; 101. A memory; 102. A processor. DETAILED DESCRIPTION

[0031] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0032] An embodiment of the present invention provides a PLC ladder diagram detection method, comprising:

[0033] Acquire a data structure of a ladder diagram, wherein the data structure includes a plurality of elements to be tested and connection relationships;

[0034] Determine the input element and the output element of each of the elements to be tested according to the connection relationship, and detect whether there is a circuit break in the ladder diagram;

[0035] If not, the plurality of elements to be tested are associated according to the connection relationship to obtain a node graph;

[0036] Filling the plurality of elements to be tested into a binary tree structure according to the input elements, the output elements and the node graph;

[0037] It is detected whether the multiple elements to be tested are all filled into the nodes of the binary tree structure. If not, there is a path abnormality in the ladder diagram.

[0038] As can be seen from the above description, the beneficial effects of the present invention are: firstly obtain the elements to be tested and the connection relationship of the ladder diagram, determine the input elements and output elements of each element to be tested based on the connection relationship, and detect whether there is a circuit break in the current ladder diagram, that is, use the characteristics of the circuit break data structure to complete the detection of the circuit break problem when the element to be tested is in a discrete state. If there is no circuit break in the ladder diagram, the elements to be tested are associated through the connection relationship to form a node diagram, so that the elements to be tested that are originally in a discrete state are filled into the binary tree structure based on the node diagram and the input and output elements. Since the ladder diagram with normal paths can be completely converted into a binary tree structure, based on this characteristic, by detecting whether the elements to be tested are all filled into the binary tree structure, it is verified whether the binary tree covers the paths of all discrete points, thereby determining whether there is an abnormality in the path of the current ladder diagram. By converting discrete ladder diagram elements into a structure with input and output information through a binary tree structure, it is not only possible to cover complex logical structures, but also to accurately describe the data structure of the ladder diagram, thereby improving the detection accuracy.

[0039] Furthermore, the data structure for obtaining the ladder diagram includes:

[0040] Traversing a two-dimensional array storing a data structure of the ladder diagram;

[0041] All non-empty array elements in the two-dimensional array are extracted to obtain the elements to be tested, and the indexes of the non-empty array elements pointing to other array elements are extracted to obtain the connection relationship.

[0042] From the above description, it can be seen that since the ladder diagram before compilation is in a discrete state, each array element in the two-dimensional array is used to store the element to be tested in a discrete state to characterize the relative position structure between the elements, and the array element records other elements connected to the element to be tested, that is, the index, thereby ensuring that the data structure of the ladder diagram can be completely recorded and stored.

[0043] Further, the determining the input element and the output element of each of the elements to be tested according to the connection relationship comprises:

[0044] If the other array element pointed to by the index is the element to be tested, then the non-empty array element corresponding to the index is marked as the input element of the element to be tested;

[0045] If the non-empty array element corresponding to the index is the element to be tested, then other array elements pointed to by the index are marked as output elements of the element to be tested.

[0046] From the above description, it can be seen that in a two-dimensional array, the index records the relative connection relationship between two non-empty array elements. The input and output directions of the elements can be determined based on the directionality of the index. In this way, the input elements and output elements can be accurately extracted based on the elements to be tested in a discrete state, thereby ensuring the accuracy of subsequent detection.

[0047] Further, the detecting whether the ladder diagram has a circuit break includes:

[0048] Check whether the other array elements pointed to by the index are empty results;

[0049] If so, there is a circuit break in the ladder diagram;

[0050] Otherwise, there is no open circuit in the ladder diagram.

[0051] From the above description, it can be seen that when the other array elements pointed to by the index of the element to be tested are empty results, it means that the element connected to the element to be tested is blank, that is, the element to be tested has a connection relationship, but is not connected to the actual element to be tested, which indicates that the element to be tested is a broken element. In this way, it is possible to quickly determine whether there is a broken circuit in the ladder diagram.

[0052] Further, filling the plurality of elements to be tested into a binary tree structure according to the input elements, the output elements and the node graph includes:

[0053] Traversing the node graph, comparing the input elements and the output elements of any two elements to be tested, and determining a merging relationship between the two elements to be tested according to the comparison result;

[0054] The multiple elements to be tested are sequentially filled into a binary tree structure according to the merging relationship and the connection order in the node graph.

[0055] From the above description, it can be seen that since the elements to be tested are easier to maintain consistency and correctness after merging, after determining the merging relationship between two elements to be tested, the elements to be tested are filled into the binary tree structure based on the merging relationship, which can ensure the reliability of the element filling operation and improve the detection accuracy.

[0056] Further, the comparing the input element and the output element of any two elements to be tested, and determining the merging relationship between the two elements to be tested according to the comparing result includes:

[0057] Detecting whether the input elements and the output elements of any two elements to be tested are the same;

[0058] If so, it is determined that the two elements to be tested are in a parallel merge relationship.

[0059] From the above description, it can be seen that the parallel merge relationship, that is, the relationship between the two elements to be tested belongs to the "or" logic operation relationship, so the input and output elements between the two elements to be tested are the same.

[0060] Furthermore, the comparing the input element and the output element of any two elements to be tested and determining the merging relationship between the two elements to be tested according to the comparing result further includes:

[0061] Detecting whether the two elements to be detected are associated and whether the input element or the output element of one element to be detected only includes the other element to be detected;

[0062] If so, it is determined that the two elements to be tested are in a series merge relationship.

[0063] From the above description, it can be seen that the serial merging relationship, that is, the relationship between the two elements to be tested, belongs to the "AND" logic operation relationship, so the output element of one element to be tested is completely equal to the input element of the other element to be tested.

[0064] Further, the step of sequentially filling the plurality of elements to be tested into a binary tree structure according to the merging relationship and the connection order in the node graph includes:

[0065] In a binary tree structure, if the merging relationship is a parallel merging relationship, a parallel root node is generated in the binary tree structure, and two elements to be tested corresponding to the parallel merging relationship are respectively filled as child nodes of the parallel root node;

[0066] If the merging relationship is a serial merging relationship, a serial root node is generated in the binary tree structure, and two elements to be tested corresponding to the serial merging relationship are respectively filled as child nodes of the serial root node;

[0067] The parallel root nodes and the series root nodes are sequentially connected according to the connection order in the node graph to form a binary tree group.

[0068] From the above description, it can be seen that different binary tree nodes are generated based on different types of merge relationships, so that the elements to be tested are filled into the binary tree structure to accurately describe the data structure of the ladder diagram without building a complex structure, with simple logic and strong scalability.

[0069] Furthermore, before detecting whether the plurality of elements to be tested are all filled into the nodes of the binary tree structure, the method further includes:

[0070] Traverse each node in the binary tree structure, and perform corresponding merging processing on the nodes in the binary tree structure filled with the elements to be tested according to the parallel root node and the series root node to generate a new binary tree structure, until the new binary tree structure can no longer perform the merging processing, then detect whether the multiple elements to be tested are all filled into the nodes of the binary tree structure.

[0071] From the above description, it can be seen that after the elements to be tested are filled into the binary tree, the binary tree structure is merged, which simplifies the binary tree structure while ensuring data accuracy, so as to facilitate verification of whether the binary tree contains all the elements in the ladder diagram. In this way, in the process of verifying whether there is an abnormality in the ladder diagram path, there is no need to exhaustively enumerate the possibility of all path errors, and verification can be completed by traversing the binary tree structure, which improves detection efficiency while ensuring detection accuracy.

[0072] Another embodiment of the present invention provides a PLC ladder diagram detection terminal, including a memory, a processor, and a computer program stored in the memory and running on the processor, and when the processor executes the computer program, each step in the above-mentioned PLC ladder diagram detection method is implemented.

[0073] As can be seen from the above description, the beneficial effects of the present invention are: firstly obtain the elements to be tested and the connection relationship of the ladder diagram, determine the input elements and output elements of each element to be tested based on the connection relationship, and detect whether there is a circuit break in the current ladder diagram, that is, use the characteristics of the circuit break data structure to complete the detection of the circuit break problem when the element to be tested is in a discrete state. If there is no circuit break in the ladder diagram, the elements to be tested are associated through the connection relationship to form a node diagram, so that the elements to be tested that are originally in a discrete state are filled into the binary tree structure based on the node diagram and the input and output elements. Since the ladder diagram with normal paths can be completely converted into a binary tree structure, based on this characteristic, by detecting whether the elements to be tested are all filled into the binary tree structure, it is verified whether the binary tree covers the paths of all discrete points, thereby determining whether there is an abnormality in the path of the current ladder diagram. By converting discrete ladder diagram elements into a structure with input and output information through a binary tree structure, it is not only possible to cover complex logical structures, but also to accurately describe the data structure of the ladder diagram, thereby improving the detection accuracy.

[0074] The embodiments of the present invention provide a PLC ladder diagram detection method and terminal, which can be applied to the PLC ladder diagram compilation detection scenario, can not only cover complex logical structures, but also accurately describe the data structure of the ladder diagram, and improve the detection accuracy. The following is explained by specific embodiments:

[0075] Please refer to Figures 1 to 14 , Embodiment 1 of the present invention is:

[0076] A PLC ladder diagram detection method, comprising:

[0077] S1. Obtain a data structure of a ladder diagram, wherein the data structure includes a plurality of elements to be tested and connection relationships.

[0078] Specifically, the step S1 includes:

[0079] S11, traverse the two-dimensional array storing the data structure of the ladder diagram.

[0080] In some embodiments, the ladder diagram stored in the two-dimensional array is an uncompiled data structure. The elements to be tested in the data structure are specifically contacts, coils, left busbars, right busbars or function blocks, etc. The ladder diagram in the two-dimensional array is in a discrete state, and there are no physical connecting lines between the elements to be tested.

[0081] S12. Extract all non-empty array elements in the two-dimensional array to obtain elements to be tested, and extract indexes of the non-empty array elements pointing to other array elements to obtain connection relationships.

[0082] In some embodiments, Figure 3 As shown, the data structure of the ladder diagram is stored in a two-dimensional array of size 2 × 7. Among them, the element to be tested M1 is stored in array [1,1], the element to be tested M2 is stored in array [1,2], the element to be tested M3 is stored in array [2,2], the element to be tested M4 is stored in array [1,3], the element to be tested Y1 is stored in array [1,7], and the element to be tested Y2 is stored in array [2,7].

[0083] In some embodiments, the array elements of the two-dimensional array store the elements to be tested and the indexes related to the elements to be tested. Specifically, the element to be tested stored in the array element at [1,1] in the current two-dimensional array is M1, and the first index [1,1] points to [1,2] and the second index [1,1] points to [2,2] are also stored, which indicates that the right side of M1 is connected to M2 and M3 respectively. The element to be tested stored in the array element at [1,2] in the current two-dimensional array is M2, and the third index [1,1] points to [1,2] and the fourth index [1,2] points to [1,3] are also stored, which indicates that the left side of M2 is connected to M1 and the right side of M2 is connected to M4.

[0084] S2. Determine the input element and the output element of each of the elements to be tested according to the connection relationship, and detect whether there is a break in the ladder diagram.

[0085] Specifically, in step S2, determining the input element and the output element of each element to be tested according to the connection relationship includes:

[0086] S21. If the other array element pointed to by the index is the element to be tested, mark the non-empty array element corresponding to the index as an input element of the element to be tested.

[0087] In some embodiments, Figure 3 As shown, if the element to be tested that currently needs to determine the input element and the output element is M2, the non-empty array element pointed to by the third index is [1,2], that is, the element to be tested M2. Therefore, the element to be tested M1 in the non-empty array element [1,1] corresponding to the third index is the input element of the element to be tested M2.

[0088] S22. If the non-empty array element corresponding to the index is the element to be tested, mark the other array elements pointed to by the index as output elements of the element to be tested.

[0089] In some embodiments, Figure 3 As shown, if the element to be tested that currently needs to determine the input element and the output element is M2, the non-empty array element corresponding to the fourth index is [1,2], that is, the element to be tested M2. Therefore, the element to be tested M4 in the non-empty array element [1,3] pointed to by the fourth index is the output element of the element to be tested M2.

[0090] Based on step S21 to step S22, the input elements and output elements of the elements to be measured M1, M2, M3, M4, Y1 and Y2 are as shown in Table 1.

[0091] Table 1 Input elements and output elements of the elements to be measured

[0092]

[0093] Specifically, in step S2, detecting whether the ladder diagram has a circuit break includes:

[0094] S21. Detect whether other array elements pointed to by the index are empty results. If so, there is a break in the ladder diagram. Otherwise, there is no break in the ladder diagram.

[0095] In some embodiments, Figure 4 As shown, the element M1 to be tested has two connection lines, that is, the element M1 to be tested has two indexes, one of the indexes points to the other array element Y1 to be tested, and the other index points to the other array element with an empty result, so there is a circuit break in the ladder diagram.

[0096] In some embodiments, if a circuit break is detected in the ladder diagram, the detection is terminated, and a prompt is given that a path abnormality exists in the current ladder diagram and the compilation fails.

[0097] S3. If not, the plurality of elements to be tested are associated according to the connection relationship to obtain a node graph.

[0098] In some embodiments, multiple elements to be tested are associated according to the connection relationship, specifically: the elements to be tested are associated in sequence according to the traversal order of the ladder diagram and the connection relationship, wherein the traversal order of the ladder diagram is from left to right and from top to bottom.

[0099] In some embodiments, before the multiple elements to be tested are associated, the multiple elements to be tested are recorded in the node graph in a scattered and unrelated state. Can be characterized as:

[0100] , where node j represents the jth node in the node graph with scattered and unrelated states, represents the jth element to be tested, m j Represents the input element of the jth element to be tested, n j Represents the output element of the jth element to be tested.

[0101] like Figure 5 As shown, the data structure stored in the two-dimensional array is converted into a node diagram, where the output of the left bus is connected to the input of the element to be measured M1, the output of the element to be measured M1 is respectively connected to the inputs of the element to be measured M2 and the element to be measured M3, the outputs of the element to be measured M2 and the element to be measured M3 are both connected to the input of the element to be measured M4, and the output of the element to be measured M4 is respectively connected to the inputs of the element to be measured Y1 and the element to be measured Y2.

[0102] S4. Fill the multiple elements to be tested into a binary tree structure according to the input elements, the output elements and the node graph.

[0103] Specifically, step S4 includes:

[0104] S41, traversing the node graph, comparing the input elements and the output elements of any two elements to be tested, and determining a merging relationship between the two elements to be tested according to the comparison result.

[0105] In some embodiments, two elements to be tested that have a merge relationship may be merged into one element.

[0106] Specifically, the step S41 includes:

[0107] S411, detecting whether the input elements and the output elements of any two elements to be tested are the same, and if so, determining that the two elements to be tested are in a parallel merge relationship.

[0108] In some embodiments, referring to Table 1, it can be determined that the element to be measured M2 and the element to be measured M3 are in a parallel-merged relationship, and the element to be measured Y1 and the element to be measured Y2 are in a parallel-merged relationship.

[0109] Specifically, the step S41 further includes:

[0110] S412: Detect whether the two elements to be tested are associated and whether the input element or the output element of one element to be tested only includes another element to be tested. If so, determine that the two elements to be tested are in a series merge relationship.

[0111] In some embodiments, based on the parallel merging relationship determined in step S411, the corresponding elements to be tested may be parallel merged before step S412 is performed. Figure 6 As shown, the element to be tested M2 and the element to be tested M3 are merged in parallel to obtain a new element (M2*M3), and the element to be tested Y1 and the element to be tested Y2 are merged in parallel to obtain a new element (Y1*Y2). At this time, the element to be tested M1 and the new element (M2*M3) are associated, and the output element of the element to be tested M1 is only the new element (M2*M3). Therefore, the element to be tested M1 and the new element (M2*M3) are in a series merge relationship. Similarly, the new element (M2*M3) and the element to be tested M4 are in a series merge relationship, and the element to be tested M4 and the new element (Y1*Y2) are in a series merge relationship.

[0112] In some embodiments, after determining the merging relationship between the two elements to be tested according to the comparison results, it also includes: detecting whether there is a short circuit in the ladder diagram according to the input elements and output elements of each element to be tested; if there is, then the detection is terminated, and a prompt is given that there is a path abnormality in the current ladder diagram and the compilation fails; if there is no path abnormality in the current ladder diagram, then step S42 is executed. Specifically, according to the merging relationship between the tuples to be tested, the elements to be tested are merged to obtain a new element to be tested, and according to the input elements and output elements of the new element to be tested, it is detected whether there is a short circuit in the current ladder diagram. Figure 7 As shown, the element to be tested M2 and the element to be tested M3 are in a series merge relationship. The element to be tested M2 and the element to be tested M3 are processed in series and merged to obtain a new element to be tested (M2+M3). At this time, the output element of the element to be tested M1 includes the new element to be tested (M2+M3) and the element to be tested Y1, and the output element of the new element to be tested (M2+M3) also includes the element to be tested Y1. Therefore, the element to be tested M1 can be directly connected to the element to be tested Y1 without passing through the element to be tested Y1, so it can be determined that the current ladder diagram has a short circuit. That is, when there is an input-output relationship between the output elements of the elements to be tested, the ladder diagram has a short circuit.

[0113] S42: filling the multiple elements to be tested into a binary tree structure in sequence according to the merging relationship and the connection order in the node graph.

[0114] Specifically, the step S42 includes:

[0115] S421. In a binary tree structure, if the merging relationship is a parallel merging relationship, a parallel root node is generated in the binary tree structure, and two elements to be tested corresponding to the parallel merging relationship are respectively filled as child nodes of the parallel root node.

[0116] S422: If the merging relationship is a serial merging relationship, a serial root node is generated in the binary tree structure, and two elements to be tested corresponding to the serial merging relationship are respectively filled as child nodes of the serial root node.

[0117] S423. Connect the parallel root node and the series root node in sequence according to the connection order in the node graph to form a binary tree group.

[0118] In some embodiments, Figure 8 As shown, "+" represents a serial root node, and "*" represents a parallel root node. Specifically, since the element to be measured M2 and the element to be measured M3 are in a parallel merge relationship, a parallel root node 21 is generated, and the element to be measured M2 and the element to be measured M3 are respectively filled as the left child node and the right child node of the parallel root node 21. Since the element to be measured Y1 and the element to be measured Y2 are in a parallel merge relationship, a parallel root node 22 is generated, and the element to be measured Y1 and the element to be measured Y2 are respectively filled as the left child node and the right child node of the parallel root node 22. Since the new element after the parallel merge processing of the element to be measured M2 and the element to be measured M3 is in a serial merge relationship with the element to be measured M1, a serial root node 11 is generated, and the element to be measured M1 and the parallel root node 21 are filled as the left child node and the right child node of the serial root node 11. Since the new element after the parallel merging of the tested element Y1 and the tested element Y2 is in a series merging relationship with the tested element M4, a series root node 12 is generated, and the tested element M4 and the parallel root node 22 are filled as the left child node and the right child node of the series root node 12. In this way, a binary tree group is formed.

[0119] S5. Detect whether the multiple elements to be tested are all filled into the nodes of the binary tree structure. If not, there is a path abnormality in the ladder diagram.

[0120] Before step S5, the method further includes:

[0121] S501, traverse each node in the binary tree structure, and perform corresponding merging processing on the nodes in the binary tree structure filled with the elements to be tested according to the parallel root node and the series root node to generate a new binary tree structure, until the new binary tree structure can no longer perform the merging processing, then detect whether the multiple elements to be tested are all filled into the nodes of the binary tree structure.

[0122] In some embodiments, Fig. 9 As shown, Figure 8 The elements M2 and M3 to be tested in the binary tree structure are processed in parallel and merged to obtain a new element (M2*M3), and the elements Y1 and Y2 to be tested are processed in parallel and merged to obtain a new element (Y1*Y2). The obtained new elements (M2*M3) and (Y1*Y2) are filled into the corresponding parallel root nodes 21 and parallel root nodes 22 respectively to obtain a new binary tree structure.

[0123] In some embodiments, Fig.10 As shown, Fig. 9 The element M1 to be tested and the new element (M2*M3) in the binary tree structure are processed in series and merged to obtain a new element (M1+(M2*M3)), and the element M4 to be tested and the new element (Y1*Y2) are processed in series and merged to obtain a new element (M4+(Y1*Y2)). The obtained new elements (M1+(M2*M3)) and (M4+(Y1*Y2)) are respectively filled into the corresponding series root nodes 11 and series root nodes 12 to obtain a new binary tree structure.

[0124] It should be noted that for a ladder diagram with a normal path, after merging, it can achieve the ideal state of having only one input and one output, that is, , Represents an input, represents an output where , that is, all ladder diagram elements can be regarded as the only output element after merging. Represents all elements after serial merging. Represents all elements after parallel processing. Fig.11In the ladder diagram shown, when the isolated element to be tested Y2 does not exist, since the element to be tested M4 is associated with the element to be tested M5, and the output element of the element to be tested M4 is only the element to be tested M5, and the input element of the element to be tested M5 is only the element to be tested M4, it is determined that the element to be tested M4 and the element to be tested M5 are in a series merged relationship, and the element to be tested M2 and the element to be tested M3 are in a series merged relationship. At this time, all the elements to be tested in the ladder diagram can be filled into a binary tree structure. After the filling is completed, the elements to be tested in the binary tree structure are merged, and finally a state with only one input and one output can be achieved. Specifically, the element M2 to be tested and the element M3 to be tested are connected in series and merged to obtain a new element (M2+M3), the element M4 to be tested and the element M5 to be tested are connected in series and merged to obtain a new element (M4+M5), the new element (M2+M3) and (M4+M5) are connected in parallel and merged to obtain a new element (M2+M3)*(M4+M5), and finally the element M1 to be tested, the new element (M2+M3)*(M4+M5) and the element Y1 to be tested are connected in series and merged in sequence to obtain only one new element: =M1+[(M2+M3)*(M4+M5)]+Y1. Therefore, after the merging process, only one input left bus is realized and an output ideal state.

[0125] For ladder diagrams with abnormal paths, isolated elements still exist after merging, which means that the ideal state of having only one output cannot be achieved. Fig.11 In the ladder diagram shown, when the isolated element to be tested Y2 exists, since the output element of the element to be tested M4 includes the tuple to be tested M5 and the element to be tested Y2, and the input element of the element to be tested M5 includes the element to be tested M4 and the element to be tested Y2, the element to be tested M4 and the element to be tested M5 cannot form a series merge relationship, and the element to be tested M5 and the element to be tested Y2 cannot form a parallel merge relationship. At this time, all the elements to be tested in the ladder diagram cannot be filled into a binary tree structure, and after the merge process, an output state cannot be obtained.

[0126] In some embodiments, the step S42 can be replaced by: merging the multiple elements to be tested according to the merging relationship and the connection order in the node graph to generate new elements to be tested, and filling the new elements to be tested into a binary tree structure. Fig.12In the node diagram shown, the output of the left bus is connected to the input of the element to be measured M1, the output of the element to be measured M1 is respectively connected to the inputs of the elements to be measured M2, M3 and M4, the outputs of the elements to be measured M2, M3 and M4 are all connected to the input of the element to be measured M5, and the output of the element to be measured M5 is respectively connected to the input of the element to be measured Y1. Among them, M2 and M3 are in a parallel merge relationship, and M6 and M7 are in a parallel merge relationship. Therefore, the elements to be measured M2 and M3 are processed in parallel and merged to obtain a new element (M2*M3), and the elements to be measured M6 and M7 are processed in parallel and merged to obtain a new element (M6*M7). The resulting node diagram is as follows Fig.13 As shown. Fig.13 In the node diagram shown, M4 and (M2*M3) are in parallel merge relationship. Therefore, the element to be tested M4 and (M2*M3) are parallel merged to obtain a new element (M2*M3*M4). The obtained node diagram is as follows: Fig.14 At this time, based on Fig.14 The node graph in fills the new elements to be tested into the binary tree structure.

[0127] Please refer to Fig.15 , Embodiment 2 of the present invention is:

[0128] A PLC ladder diagram detection terminal 100 includes a memory 101, a processor 102, and a computer program stored in the memory 101 and running on the processor 102. When the processor 102 executes the computer program, each step of a PLC ladder diagram detection method in embodiment 1 is implemented.

[0129] In summary, the present invention provides a PLC ladder diagram detection method and terminal, obtains the elements to be tested and the connection relationship of the ladder diagram, determines the input elements and output elements of each element to be tested based on the connection relationship, thereby detecting whether the current ladder diagram has a circuit break, that is, using the characteristics of the circuit break data structure, the detection of the circuit break problem is completed when the element to be tested is in a discrete state. If there is no circuit break in the ladder diagram, the elements to be tested are associated through the connection relationship to form a node graph, and the node graph and the input and output elements are filled into the binary tree structure. In the filling process, the merge processing is performed based on the merge relationship between the elements to be tested, thereby simplifying the binary tree structure and improving the traversal detection efficiency. The present invention converts discrete ladder diagram elements into a structure with input and output information, and fills them into the binary tree by merging for detection. If the ladder diagram elements can all be filled into the binary tree, it means that the ladder diagram path is normal. This detection method can not only cover complex logical structures, but also accurately describe the data structure of the ladder diagram, thereby improving the detection accuracy. And this detection method does not need to exhaust all the possibilities of errors, the implementation logic is simple, and the detection efficiency is high.

[0130] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A PLC ladder diagram detection method, characterized in that: include: Acquire a data structure of a ladder diagram, wherein the data structure includes a plurality of elements to be tested and connection relationships; Determine the input element and the output element of each of the elements to be tested according to the connection relationship, and detect whether there is a circuit break in the ladder diagram; If not, the plurality of elements to be tested are associated according to the connection relationship to obtain a node graph; Filling the plurality of elements to be tested into a binary tree structure according to the input elements, the output elements and the node graph; Detecting whether the plurality of elements to be tested are all filled into the nodes of the binary tree structure, if not, there is a path abnormality in the ladder diagram; The data structure for obtaining the ladder diagram includes: Traversing a two-dimensional array storing a data structure of the ladder diagram; Extract all non-empty array elements in the two-dimensional array to obtain the elements to be tested, and extract the indexes of the non-empty array elements pointing to other array elements to obtain the connection relationship; The detecting whether the ladder diagram has a circuit break comprises: Check whether the other array elements pointed to by the index are empty results; If so, there is a circuit break in the ladder diagram; Otherwise, there is no open circuit in the ladder diagram; The step of filling the plurality of elements to be tested into a binary tree structure according to the input elements, the output elements and the node graph comprises: Traversing the node graph, comparing the input elements and the output elements of any two elements to be tested, and determining a merging relationship between the two elements to be tested according to the comparison result; Filling the plurality of elements to be tested into a binary tree structure in sequence according to the merging relationship and the connection order in the node graph; After determining the merging relationship between the two elements to be tested according to the comparison result, the method further includes: The ladder diagram is detected to determine whether there is a short circuit according to the input elements and output elements of each element to be tested; if so, the detection is terminated and a prompt is given that there is a path abnormality in the current ladder diagram; if not, the multiple elements to be tested are sequentially filled into a binary tree structure according to the merging relationship and the connection order in the node diagram.

2. A PLC ladder diagram detection method according to claim 1, characterized in that: The step of determining the input element and the output element of each of the elements to be tested according to the connection relationship comprises: If the other array element pointed to by the index is the element to be tested, then the non-empty array element corresponding to the index is marked as the input element of the element to be tested; If the non-empty array element corresponding to the index is the element to be tested, then other array elements pointed to by the index are marked as output elements of the element to be tested.

3. A PLC ladder diagram detection method according to claim 1, characterized in that: The step of comparing the input element and the output element of any two elements to be tested, and determining the merging relationship between the two elements to be tested according to the comparison result includes: Detecting whether the input elements and the output elements of any two elements to be tested are the same; If so, it is determined that the two elements to be tested are in a parallel merge relationship.

4. A PLC ladder diagram detection method according to claim 3, characterized in that: The step of comparing the input element and the output element of any two elements to be tested and determining the merging relationship between the two elements to be tested according to the comparison result further includes: Detecting whether the two elements to be detected are associated and whether the input element or the output element of one element to be detected only includes the other element to be detected; If so, it is determined that the two elements to be tested are in a series merge relationship.

5. A PLC ladder diagram detection method according to claim 4, characterized in that: The step of sequentially filling the plurality of elements to be tested into a binary tree structure according to the merging relationship and the connection order in the node graph includes: In a binary tree structure, if the merging relationship is a parallel merging relationship, a parallel root node is generated in the binary tree structure, and two elements to be tested corresponding to the parallel merging relationship are respectively filled as child nodes of the parallel root node; If the merging relationship is a serial merging relationship, a serial root node is generated in the binary tree structure, and two elements to be tested corresponding to the serial merging relationship are respectively filled as child nodes of the serial root node; The parallel root nodes and the series root nodes are sequentially connected according to the connection order in the node graph to form a binary tree group.

6. A PLC ladder diagram detection method according to claim 5, characterized in that: Before detecting whether the plurality of elements to be tested are all filled into the nodes of the binary tree structure, the method further includes: Traverse each node in the binary tree structure, and perform corresponding merging processing on the nodes in the binary tree structure filled with the elements to be tested according to the parallel root node and the series root node to generate a new binary tree structure, until the new binary tree structure can no longer perform the merging processing, then detect whether the multiple elements to be tested are all filled into the nodes of the binary tree structure.

7. A PLC ladder diagram detection terminal, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, each step in the PLC ladder diagram detection method as described in any one of claims 1 to 6 is implemented.

Images