An etching method for forming a through silicon via

Abstract

The present invention provides an etching method for forming a through silicon via, the etching method comprising the following steps: (1) using a mixture of a gaseous fluorine source and an inert gas to perform pre-etching treatment on a silicon wafer to obtain a pre-etched silicon wafer; (2) using a first Bosch etching process to etch the pre-etched silicon wafer obtained in step (1) to obtain a one-step etched silicon wafer; (3) using a second Bosch etching process to etch the one-step etched silicon wafer obtained in step (2) to obtain a two-step etched silicon wafer; (4) using a bottom etching process to etch the two-step etched silicon wafer obtained in step (3) to complete etching. The present invention forms a through silicon via by combining pre-etching with a three-step etching process, which can not only achieve a larger aspect ratio of the through silicon via structure, but also improve the etching morphology and side wall roughness, thereby alleviating the problem of a sharp increase in the top side wall roughness caused by the instability of the sheath layer at the beginning of etching.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor processing and relates to an etching method for forming a through silicon via. Background Art

[0002] Through silicon via (TSV) technology is a new technical solution for interconnecting stacked chips in three-dimensional integrated circuits. Since TSV technology can make the chips stacked in three dimensions with high density, short interconnection lines between chips and small dimensions, it can effectively realize this three-dimensional chip stacking and manufacture chips with more complex structures, stronger performance and more cost-effectiveness. Therefore, it has become a technology that attracts attention in current electronic packaging technology.

[0003] The Bosch process is widely used in the manufacture of vertical interconnect structures of 3D integrated circuit through silicon vias (TSVs). The so-called Bosch process refers to a process that etches the semiconductor substrate deeply in the vertical direction by periodically repeating the plasma etching process and the plasma deposition process. However, this method is prone to sidewall roughness caused by periodic etching / passivation. Sidewall roughness will significantly affect the coverage of dielectric and metal steps and via filling, and affect the leakage performance between vias.

[0004] CN103646917A discloses a method for forming a through silicon via, comprising: obtaining a first etching stage and a second etching stage according to the through silicon via to be formed; at a first etching temperature, in the first etching stage, etching the silicon substrate by a first Bosch process to form a first through hole; at a second etching temperature, in the second etching stage, etching the silicon substrate along the first through hole by a second Bosch process until a through silicon via is formed, wherein the second Bosch process comprises: etching the silicon substrate by a first etching process to form an opening; forming a protective layer on the sidewall and bottom of the opening by a passivation deposition; cyclically adopting the first etching and the passivation deposition in sequence until a through silicon via is formed; wherein the second etching temperature is less than the first etching temperature, or the second etching temperature is greater than the first etching temperature.

[0005] CN105826239A discloses a method for forming a through silicon via, belonging to the field of semiconductor manufacturing process technology, including providing a semiconductor substrate; forming a mask layer with an opening on the semiconductor substrate; etching the semiconductor substrate using a first Bosch etching process to form a first groove in the semiconductor substrate below the opening, and the mask layer protrudes from the side wall of the first groove; etching the semiconductor substrate at the bottom of the first groove using a second Bosch etching process to form a second groove; the width of the first groove is greater than the width of the second groove.

[0006] The method for forming a through silicon via described in the above scheme results in a rough inner wall of the through silicon via, and a shrinkage cavity will appear at the bottom, which affects the aspect ratio of the through hole and causes its performance to decrease. Therefore, it is necessary to reduce the side wall roughness by studying the process method to improve the high frequency performance of the device and reduce the insertion loss. Summary of the invention

[0007] The purpose of the present invention is to provide an etching method for forming a through silicon via. The present invention forms a through silicon via by combining pre-etching with a three-stage etching process, which can not only make the through silicon via structure have a larger aspect ratio, but also improve the etching morphology and side wall roughness, thereby alleviating the problem of a sharp increase in the top side wall roughness caused by the instability of the top sheath layer.

[0008] In order to achieve the purpose of the invention, the present invention adopts the following technical solutions:

[0009] In a first aspect, the present invention provides an etching method for forming a through silicon via, the etching method comprising the following steps:

[0010] (1) Pre-etching a silicon wafer using a mixture of a gaseous fluorine source and an inert gas to obtain a pre-etched silicon wafer;

[0011] (2) etching the pre-etched silicon wafer obtained in step (1) using the first Bosch etching process to obtain a one-step etched silicon wafer;

[0012] (3) etching the one-step etched silicon wafer obtained in step (2) using the second Bosch etching process to obtain a two-step etched silicon wafer;

[0013] (4) etching the two-step etched silicon wafer obtained in step (3) using a bottom etching process to complete etching;

[0014] Wherein, the first Bosch etching process and the second Bosch etching process independently include at least one cyclic step of passivation deposition, cleaning and etching;

[0015] The bottom etching process includes at least one cyclic step of cleaning and etching.

[0016] The etching method for forming a through silicon via of the present invention opens the oxide layer on the top of the silicon wafer by pre-etching treatment and introduces fluorine ions to reduce the oxide layer barrier. The present invention performs pre-etching treatment before the first Bosch etching process, improves the stability of the sheath layer, reduces the impact of the instability of the sheath layer, improves the top sidewall morphology, and lays a foundation for the subsequent sidewall morphology. A conventional Bosch process is used for etching to a large extent. Here, due to the foundation of the aforementioned steps, deep etching can be performed to ensure the etching rate. The present invention finally avoids the closing phenomenon and V-shaped morphology caused by etching with a large aspect ratio by a bottom etching method. Etching through this step can expand the bottom, etch the bottom to both sides of the originally closed morphology, and then correct and improve the bottom morphology while ensuring the depth, reduce the closing phenomenon, thereby improving the verticality of the etching morphology, and improving the high aspect ratio limit of the etching. At the same time, an appropriate degree of bottom etching can alleviate the opposition between the etching morphology and the sidewall roughness, and improve the process window.

[0017] During the passivation deposition, cleaning and etching processes of the first Bosch etching process and the second Bosch etching process of the present invention, the pressure, temperature, source power and bias power used are determined according to requirements and may be the same or different.

[0018] Preferably, the gaseous fluorine source in step (1) comprises carbon tetrafluoride.

[0019] Preferably, the inert gas in step (1) includes argon.

[0020] Preferably, in the mixed gas of step (1), the volume ratio of the gaseous fluorine source to the inert gas is (0.5-1.5):1, for example: 0.5:1, 0.8:1, 1:1, 1.2:1 or 1.5:1, etc., and is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0021] Preferably, the temperature of the pre-etching treatment in step (1) is -10°C to 20°C, for example: -10°C, -5°C, 0°C, 10°C or 20°C, etc., and is not limited to the listed values. Other values ​​not listed within the numerical range are also applicable.

[0022] Preferably, the pressure of the pre-etching treatment in step (1) is 1 mtorr to 50 mtorr, for example, 1 mtorr, 10 mtorr, 20 mtorr, 40 mtorr or 50 mtorr, etc., and is not limited to the listed values. Other values ​​not listed within the range are also applicable.

[0023] Preferably, the source power of the pre-etching treatment in step (1) is 500W~1500W, for example: 500W, 800W, 1000W, 1200W or 1500W, etc., not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0024] Preferably, the bias power of the pre-etching treatment in step (1) is 0W~200W, for example: 0W, 10W, 50W, 100W or 200W, etc., not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0025] Preferably, the pre-etching treatment time in step (1) is 1s to 15s, for example, 1s, 3s, 6s, 9s, 12s or 15s, etc., and is not limited to the listed values. Other values ​​not listed within the numerical range are also applicable.

[0026] Preferably, the temperature of the first Bosch etching process in step (2) is -10°C to 20°C, for example: -10°C, -5°C, 0°C, 10°C or 20°C, etc., not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0027] Preferably, in step (2), the pressure of the first Bosch etching process is 30 mtorr to 70 mtorr, for example, 30 mtorr, 40 mtorr, 50 mtorr, 60 mtorr or 70 mtorr, etc., and is not limited to the listed values. Other values ​​not listed within the range are also applicable.

[0028] Preferably, in step (2), the source power of the first Bosch etching process is 500W~2000W, for example: 500W, 800W, 1000W, 1500W or 2000W, etc., not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0029] Preferably, in step (2), the bias power of the first Bosch etching process is 0 W to 200 W, for example, 0 W, 10 W, 50 W, 100 W or 200 W, etc., and is not limited to the listed values. Other values ​​not listed within the numerical range are also applicable.

[0030] Preferably, in the passivation deposition process of the first Bosch etching process in step (2), the passivation gas used includes octafluorocyclobutane.

[0031] Preferably, in the cleaning process of the first Bosch etching process in step (2), the cleaning gas used includes any one of sulfur hexafluoride, oxygen or nitrogen, or a combination of at least two of them. Typical but non-limiting combinations include a combination of sulfur hexafluoride and nitrogen, a combination of oxygen and nitrogen, or a combination of sulfur hexafluoride and oxygen, etc.

[0032] Preferably, in the etching process of the first Bosch etching process in step (2), the etching gas used includes sulfur hexafluoride.

[0033] Preferably, the temperature of the second Bosch etching process in step (3) is 0°C-20°C, for example, 0°C, 1°C, 5°C, 10°C or 20°C, etc., and is not limited to the listed values. Other values ​​not listed within the range are also applicable.

[0034] Preferably, the pressure of the second Bosch etching process in step (3) is 1 mtorr to 100 mtorr, for example, 1 mtorr, 20 mtorr, 40 mtorr, 50 mtorr or 100 mtorr, etc., and is not limited to the listed values. Other values ​​not listed within the range are also applicable.

[0035] Preferably, in step (3), the source power of the second Bosch etching process is 500W~3000W, for example: 500W, 800W, 1000W, 2000W or 3000W, etc., not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0036] Preferably, in step (3), the bias power of the second Bosch etching process is 0 W to 200 W, for example, 0 W, 10 W, 50 W, 100 W or 200 W, etc., and is not limited to the listed values. Other values ​​not listed within the numerical range are also applicable.

[0037] Preferably, in the passivation deposition process of the second Bosch etching process in step (3), the passivation gas used includes octafluorocyclobutane.

[0038] Preferably, in the cleaning process of the second Bosch etching process in step (3), the cleaning gas used includes any one of sulfur hexafluoride, oxygen or nitrogen, or a combination of at least two of them. Typical but non-limiting combinations include a combination of sulfur hexafluoride and nitrogen, a combination of oxygen and nitrogen, or a combination of sulfur hexafluoride and oxygen, etc.

[0039] Preferably, in the etching process of the second Bosch etching process in step (3), the etching gas used includes sulfur hexafluoride.

[0040] Preferably, the temperature of the bottom etching process in step (4) is 0°C~20°C, for example: 0°C, 1°C, 5°C, 10°C or 20°C, etc., not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0041] Preferably, the pressure of the second Bosch etching process in step (3) and the bottom etching process in step (4) is 1 mtorr to 100 mtorr, for example, 1 mtorr, 20 mtorr, 40 mtorr, 50 mtorr or 100 mtorr, etc., and is not limited to the listed values. Other values ​​not listed within the numerical range are also applicable.

[0042] Preferably, the source power of the bottom etching process in step (4) is 500W~3000W, for example: 500W, 800W, 1000W, 2000W or 3000W, etc., not limited to the listed values, other values ​​not listed within the numerical range are also applicable.

[0043] Preferably, the bias power of the bottom etching process in step (4) is 0W~200W, for example: 0W, 10W, 50W, 100W or 200W, etc., not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0044] Preferably, in the cleaning process of the bottom etching process in step (4), the cleaning gas used includes any one of sulfur hexafluoride, oxygen or nitrogen, or a combination of at least two of them. Typical but non-limiting combinations include a combination of sulfur hexafluoride and nitrogen, a combination of oxygen and nitrogen, or a combination of sulfur hexafluoride and oxygen, etc.

[0045] Preferably, during the bottom etching process in step (4), the etching gas used includes sulfur hexafluoride.

[0046] Preferably, the source power of the first Bosch etching process is less than the source power of the second Bosch etching process.

[0047] In the present invention, the source power of the first Bosch etching process is less than the source power of the second Bosch etching process, that is, the source power of a certain step with the same function in the first Bosch etching process and the second Bosch etching process is compared, for example, the source power of the passivation deposition in the first Bosch etching process is less than the source power of the passivation deposition in the second Bosch etching process, and the same applies to the following.

[0048] Preferably, the temperature of the first Bosch etching process is less than the temperature of the second Bosch etching process.

[0049] Preferably, the pressure of the bottom etching process is greater than the pressure of the second Bosch etching process.

[0050] Preferably, the temperature of the bottom etching process is greater than the temperature of the second Bosch etching process.

[0051] Preferably, taking the total etching depth as 100%, the etching depth of the first Bosch etching process is 5% to 10%, for example, 5%, 6%, 8%, 9% or 10%, etc., and is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0052] Preferably, the etching depth of the second Bosch etching process is 85% to 94%, for example, 85%, 88%, 90%, 92% or 94%, etc., and is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0053] Preferably, the etching depth of the bottom etching process is 1% to 5%, for example, 1%, 2%, 3%, 4% or 5%, etc., and is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0054] Compared with the prior art, the present invention has the following beneficial effects:

[0055] (1) The present invention forms a through silicon via by combining a pre-etching process with a three-stage etching process, which can not only achieve a higher aspect ratio of the through silicon via structure, but also improve the etching morphology and side wall roughness, thereby alleviating the problem of rapid expansion of the top side wall roughness caused by the instability of the top sheath layer.

[0056] (2) The etching method of the present invention reduces ion damage during the etching process, prevents side wall roughness caused by ion damage, and avoids affecting device performance and reliability.

[0057] (3) The sidewall roughness depth of the through silicon via obtained by the etching method of the present invention can be within 15.72 nm, and the aspect ratio can be greater than 8. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 This is a SEM slice image of the through hole obtained by the etching method described in Example 1.

[0059] Figure 2 This is a SEM slice image of the side wall of the through hole obtained by the etching method described in Example 1.

[0060] Figure 3 This is a SEM slice image of the through hole obtained by the etching method described in Example 3.

[0061] Figure 4 This is a SEM slice image of the side wall of the through hole obtained by the etching method described in Example 3.

[0062] Figure 5 It is a schematic diagram of the aspect ratio of through silicon via. DETAILED DESCRIPTION

[0063] The technical solution of the present invention is further described below by specific implementation methods. It should be understood by those skilled in the art that the embodiments are only to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0064] Example 1

[0065] This embodiment provides an etching method for forming a through silicon via, the etching method comprising the following steps:

[0066] (1) Pre-etching the silicon wafer using a mixture of carbon tetrafluoride and argon in a volume ratio of 1:1, wherein the pre-etching temperature is -10°C, the pressure is 20 mtorr, the source power is 1000 W, the bias power is 100 W, and the pre-etching time is 12 s;

[0067] (2) etching the pre-etched silicon wafer obtained in step (1) using the first Bosch etching process (60 cycles), wherein the specific operation of each cycle is as follows: using octafluorocyclobutane at -10°C, 60 mtorr pressure, 600 W source power, 20 W bias power for passivation deposition, then using sulfur hexafluoride at -10°C, 50 mtorr pressure, 600 W source power, 100 W bias power for cleaning, and then using sulfur hexafluoride at -10°C, 70 mtorr pressure, 600 W source power, 20 W bias power for etching, to obtain a one-step etched silicon wafer;

[0068] (3) etching the one-step etched silicon wafer obtained in step (2) using the second Bosch etching process (800 cycles), wherein the specific operation of each cycle is as follows: using octafluorocyclobutane at 0°C, 90 mtorr pressure, 3000 W source power, 20 W bias power for passivation deposition, then using sulfur hexafluoride at 0°C, 80 mtorr pressure, 3000 W source power, 100 W bias power for cleaning, and then using sulfur hexafluoride at 0°C, 100 mtorr pressure, 3000 W source power, 0 W bias power for etching, to obtain a two-step etched silicon wafer;

[0069] (4) The two-step etched silicon wafer obtained in step (3) was etched using a bottom etching process (15 cycles). The specific operation of each cycle was as follows: using sulfur hexafluoride at 10°C, 60mtorr pressure, 3000W source power, 100W bias power for cleaning, and then using sulfur hexafluoride at 10°C, 140mtorr pressure, 3000W source power, 0W bias power for etching. After etching, the SEM slice image of the through hole was obtained as shown in FIG. Figure 1 As shown, the SEM slice image of the side wall of the through hole is as follows Figure 2 As shown;

[0070] Wherein, taking the total etching depth as 100%, the etching depth of the first Bosch etching process is 8.5%, the etching depth of the second Bosch etching process is 87.5%, and the etching depth of the bottom etching process is 4%.

[0071] Example 2

[0072] This embodiment provides an etching method for forming a through silicon via, the etching method comprising the following steps:

[0073] (1) Pre-etching the silicon wafer using a mixed gas of carbon tetrafluoride and argon with a volume ratio of 0.8:1, the pre-etching temperature is 0°C, the pressure is 35 mtorr, the source power is 800 W, the bias power is 150 W, and the pre-etching time is 9 s;

[0074] (2) etching the pre-etched silicon wafer obtained in step (1) using the first Bosch etching process (45 cycles), wherein the specific operation of each cycle is as follows: using octafluorocyclobutane at 0°C, 50 mtorr pressure, 800 W source power, 10 W bias power for passivation deposition, then using sulfur hexafluoride at 0°C, 60 mtorr pressure, 800 W source power, 80 W bias power for cleaning, and then using sulfur hexafluoride at 0°C, 70 mtorr pressure, 800 W source power, 10 W bias power for etching, to obtain a one-step etched silicon wafer;

[0075] (3) etching the one-step etched silicon wafer obtained in step (2) using the second Bosch etching process (600 cycles), wherein the specific operation of each cycle is as follows: using octafluorocyclobutane at 10° C., 80 mtorr pressure, 2500 W source power, 10 W bias power for passivation deposition, then using sulfur hexafluoride at 10° C., 70 mtorr pressure, 2500 W source power, 80 W bias power for cleaning, and then using sulfur hexafluoride at 10° C., 90 mtorr pressure, 2500 W source power, 10 W bias power for etching, to obtain a two-step etched silicon wafer;

[0076] (4) etching the two-step etched silicon wafer obtained in step (3) using a bottom etching process (12 cycles), wherein each cycle is performed as follows: cleaning is performed using sulfur hexafluoride at 15° C., 70 mtorr pressure, 2500 W source power, 80 W bias power, and then etching is performed using sulfur hexafluoride at 15° C., 120 mtorr pressure, 2500 W source power, 10 W bias power, to complete etching;

[0077] Wherein, taking the total etching depth as 100%, the etching depth of the first Bosch etching process is 6%, the etching depth of the second Bosch etching process is 91.5%, and the etching depth of the bottom etching process is 2.5%.

[0078] Example 3

[0079] This embodiment provides an etching method for forming a through silicon via, the etching method comprising the following steps:

[0080] (1) Pre-etching the silicon wafer using a mixture of carbon tetrafluoride and argon with a volume ratio of 0.6, the pre-etching temperature is 10° C., the pressure is 50 mtorr, the source power is 600 W, the bias power is 200 W, and the pre-etching time is 6 s;

[0081] (2) etching the pre-etched silicon wafer obtained in step (1) by using the first Bosch etching process (30 cycles), wherein the specific operation of each cycle is as follows: using octafluorocyclobutane at 10° C., 40 mtorr pressure, 1000 W source power, 0 W bias power for passivation deposition, then using sulfur hexafluoride at 10° C., 70 mtorr pressure, 1000 W source power, 60 W bias power for cleaning, and then using sulfur hexafluoride at 10° C., 70 mtorr pressure, 1000 W source power, 0 W bias power for etching, to obtain a one-step etched silicon wafer;

[0082] (3) etching the one-step etched silicon wafer obtained in step (2) using the second Bosch etching process (400 cycles), wherein the specific operation of each cycle is as follows: using octafluorocyclobutane at 20° C., 70 mtorr pressure, 2000 W source power, 0 W bias power for passivation deposition, then using sulfur hexafluoride at 20° C., 60 mtorr pressure, 2000 W source power, 60 W bias power for cleaning, and then using sulfur hexafluoride at 20° C., 80 mtorr pressure, 2000 W source power, 20 W bias power for etching, to obtain a two-step etched silicon wafer;

[0083] (4) etching the two-step etched silicon wafer obtained in step (3) using a bottom etching process (9 cycles), wherein each cycle is performed as follows: cleaning is performed using sulfur hexafluoride at 20° C., 80 mtorr pressure, 2000 W source power, 60 W bias power, and then etching is performed using sulfur hexafluoride at 20° C., 100 mtorr pressure, 2000 W source power, 20 W bias power, to complete etching;

[0084] Wherein, taking the total etching depth as 100%, the etching depth of the first Bosch etching process is 5%, the etching depth of the second Bosch etching process is 94%, and the etching depth of the bottom etching process is 1%.

[0085] Example 4

[0086] The difference between this embodiment and the first embodiment is that the temperature of the first Bosch etching process = the temperature of the second Bosch etching process = 0° C., and other conditions and parameters are exactly the same as those of the first embodiment.

[0087] Example 5

[0088] The only difference between this embodiment and the first embodiment is that the temperature of the first Bosch etching process is 5° C., and the other conditions and parameters are exactly the same as those of the first embodiment.

[0089] Example 6

[0090] The only difference between this embodiment and Embodiment 1 is that the source power of the first Bosch etching process = the source power of the second Bosch etching process = 3000 W, and other conditions and parameters are exactly the same as those in Embodiment 1.

[0091] Example 7

[0092] The only difference between this embodiment and Embodiment 1 is that the source power of the first Bosch etching process is 1000 W, and the other conditions and parameters are exactly the same as those of Embodiment 1.

[0093] Example 8

[0094] The only difference between this embodiment and the first embodiment is that the pressure of the bottom etching process = the pressure of the second Bosch etching process = 100 mtorr, and the other conditions and parameters are exactly the same as those in the first embodiment.

[0095] Example 9

[0096] The only difference between this embodiment and embodiment 1 is that the pressure of the bottom etching process is 30 mtorr, and other conditions and parameters are exactly the same as those in embodiment 1.

[0097] Example 10

[0098] The difference between this embodiment and the first embodiment is that the temperature of the bottom etching process = the temperature of the second Bosch etching process = 0° C., and other conditions and parameters are exactly the same as those of the first embodiment.

[0099] Embodiment 11

[0100] The only difference between this embodiment and embodiment 1 is that the temperature of the bottom etching process is -5°C, and other conditions and parameters are exactly the same as those in embodiment 1.

[0101] Comparative Example 1

[0102] The only difference between this comparative example and Example 1 is that no pre-etching process is performed, and other conditions and parameters are exactly the same as those in Example 1.

[0103] Comparative Example 2

[0104] The only difference between this comparative example and Example 1 is that no bottom etching process is performed, and other conditions and parameters are exactly the same as those in Example 1.

[0105] Comparative Example 3

[0106] The only difference between this comparative example and Example 1 is that no pre-etching treatment and bottom etching treatment are performed, and only two-stage Bosch process is used for etching. Other conditions and parameters are exactly the same as those in Example 1. The SEM slice image of the through hole is as follows: Figure 3 As shown, the SEM slice image of the side wall of the through hole is as follows Figure 4 shown.

[0107] Comparative Example 4

[0108] The only difference between this comparative example and Example 1 is that the etching gas in step (1) is only carbon tetrafluoride, and no argon is added. The other conditions and parameters are exactly the same as those in Example 1.

[0109] Performance Test:

[0110] The roughness depth and aspect ratio of the through silicon via are obtained by testing the embodiment and the comparative example (the width of the aspect ratio is the width of the through hole. Since etching will cause a shrinkage phenomenon at the bottom, the depth is the minimum depth from the opening to the vertical part of the bottom, as shown in the schematic diagram Figure 5 As shown in Table 1, b is the width and d is the depth.

[0111] Table 1

[0112]

[0113] It can be seen from Table 1 that according to Examples 1-3, the roughness depth of the sidewall of the through silicon via obtained by the etching method of the present invention can reach within 15.72 nm, and the aspect ratio can reach more than 15.

[0114] By comparing Example 1 with Examples 4-5, it can be seen that in the etching process for forming silicon through vias described in the present invention, the temperature of the first Bosch etching process is controlled to be less than the temperature of the second Bosch etching process, and the etching effect is better. If the temperature of the first Bosch etching process is too high, it will lead to instability in the formation of the top sheath layer and weak protection of the top sidewall, thereby causing certain damage to the top sidewall morphology.

[0115] By comparing Example 1 with Examples 6-7, it can be seen that in the etching process for forming silicon through vias described in the present invention, the source power of the first Bosch etching process is controlled to be less than the source power of the second Bosch etching process, and the etching effect is better. If the source power of the first Bosch etching process is too high, the top morphology will be excessively damaged due to the high degree of dissociation of the etching gas at the top.

[0116] By comparing Example 1 with Examples 8-9, it can be seen that in the etching process for forming silicon through vias described in the present invention, the pressure of the bottom etching process is controlled to be greater than the pressure of the second Bosch etching process, and the etching effect is better. If the pressure of the bottom etching process is too low, it is difficult for ions to enter and exit the groove, resulting in a closing of the top morphology, which in turn leads to a decrease in the actual effective aspect ratio.

[0117] By comparing Example 1 with Examples 10-11, it can be seen that in the etching process for forming silicon through vias described in the present invention, the temperature of the bottom etching process is controlled to be greater than the temperature of the second Bosch etching process, and the etching effect is better. If the temperature of the bottom etching process is too low, it will lead to excessive accumulation of top deposits, aggravate the bottom closing phenomenon, and significantly reduce the effective aspect ratio.

[0118] By comparing Example 1 and Comparative Example 1, it can be seen that the present invention performs a pre-etching treatment before the first Bosch etching process. The pre-etching treatment opens the oxide layer on the top of the silicon wafer and introduces fluorine ions to reduce the oxide layer barrier, thereby improving the stability of the sheath layer, reducing the impact of the instability of the sheath layer, and improving the top sidewall morphology, which lays a foundation for maintaining the subsequent sidewall morphology.

[0119] By comparing Example 1 and Comparative Example 2, it can be seen that the present invention can expand the bottom morphology through bottom etching, reduce the closing phenomenon, improve the verticality and aspect ratio, and the appropriate degree of bottom etching can alleviate the opposition between the etching morphology and the sidewall roughness, thereby improving the process window.

[0120] The SEM slice image of the through hole obtained by the method described in the embodiment is as follows Figure 1 As shown, the SEM slice image of the side wall of the through hole is as follows Figure 2 As shown, the SEM slice image of the through hole obtained by the method described in Comparative Example 3 is as follows Figure 3 As shown, the SEM slice image of the side wall of the through hole is as follows Figure 4 As shown, by comparing Example 1 and Comparative Example 3, the present invention forms a through silicon via by combining a pre-etching + a three-stage etching process, which can not only make the through silicon via structure have a larger aspect ratio, but also improve the etching morphology and side wall roughness, thereby alleviating the problem of a sharp increase in the roughness of the top side wall of the morphology caused by the instability of the top sheath layer.

[0121] From the comparison between Example 1 and Comparative Example 4, it can be seen that in the present invention, argon is added to the etching gas in the pre-etching treatment, and an appropriate proportion of argon can act as a carrier gas therein, thereby promoting the accumulation of top deposits and protecting the side walls to a certain extent.

[0122] The applicant declares that the above is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention shall fall within the protection scope and disclosure scope of the present invention.

Claims

1. An etching method for forming a through silicon via, characterized in that: The etching method comprises the following steps: (1) Pre-etching a silicon wafer using a mixture of a gaseous fluorine source and an inert gas to obtain a pre-etched silicon wafer; (2) etching the pre-etched silicon wafer obtained in step (1) using the first Bosch etching process to obtain a one-step etched silicon wafer; (3) etching the one-step etched silicon wafer obtained in step (2) using the second Bosch etching process to obtain a two-step etched silicon wafer; (4) etching the two-step etched silicon wafer obtained in step (3) using a bottom etching process to complete etching; Wherein, the first Bosch etching process and the second Bosch etching process independently include at least one cyclic step of passivation deposition, cleaning and etching; The bottom etching process includes at least one cycle step of cleaning and etching; In step (1), the gaseous fluorine source includes carbon tetrafluoride, the inert gas includes argon, and in the mixed gas, the volume ratio of the gaseous fluorine source to the inert gas is (0.5-1.5):

1.

2. The etching method according to claim 1, characterized in that: The temperature of the pre-etching treatment in step (1) is -10°C to 20°C.

3. The etching method according to claim 1, characterized in that: The pressure of the pre-etching treatment in step (1) is 1 mtorr~50 mtorr.

4. The etching method according to claim 1, characterized in that: The source power of the pre-etching process in step (1) is 500W~1500W.

5. The etching method according to claim 1, characterized in that: The bias power of the pre-etching process in step (1) is 0W~200W.

6. The etching method according to claim 1, characterized in that: The pre-etching treatment time in step (1) is 1s to 15s.

7. The etching method according to claim 1, characterized in that: Step (2) The temperature of the first Bosch etching process is -10°C to 20°C.

8. The etching method according to claim 1, characterized in that: Step (2) The pressure of the first Bosch etching process is 30 mtorr~70 mtorr.

9. The etching method according to claim 1, characterized in that: Step (2) The source power of the first Bosch etching process is 500W~2000W.

10. The etching method according to claim 1, characterized in that: Step (2) The bias power of the first Bosch etching process is 0W~200W.

11. The etching method according to claim 1, characterized in that: Step (2) During the passivation deposition process of the first Bosch etching process, the passivation gas used includes octafluorocyclobutane.

12. The etching method according to claim 1, characterized in that: In step (2), during the cleaning process of the first Bosch etching process, the cleaning gas used includes any one of sulfur hexafluoride, oxygen or nitrogen, or a combination of at least two of them.

13. The etching method according to claim 1, characterized in that: Step (2) During the etching process of the first Bosch etching process, the etching gas used includes sulfur hexafluoride.

14. The etching method according to claim 1, characterized in that: Step (3) The temperature of the second Bosch etching process is 0°C to 20°C.

15. The etching method according to claim 1, characterized in that: In step (3), the pressure of the second Bosch etching process is 1 mtorr to 100 mtorr.

16. The etching method according to claim 1, characterized in that: Step (3) The source power of the second Bosch etching process is 500W~3000W.

17. The etching method according to claim 1, characterized in that: Step (3) The bias power of the second Bosch etching process is 0W~200W.

18. The etching method according to claim 1, characterized in that: Step (3) During the passivation deposition process of the second Bosch etching process, the passivation gas used includes octafluorocyclobutane.

19. The etching method according to claim 1, characterized in that: Step (3) During the cleaning process of the second Bosch etching process, the cleaning gas used includes any one of sulfur hexafluoride, oxygen or nitrogen, or a combination of at least two of them.

20. The etching method according to claim 1, characterized in that: Step (3) During the etching process of the second Bosch etching process, the etching gas used includes sulfur hexafluoride.

21. The etching method according to claim 1, characterized in that: The temperature of the bottom etching process in step (4) is 0°C~20°C.

22. The etching method according to claim 1, characterized in that: The pressure of the second Bosch etching process in step (3) and the bottom etching process in step (4) is 1 mtorr to 100 mtorr.

23. The etching method according to claim 1, characterized in that: The source power of the bottom etching process in step (4) is 500W~3000W.

24. The etching method according to claim 1, characterized in that: The bias power of the bottom etching process in step (4) is 0W~200W.

25. The etching method according to claim 1, characterized in that: In the cleaning process of the bottom etching process in step (4), the cleaning gas used includes any one of sulfur hexafluoride, oxygen or nitrogen, or a combination of at least two of them.

26. The etching method according to claim 1, characterized in that: In the bottom etching process of step (4), the etching gas used includes sulfur hexafluoride.

27. The etching method according to claim 1, characterized in that: The source power of the first Bosch etching process is less than the source power of the second Bosch etching process.

28. The etching method according to claim 1, characterized in that: The temperature of the first Bosch etching process is less than the temperature of the second Bosch etching process.

29. The etching method according to claim 1, characterized in that: The pressure of the bottom etching process is greater than the pressure of the second Bosch etching process.

30. The etching method according to claim 1, characterized in that: The temperature of the bottom etching process is greater than the temperature of the second Bosch etching process.

31. The etching method according to claim 1, characterized in that: Taking the total etching depth as 100%, the etching depth of the first Bosch etching process is 5% to 10%.

32. The etching method according to claim 31, characterized in that: The etching depth of the second Bosch etching process is 85%~94%.

33. The etching method according to claim 31, characterized in that: The etching depth of the bottom etching process is 1% to 5%.

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