Semiconductor chip and method for manufacturing the same

Abstract

The present invention provides a semiconductor chip and a manufacturing method thereof, wherein the semiconductor chip comprises: a substrate, wherein the top of the substrate comprises at least one well region, wherein the top of the well region comprises a metal silicide region arranged at intervals; a buried oxide layer arranged on the surface of the substrate; an active silicon layer arranged on the surface of the buried oxide layer; a polysilicon column structure, wherein the polysilicon column structure extends from the surface of the buried oxide layer to the surface of the metal silicide region, wherein at the top of a well region, the polarities of the polysilicon column structures on the surface of the metal silicide region arranged at intervals are different; and a metal plug, wherein the metal plug extends from the surface of the active silicon layer to the top of the polysilicon column structure; wherein, on the well region, the top of the polysilicon column structure with different polarities is externally connected to a power source to form a closed conductive loop. The present invention can achieve heat dissipation of a local high-temperature region of a chip, and can also reduce the space volume required for heat dissipation treatment of the chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor chip and a manufacturing method thereof. Background Art

[0002] High-performance chips generate a lot of heat during operation. Excessive temperature will reduce the performance and stability of the chip. In the prior art, a heat sink is usually used to reduce the chip temperature. There are air cooling and more efficient liquid cooling. In addition, integrated circuit thermal management technology, including chip built-in temperature sensors, dynamic thermal management, active cooling technology, etc., can also help improve the heat dissipation efficiency of the chip.

[0003] However, the high temperature of the chip only occurs in a local area of ​​the chip. The heat dissipation method of the existing technology is to dissipate the heat of the chip as a whole, but it is unable to effectively dissipate the heat of the local high temperature area of ​​the chip, resulting in that the heat dissipation performance still needs to be improved. Summary of the invention

[0004] The present invention provides a semiconductor chip and a manufacturing method thereof, so as to solve the technical problem in the prior art that the local high temperature area of ​​the chip cannot be effectively cooled.

[0005] The present invention provides a semiconductor chip, comprising:

[0006] A substrate, wherein the top of the substrate includes at least one well region, and the top of the well region includes a metal silicide region arranged at intervals;

[0007] A buried oxide layer is disposed on the surface of the substrate;

[0008] An active silicon layer is disposed on the surface of the buried oxide layer;

[0009] a polysilicon column structure, wherein the polysilicon column structure extends from the surface of the buried oxide layer to the surface of the metal silicide region, and the polarities of the polysilicon column structures on the surface of the metal silicide region arranged at intervals at the top of one of the well regions are different; and

[0010] A metal plug extending from a surface of the active silicon layer to a top of the polysilicon column structure;

[0011] Wherein, on the well region, the top of the polysilicon column structure with different polarities is externally connected to a power source to form a closed conductive loop to transfer the heat at the top of the polysilicon column structure to the bottom of the polysilicon column structure.

[0012] In one embodiment of the present invention, the semiconductor chip further includes:

[0013] a deep trench isolation structure, disposed outside the well region, the deep trench isolation structure extending from the surface of the active silicon layer into the substrate; and

[0014] A shallow trench isolation structure is arranged outside the metal plug, and the shallow trench isolation structure extends from the surface of the active silicon layer to the surface of the buried oxide layer.

[0015] In one embodiment of the present invention, when the number of the well region is one, the deep trench isolation structure is disposed outside the well region;

[0016] When the number of the well regions is at least two, two adjacent well regions share the same deep trench isolation structure, or the deep trench isolation structures are respectively disposed outside at least two of the well regions.

[0017] In one embodiment of the present invention, the semiconductor chip further includes a heat sink, and the heat sink is disposed at the bottom of the substrate.

[0018] In one embodiment of the present invention, on the surfaces of two adjacent metal silicide regions in the same well region, the polysilicon column structure on the surface of one metal silicide region is a P-type polysilicon column structure, and the top of the P-type polysilicon column structure is externally connected to an input terminal of a current;

[0019] Another polysilicon column structure on the surface of the metal silicide region is an N-type polysilicon column structure, and the top of the N-type polysilicon column structure is externally connected to an output terminal of the current.

[0020] In one embodiment of the present invention, the top of the well region includes two metal silicide regions, and on the same side of at least two of the well regions, the polysilicon column structure on the surface of the metal silicide region is a P-type polysilicon column structure;

[0021] On the same other side of at least two of the well regions, the polysilicon column structure on the surface of the metal silicide region is an N-type polysilicon column structure.

[0022] The present invention also provides a method for manufacturing a semiconductor chip, comprising:

[0023] Providing a substrate, forming at least one well region on the top of the substrate, and forming a metal silicide region spaced apart on the top of the well region;

[0024] forming a buried oxide layer on the surface of the substrate;

[0025] A polysilicon column structure is formed from the surface of the metal silicide region to the surface of the buried oxide layer, wherein the polysilicon column structure with different polarities is formed on the surface of the metal silicide region spaced apart at the top of one of the well regions;

[0026] forming an active silicon layer on the surface of the buried oxide layer;

[0027] forming a metal plug from the top of the polysilicon column structure to the surface of the active silicon layer;

[0028] Wherein, on the well region, the polysilicon column structures with different polarities are externally connected to a power source to form a closed conductive loop to transfer the heat at the top of the polysilicon column structure to the bottom of the polysilicon column structure.

[0029] In one embodiment of the present invention, after the step of forming a metal plug from the top of the polysilicon column structure to the surface of the active silicon layer, the method further comprises:

[0030] On the outside of the well region, a deep trench isolation structure is formed from the surface of the active silicon layer to the inside of the substrate;

[0031] A shallow trench isolation structure is formed outside the metal plug from the surface of the active silicon layer to the surface of the buried oxide layer.

[0032] In one embodiment of the present invention, the step of forming a deep trench isolation structure outside the well region from the surface of the active silicon layer to the substrate includes:

[0033] When the number of the well region is one, a deep trench isolation structure is formed outside the well region from the surface of the active silicon layer to the inside of the substrate;

[0034] When the number of the well regions is at least two, deep trench isolation structures are respectively formed on the outer sides of at least two of the well regions, or the same deep trench isolation structure is formed on the side where two adjacent well regions are close to each other, and different deep trench isolation structures are respectively formed on the side where two adjacent well regions are far away from each other.

[0035] In one embodiment of the present invention, after the step of forming a metal plug from the top of the polysilicon column structure to the surface of the active silicon layer, the method further comprises:

[0036] A heat sink is disposed at the bottom of the substrate.

[0037] Beneficial effects of the invention: A semiconductor chip and a manufacturing method thereof proposed in the invention can improve the problem that the heat insulation effect in the chip is not conducive to heat dissipation, and a semiconductor chip with a cooling effect is integrated into the chip to achieve heat dissipation in the local high-temperature area of ​​the chip. In addition, the space volume required for heat dissipation of the chip can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0039] Figure 1 A schematic diagram of a semiconductor chip provided according to an embodiment of the present invention.

[0040] Figure 2 A working principle diagram of heat dissipation of a semiconductor chip provided by an embodiment of the present invention.

[0041] Figure 3 A schematic diagram of forming a heat sink at the bottom of a substrate according to an embodiment of the present invention.

[0042] Figure 4 A schematic diagram of a semiconductor chip provided according to yet another embodiment of the present invention.

[0043] Figure 5 A schematic flow chart of a method for manufacturing a semiconductor chip provided by an embodiment of the present invention.

[0044] Figure 6 A schematic diagram of forming a well region and a metal silicide region on the top of a substrate provided by an embodiment of the present invention.

[0045] Figure 7 A schematic diagram of forming a buried oxide layer on the surface of a substrate provided by an embodiment of the present invention.

[0046] Figure 8 A schematic diagram of forming a trench in a buried oxide layer according to an embodiment of the present invention.

[0047] Fig. 9 A schematic diagram of forming a polysilicon pillar structure in a trench of a buried oxide layer according to an embodiment of the present invention.

[0048] Fig.10 A schematic diagram of forming an active silicon layer on the surface of a buried oxide layer according to an embodiment of the present invention.

[0049] Fig.11 A schematic diagram of forming a metal plug on an active silicon layer according to an embodiment of the present invention.

[0050] Description of Figure Numbers

[0051] 10. Substrate; 110. Well region; 120. Metal silicide region; 20. Buried oxide layer; 30. Active silicon layer; 40. Polysilicon column structure; 410. N-type polysilicon column structure; 420. P-type polysilicon column structure; 430. Metal plug; 440. Trench; 510. Deep trench isolation structure; 520. Shallow trench isolation structure; 60. Current flow direction; 70. Heat dissipation direction; 80. Heat sink; 90. Power supply. DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0053] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0054] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0055] See also Figures 1 to 11 The present invention proposes a semiconductor chip and a method for manufacturing the same, which can be applied to the heat dissipation field of semiconductor high-performance chips, such as the heat dissipation of silicon on insulator (SOI) process chips and three-dimensional (3D) process chips. The present invention can integrate a cooling device in the chip, and can reduce the space volume of the entire system while improving the heat dissipation performance of the local high-temperature area of ​​the chip. The following is a detailed description through specific embodiments.

[0056] See also Figure 1In one embodiment of the present invention, a semiconductor chip is provided, which may include a substrate 10, a buried oxide layer 20, an active silicon layer 30, a polysilicon column structure 40 and a metal plug 430. The buried oxide layer (BOX) 20 is disposed on the surface of the substrate 10, and the active silicon layer 30 is disposed on the surface of the buried oxide layer 20. The top active silicon layer 30, the middle buried oxide layer 20, and the bottom supporting silicon substrate form a silicon-on-insulator structure.

[0057] In one embodiment of the present invention, Figure 1 As shown, the top of the substrate 10 includes at least one well region 110. Figure 1 A schematic diagram of two well regions 110 being arranged on the top of the substrate 10 is given in FIG. One well region 110 may be arranged on the top of the substrate 10, and three or more well regions 110 may be arranged on the top of the substrate 10. At least two metal silicide regions (Salicide, Self-aligned silicide) 120 may be included on the top of a well region 110, and at least two metal silicide regions 120 may be arranged at intervals from each other.

[0058] Specifically, the polysilicon column structure 40 extends from the surface of the buried oxide layer 20 to the surface of the metal silicide region 120. At the top of a well region 110, the polysilicon column structures 40 on the surface of the metal silicide regions 120 arranged at intervals have different polarities. The metal plug 430 extends from the surface of the active silicon layer 30 to the top of the polysilicon column structure 40. On the well region 110, the top of the polysilicon column structure 40 with different polarities is externally connected to a power source 90 to form a closed conductive loop to transfer the heat at the top of the polysilicon column structure 40 to the bottom of the polysilicon column structure 40.

[0059] In one embodiment of the present invention, Figure 1 and Figure 2 As shown, on the well region 110, the polysilicon column structures 40 with different polarities are externally connected to a power source 90 to form a closed conductive loop. In the closed conductive loop, the positively charged holes in the P-type polysilicon column structure 420 move, so that heat absorption occurs at the current inflow end of the P-type polysilicon column structure 420, and heat release occurs at the current outflow end of the P-type polysilicon column structure 420. The negatively charged electrons in the N-type polysilicon column structure 410 move, so that heat absorption occurs at the current outflow end of the N-type polysilicon column structure 410, and heat release occurs at the current inflow end of the N-type polysilicon column structure 410.

[0060] It can be seen that in the prior art silicon-on-insulator (SOI) process chip, the buried oxide layer 20 can achieve dielectric isolation of components in the integrated circuit, for example, completely eliminating the parasitic latch effect in the bulk silicon complementary metal oxide semiconductor (CMOS) circuit. However, the buried oxide layer 20 has a heat insulation effect, which is not conducive to heat dissipation. Excessive temperature will reduce the performance and working stability of the chip.

[0061] In addition, in three-dimensional (3D) process chips, the density of Fin Field-Effect Transistor (Finfet) transistors is higher, which is not conducive to heat dissipation. Even if liquid heat dissipation is used, using embedded microfluidic channel cooler technology to etch microfluidic channels on the back of the semiconductor substrate to dissipate heat, it only dissipates heat for the entire chip. In the case of cooling the entire chip, since the heat dissipation speed in the local area is much lower than the heat generation speed, a local high-temperature area is formed, which will still reduce the performance and working stability of the chip.

[0062] From the above analysis, it can be known that in this embodiment, by providing a penetrating polysilicon column structure 40 in the buried oxide layer 20, for example, the N-type polysilicon column structure 410 and the P-type polysilicon column structure 420 will absorb heat at the active silicon layer 30 end and release heat at the substrate 10 end, thereby improving the problem that the buried oxide layer 20 has a heat insulation effect that is not conducive to heat dissipation.

[0063] In addition, since the high temperature heating of the chip only occurs in a local area of ​​the chip, the present invention abandons the method of heat dissipation outside the chip, but integrates a semiconductor chip with a cooling effect into the chip. The semiconductor chip in this embodiment is used in the area where the chip needs to use high performance to achieve heat dissipation of the local high temperature area of ​​the chip. That is, the active silicon layer 30 corresponding to the top of the semiconductor chip of this embodiment can continue to grow and etch to form an integrated circuit structure, thereby improving the heat dissipation performance of the chip. And because the semiconductor chip with a cooling effect is integrated into the chip, the space volume required for heat dissipation of the chip can also be reduced.

[0064] See also Figure 1 and Figure 2In one embodiment of the present invention, on the surfaces of two adjacent metal silicide regions 120 in the same well region 110, the polysilicon column structure 40 on the surface of one metal silicide region 120 is a P-type polysilicon column structure 420, and the top of the P-type polysilicon column structure 420 is externally connected to the input end of the power source 90, that is, the power source 90 flows current into the top of the P-type polysilicon column structure 420. The polysilicon column structure 40 on the surface of the other metal silicide region 120 is an N-type polysilicon column structure 410, and the top of the N-type polysilicon column structure 410 is externally connected to the output end of the power source 90, that is, the top of the N-type polysilicon column structure 410 flows current into the power source 90.

[0065] Specifically, the positively charged holes in the P-type polysilicon column structure 420 move, so that heat absorption occurs at the top of the P-type polysilicon column structure 420, and heat release occurs at the bottom of the P-type polysilicon column structure 420. The negatively charged electrons in the N-type polysilicon column structure 410 move, so that heat absorption occurs at the top of the N-type polysilicon column structure 410, and heat release occurs at the bottom of the N-type polysilicon column structure 410.

[0066] See also Figure 1 and Figure 2 In one embodiment of the present invention, the top of the well region 110 includes two metal silicide regions 120. On the same side of at least two well regions 110, the polysilicon column structure 40 on the surface of the metal silicide region 120 is a P-type polysilicon column structure 420. On the other same side of at least two well regions 110, the polysilicon column structure 40 on the surface of the metal silicide region 120 is an N-type polysilicon column structure 410.

[0067] Specifically, the polysilicon column structure 40 on the surface of the metal silicide region 120 on the same side of at least two well regions 110 is a P-type polysilicon column structure 420, and the polysilicon column structure 40 on the surface of the metal silicide region 120 on the same other side of at least two well regions 110 is an N-type polysilicon column structure 410. The advantage is that it is easy to manage, and only the positions of the P-type polysilicon column structure 420 and the N-type polysilicon column structure 410 on one well region 110 need to be confirmed, and the positions of the P-type polysilicon column structure 420 and the N-type polysilicon column structure 410 on other well regions 110 can be confirmed.

[0068] See also Figure 1 and Figure 3 In one embodiment of the present invention, the semiconductor chip further includes a heat sink 80, which is disposed at the bottom of the substrate 10. The polysilicon column structure 40 in the buried oxide layer 20 transfers the heat generated during the operation of the chip to the substrate 10, and the heat is dissipated through the external heat sink 80.

[0069] See also Figure 4As shown, in one embodiment of the present invention, the semiconductor chip further includes a deep trench isolation structure 510 and a shallow trench isolation structure 520. The deep trench isolation structure 510 may be disposed outside the well region 110, and the deep trench isolation structure 510 extends from the surface of the active silicon layer 30 to the inside of the substrate 10. The shallow trench isolation structure 520 may be disposed outside the metal plug 430, and the shallow trench isolation structure 520 extends from the surface of the active silicon layer 30 to the surface of the buried oxide layer 20.

[0070] Specifically, a deep trench isolation structure (DT moat, Deep Trench moat) 510 is used to electrically isolate the polysilicon column structure 40. Figure 3 and Figure 4 As shown, Figure 3 If the deep trench isolation structure 510 is not provided in the semiconductor chip, the heat released from the lower end of the polysilicon pillar structure 40 will diffuse to the surrounding side and affect other semiconductor devices on the surrounding side. Figure 4 In the embodiment, the deep trench isolation structure 510 is used to electrically isolate the polysilicon pillar structure 40, and the heat corresponding to a well region 110 is promptly dissipated, so that other semiconductor devices on the surrounding side will not be affected. Similarly, by setting a shallow trench isolation structure 520, it can also be used to isolate adjacent components in a semiconductor chip.

[0071] See also Figure 4 As shown, in one embodiment of the present invention, when the number of the well region 110 is one, a deep trench isolation structure 510 is disposed outside the well region 110. When the number of the well region 110 is at least two, two adjacent well regions 110 share the same deep trench isolation structure 510, or deep trench isolation structures 510 are disposed outside at least two well regions 110, respectively.

[0072] Specifically, when the number of well regions 110 is at least two, the same deep trench isolation structure 510 can be shared between two adjacent well regions 110, that is, the same deep trench isolation structure 510 is formed on the side where the two adjacent well regions 110 are close to each other, and different deep trench isolation structures 510 are formed on the side where the two adjacent well regions 110 are far away from each other. For example, when the distance between two adjacent well regions 110 is relatively close, the process technology of part of the deep trench isolation structure 510 can be reduced.

[0073] Alternatively, when there are at least two well regions 110, deep trench isolation structures 510 are respectively disposed outside at least two well regions 110. For example, when two adjacent well regions 110 are far apart, local cooling of the chip can be performed to effectively reduce the local temperature of the chip.

[0074] See also Figure 5In one embodiment of the present invention, a method for manufacturing a semiconductor chip may be provided, which may include the following steps.

[0075] Step S10, providing a substrate, forming at least one well region on the top of the substrate, and forming spaced metal silicide regions on the top of the well region.

[0076] Step S20: forming a buried oxide layer on the surface of the substrate.

[0077] Step S30, forming a polysilicon column structure from the surface of the metal silicide region to the surface of the buried oxide layer, wherein a polysilicon column structure with different polarities is formed on the surface of the metal silicide region spaced apart at the top of a well region.

[0078] Step S40: forming an active silicon layer on the surface of the buried oxide layer.

[0079] Step S50: forming a metal plug from the top of the polysilicon column structure to the surface of the active silicon layer.

[0080] In which, on the well region, the polysilicon column structures with different polarities are connected to the power source to form a closed conductive loop to transfer the heat at the top of the polysilicon column structure to the bottom of the polysilicon column structure.

[0081] Specifically, in one embodiment of the present invention, Figure 1 and Figure 2 As shown, on the well region 110, the polysilicon column structures 40 with different polarities are externally connected to a power source 90 to form a closed conductive loop. In the closed conductive loop, the positively charged holes in the P-type polysilicon column structure 420 move, so that heat absorption occurs at the current inflow end of the P-type polysilicon column structure 420, and heat release occurs at the current outflow end of the P-type polysilicon column structure 420. The negatively charged electrons in the N-type polysilicon column structure 410 move, so that heat absorption occurs at the current outflow end of the N-type polysilicon column structure 410, and heat release occurs at the current inflow end of the N-type polysilicon column structure 410.

[0082] In this embodiment, a penetrating polysilicon column structure 40 is provided in the buried oxide layer 20, for example, an N-type polysilicon column structure 410 and a P-type polysilicon column structure 420 absorb heat at the active silicon layer 30 end and release heat at the substrate 10 end, thereby improving the problem that the buried oxide layer 20 has a heat insulation effect that is not conducive to heat dissipation.

[0083] In addition, the semiconductor chip of this embodiment is used in the area of ​​the chip that needs to use high performance to achieve heat dissipation of the local high-temperature area of ​​the chip. That is, the active silicon layer 30 corresponding to the top of the semiconductor chip of this embodiment can continue to grow and etch to form an integrated circuit structure, thereby improving the heat dissipation performance of the chip. And because the semiconductor chip with a cooling effect is integrated into the chip, the space volume required for heat dissipation of the chip can also be reduced.

[0084] See also Figures 6 to 11 , in one embodiment of the present invention, is a structural diagram corresponding to different steps in a method for manufacturing a semiconductor chip.

[0085] See also Figure 6 A substrate 10 is provided, and a well region 110 may be formed on the top of the substrate 10 by ion implantation. After the well region 110 is formed on the top of the substrate 10, a metal silicide region 120 may be formed on the well region 110 not covered by oxide by a Salicide process.

[0086] See also Figure 7 After forming the well region 110 and the metal silicide region 120 on the substrate 10 , a buried oxide layer 20 may be formed on the surface of the substrate 10 , that is, a buried oxide layer (BOX) 20 is formed on the surfaces of the substrate 10 , the well region 110 , and the metal silicide region 120 .

[0087] See also Figure 8 After the buried oxide layer 20 is formed on the surface of the substrate 10, a patterned photoresist layer (not shown in the figure) can be formed on the surface of the buried oxide layer 20. The exposed buried oxide layer 20 is etched using the patterned photoresist layer as a mask to form a groove 440. The groove 440 can penetrate from the surface of the buried oxide layer 20 to the bottom of the buried oxide layer 20.

[0088] See also Fig. 9 After forming the trench 440 on the buried oxide layer 20, a polysilicon (Poly) material may be deposited in the trench 440 until the polysilicon material covers the surface of the buried oxide layer 20. Then, the polysilicon material is planarized, for example, by using a chemical mechanical polishing (CMP) process to planarize the polysilicon material, and the polysilicon material on the surface of the buried oxide layer 20 is removed until the polysilicon material is flush with the surface of the buried oxide layer 20, so as to form a polysilicon column structure 40.

[0089] See also Fig.10 , an active silicon layer 30 is formed on the surface of the buried oxide layer 20 , that is, the active silicon layer 30 is formed on the top of the buried oxide layer 20 and the polysilicon column structure 40 .

[0090] See also Fig.11After the active silicon layer 30 is formed on the surface of the buried oxide layer 20, a via can be formed on the active silicon layer 30 by photolithography and etching, and a metal plug 430 can be formed in the via by deposition, planarization and other processes to complete the production of the semiconductor chip.

[0091] See also Figure 5 In one embodiment of the present invention, after the step of forming the metal plug 430 from the top of the polysilicon column structure 40 to the surface of the active silicon layer 30, the method further includes steps S610 and S620.

[0092] Step S610 may be represented as forming a deep trench isolation structure 510 outside the well region 110 , from the surface of the active silicon layer 30 to the inside of the substrate 10 .

[0093] Step S620 may be represented as forming a shallow trench isolation structure 520 outside the metal plug 430 , from the surface of the active silicon layer 30 to the surface of the buried oxide layer 20 .

[0094] Specifically, the deep trench isolation structure 510 is used to electrically isolate the polysilicon column structure 40, and the heat corresponding to a well region 110 is promptly dissipated, so that other semiconductor devices on the surrounding side will not be affected. Similarly, by setting a shallow trench isolation structure 520, it can also be used to isolate adjacent components in a semiconductor chip.

[0095] In one embodiment of the present invention, step S610 may include step S611 and step S612.

[0096] Step S611 may be represented as forming a deep trench isolation structure 510 from the surface of the active silicon layer 30 to the inside of the substrate 10 outside the well region 110 when the number of the well region 110 is one.

[0097] Step S612 can be represented as when the number of well regions 110 is at least two, deep trench isolation structures 510 are respectively formed on the outer sides of at least two well regions 110, or the same deep trench isolation structure 510 is formed on the side where two adjacent well regions 110 are close to each other, and different deep trench isolation structures 510 are respectively formed on the side where two adjacent well regions 110 are far away from each other.

[0098] Specifically, when the number of well regions 110 is at least two, the same deep trench isolation structure 510 can be shared between two adjacent well regions 110, that is, the same deep trench isolation structure 510 is formed on the side where the two adjacent well regions 110 are close to each other, and different deep trench isolation structures 510 are formed on the side where the two adjacent well regions 110 are far away from each other. For example, when the distance between two adjacent well regions 110 is relatively close, the process technology of part of the deep trench isolation structure 510 can be reduced.

[0099] Alternatively, when there are at least two well regions 110, deep trench isolation structures 510 are respectively disposed outside at least two well regions 110. For example, when two adjacent well regions 110 are far apart, local cooling of the chip can be performed to effectively reduce the local temperature of the chip.

[0100] See also Figure 5 In one embodiment of the present invention, after the step of forming the metal plug 430 from the top of the polysilicon column structure 40 to the surface of the active silicon layer 30 , step S70 may be further included.

[0101] Step S70 can be represented as disposing a heat sink 80 at the bottom of the substrate 10. Specifically, the polysilicon column structure 40 in the buried oxide layer 20 transfers the heat generated during the operation of the chip to the substrate 10, and the heat sink 80 is used for heat dissipation.

[0102] In summary, the present invention proposes a semiconductor chip and a method for manufacturing the same, which can improve the problem that the heat insulation effect inside the chip is not conducive to heat dissipation. A semiconductor chip with a cooling effect is integrated into the chip to achieve heat dissipation in the local high-temperature area of ​​the chip. In addition, the space volume required for heat dissipation of the chip can be reduced.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the art without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention. As used in the description herein and in the following entire claims, unless otherwise specified, "one", and "the" include plural references. Similarly, as used in the description herein and in the following entire claims, unless otherwise specified, the meaning of "in..." includes "in..." and "on...".

Claims

1. A semiconductor chip, characterized in that: include: A substrate, wherein the top of the substrate includes at least one well region, and the top of the well region includes a metal silicide region arranged at intervals; A buried oxide layer is disposed on the surface of the substrate; An active silicon layer is disposed on the surface of the buried oxide layer; A polysilicon column structure, wherein the polysilicon column structure extends from the surface of the buried oxide layer to the surface of the metal silicide region, and the polarities of the polysilicon column structures on the surface of the metal silicide region arranged at intervals at the top of one of the well regions are different; A metal plug extending from a surface of the active silicon layer to a top of the polysilicon column structure; A deep trench isolation structure is arranged outside the well region, and the deep trench isolation structure extends from the surface of the active silicon layer to the inside of the substrate; A shallow trench isolation structure is arranged outside the metal plug, and the shallow trench isolation structure extends from the surface of the active silicon layer to the surface of the buried oxide layer; Wherein, on the well region, the top of the polysilicon column structure with different polarities is externally connected to a power source to form a closed conductive loop to transfer the heat at the top of the polysilicon column structure to the bottom of the polysilicon column structure.

2. The semiconductor chip according to claim 1, characterized in that When the number of the well region is one, the deep trench isolation structure is arranged outside the well region; When the number of the well regions is at least two, two adjacent well regions share the same deep trench isolation structure, or the deep trench isolation structures are respectively disposed outside at least two of the well regions.

3. The semiconductor chip according to claim 1, characterized in that The semiconductor chip further comprises a heat sink, and the heat sink is arranged at the bottom of the substrate.

4. The semiconductor chip according to claim 1, characterized in that On the surfaces of two adjacent metal silicide regions in the same well region, the polysilicon column structure on the surface of one metal silicide region is a P-type polysilicon column structure, and the top of the P-type polysilicon column structure is externally connected to an input terminal of a current; Another polysilicon column structure on the surface of the metal silicide region is an N-type polysilicon column structure, and the top of the N-type polysilicon column structure is externally connected to an output terminal of the current.

5. The semiconductor chip according to claim 1, characterized in that The top of the well region includes two metal silicide regions, and on the same side of at least two of the well regions, the polysilicon column structure on the surface of the metal silicide region is a P-type polysilicon column structure; On the same other side of at least two of the well regions, the polysilicon column structure on the surface of the metal silicide region is an N-type polysilicon column structure.

6. A method for manufacturing a semiconductor chip, characterized in that: include: Providing a substrate, forming at least one well region on the top of the substrate, and forming a metal silicide region spaced apart on the top of the well region; forming a buried oxide layer on the surface of the substrate; A polysilicon column structure is formed from the surface of the metal silicide region to the surface of the buried oxide layer, wherein the polysilicon column structure with different polarities is formed on the surface of the metal silicide region spaced apart at the top of one of the well regions; forming an active silicon layer on the surface of the buried oxide layer; forming a metal plug from the top of the polysilicon column structure to the surface of the active silicon layer; On the outside of the well region, a deep trench isolation structure is formed from the surface of the active silicon layer to the inside of the substrate; On the outer side of the metal plug, a shallow trench isolation structure is formed from the surface of the active silicon layer to the surface of the buried oxide layer; Wherein, on the well region, the polysilicon column structures with different polarities are externally connected to a power source to form a closed conductive loop to transfer the heat at the top of the polysilicon column structure to the bottom of the polysilicon column structure.

7. The method for manufacturing a semiconductor chip according to claim 6, characterized in that: The step of forming a deep trench isolation structure from the surface of the active silicon layer to the substrate outside the well region includes: When the number of the well region is one, a deep trench isolation structure is formed outside the well region from the surface of the active silicon layer to the inside of the substrate; When the number of the well regions is at least two, deep trench isolation structures are respectively formed on the outer sides of at least two of the well regions, or the same deep trench isolation structure is formed on the side where two adjacent well regions are close to each other, and different deep trench isolation structures are respectively formed on the side where two adjacent well regions are far away from each other.

8. The method for manufacturing a semiconductor chip according to claim 6, characterized in that: After the step of forming a metal plug from the top of the polysilicon column structure to the surface of the active silicon layer, the method further comprises: A heat sink is disposed at the bottom of the substrate.

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