An ultra-wide voltage range relative voltage difference level comparison circuit

Abstract

The present invention discloses an ultra-wide voltage range relative voltage difference level comparison circuit, comprising: a relative voltage difference level generation module, a transmission gate and a rail-to-rail comparator; the relative voltage difference level generation module generates a set of relative voltage difference levels based on a reference level, and the transmission gate is used to control one of the relative voltage difference levels to enter the rail-to-rail comparator for comparison with a comparison voltage to form a hysteresis window. The ultra-wide voltage range relative voltage difference level comparison circuit of the present invention changes the ordinary PMOS differential pair comparator or NMOS differential pair comparator in the prior art into a rail-to-rail comparator, and realizes an ultra-wide voltage range by changing the structure of the comparator; secondly, the present invention designs a relative voltage difference level generation module, which can not only realize an ultra-wide input voltage range, but also generate a relative voltage difference level signal of a wide voltage range, thereby realizing an ultra-wide voltage range relative voltage difference comparison function.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuits and semiconductor integrated circuits, and in particular to an ultra-wide voltage range relative voltage difference level comparison circuit. Background Art

[0002] like Figure 1 The existing level comparison circuit comparator has two analog voltage input terminals V0 and V1, and a digital state output terminal VOUT. The output terminal has only two states to indicate the high and low potential relationship between the two input terminals. It can be easily seen that the input voltage range of this structure is limited. Depending on whether the comparator uses a PMOS differential pair tube or an NMOS differential pair tube, the input range of V0 and V1 is Vth to VDD or 0 to VDD-Vth, where Vth is the conduction threshold voltage of the MOS tube, which is difficult to apply in the field of ultra-wide input voltage. In addition, in the process of monitoring voltage signals, it is usually necessary to detect whether the relative voltage difference between the two voltage signals meets certain requirements. For example, when the input signal V0 is greater than the input signal V150mV, a logic level signal can be output. To achieve this function, a comparator circuit is required, and the traditional comparator structure is mostly gate input, which can only realize equal value detection. The relative difference detection must be achieved by adding offset or hysteresis. The circuit accuracy increased by this type of structure will change with the change of device process deviation, especially when the required difference is less than 100mV. The change of device process deviation may be greater than the required difference, which is difficult to meet the requirements of mass production. Summary of the invention

[0003] In view of the problems existing in the prior art, the present invention provides an ultra-wide voltage range relative voltage difference level comparison circuit, which can realize the relative voltage difference level comparison function under the ultra-wide input voltage range, and further realize the flexible level comparison function.

[0004] To achieve the above technical objectives, the present invention adopts the following technical solutions: an ultra-wide voltage range relative voltage difference level comparison circuit, comprising: a relative voltage difference level generation module, a transmission gate and a rail-to-rail comparator;

[0005] The relative pressure difference level generating module generates a set of relative pressure difference levels based on the reference level;

[0006] The transmission gate is used to control one of the relative voltage difference levels to enter the rail-to-rail comparator for comparison with the comparison voltage, thereby forming a hysteresis window.

[0007] Furthermore, the relative pressure difference level generating module is divided into a negative relative pressure difference level generating module and a positive relative pressure difference level generating module. The negative relative pressure difference level generating module is used to generate a negative relative pressure difference level based on a reference level; the positive relative pressure difference level generating module is used to generate a positive relative pressure difference level based on a reference level.

[0008] Furthermore, the negative relative voltage difference level generating module includes: a first current source, a first NMOS tube, a first resistor, a second resistor and a second NMOS tube, the positive end of the first current source is connected to VDD, the negative end of the first current source is respectively connected to the drain of the first NMOS tube, the gate of the first NMOS tube and the gate of the second NMOS tube, the source of the first NMOS tube and the source of the second NMOS tube are both grounded, the drain of the second NMOS tube is connected to one end of the second resistor, the other end of the second resistor is connected to one end of the first resistor, and the other end of the first resistor is connected to a reference level V0.

[0009] Further, one end of the first resistor and the other end of the second resistor serve together as a first output end; one end of the second resistor and the drain of the second NMOS tube serve together as a second output end.

[0010] Further, the positive relative voltage difference level generating module includes: a first PMOS tube, a second current source, a second PMOS tube, a third resistor and a fourth resistor, the source of the first PMOS tube and the source of the second PMOS tube are both connected to VDD, the gate of the first PMOS tube, the drain of the first PMOS tube and the gate of the second PMOS tube are all connected to the positive end of the second current source, the negative end of the second current source is grounded, the drain of the second PMOS tube is connected to one end of the third resistor, the other end of the third resistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the reference level V0.

[0011] Furthermore, the drain of the second PMOS tube and one end of the third resistor serve together as the first output end; the other end of the third resistor and one end of the fourth resistor serve together as the second output end.

[0012] Further, the positive end of the transmission gate is connected to the first output end of the relative voltage difference level generating module, the negative end of the transmission gate and the second output end of the relative voltage difference level generating module are both connected to the negative phase input end of the rail-to-rail comparator, the positive phase input end of the rail-to-rail comparator is connected to the comparison voltage V1, the output end of the rail-to-rail comparator is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is the output signal VOUT.

[0013] Furthermore, the positive logic control terminal of the transmission gate, the output terminal of the rail-to-rail comparator, and the input terminal of the first inverter are all connected to a logic level B signal; the negative logic control terminal of the transmission gate, the output terminal of the first inverter, and the input terminal of the second inverter are all connected to a logic level BB signal.

[0014] Furthermore, the logic level B signal and the logic level BB signal are mutually inverted signals.

[0015] Compared with the prior art, the present invention has the following beneficial effects: the ultra-wide voltage range relative voltage difference level comparison circuit of the present invention changes the ordinary PMOS differential pair comparator or NMOS differential pair comparator in the prior art into a rail-to-rail comparator, and realizes the ultra-wide voltage range by changing the structure of the comparator; secondly, the present invention designs a relative voltage difference level generation module, which can not only realize the ultra-wide input voltage range, but also generate a relative voltage difference level signal in a wide voltage range, thereby realizing the ultra-wide voltage range relative voltage difference comparison function; in addition, the present invention respectively designs a negative relative voltage difference level generation module and a positive relative voltage difference level generation module, so that the relative voltage difference level can be accurately controlled in both positive and negative directions, and compared with the traditional comparator, the circuit power consumption, resistance and area are easier to compromise. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of a traditional level comparison circuit;

[0017] Figure 2 A schematic diagram of a negative relative voltage difference level comparison circuit in an ultra-wide voltage range provided by the present invention;

[0018] Figure 3 A schematic diagram of an ultra-wide voltage range positive relative voltage difference level comparison circuit provided by the present invention;

[0019] Figure 4 is a circuit diagram of a negative relative voltage difference level generating module in the present invention;

[0020] Figure 5 FIG. 4 is a circuit diagram of a positive relative voltage difference level generating module in the present invention. DETAILED DESCRIPTION

[0021] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0022] The present invention provides an ultra-wide voltage range relative voltage difference level comparison circuit, comprising: a relative voltage difference level generation module, a transmission gate and a rail-to-rail comparator; the relative voltage difference level generation module generates a set of relative voltage difference levels based on a reference level, and the transmission gate is used to control one of the relative voltage difference levels to enter the rail-to-rail comparator for comparison with a comparison voltage to form a hysteresis window. Firstly, the present invention changes the ordinary PMOS differential pair comparator or NMOS differential pair comparator in the prior art into a rail-to-rail comparator, and realizes an ultra-wide voltage range by changing the structure of the comparator; secondly, the present invention designs a relative voltage difference level generation module, which can not only realize an ultra-wide input voltage range, but also generate a relative voltage difference level signal of a wide voltage range, thereby realizing an ultra-wide voltage range relative voltage difference comparison function.

[0023] In the present invention, the relative voltage difference level generating module is divided into a negative relative voltage difference level generating module 201 and a positive relative voltage difference level generating module 301. The negative relative voltage difference level generating module 201 is used to generate a negative relative voltage difference level based on a reference level, and the input voltage V0 of the negative relative voltage difference level generating module 201 ranges from Vdsat to VDD; the positive relative voltage difference level generating module 301 is used to generate a positive relative voltage difference level based on a reference level, and the input voltage V0 of the positive relative voltage difference level generating module 301 ranges from 0 to VDD-Vdsat, wherein Vdsat=Vgs-Vth, Vgs is the voltage difference between the gate terminal and the source terminal of the first NMOS tube 402 or the first PMOS tube 406, and Vth is the conduction threshold voltage of the first NMOS tube 402 or the first PMOS tube 406. Therefore, the negative relative voltage difference level generating module 201 or the positive relative voltage difference level generating module 301 of the present invention can both realize an ultra-wide input voltage range and generate a relative voltage difference level signal in a wide voltage range, thereby realizing an ultra-wide voltage range relative voltage difference comparison function.

[0024] like Figure 4The negative relative voltage difference level generating module 201 includes: a first current source 401, a first NMOS transistor 402, a first resistor 403, a second resistor 404 and a second NMOS transistor 405. The positive end of the first current source 401 is connected to VDD, and the negative end of the first current source 401 is respectively connected to the drain of the first NMOS transistor 402, the gate of the first NMOS transistor 402 and the gate of the second NMOS transistor 405. The source of the first NMOS transistor 402 and the source of the second NMOS transistor 405 are both grounded. The drain of the second NMOS transistor 405 is connected to one end of the second resistor 404, and the other end of the second resistor 404 is connected to one end of the first resistor 403, and the other end of the first resistor 403 is connected to the reference level V0. One end of the first resistor 403 and the other end of the second resistor 404 serve as the first output end; one end of the second resistor 404 and the drain of the second NMOS transistor 405 serve as the second output end.

[0025] like Figure 5 The positive relative voltage difference level generating module 301 includes: a first PMOS transistor 406, a second current source 407, a second PMOS transistor 408, a third resistor 409 and a fourth resistor 410. The source of the first PMOS transistor 406 and the source of the second PMOS transistor 408 are both connected to VDD, the gate of the first PMOS transistor 406, the drain of the first PMOS transistor 406 and the gate of the second PMOS transistor 408 are all connected to the positive end of the second current source 407, the negative end of the second current source 407 is grounded, the drain of the second PMOS transistor 408 is connected to one end of the third resistor 409, the other end of the third resistor 409 is connected to one end of the fourth resistor 410, and the other end of the fourth resistor 410 is connected to the reference level V0. The drain of the second PMOS transistor 408 and one end of the third resistor 409 are used as the first output end; the other end of the third resistor 409 and one end of the fourth resistor 410 are used as the second output end.

[0026] In the present invention, the positive end of the transmission gate is connected to the first output end of the relative voltage difference level generating module, the negative end of the transmission gate and the second output end of the relative voltage difference level generating module are both connected to the negative phase input end of the rail-to-rail comparator, the positive phase input end of the rail-to-rail comparator is connected to the comparison voltage V1, the output end of the rail-to-rail comparator is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is the output signal VOUT.

[0027] In the present invention, the positive logic control terminal of the transmission gate, the output terminal of the rail-to-rail comparator, and the input terminal of the first inverter are all connected to the logic level B signal; the negative logic control terminal of the transmission gate, the output terminal of the first inverter, and the input terminal of the second inverter are all connected to the logic level BB signal. The logic level B signal and the logic level BB signal are mutually inverted signals, which are used to control the level compared with the comparison voltage V1. When B=0 and BB=1, the transmission gate is in the on state; when B=1 and BB=0, the transmission gate is in the off state.

[0028] Example 1

[0029] like Figure 2 This embodiment provides an ultra-wide voltage range negative relative voltage difference level comparison circuit, including Figure 4 A negative relative voltage difference level generating module 201 is provided, wherein the positive end of the transmission gate 202 is connected to the first output end V2 of the negative relative voltage difference level generating module 201, the negative end of the transmission gate 202 and the second output end of the negative relative voltage difference level generating module 201 are both connected to the negative phase input end of the rail-to-rail comparator 203, the positive phase input end of the rail-to-rail comparator 203 is connected to the comparison voltage V1, the output end of the rail-to-rail comparator 203 is connected to the input end of the first inverter 204, the output end of the first inverter 204 is connected to the input end of the second inverter 205, and the output end of the second inverter 205 is the output signal VOUT. The positive logic control end of the transmission gate 202, the output end of the rail-to-rail comparator 203, and the input end of the first inverter 204 are all connected to the logic level B signal; the negative logic control end of the transmission gate 202, the output end of the first inverter 204, and the input end of the second inverter 205 are all connected to the logic level BB signal. When B=0 and BB=1, the transmission gate 202 is in the on state; when B=1 and BB=0, the transmission gate 202 is in the off state.

[0030] The working process of the ultra-wide voltage range negative relative voltage difference level comparison circuit proposed by the present invention is divided into two stages. The first stage is that the negative relative voltage difference level generation module 201 generates level signals V2 and V3 with a voltage difference from the reference level V0. In the process of the comparison voltage V1 changing from 0 to VDD, it will first be compared with the level V2 of the first output terminal of the negative relative voltage difference level generation module 201, and the output signal VOUT will change from logic 0 to logic 1; the second stage is that the negative relative voltage difference level generation module 201 generates level signals V2 and V3 with a voltage difference from the reference voltage V0. In the process of the comparison level V1 changing from VDD to 0, it will be compared with the level V3 of the second output terminal of the negative relative voltage difference level generation module 201, and the output signal VOUT will change from logic 1 to logic 0. The ultra-wide voltage range negative relative voltage difference level comparison circuit generates a logical relationship with different level comparisons during the power-on and power-off process of the comparison voltage V1, forming a hysteresis window function, thereby avoiding false triggering before the level reaches the relative voltage difference level designed by the present invention.

[0031] Assume that the first current source 401 determines the initial branch current I0, which is output to the reference branch through the first NMOS tube 402 and the second NMOS tube 405. The reference branch is composed of the second resistor 404 and the first resistor 403. The ratio of the number of the first NMOS tube 402 and the second NMOS tube 405 is set to 1:N, then the reference branch current is N*I0; the resistance values ​​of the first resistor 403 and the second resistor 404 are set to R1 and R2 respectively, then the output voltage V2=V0-N*I0*R1, V3=V0-N*I0*(R1+R2), and the hysteresis voltage generated is Vhsy=N*I0*R2.

[0032] Example 2

[0033] like Figure 3 This embodiment provides an ultra-wide voltage range positive relative voltage difference level comparison circuit, including Figure 5A positive relative voltage difference level generating module 301 is provided, wherein the positive end of the transmission gate 302 is connected to the first output end V2 of the positive relative voltage difference level generating module 301, the negative end of the transmission gate 302 and the second output end of the positive relative voltage difference level generating module 301 are both connected to the negative phase input end of the rail-to-rail comparator 303, the positive phase input end of the rail-to-rail comparator 303 is connected to the comparison voltage V1, the output end of the rail-to-rail comparator 303 is connected to the input end of the first inverter 304, the output end of the first inverter 304 is connected to the input end of the second inverter 305, and the output end of the second inverter 305 is the output signal VOUT. The positive logic control end of the transmission gate 302, the output end of the rail-to-rail comparator 303, and the input end of the first inverter 304 are all connected to the logic level B signal; the negative logic control end of the transmission gate 302, the output end of the first inverter 304, and the input end of the second inverter 305 are all connected to the logic level BB signal. When B=0 and BB=1, the transmission gate 302 is in the on state; when B=1 and BB=0, the transmission gate 302 is in the off state.

[0034] The working process of the ultra-wide voltage range positive relative voltage difference level comparison circuit proposed in the present invention is divided into two stages: the first stage is that the positive relative voltage difference level generation module 301 generates level signals V2 and V3 with a voltage difference from the reference level V0. In the process of the comparison voltage V1 changing from 0 to VDD, it will first be compared with the level V2 of the first output terminal of the positive relative voltage difference level generation module 301, and the output signal VOUT will change from logic 0 to logic 1; the second stage is that the positive relative voltage difference level generation module 301 generates level signals V2 and V3 with a voltage difference from the reference level V0. In the process of the comparison level V1 changing from VDD to 0, it will first be compared with the level V3 of the second output terminal of the positive relative voltage difference level generation module 301, and the output signal VOUT will change from logic 1 to logic 0; it generates a logical relationship with different level comparisons during the power-on and power-off process of the comparison voltage V1, forming a hysteresis function, thereby avoiding false triggering before the level reaches the relative voltage difference level designed by the present invention.

[0035] Assume that the second current source 407 determines the initial branch current I0, which is output to the reference branch through the first PMOS tube 406 and the second PMOS tube 408. The reference branch is composed of a third resistor 409 and a fourth resistor 410. The ratio of the number of the first PMOS tube 406 and the second PMOS tube 408 is set to 1:N, then the reference branch current is N*I0; the resistance values ​​of the third resistor 409 and the fourth resistor 410 are set to R3 and R4 respectively, then the output voltage V2=V0+N*I0*R3, V3=V0+N*I0*(R3+R4), and the hysteresis voltage generated is Vhsy=N*I0*R4.

[0036] The present invention provides two relative voltage difference level comparison schemes, positive and negative, both of which can realize the relative voltage difference level comparison function in an ultra-wide voltage range.

[0037] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. An ultra-wide voltage range relative voltage difference level comparison circuit, characterized in that: include: Relative voltage difference level generation module, transmission gate and rail-to-rail comparator; The relative pressure difference level generating module generates a set of relative pressure difference levels based on the reference level; The transmission gate is used to control one of the relative voltage difference levels to enter the rail-to-rail comparator for comparison with the comparison voltage to form a hysteresis window; The relative pressure difference level generating module is divided into a negative relative pressure difference level generating module (201) and a positive relative pressure difference level generating module (301), wherein the negative relative pressure difference level generating module (201) is used to generate a negative relative pressure difference level based on a reference level; The positive relative pressure difference level generating module (301) is used to generate a positive relative pressure difference level based on a reference level; The negative relative voltage difference level generating module (201) comprises: a first current source (401), a first NMOS transistor (402), a first resistor (403), a second resistor (404) and a second NMOS transistor (405); the positive end of the first current source (401) is connected to VDD; the negative end of the first current source (401) is respectively connected to the drain of the first NMOS transistor (402), the gate of the first NMOS transistor (402) and the gate of the second NMOS transistor (405); the source of the first NMOS transistor (402) and the source of the second NMOS transistor (405) are both grounded; the drain of the second NMOS transistor (405) is connected to one end of the second resistor (404); the other end of the second resistor (404) is connected to one end of the first resistor (403); and the other end of the first resistor (403) is connected to a reference level V0.

2. The ultra-wide voltage range relative voltage difference level comparison circuit according to claim 1, characterized in that: One end of the first resistor (403) and the other end of the second resistor (404) serve together as a first output end; one end of the second resistor (404) and the drain of the second NMOS transistor (405) serve together as a second output end.

3. The ultra-wide voltage range relative voltage difference level comparison circuit according to claim 1, characterized in that: The positive relative voltage difference level generating module (301) comprises: a first PMOS transistor (406), a second current source (407), a second PMOS transistor (408), a third resistor (409) and a fourth resistor (410); the source of the first PMOS transistor (406) and the source of the second PMOS transistor (408) are both connected to VDD; the gate of the first PMOS transistor (406), the drain of the first PMOS transistor (406) and the gate of the second PMOS transistor (408) are all connected to the positive end of the second current source (407); the negative end of the second current source (407) is grounded; the drain of the second PMOS transistor (408) is connected to one end of the third resistor (409); the other end of the third resistor (409) is connected to one end of the fourth resistor (410); and the other end of the fourth resistor (410) is connected to a reference level V0.

4. The ultra-wide voltage range relative voltage difference level comparison circuit according to claim 3, characterized in that: The drain of the second PMOS tube (408) and one end of the third resistor (409) serve together as a first output end; the other end of the third resistor (409) and one end of the fourth resistor (410) serve together as a second output end.

5. The ultra-wide voltage range relative voltage difference level comparison circuit according to claim 2 or 4, characterized in that: The positive end of the transmission gate is connected to the first output end of the relative voltage difference level generating module, the negative end of the transmission gate and the second output end of the relative voltage difference level generating module are both connected to the negative phase input end of the rail-to-rail comparator, the positive phase input end of the rail-to-rail comparator is connected to the comparison voltage V1, the output end of the rail-to-rail comparator is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter is the output signal VOUT.

6. The ultra-wide voltage range relative voltage difference level comparison circuit according to claim 5, characterized in that: The positive logic control terminal of the transmission gate, the output terminal of the rail-to-rail comparator, and the input terminal of the first inverter are all connected to a logic level B signal; the negative logic control terminal of the transmission gate, the output terminal of the first inverter, and the input terminal of the second inverter are all connected to a logic level BB signal.

7. The ultra-wide voltage range relative voltage difference level comparison circuit according to claim 6, characterized in that: The logic level B signal and the logic level BB signal are mutually inverted signals.

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