A kind of acoustic piezoelectric structure and preparation method thereof

Abstract

The present invention provides an acoustic piezoelectric structure and a preparation method thereof, which relates to the field of acoustic sensing technology. The method reduces the thickness of a single etching by etching for multiple times during the process of processing a first electrode lead-out hole, thereby optimizing the phenomenon of excessive consumption of photoresist in etching through holes of thick and difficult-to-etch piezoelectric thin films. In addition, in each of the multiple etchings, the material difference between the electrode layer and the piezoelectric layer is fully utilized, the depth of each etching is accurately controlled to be more appropriate, and the morphology of the sub-hole is optimized, so that the first electrode lead-out hole finally formed has good performance, which facilitates the batch application of the preparation method in the processing and manufacturing of wafers.

Description

Technical Field

[0001] The present invention relates to the field of acoustic sensing technology, and in particular to an acoustic piezoelectric structure and a preparation method thereof. Background Art

[0002] In recent years, MEMS acoustic piezoelectric structures manufactured using MEMS (micro-electromechanical systems) technology have been increasingly used in devices such as smartphones. MEMS acoustic piezoelectric structures are devices that can convert signals such as sound and vibration into electrical signals. They use the piezoelectric effect to convert the mechanical energy of vibration into electrical energy through piezoelectric film materials and output it.

[0003] In order to improve the sensitivity of the device, the piezoelectric layer in the MEMS acoustic piezoelectric structure can be designed as a double-layer piezoelectric film structure, and the two layers of piezoelectric film structure work and output together, thereby improving the output of electrical signals. In order to facilitate the interconnection between electrodes, it is necessary to make vias in the double-layer piezoelectric film structure to realize the lead-out of the electrode layer below the double-layer piezoelectric film structure. Therefore, when etching the via, it is necessary to continuously penetrate the two layers of piezoelectric film, which makes etching difficult and difficult to use for batch processing and production of wafers. Summary of the invention

[0004] The object of the present invention is to provide an acoustic piezoelectric structure and a method for preparing the same, in view of the above-mentioned deficiencies in the prior art.

[0005] To achieve the above purpose, the technical solution adopted by the embodiment of the present invention is as follows:

[0006] According to one aspect of an embodiment of the present invention, a method for preparing an acoustic piezoelectric structure is provided, the method comprising:

[0007] Forming a piezoelectric stack layer on a substrate, wherein the piezoelectric stack layer includes a first electrode layer, a first piezoelectric layer, a second electrode layer, a second piezoelectric layer and a third electrode layer stacked in sequence, and a lead-out portion of the first electrode layer is not blocked by the second electrode layer and the third electrode layer in a stacking direction;

[0008] Using the second electrode layer as an etching stop layer, a first sub-hole is formed in the second piezoelectric layer by photolithography and etching processes, wherein the bottom end of the first sub-hole extends to the surface of the first piezoelectric layer, and the first sub-hole corresponds to the lead-out portion of the first electrode layer in the stacking direction;

[0009] Using the first electrode layer as an etching stop layer, a second sub-hole is formed in the first piezoelectric layer exposed at the bottom of the first sub-hole through photolithography and etching processes, wherein the bottom of the second sub-hole extends to the lead-out portion of the first electrode layer, and the second sub-hole and the first sub-hole are connected to form a first electrode lead-out hole.

[0010] Optionally, the piezoelectric stack further includes an insulating layer covering a side of the third electrode layer away from the second piezoelectric layer. Before forming the first sub-hole in the second piezoelectric layer by photolithography and etching processes using the second electrode layer as an etching stop layer, the method further includes:

[0011] Using the third electrode layer as an etching stop layer, a third sub-hole is formed on the insulating layer by photolithography and etching processes, wherein the bottom end of the third sub-hole extends to the surface of the second piezoelectric layer, and the third sub-hole corresponds to the lead-out portion of the first electrode layer in the stacking direction;

[0012] Optionally, using the second electrode layer as an etching stop layer, forming a first sub-hole in the second piezoelectric layer by photolithography and etching processes includes:

[0013] The second electrode layer is used as an etching stop layer, and a first sub-hole is formed in the second piezoelectric layer exposed at the bottom end of the third sub-hole through photolithography and etching processes.

[0014] Optionally, the lead-out portion of the second electrode layer is not blocked by the third electrode layer in the stacking direction; and forming the third sub-hole on the insulating layer by photolithography and etching processes using the third electrode layer as an etching stop layer comprises:

[0015] Using the same photolithography mask and taking the third electrode layer as the etching stop layer, a third electrode lead-out hole, a third sub-hole and a fourth sub-hole are formed on the insulating layer through photolithography and etching processes, wherein the bottom end of the third electrode lead-out hole extends to the lead-out surface of the third electrode layer, the bottom ends of the third sub-hole and the fourth sub-hole both extend to the surface of the second piezoelectric layer, and the third sub-hole corresponds to the lead-out portion of the first electrode layer in the stacking direction, and the fourth sub-hole corresponds to the lead-out portion of the second electrode layer in the stacking direction.

[0016] Optionally, using the second electrode layer as an etching stop layer, forming the first sub-hole in the second piezoelectric layer exposed at the bottom end of the third sub-hole by photolithography and etching processes comprises:

[0017] Using the same photolithography mask and taking the second electrode layer as an etching stop layer, a first sub-hole is formed in the second piezoelectric layer exposed at the bottom end of the third sub-hole, and a fifth sub-hole is formed in the second piezoelectric layer exposed at the bottom end of the fourth sub-hole through photolithography and etching processes, wherein the bottom end of the first sub-hole extends to the surface of the first piezoelectric layer, the bottom end of the fifth sub-hole extends to the surface of the lead-out portion of the second electrode layer, and the fourth sub-hole is connected to the fifth sub-hole to form a second electrode lead-out hole.

[0018] Optionally, the bottom area of ​​the first sub-hole is larger than the opening area of ​​the top end of the second sub-hole.

[0019] Optionally, the opening area of ​​the top end of the first sub-hole is greater than or equal to 2 micrometers, and / or the opening area of ​​the top end of the second sub-hole is greater than or equal to 1 micrometer.

[0020] Optionally, the opening area of ​​the bottom end of the first sub-hole is greater than or equal to 2 micrometers.

[0021] Optionally, the top opening area of ​​the second sub-hole is equal to the top opening area of ​​the fifth sub-hole.

[0022] Optionally, the first sub-hole and the fifth sub-hole are formed in the second piezoelectric layer by using gentle slope etching;

[0023] A second sub-hole is formed in the first piezoelectric layer by using a gentle slope etching.

[0024] Optionally, a first sub-hole is formed in the second piezoelectric layer exposed at the bottom end of the third sub-hole, and a fifth sub-hole is formed in the second piezoelectric layer exposed at the bottom end of the fourth sub-hole by photolithography and dry etching processes;

[0025] A second sub-hole is formed in the first piezoelectric layer exposed at the bottom end of the first sub-hole by photolithography and dry etching processes.

[0026] Optionally, using the first electrode layer as an etching stop layer, forming the second sub-hole in the first piezoelectric layer exposed at the bottom end of the first sub-hole by photolithography and etching processes comprises:

[0027] Forming a sixth sub-hole in the first piezoelectric layer exposed at the bottom end of the first sub-hole by photolithography and dry etching processes, wherein a gap exists between the bottom end of the sixth sub-hole and the surface of the first electrode layer;

[0028] Using the first electrode layer as an etching stop layer, a seventh sub-hole is formed in the first piezoelectric layer at the bottom of the sixth sub-hole through a wet etching process, wherein the seventh sub-hole extends to the surface of the first electrode layer, and the sixth sub-hole and the seventh sub-hole are connected to form a second sub-hole.

[0029] Another aspect of the embodiments of the present invention provides an acoustic piezoelectric structure, which is prepared by any of the above-mentioned methods for preparing an acoustic piezoelectric structure.

[0030] The beneficial effects of the present invention include:

[0031] The present invention provides an acoustic piezoelectric structure and a preparation method thereof. The method reduces the thickness of a single etching by etching for multiple times during the process of processing a first electrode lead-out hole, thereby optimizing the phenomenon of excessive consumption of photoresist in etching through holes of thick and difficult-to-etch piezoelectric thin films. In addition, in each of the multiple etchings, the material difference between the electrode layer and the piezoelectric layer is fully utilized, the depth of each etching is accurately controlled to be more appropriate, and the morphology of the sub-hole is optimized, so that the first electrode lead-out hole finally formed has good performance, which facilitates the batch application of the preparation method in the processing and manufacturing of wafers. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 A schematic structural diagram of an acoustic dual piezoelectric structure provided by an embodiment of the present invention;

[0034] Figure 2 One of the state schematic diagrams of a method for preparing an acoustic piezoelectric structure provided by an embodiment of the present invention;

[0035] Figure 3 A second state schematic diagram of a method for preparing an acoustic piezoelectric structure provided by an embodiment of the present invention;

[0036] Figure 4 A third state schematic diagram of a method for preparing an acoustic piezoelectric structure provided by an embodiment of the present invention;

[0037] Figure 5 A fourth state schematic diagram of a method for preparing an acoustic piezoelectric structure provided by an embodiment of the present invention;

[0038] Figure 6 A fifth state diagram of a method for preparing an acoustic piezoelectric structure provided by an embodiment of the present invention;

[0039] Figure 7 A schematic structural diagram of an acoustic piezoelectric structure provided in an embodiment of the present invention.

[0040] Icon: 110-substrate; 120-silicon dioxide layer; 130-first electrode layer; 140-first piezoelectric layer; 150-second electrode layer; 160-second piezoelectric layer; 170-third electrode layer; 180-insulating layer; 190-via; a-stacking direction; 210-first electrode lead-out hole; 211-third sub-hole; 212-first sub-hole; 213-second sub-hole; 214-sixth sub-hole; 220-second electrode lead-out hole; 221-fourth sub-hole; 222-fifth sub-hole; 230-third electrode lead-out hole; 240-wiring layer; 250-air cavity. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. It should be noted that, in the absence of conflict, the various features in the embodiments of the present invention can be combined with each other, and the combined embodiments are still within the protection scope of the present invention.

[0042] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0043] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0044] The double-layer piezoelectric film structure has two piezoelectric layers. When meeting the interconnection requirements of the electrodes, it is necessary to form vias penetrating the two piezoelectric layers through photolithography and etching processes on the two piezoelectric layers. Different from the via etching of a single piezoelectric layer, the via etching penetrating the two piezoelectric layers undoubtedly greatly increases the etching depth, especially when the piezoelectric layer is a doped (doped element such as Sc) aluminum nitride material. The etching rate of the doped aluminum nitride material is extremely low and etching is very difficult. Therefore, in the via processing of such thick and difficult-to-etch piezoelectric materials, the vias may not be completely etched in place, and the photoresist has been completely consumed. If the vias continue to be etched, other hierarchical structures will be damaged, affecting the performance and reliability of the device.

[0045] To alleviate the above problems, please refer to Figure 1, shows an acoustic bi-piezoelectric structure, which includes a substrate 110 and a piezoelectric stack layer formed on the substrate 110, wherein the piezoelectric stack layer includes a first electrode layer 130, a first piezoelectric layer 140, a second electrode layer 150, a second piezoelectric layer 160 and a third electrode layer 170 sequentially stacked on the substrate 110. In order to facilitate wiring on the piezoelectric stack layer, the piezoelectric stack layer may further include an insulating layer 180 located above the third electrode layer 170, so as to facilitate proper isolation of the wiring layer from the lower layer through the insulating layer 180.

[0046] Please continue to refer to Figure 1 In order to meet the interconnection requirements between electrodes, before wiring on the piezoelectric stack layer, it is necessary to first make a via hole 190 extending to the surface of the first electrode layer 130 in the piezoelectric stack layer through a photolithography and etching process, so that the first electrode layer 130 can be led out through the via hole. For ease of understanding, the processing method of the via hole 190 will be described below.

[0047] In processing Figure 1 When forming the via hole 190 in the insulating layer 180, firstly, a whole layer of photoresist is coated on the upper surface of the insulating layer 180, and then the photoresist is patterned through the steps of exposure and development. The patterned photoresist has a window, so that a part of the upper surface of the insulating layer 180 is exposed in the window, and the position of the window is aligned with the position of the via hole finally formed along the stacking direction. Then, the insulating layer 180 not exposed by the window is protected by the patterned photoresist layer, and the insulating layer 180 exposed in the window is etched to form a through hole penetrating the insulating layer 180 directly below the window, thereby completing the patterning of the insulating layer 180 and making it a hard mask layer. In this way, the remaining patterned photoresist and hard mask layers jointly protect the parts that do not need to be etched, and the etching of the first piezoelectric layer 140 and the second piezoelectric layer 160 below is completed, thereby forming a via hole 190 penetrating the first piezoelectric layer 140 and the second piezoelectric layer 160.

[0048] After the via 190 is etched, a remaining photoresist layer and a hard mask layer are formed above the third electrode layer 170. At this time, the following problems exist in the process of removing the photoresist layer: if the hard mask layer is removed at the same time as the photoresist layer, the insulating layer 180 originally located above the second piezoelectric layer 160 will also no longer exist. However, in view of the wiring requirements, an electrical insulating layer must be formed on the upper surface of the second piezoelectric layer 160. This requires re-depositing a new electrical insulating layer after removing the hard mask layer. However, this approach will cause the via 190 that has been etched open to be filled with the electrical insulating layer, affecting the smooth lead-out of the first electrode layer 130. On the contrary, if the remaining hard mask layer is retained when the photoresist layer is removed, and the remaining hard mask layer is directly used as the electrical insulating layer, then there is a problem that its thickness uniformity and surface morphology are uncontrollable, which has an adverse effect on subsequent wiring processes (metal deposition, patterning, etc.) and reliability. Therefore, the technology of directly using the insulating layer 180 as a hard mask layer has the problem of process incompatibility and cannot be used, which affects the batch processing and production of wafers.

[0049] On this basis, an embodiment of the present invention provides a method for preparing an acoustic piezoelectric structure, which optimizes the above-mentioned technology, and the method includes:

[0050] S10: forming a piezoelectric stack layer on a substrate, wherein the piezoelectric stack layer includes a first electrode layer, a first piezoelectric layer, a second electrode layer, a second piezoelectric layer and a third electrode layer stacked in sequence, and a lead-out portion of the first electrode layer is not blocked by the second electrode layer and the third electrode layer in a stacking direction.

[0051] A piezoelectric stack layer is also formed on the substrate, wherein the piezoelectric stack layer includes a first electrode layer, a first piezoelectric layer, a second electrode layer, a second piezoelectric layer and a third electrode layer which are sequentially stacked on the substrate.

[0052] The first electrode layer is blocked by the layer above it, so in order to facilitate the interconnection between the first electrode layer and other electrodes, the first electrode layer needs to be led out through via holes. When led out through via holes, the lead-out portion of the first electrode layer can be specifically led out.

[0053] Furthermore, the positional relationship between the first electrode layer, the second electrode layer, and the third electrode layer can be optimized, for example, the lead-out portion of the first electrode layer can be not blocked by the second electrode layer and the third electrode layer in the stacking direction, so that when the first electrode lead-out hole is subsequently formed, the etching of the first electrode lead-out hole can be smoother and more controllable, thereby optimizing the performance of the first electrode lead-out hole. When the first electrode layer, the second electrode layer, and the third electrode layer are formed on the surface of the substrate, the final piezoelectric stack structure can meet this requirement through corresponding patterning.

[0054] When making the first electrode lead-out hole, it can be completed by etching multiple times, for example, the first electrode lead-out hole is formed by etching twice in S20 and S30:

[0055] S20: Using the second electrode layer as an etching stop layer, a first sub-hole is formed in the second piezoelectric layer exposed at the bottom of the third sub-hole through photolithography and etching processes, wherein the bottom of the first sub-hole extends to the surface of the first piezoelectric layer, and the first sub-hole corresponds to the lead-out portion of the first electrode layer in the stacking direction.

[0056] When performing the first etching, the second electrode layer is used as an etching stop layer, and a first sub-hole is formed in the second piezoelectric layer exposed relative to the third electrode layer through photolithography and etching processes. The photolithography process and etching process are described in sequence below:

[0057] Photolithography process:

[0058] A whole photoresist layer is coated on the third electrode layer and the upper surface of the exposed second piezoelectric layer, and then the photoresist layer is patterned (e.g., by exposure, development, etc.) so as to open a window on the portion of the photoresist layer covering the upper surface of the second piezoelectric layer. The window in the photoresist layer corresponds to the position of the lead-out portion of the first electrode layer in the stacking direction. In this way, the portion of the second piezoelectric layer originally located in the window will be exposed through the window accordingly.

[0059] Etching process:

[0060] Then, the second piezoelectric layer exposed in the window is etched while the photoresist layer provides protection for the third electrode layer and the portion of the second piezoelectric layer that does not need to be etched. The present invention does not specifically limit the type of etching process. For example, dry etching can be used, that is, the second piezoelectric layer exposed in the window is etched by etching gas to form a first sub-hole that penetrates the second piezoelectric layer. In the process of etching the second piezoelectric layer to form the first sub-hole, the second electrode layer can be used as an etching stop layer to accurately control the etching of the second piezoelectric layer, so that the bottom end of the first sub-hole just extends to the surface of the first piezoelectric layer and stops, so that the morphology of the first sub-hole can be better controlled.

[0061] Based on the position of the window on the photoresist layer in the aforementioned second etching, the first sub-hole formed in the second piezoelectric layer corresponds to the lead-out portion of the first electrode layer along the stacking direction.

[0062] After the first sub-hole is formed, the photoresist layer remaining on the surface of the third electrode layer and the second piezoelectric layer can be removed, and the first etching is completed.

[0063] It should be understood that when the second electrode layer is used as an etching stop layer to control the formation of the first sub-hole, specifically, the portion of the second electrode layer in the functional area of ​​the device or the portion of the second electrode layer in the non-functional area of ​​the device can be utilized (the second electrode layer can reserve a portion located in the non-functional area, and the portion can be disconnected from the portion located in the functional area). For example, when utilizing the portion of the second electrode layer located in the non-functional area of ​​the device, when etching the first sub-hole through photolithography and etching processes, a through hole of the same size is simultaneously etched in the non-functional area of ​​the device. When the bottom end of the through hole extends to the upper surface of the second electrode layer, the bottom end of the first sub-hole should also be synchronously extended to the upper surface of the second piezoelectric layer.

[0064] S30: Using the first electrode layer as an etching stop layer, a second sub-hole is formed in the first piezoelectric layer exposed at the bottom of the first sub-hole through photolithography and etching processes, wherein the bottom of the second sub-hole extends to the lead-out portion of the first electrode layer, and the second sub-hole and the first sub-hole are connected to form a first electrode lead-out hole.

[0065] When performing the second etching, the first electrode layer is used as an etching stop layer, and a second sub-hole is formed in the first piezoelectric layer exposed at the bottom of the first sub-hole through photolithography and etching processes. The photolithography process and etching process are described in order below:

[0066] Photolithography process:

[0067] A whole layer of photoresist is re-coated on the third electrode layer and the upper surface of the exposed second piezoelectric layer. At this time, the photoresist layer has a portion covering the side wall and the bottom wall of the first sub-hole, and then the photoresist layer is patterned (for example, by exposure, development, etc.) so as to open a window on the portion covering the bottom wall of the first sub-hole. Therefore, at this time, the window in the photoresist layer corresponds to the position of the lead-out portion of the first electrode layer in the stacking direction. In this way, the portion of the first piezoelectric layer originally located in the window will be exposed through the window accordingly.

[0068] Etching process:

[0069] Then, the first piezoelectric layer exposed in the window is etched while the photoresist layer provides protection for the third electrode layer, the second piezoelectric layer, and the portion of the first piezoelectric layer (if any) that does not need to be etched. The present invention still does not impose specific restrictions on the type of etching process. For example, dry etching can be used, that is, the first piezoelectric layer exposed in the window is etched by etching gas to form a second sub-hole that penetrates the first piezoelectric layer. In the process of etching the first piezoelectric layer to form the second sub-hole, the first electrode layer can be used as an etching stop layer to accurately control the etching of the first piezoelectric layer, so that the bottom end of the second sub-hole just extends to the surface of the lead-out portion of the first electrode layer and stops, so that the morphology of the second sub-hole can be better controlled.

[0070] Based on the first sub-hole and the second sub-hole formed above, the two are connected from top to bottom, so as to form a first electrode lead-out hole, so that the lead-out portion of the first electrode layer can be conveniently led out through the first electrode lead-out hole.

[0071] After the second sub-hole is formed, the remaining photoresist layer may be removed, thereby completing the second etching.

[0072] In summary, in the process of processing the first electrode lead-out hole, etching is performed multiple times, reducing the thickness of a single etching, thereby optimizing the phenomenon of excessive consumption of photoresist in etching through holes of thick and difficult-to-etch piezoelectric thin films. In addition, in each of the multiple etchings, the material difference between the electrode layer and the piezoelectric layer is fully utilized, and the depth of each etching is precisely controlled to be more appropriate, and the morphology of the sub-hole is optimized, so that the first electrode lead-out hole finally formed has good performance, which facilitates the batch application of the preparation method in the processing and manufacturing of wafers.

[0073] On this basis, an embodiment of the present invention provides a method for preparing an acoustic piezoelectric structure, which further optimizes the above-mentioned technology. The difference from the previous preparation method is that the piezoelectric stack layer also includes an insulating layer. The method includes:

[0074] S10: forming a piezoelectric stack layer on a substrate, wherein the piezoelectric stack layer comprises a first electrode layer, a first piezoelectric layer, a second electrode layer, a second piezoelectric layer, a third electrode layer and an insulating layer stacked in sequence, and a lead-out portion of the first electrode layer is not blocked by the second electrode layer and the third electrode layer in a stacking direction.

[0075] like Figure 2 As shown, a piezoelectric stack is also formed on the substrate 110, wherein the piezoelectric stack includes a first electrode layer 130, a first piezoelectric layer 140, a second electrode layer 150, a second piezoelectric layer 160, a third electrode layer 170 and an insulating layer 180 sequentially stacked on the substrate 110. The insulating layer 180 can facilitate subsequent wiring on the piezoelectric stack.

[0076] The first electrode layer 130 is blocked by the layers above it. Therefore, in order to facilitate the interconnection between the first electrode layer 130 and other electrodes, the first electrode layer 130 needs to be led out in the form of vias. When the first electrode layer 130 is led out through the vias, the lead-out portion of the first electrode layer 130 can be specifically led out, for example Figure 2 In the figure, the portion of the first electrode layer 130 close to the left side serves as its lead portion.

[0077] Furthermore, Figure 2As shown, the positional relationship among the first electrode layer 130, the second electrode layer 150 and the third electrode layer 170 can be optimized, for example, the lead-out portion of the first electrode layer 130 can be not blocked by the second electrode layer 150 and the third electrode layer 170 in the stacking direction, so that when the first electrode lead-out hole 210 is subsequently formed, the etching of the first electrode lead-out hole 210 can be smoother and more controllable, thereby optimizing the performance of the first electrode lead-out hole 210. When the first electrode layer 130, the second electrode layer 150 and the third electrode layer 170 are formed on the surface of the substrate 110, corresponding patterning can be performed so that the final piezoelectric stack structure meets this requirement.

[0078] When the first electrode lead-out hole 210 is formed, etching can be performed in multiple steps. For example, the first electrode lead-out hole 210 is formed by etching in three steps, S20, S30 and S40:

[0079] S40: Using the third electrode layer as an etching stop layer, a third sub-hole is formed on the insulating layer by photolithography and etching processes, wherein the bottom end of the third sub-hole extends to the surface of the second piezoelectric layer, and the third sub-hole corresponds to the lead-out portion of the first electrode layer in the stacking direction.

[0080] When performing the first etching, the third electrode layer 170 is used as an etching stop layer, and a third sub-hole 211 is formed on the insulating layer 180 by photolithography and etching processes. The photolithography process and the etching process are described in sequence below:

[0081] Photolithography process:

[0082] First, a whole layer of photoresist is coated on the upper surface of the insulating layer 180, and the photoresist is patterned (e.g., by exposure, development, etc.) to open a window thereon. The window in the photoresist layer corresponds to the position of the lead-out portion of the first electrode layer 130 in the stacking direction a (or the thickness direction of the substrate 110, which is the direction of the stacking direction in the following text). In other words, the window is located directly above the lead-out portion of the first electrode layer 130. In this way, the portion of the upper surface of the insulating layer 180 that was originally located in the window will be exposed through the window accordingly.

[0083] Etching process:

[0084] like Figure 3As shown, the insulating layer 180 exposed in the window is etched while the photoresist layer provides protection for the portion of the insulating layer 180 that does not need to be etched. The present invention does not specifically limit the type of etching process. For example, dry etching can be used, that is, the insulating layer 180 exposed in the window is etched by etching gas, so as to form a third sub-hole 211 penetrating the insulating layer 180. In the process of etching the insulating layer 180 to form the third sub-hole 211, the etching of the insulating layer 180 can be precisely controlled by using the third electrode layer 170 as an etching stop layer, so that the bottom end of the third sub-hole 211 just extends to the surface of the second piezoelectric layer 160 and stops, so that the morphology of the third sub-hole 211 can be better controlled.

[0085] Based on the positive relationship between the window on the photoresist layer and the lead-out portion of the first electrode layer 130 in the aforementioned first etching, the third sub-hole 211 formed in the insulating layer 180 remains positively corresponding to the lead-out portion of the first electrode layer 130 along the stacking direction a.

[0086] After the third sub-hole 211 is formed, the photoresist layer remaining on the surface of the insulating layer 180 may be removed, and the first etching is completed.

[0087] It should be understood that when the third electrode layer 170 is used as an etching stop layer to control the formation of the third sub-hole 211, specifically, the portion of the third electrode layer 170 in the functional area of ​​the device or the portion of the third electrode layer 170 in the non-functional area of ​​the device can be utilized (the third electrode layer 170 can reserve a portion located in the non-functional area, and the portion can be disconnected from the portion located in the functional area). For example, when utilizing the portion of the third electrode layer 170 located in the non-functional area of ​​the device, when etching the third sub-hole 211 through the photolithography and etching process, a through hole of the same size is simultaneously etched in the non-functional area of ​​the device. When the bottom end of the through hole extends to the upper surface of the third electrode layer 170, the bottom end of the third sub-hole 211 should also be simultaneously extended to the upper surface of the second piezoelectric layer 160.

[0088] S20: using the second electrode layer as an etching stop layer, forming a first sub-hole in the second piezoelectric layer exposed at the bottom end of the third sub-hole through photolithography and etching processes, wherein the bottom end of the first sub-hole extends to the surface of the first piezoelectric layer.

[0089] When performing the second etching, the second electrode layer 150 is used as an etching stop layer, and the first sub-hole 212 is formed in the second piezoelectric layer 160 exposed at the bottom of the third sub-hole 211 through photolithography and etching processes. The photolithography process and etching process are described in order below:

[0090] Photolithography process:

[0091] A whole layer of photoresist is re-coated on the upper surface of the insulating layer 180. At this time, the photoresist layer has a portion covering the side wall and the bottom wall of the third sub-hole 211 (i.e., the surface of the second piezoelectric layer 160 exposed in the third sub-hole 211), and then the photoresist layer is patterned (e.g., by exposure, development, etc.) so as to open a window on the portion covering the bottom wall of the third sub-hole 211. Therefore, at this time, the window in the photoresist layer corresponds to the position of the lead-out portion of the first electrode layer 130 in the stacking direction a. In this way, the portion of the second piezoelectric layer 160 originally located in the window will be exposed through the window accordingly.

[0092] Etching process:

[0093] like Figure 4 As shown, the second piezoelectric layer 160 exposed in the window is etched while the photoresist layer provides protection for the insulating layer 180 and the part of the second piezoelectric layer 160 (if any) that does not need to be etched. The present invention still does not impose specific restrictions on the type of etching process. For example, dry etching can be used, that is, the second piezoelectric layer 160 exposed in the window is etched by etching gas, so as to form a first sub-hole 212 that penetrates the second piezoelectric layer 160. In the process of etching the second piezoelectric layer 160 to form the first sub-hole 212, the second electrode layer 150 can be used as an etching stop layer to accurately control the etching of the second piezoelectric layer 160, so that the bottom end of the first sub-hole 212 just extends to the surface of the first piezoelectric layer 140 and stops, so that the morphology of the first sub-hole 212 can be better controlled.

[0094] Based on the position of the window on the photoresist layer in the aforementioned second etching, the first sub-hole 212 formed in the second piezoelectric layer 160 remains in direct correspondence with the lead-out portion of the first electrode layer 130 along the stacking direction a, and the bottom end of the third sub-hole 211 is connected to the top end of the first sub-hole 212 up and down.

[0095] After the first sub-hole 212 is formed, the photoresist layer remaining on the surface of the insulating layer 180 and the second piezoelectric layer 160 (if any) may be removed, and the second etching is completed.

[0096] It should be understood that when the second electrode layer 150 is used as an etch stop layer to control the formation of the first sub-hole 212 , the aforementioned scheme of using the third electrode layer 170 as an etch stop layer to control the formation of the third sub-hole 211 may be referred to, which will not be repeated here.

[0097] S30: Using the first electrode layer as an etching stop layer, a second sub-hole is formed in the first piezoelectric layer exposed at the bottom of the first sub-hole through photolithography and etching processes, wherein the bottom of the second sub-hole extends to the lead-out portion of the first electrode layer, and the second sub-hole, the first sub-hole and the third sub-hole are connected to form a first electrode lead-out hole.

[0098] When performing the third etching, the first electrode layer 130 is used as an etching stop layer, and the second sub-hole 213 is formed in the first piezoelectric layer 140 exposed at the bottom of the first sub-hole 212 by photolithography and etching processes. The photolithography process and etching process are described in sequence below:

[0099] Photolithography process:

[0100] A whole layer of photoresist is re-coated on the upper surface of the insulating layer 180. At this time, the photoresist layer has a portion covering the side walls and bottom walls of the third sub-hole 211 and the first sub-hole 212. Then the photoresist layer is patterned (for example, by exposure, development, etc.) so as to open a window on the portion covering the bottom wall of the first sub-hole 212. Therefore, at this time, the window in the photoresist layer corresponds to the position of the lead-out portion of the first electrode layer 130 in the stacking direction a. In this way, the portion of the first piezoelectric layer 140 originally located in the window will be exposed through the window accordingly.

[0101] Etching process:

[0102] like Figure 5 As shown, the first piezoelectric layer 140 exposed in the window is etched while the photoresist layer provides protection for the insulating layer 180, the second piezoelectric layer 160 and the first piezoelectric layer 140 (if any) that does not need to be etched. The present invention still does not impose specific restrictions on the type of etching process. For example, dry etching can be used, that is, the first piezoelectric layer 140 exposed in the window is etched by etching gas, so as to form a second sub-hole 213 that penetrates the first piezoelectric layer 140. In the process of etching the first piezoelectric layer 140 to form the second sub-hole 213, the first electrode layer 130 can be used as an etching stop layer to accurately control the etching of the first piezoelectric layer 140, so that the bottom end of the second sub-hole 213 just extends to the surface of the lead-out portion of the first electrode layer 130 and stops, so that the morphology of the second sub-hole 213 can be better controlled.

[0103] Based on the third sub-hole 211 , the first sub-hole 212 and the second sub-hole 213 formed above, the three are connected from top to bottom, so that the lead-out portion of the first electrode layer 130 can be conveniently led out through the first electrode lead-out hole 210 .

[0104] After the second sub-hole 213 is formed, the photoresist layer remaining on the surface of the insulating layer 180 , the second piezoelectric layer 160 , and the first piezoelectric layer 140 (if any) may be removed, and the third etching is completed.

[0105] In summary, in the process of processing the first electrode lead-out hole 210, etching is performed multiple times, reducing the thickness of a single etching, thereby optimizing the phenomenon of excessive consumption of photoresist in etching through holes of thick and difficult-to-etch piezoelectric films, ensuring that the surface morphology and quality of the insulating layer 180 meet the requirements, thereby overcoming the problem of incompatibility of hard mask process technology. In addition, in each of the multiple etchings, the material differences between the insulating layer 180, the electrode layer and the piezoelectric layer are fully utilized, and the depth of each etching is precisely controlled to be more appropriate, and the morphology of the sub-hole is optimized, so that the first electrode lead-out hole 210 finally formed has good performance, which facilitates the batch application of the preparation method in the processing and manufacturing of wafers.

[0106] Of course, in other embodiments of the present invention not shown, the piezoelectric stack may also include more piezoelectric layers and electrode layers, but it should be understood that when forming electrode lead-out holes in multiple piezoelectric layers, the acoustic piezoelectric structure preparation method provided by the present invention may be referred to for corresponding production, such as repeatedly producing the first sub-hole 212 in different piezoelectric layers before forming the second sub-hole 213, thereby achieving the purpose of the electrode lead-out hole penetrating more piezoelectric layers. On this basis, the acoustic piezoelectric structure or piezoelectric stack may also include other levels, such as providing an insulating layer or a seed layer before the first electrode layer (for improving the subsequent film growth quality); or providing a repair layer near the second electrode layer (for improving the growth quality of the second piezoelectric layer); or providing a passivation layer (for device protection) instead of an insulating layer after the last third electrode layer. These functional films that are not related to the basic piezoelectric stack or are additional should not be regarded as features that can bypass the scope of protection of the present invention.

[0107] The above method can be used to process high-quality first electrode lead-out holes 210 in the piezoelectric stack layer. On this basis, the second electrode lead-out holes 220 (used to lead out the lead-out portion of the second electrode layer 150) and the third electrode lead-out holes 230 (used to lead out the lead-out portion of the third electrode layer 170) can be further processed to facilitate the interconnection of the first electrode layer 130, the second electrode layer 150 and the third electrode layer 170. For ease of understanding, the processing of the second electrode lead-out holes 220 and the third electrode lead-out holes 230 will be described below.

[0108] Please refer to Figure 2 The first electrode layer 130, the second electrode layer 150 and the third electrode layer 170 are all blocked by the layers above them. Therefore, in order to facilitate the interconnection between the electrodes, the first electrode layer 130, the second electrode layer 150 and the third electrode layer 170 need to be led out by via holes. When the lead-out is through the via hole, the lead-out portion of the first electrode layer 130 can be specifically led out, such as Figure 2In the embodiment, the portion of the first electrode layer 130 close to the left side is used as its lead-out portion; specifically, the lead-out portion of the second electrode layer 150 is led out, such as Figure 2 In the figure, the portion of the first electrode layer 130 close to the right side is used as its lead-out portion; specifically, the lead-out portion of the third electrode layer 170 is led out, such as Figure 2 The left part (of course, it can also be the right part) of the third electrode layer 170 is used as its lead-out part.

[0109] Furthermore, Figure 2 As shown, the positional relationship between the first electrode layer 130, the second electrode layer 150 and the third electrode layer 170 can be optimized. For example, the lead-out portion of the second electrode layer 150 can be not blocked by the third electrode layer 170 in the stacking direction on the basis that the lead-out portion of the first electrode layer 130 is not blocked by the second electrode layer 150 and the third electrode layer 170 in the stacking direction. In this way, when the first electrode lead-out hole 210 and the second electrode lead-out hole 220 are subsequently formed, the etching of the first electrode lead-out hole 210 and the second electrode lead-out hole 220 can be smoother and more controllable, thereby optimizing the performance of the first electrode lead-out hole 210 and the second electrode lead-out hole 220. When the first electrode layer 130, the second electrode layer 150 and the third electrode layer 170 are formed on the surface of the substrate 110, the final piezoelectric stack structure can meet this requirement through corresponding patterning.

[0110] Optionally, when the third sub-hole 211 is formed through S40, the same photolithography mask can be used, and the third electrode layer 170 can be used as an etching stop layer to form a third electrode lead-out hole 230, a third sub-hole 211 and a fourth sub-hole 221 on the insulating layer 180 through photolithography and etching processes. In this way, the first etching of the second electrode lead-out hole 220 and the first electrode lead-out hole 210 can be completed simultaneously while the third electrode lead-out hole 230 is formed, thereby reducing the number of masks and the number of photolithography times, thereby reducing the photolithography cost.

[0111] The first etching of the first electrode lead-out hole 210, the first etching of the second electrode lead-out hole 220, and the etching of the third electrode lead-out hole 230 are described in detail in sequence by the photolithography process and the etching process:

[0112] Photolithography process:

[0113] First, a whole photoresist layer is coated on the upper surface of the insulating layer 180, and the photoresist layer is patterned (for example, by exposure, development, etc.) so as to open a plurality of windows thereon. It should be noted that part of the windows in the photoresist layer is located directly above the lead-out portion of the first electrode layer 130, another part of the windows in the photoresist layer is located directly above the lead-out portion of the second electrode layer 150, and another part of the windows in the photoresist layer is located directly above the lead-out portion of the third electrode layer 170. In this way, the parts of the upper surface of the insulating layer 180 that were originally located at the plurality of windows will be exposed through the windows accordingly.

[0114] Etching process:

[0115] like Figure 3 As shown, the insulating layer 180 exposed in multiple windows is then etched synchronously while the photoresist layer provides protection for the portion of the insulating layer 180 that does not need to be etched. The present invention does not impose any specific restrictions on the type of etching process. For example, dry etching can be used, that is, etching the insulating layer 180 exposed in multiple windows with an etching gas, thereby forming independent third electrode lead-out holes 230, third sub-holes 211 and fourth sub-holes 221 that penetrate the insulating layer 180. In the process of etching the insulating layer 180 to form the third electrode lead-out hole 230, the third sub-hole 211 and the fourth sub-hole 221, the bottom end of the third electrode lead-out hole 230 is made to extend to the surface of the third electrode layer 170 and stop, so that the etching of the insulating layer 180 can be accurately controlled with the third electrode layer 170 as an etching stop layer. When the etching of the third electrode lead-out hole 230 stops, the etching of the third sub-hole 211 and the fourth sub-hole 221 is also stopped synchronously, so that the bottom ends of the third sub-hole 211 and the fourth sub-hole 221 are made to extend to the surface of the second piezoelectric layer 160 and stop, so that the morphology of the third electrode lead-out hole 230, the third sub-hole 211 and the fourth sub-hole 221 can be better controlled.

[0116] Based on the positive relationship between the multiple windows on the photoresist layer in the aforementioned etching and the lead-out portions of the first electrode layer 130, the second electrode layer 150 and the third electrode layer 170, respectively, the third sub-hole 211 formed in the insulating layer 180 is located directly above the lead-out portion of the first electrode layer 130, the fourth sub-hole 221 is located directly above the lead-out portion of the second electrode layer 150, the third electrode lead-out hole 230 is located directly above the lead-out portion of the third electrode layer 170, and the third electrode lead-out hole 230 directly leads out the lead-out portion of the third electrode layer 170.

[0117] At this point, the photoresist layer remaining on the surface of the insulating layer 180 may be removed.

[0118] Optionally, when the first sub-hole 212 is formed through S20, the same photolithography mask can be used, and the second electrode layer 150 can be used as an etching stop layer to form the first sub-hole 212 and the fifth sub-hole 222 on the second piezoelectric layer 160 through photolithography and etching processes. In this way, the second electrode lead-out hole 220 can be formed while the second etching of the first electrode lead-out hole 210 is completed simultaneously, thereby reducing the number of masks and the number of photolithography times, thereby reducing the photolithography cost.

[0119] The second etching of the first electrode lead-out hole 210 and the second etching of the second electrode lead-out hole 220 are described in detail in the following order:

[0120] Photolithography process:

[0121] A whole layer of photoresist is re-coated on the upper surface of the insulating layer 180. At this time, the photoresist layer has a portion covering the side wall and bottom wall of the third sub-hole 211 (i.e., the surface of the second piezoelectric layer 160 exposed in the third sub-hole 211), a portion covering the side wall and bottom wall of the fourth sub-hole 221 (i.e., the surface of the second piezoelectric layer 160 exposed in the fourth sub-hole 221), and a portion covering the side wall and bottom wall of the third electrode lead-out hole 230. Then, the photoresist layer is patterned (e.g., by exposure, development, etc.) so as to open a window on the portion covering the bottom wall of the third sub-hole 211 and a window on the portion covering the bottom wall of the fourth sub-hole 221. In this way, the portion of the second piezoelectric layer 160 originally located in the window of the third sub-hole 211 and the portion of the window of the fourth sub-hole 221 will be exposed through the windows accordingly.

[0122] Etching process:

[0123] like Figure 4As shown, the second piezoelectric layer 160 exposed in the window in the third sub-hole 211 and the window in the fourth sub-hole 221 is etched while the photoresist layer provides protection for the insulating layer 180 and the portion of the second piezoelectric layer 160 (if any) that does not need to be etched. The present invention still does not impose specific restrictions on the type of etching process. For example, dry etching can be used, that is, the second piezoelectric layer 160 exposed in the window is etched by etching gas, thereby forming the first sub-hole 212 and the fifth sub-hole 222 that penetrate the second piezoelectric layer 160. In the process of etching the second piezoelectric layer 160 to form the first sub-hole 212 and the fifth sub-hole 222, the bottom end of the fifth sub-hole 222 is made to extend just to the upper surface of the lead-out portion of the second electrode layer 150 and stop, so that the etching of the second piezoelectric layer 160 can be precisely controlled with the second electrode layer 150 as an etching stop layer. When the etching of the fifth sub-hole 222 stops, the etching of the first sub-hole 212 is also stopped synchronously, so that the bottom end of the first sub-hole 212 is made to extend just to the surface of the first piezoelectric layer 140 and stop, so that the morphology of the first sub-hole 212 and the fifth sub-hole 222 can be better controlled. When the thickness of the first piezoelectric layer and the second piezoelectric layer is consistent or substantially consistent, the consistency of the thickness of the upper and lower layers of the bi-piezoelectric layer of the finally formed first electrode lead-out hole 210 is ensured.

[0124] Furthermore, the fifth sub-hole 222 and the fourth sub-hole 221 are connected vertically, thereby forming a second electrode lead-out hole 220 , through which the second electrode layer 150 is led out.

[0125] At this point, the photoresist layer remaining on the surfaces of the insulating layer 180 , the first piezoelectric layer 140 , the second piezoelectric layer 160 , the second electrode layer 150 , and the third electrode layer 170 may be removed.

[0126] In some possible implementations, the number of the first electrode lead-out hole 210, the second electrode lead-out hole 220, and the third electrode lead-out hole 230 is not limited. For example, Figure 5 As shown, the number of each of the three is two. Of course, in other embodiments not shown, the number can also be one, three, etc.

[0127] In some possible implementations, during the processing of the first sub-hole 212 and the second sub-hole 213, the sizes defined by the two photolithography processes are different, for example, the size of the first sub-hole 212 during the processing can be larger than the size of the second sub-hole 213 during the processing, in other words, the size of the first sub-hole 212 on the design layout is larger than the size of the second sub-hole 213 on the design layout. This is because the photolithography process of the second sub-hole 213 is exposed in the first sub-hole 212, and since the etching of the piezoelectric layer adopts a gentle slope etching, the bottom opening area of ​​the sub-hole will be smaller than the top opening area of ​​the same sub-hole.

[0128] In order to prevent the photolithography and etching of the second sub-hole 213 from affecting the side wall of the first sub-hole 212, the size defined by the photolithography during the processing of the second sub-hole 213 needs to be smaller than the bottom opening area of ​​the first sub-hole 212. In other words, the bottom area of ​​the first sub-hole 212 is larger than the top opening area of ​​the second sub-hole 213. In addition, the third sub-hole 211 and the first sub-hole 212 are the same, and the fourth sub-hole 221 and the fifth sub-hole 222 are also the same. In this way, the first electrode lead-out hole 210 and the second electrode lead-out hole 220 can both be stepped holes, and the stepped surface is located at the bottom of the third sub-hole 211, the first sub-hole 212 and the fourth sub-hole 221. The stepped surface can also be conducive to the good filling of the metal in the photoresist layer and the subsequent electrode lead-out hole metallization.

[0129] In some possible implementations, considering that the photolithography of the second sub-hole 213 requires coating of a photoresist layer at the bottom of the first sub-hole 212, too small a groove size (larger aspect ratio) will make coating of the photoresist layer difficult, resulting in problems such as too thick photoresist at the bottom. In order to optimize this problem, the photolithography size of the second sub-hole 213 during processing should not be less than 1 micron, and the photolithography size of the first sub-hole 212 during processing should not be less than 2 microns. In other words, the opening area at the top of the first sub-hole 212 is greater than or equal to 2 microns, and / or the opening area at the top of the second sub-hole 213 is greater than or equal to 1 micron.

[0130] In some possible implementations, such as Figure 5 As shown, the photolithography size of the fifth sub-hole 222 during processing can be made consistent with the photolithography size of the second sub-hole 213 during processing, that is, the top opening area of ​​the second sub-hole 213 is equal to the top opening area of ​​the fifth sub-hole 222. This is because the etching depth of the fifth sub-hole 222 is the same as the etching depth of the second sub-hole 213. Therefore, the same photolithography size can ensure that the exposed area of ​​the electrodes at the bottom of the second sub-hole 213 and the fifth sub-hole 222 is the same, so that the electrical characteristics of the first electrode lead-out hole 210 and the second electrode lead-out hole 220 are consistent.

[0131] In some possible implementations, the first sub-hole 212 and the fifth sub-hole 222 are formed in the second piezoelectric layer 160 by gentle slope etching, so that the slope of the side walls of the first sub-hole 212 and the fifth sub-hole 222 is gentler, which facilitates good metal filling during metallization of the photoresist layer and subsequent electrode lead-out holes.

[0132] In some possible implementations, the second sub-hole 213 is formed in the first piezoelectric layer 140 by gentle slope etching, so that the slope of the side wall of the second sub-hole 213 is gentle, which facilitates good metal filling during subsequent electrode lead-out hole metallization.

[0133] In some possible implementations, when the third electrode lead-out hole 230 , the third sub-hole 211 , the first sub-hole 212 , the second sub-hole 213 , the fourth sub-hole 221 and the fifth sub-hole 222 are formed by the aforementioned method, photolithography and dry etching processes may be used.

[0134] For example, the insulating layer 180 may be made of silicon dioxide. When etching the third electrode lead-out hole 230, the third sub-hole 211 and the fourth sub-hole 221, photolithography and dry etching processes may be used, wherein the etching gas may be fluorine-based C x F y Gas, which has a low reaction rate to common metal electrodes such as Mo and can have better stopping characteristics.

[0135] For example, the first piezoelectric layer 140 and the second piezoelectric layer 160 are both made of AlScN material. When etching the first sub-hole 212, the second sub-hole 213 and the fifth sub-hole 222, photolithography and dry etching processes can be used, wherein the etching gas can be a chlorine-based gas (such as chlorine), which has a good etching rate for AlScN material and is selective for metal electrodes such as Mo.

[0136] In some possible implementations, forming the second sub-hole 213 in the first piezoelectric layer 140 exposed at the bottom of the first sub-hole 212 by photolithography and etching processes using the first electrode layer 130 as an etching stop layer in S30 includes:

[0137] like Figure 6 As shown, the sixth sub-hole 214 is first formed in the first piezoelectric layer 140 exposed at the bottom of the first sub-hole 212 by photolithography and dry etching processes, wherein the bottom of the sixth sub-hole 214 is spaced from the surface of the first electrode layer 130, that is, the sixth sub-hole 214 does not penetrate the first piezoelectric layer 140, and a thinner portion of the first piezoelectric layer 140 is left between the bottom of the sixth sub-hole 214 and the upper surface of the first electrode layer 130. The thickness of this portion may preferably be one fifth of the thickness of the first piezoelectric layer 140.

[0138] Then, the first electrode layer 130 is used as an etching stop layer. Figure 5 As shown, the remaining first piezoelectric layer 140 is further etched at the bottom of the sixth sub-hole 214 through a wet etching process, so that a seventh sub-hole is further formed in the remaining first piezoelectric layer 140, wherein the seventh sub-hole extends to the surface of the first electrode layer 130, and the sixth sub-hole 214 and the seventh sub-hole are connected to form the second sub-hole 213. In this way, the high selectivity of wet etching can be used to avoid over-etching the first electrode layer 130.

[0139] Alternatively, if Figure 7 As shown, you can also Figure 5On the basis of the structure shown, the first electrode lead-out hole 210 , the second electrode lead-out hole 220 and the third electrode lead-out hole 230 are further metallized, and the wiring layer 240 on the upper surface of the insulating layer 180 is completed.

[0140] Specifically, the first electrode lead-out hole 210, the second electrode lead-out hole 220 and the third electrode lead-out hole 230 can be metallized, thereby filling the first electrode lead-out hole 210, the second electrode lead-out hole 220 and the third electrode lead-out hole 230 with metal, and the electrical lead-out of the lead-out portions of the first electrode layer 130, the second electrode layer 150 and the third electrode layer 170 can be completed by using metal.

[0141] In addition, a wiring layer 240 that contacts the metal filled in each electrode lead-out hole can be formed on the insulating layer 180 by metal deposition and patterning, and the wiring layer 240 is used to complete the interconnection between the electrodes. Figure 7 As shown, the first electrode layer 130 and the third electrode layer 170 are connected in parallel through the wiring layer 240, and the second electrode layer 150 is connected separately. Of course, the present invention does not limit the interconnection method between the electrodes, and the first electrode layer, the second electrode layer and the third electrode layer can also form other interconnection methods not shown through the wiring layer, which can be determined according to the needs.

[0142] Of course, in order to optimize the performance of the acoustic piezoelectric structure, the insulating layer 180 in the effective working area can be removed, such as Figure 7 As shown in , the middle portion of the insulating layer 180 is removed to expose the surface of the third electrode layer 170 .

[0143] In order to improve device performance, such as Figure 7 As shown, the back side of the substrate 110 may be etched to form an air cavity 250 , and the air cavity 250 may be used to reflect the acoustic waves in the piezoelectric stack layer.

[0144] In some possible implementations, such as Figures 1 to 7 As shown, a silicon dioxide layer 120 may be further disposed between the first electrode layer 130 and the substrate 110 , so that when the air cavity 250 is formed by back etching, the silicon dioxide layer 120 may be used as an etching stop layer of the substrate 110 .

[0145] Another aspect of the present invention provides an acoustic piezoelectric structure, which is prepared by any of the above-mentioned methods for preparing an acoustic piezoelectric structure. The acoustic piezoelectric structure prepared in this way has high performance.

[0146] Another aspect of the embodiments of the present invention provides an acoustic sensor, comprising any one of the acoustic piezoelectric structures described above. By applying the acoustic piezoelectric structure to the acoustic sensor, the acoustic sensor can have the effect of the acoustic piezoelectric structure described above, which will not be described in detail here.

[0147] Another aspect of the embodiments of the present invention provides an electronic device, comprising any one of the above-mentioned acoustic sensors. By applying the acoustic sensor to the electronic device, the electronic device can have the effect of the above-mentioned acoustic piezoelectric structure, which will not be described in detail here.

[0148] The electronic device in the present invention can be a smart phone, a wearable product, a sports camera, a digital camera or a computer, etc.

[0149] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for preparing an acoustic piezoelectric structure, characterized in that: The method comprises: Forming a piezoelectric stack layer on a substrate, wherein the piezoelectric stack layer includes a first electrode layer, a first piezoelectric layer, a second electrode layer, a second piezoelectric layer and a third electrode layer stacked in sequence, and a lead-out portion of the first electrode layer is not blocked by the second electrode layer and the third electrode layer in a stacking direction; Using the second electrode layer as an etching stop layer, a first sub-hole is formed in the second piezoelectric layer by photolithography and etching processes, wherein the bottom end of the first sub-hole extends to the surface of the first piezoelectric layer, and the first sub-hole corresponds to the lead-out portion of the first electrode layer in the stacking direction; Using the first electrode layer as an etching stop layer, a second sub-hole is formed in the first piezoelectric layer exposed at the bottom of the first sub-hole through photolithography and etching processes, wherein the bottom of the second sub-hole extends to the lead-out portion of the first electrode layer, and the second sub-hole and the first sub-hole are connected to form a first electrode lead-out hole.

2. The method for preparing an acoustic piezoelectric structure according to claim 1, characterized in that: The piezoelectric stack layer further includes an insulating layer covering a side of the third electrode layer away from the second piezoelectric layer. Before forming a first sub-hole in the second piezoelectric layer by photolithography and etching processes using the second electrode layer as an etching stop layer, the method further includes: Using the third electrode layer as an etching stop layer, a third sub-hole is formed on the insulating layer by photolithography and etching processes, wherein the bottom end of the third sub-hole extends to the surface of the second piezoelectric layer, and the third sub-hole corresponds to the lead-out portion of the first electrode layer in the stacking direction; The forming of the first sub-hole in the second piezoelectric layer by photolithography and etching processes using the second electrode layer as an etching stop layer comprises: The second electrode layer is used as an etching stop layer, and the first sub-hole is formed in the second piezoelectric layer exposed at the bottom end of the third sub-hole through photolithography and etching processes.

3. The method for preparing an acoustic piezoelectric structure according to claim 2, characterized in that: The lead-out portion of the second electrode layer is not blocked by the third electrode layer in the stacking direction; The forming of the third sub-hole on the insulating layer by photolithography and etching processes using the third electrode layer as an etching stop layer comprises: Using the same photolithography mask and taking the third electrode layer as an etching stop layer, a third electrode lead-out hole, a third sub-hole and a fourth sub-hole are formed on the insulating layer through photolithography and etching processes, wherein the bottom end of the third electrode lead-out hole extends to the lead-out surface of the third electrode layer, the bottom ends of the third sub-hole and the fourth sub-hole both extend to the surface of the second piezoelectric layer, and the third sub-hole corresponds to the lead-out portion of the first electrode layer in the stacking direction, and the fourth sub-hole corresponds to the lead-out portion of the second electrode layer in the stacking direction.

4. The method for preparing an acoustic piezoelectric structure according to claim 3, characterized in that: The method of forming the first sub-hole in the second piezoelectric layer exposed at the bottom end of the third sub-hole by photolithography and etching using the second electrode layer as an etching stop layer comprises: Using the same photolithography mask and taking the second electrode layer as an etching stop layer, a first sub-hole is formed in the second piezoelectric layer exposed at the bottom end of the third sub-hole, and a fifth sub-hole is formed in the second piezoelectric layer exposed at the bottom end of the fourth sub-hole through photolithography and etching processes, wherein the bottom end of the first sub-hole extends to the surface of the first piezoelectric layer, the bottom end of the fifth sub-hole extends to the lead-out surface of the second electrode layer, and the fourth sub-hole is connected to the fifth sub-hole to form a second electrode lead-out hole.

5. The method for preparing an acoustic piezoelectric structure according to any one of claims 1 to 4, characterized in that: The bottom end area of ​​the first sub-hole is larger than the opening area of ​​the top end of the second sub-hole.

6. The method for preparing an acoustic piezoelectric structure according to any one of claims 1 to 4, characterized in that: The opening area of ​​the top end of the first sub-hole is greater than or equal to 2 micrometers, and / or the opening area of ​​the top end of the second sub-hole is greater than or equal to 1 micrometer.

7. The method for preparing an acoustic piezoelectric structure according to claim 4, characterized in that: The top opening area of ​​the second sub-hole is equal to the top opening area of ​​the fifth sub-hole.

8. The method for preparing an acoustic piezoelectric structure according to claim 4, characterized in that: Forming a first sub-hole in the second piezoelectric layer exposed at the bottom end of the third sub-hole and forming a fifth sub-hole in the second piezoelectric layer exposed at the bottom end of the fourth sub-hole by photolithography and dry etching processes; A second sub-hole is formed in the first piezoelectric layer exposed at the bottom end of the first sub-hole by photolithography and dry etching processes.

9. The method for preparing an acoustic piezoelectric structure according to claim 1, characterized in that: The forming of the second sub-hole in the first piezoelectric layer exposed at the bottom end of the first sub-hole by photolithography and etching using the first electrode layer as an etching stop layer comprises: Forming a sixth sub-hole in the first piezoelectric layer exposed at the bottom end of the first sub-hole by photolithography and dry etching processes, wherein a distance exists between the bottom end of the sixth sub-hole and the surface of the first electrode layer; Using the first electrode layer as an etching stop layer, a seventh sub-hole is further formed in the first piezoelectric layer at the bottom of the sixth sub-hole through a wet etching process, wherein the seventh sub-hole extends to the surface of the first electrode layer, and the sixth sub-hole and the seventh sub-hole are connected to form the second sub-hole.

10. An acoustic piezoelectric structure, characterized in that: The acoustic piezoelectric structure is prepared by the method for preparing the acoustic piezoelectric structure as described in any one of claims 1 to 9.

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