Array substrate, preparation method thereof and display panel

Abstract

The present disclosure discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises: a plurality of pixel pairs arranged in an array, two adjacent rows of pixel pairs are provided with two gate lines, each pixel pair comprises a first pixel electrode and a second pixel electrode arranged side by side and connected to the same data line; a first pixel switch and a second pixel switch are respectively electrically connected to the first pixel electrode and the second pixel electrode; in the extension direction of the data line, the first pixel switch and the second pixel switch are respectively arranged in pairs between different two pixel pairs, and the first pixel switch and the second pixel switch corresponding to the pixel pair are located on both sides of the pixel pair; at least part of the first conductive structure is located between the two pixel pairs corresponding to each pair of first pixel switches; in the direction perpendicular to the substrate, the first conductive structure at least partially overlaps with the gate line, and in the extension direction of the data line, the first conductive structure at least partially overlaps with the first pole of the first pixel switch.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to an array substrate, a preparation method thereof and a display panel. BACKGROUND

[0002] The array substrate adopting the Dual gate+Z architecture (Dual gate architecture+pixel electrode in Z-shaped distribution) generally adopts a column inversion driving mode, and thus has the advantage of low power consumption.

[0003] However, in the above array substrate, the distances between the two pixel electrodes of the same gate and the corresponding driving transistors are different, which causes the coupling voltages of the source and drain of the driving transistors to be different, resulting in different off-state pixel holding voltages, thereby affecting the pixel electrodes and their brightness. When a user watches a display product containing the above structure, if there is a relative displacement between the user and the display product (such as the user shaking his head), the picture watched by the user will lose a frame of positive frame picture or negative frame picture, resulting in that the brightness of the positive and negative frame pictures cannot be averaged, and thus vertical lines appear, which are also called shaking lines. SUMMARY

[0004] Embodiments of the present disclosure provide an array substrate, a preparation method thereof and a display panel to solve the technical problem of shaking lines in the prior art.

[0005] In a first aspect, to solve the above technical problem, an array substrate is provided, comprising:

[0006] a substrate substrate;

[0007] a plurality of pixel pairs arranged in an array, two gate lines being arranged between two adjacent rows of the pixel pairs, each of the pixel pairs comprising a first pixel electrode and a second pixel electrode arranged side by side, the first pixel electrode and the second pixel electrode being electrically connected to the same data line, the first pixel electrode being arranged on a side of the second pixel electrode away from the data line;

[0008] a first pixel switch and a second pixel switch, respectively electrically connected to the first pixel electrode and the second pixel electrode; in an extension direction of the data line, the first pixel switch and the second pixel switch are respectively arranged in pairs between different two pixel pairs, and the first pixel switch and the second pixel switch corresponding to the pixel pair are located on two sides of the pixel pair; the first pixel switch comprises a first gate, a first electrode and a second electrode, the first gate being electrically connected to the gate line closest to the first pixel switch, the second electrode being electrically connected to the data line, and the first electrode being electrically connected to the first pixel electrode;

[0009] The first conductive structure is at least partially located between two pixel pairs corresponding to each pair of the first pixel switch; the first conductive structure at least partially overlaps the gate line in a direction perpendicular to the substrate, and at least partially overlaps the first electrode in an extension direction of the data line.

[0010] In a possible implementation, the array substrate further comprises:

[0011] A common electrode at least partially covers the pixel pairs in the same row;

[0012] The first conductive structure in the same row is electrically connected to the common electrode in the adjacent row.

[0013] In a possible implementation, the first conductive structure comprises:

[0014] A first part, a second part and a third part connected in sequence; the first part is connected between the common electrode corresponding to the second pixel electrode and the second part, and the third part is connected between the common electrode corresponding to the second pixel electrode in the adjacent row and the second part;

[0015] In the extension direction of the gate line, the width of the second part is greater than the width of the first part and the third part;

[0016] In the direction perpendicular to the substrate, the first part and the third part respectively overlap the first electrode connected to the adjacent second pixel electrode, and the second part partially overlaps two gate lines electrically connected to the first pixel switch.

[0017] In a possible implementation, in the extension direction of the data line, the length of the second part is greater than or equal to the width of the two gate lines and the gap between the two gate lines.

[0018] In a possible implementation, the extension direction of the first conductive structure in the same row is the same.

[0019] In a possible implementation, the extension direction of the first conductive structure in the adjacent two rows is different.

[0020] In a possible implementation, the array substrate further comprises:

[0021] A second conductive structure located between two pixel pairs corresponding to the second pixel switch pair, and the second conductive structure is parallel to the extension direction of the data line;

[0022] The second conductive structure is electrically connected to the common electrodes of adjacent rows, and in a direction perpendicular to the substrate, the second conductive structure overlaps the gate lines, and in an extension direction of the gate lines, the second conductive structure has a width smaller than that of the first conductive structure.

[0023] In a possible implementation, the common electrode includes:

[0024] A plurality of strip electrodes with different extension directions, and two ends of the plurality of strip electrodes with different extension directions are connected to each other.

[0025] In a possible implementation, in an extension direction of the gate lines, a width of the strip electrode overlapping the data line is greater than a width of the data line.

[0026] In a possible implementation, the array substrate further includes:

[0027] A plurality of common electrode lines arranged in a cross connection manner in a row direction and a column direction, and the common electrode lines correspond to a row of the pixel pairs.

[0028] In a possible implementation, the common electrode line includes:

[0029] A trunk electrode line in a straight line type, arranged in a region where the strip electrodes with different extension directions intersect;

[0030] A plurality of branch electrode lines, the branch electrode lines are located between the first pixel electrode and the second pixel electrode in each pixel pair, the extension direction of the branch electrode line is the same as that of the strip electrode, and an intersection point of the branch electrode line and the trunk electrode line is arranged in a region where the strip electrodes with different extension directions are connected.

[0031] In a possible implementation, the common electrode line is arranged in the same layer as the gate line, and the branch electrode line is arranged in a gap between the gate lines on both sides of the corresponding pixel pair.

[0032] In a possible implementation, the branch electrode line corresponding to the pixel pair with the blue pixel further includes a protruding part;

[0033] The protruding part is located at two ends of the corresponding branch electrode line and protrudes towards a region of the blue pixel.

[0034] In a possible implementation, the array substrate further includes:

[0035] A first connection hole, and in a direction perpendicular to the substrate, a protruding part of at least part of the common electrode partially overlapping the first connection hole is electrically connected.

[0036] In a possible implementation, the second conductive structure corresponding to the two branch electrode lines of the protrusion has different widths.

[0037] The width of the gate line overlapping position of the wider second conductive structure is greater than that of the narrower second conductive structure.

[0038] In a possible implementation, the first electrode includes:

[0039] The first sub-portion, the second sub-portion, the third sub-portion, and the first sub-portion connecting portion are connected to the first sub-portion connecting portion.

[0040] In the extension direction of the gate line, the second sub-portion and the third sub-portion are located on the side of the first sub-portion connecting portion away from the first sub-portion, the first sub-portion overlaps the first gate, the second sub-portion does not overlap the corresponding gate line, and the third sub-portion overlaps the corresponding gate line.

[0041] The second sub-portion is connected to the corresponding first pixel electrode, and the length of the second sub-portion is greater than that of the third sub-portion.

[0042] In a possible implementation, the second pixel switch includes:

[0043] The third electrode is electrically connected to the second pixel electrode, and the second electrode does not overlap the second conductive structure.

[0044] The fourth electrode is electrically connected to the data line.

[0045] The second gate is electrically connected to the gate line closest to the second pixel switch.

[0046] In a possible implementation, the third electrode includes:

[0047] The fourth sub-portion, the fifth sub-portion, and the second sub-portion connecting portion connecting the fourth sub-portion and the fifth sub-portion; in the extension direction of the gate line, the fifth sub-portion is located on the side of the second sub-portion connecting portion away from the fourth sub-portion.

[0048] The fourth sub-portion overlaps the second gate, and the fifth sub-portion overlaps the corresponding gate line.

[0049] In a possible implementation, the fifth sub-portion has an overlapping area with the corresponding gate line, and the overlapping area of the third sub-portion with the corresponding gate line is substantially the same.

[0050] In a possible implementation, in the extension direction of the gate line, the length of the first electrode is greater than that of the third electrode; and the first electrodes of the first pixel switch pair have opposite extension directions.

[0051] In a possible implementation, the same column of pixels has the same color;

[0052] The pixel electrodes corresponding to the blue color and the green color are electrically connected to the same gate line.

[0053] In a possible implementation, the data line is arranged in the same layer as the first pixel electrode and the second pixel electrode.

[0054] In a second aspect, the present disclosure provides a display panel, including:

[0055] The array substrate and the counter substrate as described in the first aspect;

[0056] The liquid crystal layer is located between the array substrate and the counter substrate.

[0057] In a third aspect, the present disclosure provides a manufacturing method of the array substrate as described in the first aspect, including:

[0058] The substrate is provided;

[0059] On one side of the substrate, a plurality of gate lines and a plurality of data lines are formed, the plurality of gate lines and the plurality of data lines define a plurality of pixel pairs arranged in an array, two gate lines are arranged between two adjacent rows of the pixel pairs; the pixel pair includes a first pixel electrode and a second pixel electrode arranged side by side, the first pixel electrode and the second pixel electrode are electrically connected to the same data line, and the first pixel electrode is arranged on a side of the second pixel electrode away from the data line;

[0060] On one side of the substrate, a first pixel switch and a second pixel switch are also formed, and are respectively electrically connected to the first pixel electrode and the second pixel electrode; in the extension direction of the data line, the first pixel switch and the second pixel switch are respectively arranged in pairs between different two pixel pairs, and the first pixel switch and the second pixel switch corresponding to the pixel pair are located on two sides of the pixel pair; the first pixel switch includes a first gate, a first electrode and a second electrode, the first gate is electrically connected to the gate line closest to the first pixel switch, the second electrode is electrically connected to the data line, and the first electrode is electrically connected to the first pixel electrode; in the extension direction of the data line, the first electrode at least partially overlaps with the second pixel electrode;

[0061] A first conductive structure is formed on a side of the plurality of data lines away from the substrate, and at least part of the first conductive structure is located between two pixel pairs corresponding to each pair of the first pixel switches; in a direction perpendicular to the substrate, the first conductive structure at least partially overlaps the gate line, and in an extension direction of the data line, the first conductive structure at least partially overlaps the first electrode. BRIEF DESCRIPTION OF DRAWINGS

[0062] Figure 1 A schematic diagram of a pixel arrangement of a Dual gate+Z architecture in the related art;

[0063] Figure 2 A comparison diagram of pixel coupling voltages of pixel switches in an off state corresponding to long connection pixels and short connection pixels, respectively;

[0064] Figure 3 A schematic diagram of a structure of an array substrate provided by an embodiment of the present disclosure;

[0065] Figure 4 A schematic diagram of another structure of an array substrate provided by an embodiment of the present disclosure;

[0066] Figure 5 A schematic diagram of a structure of a first conductive structure provided by an embodiment of the present disclosure;

[0067] Figure 6 A schematic diagram of another structure of a first conductive structure provided by an embodiment of the present disclosure;

[0068] Figure 7 A schematic diagram of a structure of a second conductive structure provided by an embodiment of the present disclosure; Figure 6 A cross-sectional view of AA' position;

[0069] Figure 8 A schematic diagram of a structure of a second conductive structure provided by an embodiment of the present disclosure;

[0070] Figure 9 A schematic diagram of a structure of a common electrode provided by an embodiment of the present disclosure;

[0071] Figure 10 A schematic diagram of another structure of an array substrate provided by an embodiment of the present disclosure;

[0072] Figure 11 A schematic diagram of an arrangement of color filters corresponding to pixels in an array substrate provided by an embodiment of the present disclosure;

[0073] Figure 12 A schematic diagram of another structure of an array substrate provided by an embodiment of the present disclosure;

[0074] Figure 13 A schematic diagram of a position of a connection hole in an array substrate provided by an embodiment of the present disclosure;

[0075] Figure 14 A cross-sectional view of a position of BB' provided for an embodiment of the present disclosure Figure 13 A cross-sectional view of a position of BB' provided for an embodiment of the present disclosure

[0076] Figure 15 A structure schematic view of a first electrode provided for an embodiment of the present disclosure

[0077] Figure 16 A structure schematic view of a second pixel switch provided for an embodiment of the present disclosure

[0078] Figure 17 A structure schematic view of a third electrode provided for an embodiment of the present disclosure

[0079] Figure 18 A length schematic view of a first electrode and a third electrode provided for an embodiment of the present disclosure

[0080] Figure 19 A principle view of an array substrate provided for an embodiment of the present disclosure

[0081] Figure 20 A pixel light and dark contrast view of a GB common gate and a RG common gate provided for an embodiment of the present disclosure

[0082] Figure 21 A structure schematic view of a display panel provided for an embodiment of the present disclosure

[0083] Figure 22 A flow chart of a preparation method of an array substrate provided for an embodiment of the present disclosure

[0084] Figure 23 A flow chart of an array substrate provided for an embodiment of the present disclosure Figure 18

[0085] Figure 24 A schematic view of forming a data line and a source-drain layer and a first pixel electrode and a second pixel electrode provided for an embodiment of the present disclosure

[0086] Reference signs:

[0087] ​Substrate substrate 0, pixel pair 1, gate line 2, data line 3, first pixel electrode 11, second pixel electrode 12, first pixel switch 4, second pixel switch 5, first conductive structure 6, first gate 4g, first pole 41, second pole 42, first pixel switch pair 4D, second pixel switch pair 5D, common electrode 7, second gate 5g, third pole 51, fourth pole 52, first part 61, second part 62, third part 63, second conductive structure 8, strip electrode 71, common electrode line 9, main electrode line 91, branch electrode line 92, protruding part 921, connection hole H, first sub-part 411, second sub-part 412, third sub-part 413, first sub-connection part 414, fourth sub-part 511, fifth sub-part 512, second sub-connection part 513. DETAILED DESCRIPTION

[0088] The array substrate and the preparation method thereof and the display panel provided by the embodiments of the present disclosure can solve the technical problem of the existing shaking lines.

[0089] In order to make the above objectives, features and advantages of the present disclosure more obvious and easy to understand, the present disclosure will be further described below with reference to the drawings and embodiments. However, the example embodiments can be implemented in various forms, and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present disclosure more comprehensive and complete, and to fully convey the ideas of the example embodiments to those skilled in the art. The same reference signs in the drawings represent the same or similar structures, so repeated descriptions thereof will be omitted. The expressions of position and direction described in the present disclosure are described with reference to the drawings, but changes can also be made as needed, and the changes made are included in the protection scope of the present disclosure. The drawings of the present disclosure are only used to illustrate the relative positional relationship and do not represent the true proportions.

[0090] It should be noted that specific details are set forth in the following description in order to provide a thorough understanding of the present disclosure. However, the present disclosure can be implemented in a variety of other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the present disclosure. Therefore, the present disclosure is not limited by the specific embodiments disclosed below. The subsequent description of the specification is a preferred embodiment for implementing the present application, and is intended to illustrate the general principles of the present application, rather than to limit the scope of the present application. The protection scope of the present application is defined by the appended claims.

[0091] Please refer to Figure 1 For the pixel arrangement schematic diagram of the Dual gate+Z architecture in the related art.

[0092] As Figure 1As shown, among pixels p1 and p2 connected to the same data line dl, pixel p2 is farther from the connected data line dl, resulting in a longer source / drain connection line. Therefore, pixel p2 is usually called a long-connected pixel. Pixel p1 is closer to the connected data line dl, resulting in a shorter source / drain connection line. Therefore, pixel p1 is usually called a short-connected pixel. The difference in the length of the connection lines for these two types of pixels causes a difference in signal coupling with the gate line g1.

[0093] Please see Figure 2 This is a comparison diagram of the pixel coupling voltages of the pixel switches corresponding to long-connected pixels and short-connected pixels in the off state. (See diagram for example.) Figure 2 As shown, the difference in the length of the connecting lines corresponding to long-connected pixels and short-connected pixels leads to a difference in the gate-source coupling capacitance (Cgs), which is reflected in the pixel voltage as the off-state pixel coupling voltage ΔVp, affecting the pixel voltage (Vp) and its brightness.

[0094] It should be understood that the aforementioned source-gate-drain capacitance is typically composed of a vertically coupled capacitor formed by the overlapping of the gate and drain in the direction perpendicular to the display panel, and a laterally coupled capacitor between the gate line and the aforementioned connecting line in the direction of data line extension.

[0095] In a positive frame, longer connected pixels are darker than shorter connected pixels; in a negative frame, longer connected pixels are brighter than shorter connected pixels. The alternation of positive and negative frames achieves a uniform distribution of brightness. When a user views the image and there is relative movement to the display screen (this is called head-shaking), the user will visually lose one positive or negative frame, causing the brightness of the positive and negative frames to be uneven, resulting in vertical lines. These vertical lines are commonly referred to as head-shaking lines.

[0096] To address the aforementioned issues, this disclosure provides an array substrate, its fabrication method, and a display panel, which will be described in detail below with reference to the accompanying drawings.

[0097] Please see Figure 3 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure. The array substrate includes:

[0098] Substrate ( Figure 3 (Not shown);

[0099] Multiple pixel pairs 1 are distributed in an array. Two gate lines 2 are provided between two adjacent rows of pixel pairs 1. Each pixel pair 1 includes a first pixel electrode 11 and a second pixel electrode 12 arranged in parallel. The first pixel electrode 11 and the second pixel electrode 12 are electrically connected to the same data line 3. The first pixel electrode 11 is located on the side of the second pixel electrode 12 away from the data line 3.

[0100] The first pixel switch 4 and the second pixel switch 5 are electrically connected with the first pixel electrode 11 and the second pixel electrode 12 respectively; in the extension direction of the data line 3, the first pixel switch 4 and the second pixel switch 5 are respectively distributed in pairs between different two pixel pairs 1, and the first pixel switch 4 and the second pixel switch 5 corresponding to the pixel pair 1 are located on both sides of the pixel pair 1; the first pixel switch 4 comprises a first gate 4g, a first electrode 41 and a second electrode 42, the first gate 4g is electrically connected with the gate line 2 closest to the first pixel switch 4, the second electrode 42 is electrically connected with the data line 3, and the first electrode 41 is electrically connected with the first pixel electrode 11;

[0101] The first conductive structure 6 is at least partially located between the two pixel pairs 1 corresponding to each pair of first pixel switches 4D; in the direction perpendicular to the substrate 0, the first conductive structure 6 at least partially overlaps with the gate line 2, and in the extension direction of the data line 3, the first conductive structure 6 at least partially overlaps with the first electrode 41 (as shown in the position of the middle s). Figure 1

[0102] The first conductive structure 6 can be connected with a specified voltage signal, such as a common signal voltage.

[0103] In the embodiments provided in the present disclosure, by arranging the pixel switches of the same type (the first pixel switch pair 4D or the second pixel switch pair 5D) between the adjacent two pixel pairs 1, and arranging the first conductive structure 6 at least partially overlapping with the gate line 2 between the first pixel switch pair 4D, and the first conductive structure 6 at least partially overlapping with the first electrode 41 of the first pixel switch 4, the first conductive structure 6 and the gate line 2 can form a vertical electric field, thereby reducing the lateral coupling capacitance formed between the gate line 2 and the first electrode 41 of the first pixel switch 4, and further reducing the difference in lateral coupling capacitance between the first pixel switch 4 and the second pixel switch 5 caused by the fact that the first electrode 41 is longer than the third electrode 51, so that the lateral coupling capacitance between the first electrode 41 in the first pixel electrode 11 and the gate line 2 is substantially the same as the lateral coupling capacitance between the third electrode 51 in the second pixel electrode 12 and the gate line 2, so that the pixel voltages of the first pixel switch 4 and the second pixel switch 5 in the off state are substantially the same, and the corresponding pixel brightness is also substantially the same. When a user watches a display screen comprising the array substrate provided in the embodiments of the present disclosure, even if the user moves relative to the display screen during the watching process, the user will not visually appear uneven light and dark distribution due to the loss of a frame of positive or negative frame picture, and the purpose of improving the shake pattern of the display panel can be finally achieved.

[0104] Please refer to Figure 4 Another structure diagram of an array substrate provided in the embodiments of the present disclosure is shown. The array substrate further comprises:

[0105] The common electrode 7 at least partially covers the pixel pairs 1 in the same row. ​

[0106] The first conductive structure 6 in the same row is electrically connected to the common electrode 7 in the adjacent row.

[0107] Please see Figure 5 This is a schematic diagram of a first conductive structure provided in an embodiment of the present invention. The first conductive structure 6 includes:

[0108] The first part 61, the second part 62, and the third part 63 are connected in sequence; the first part 61 is connected between the common electrode 7 corresponding to the second pixel electrode 12 and the second part 62, and the third part 63 is connected between the common electrode 7 corresponding to the second pixel electrode 12 in the adjacent row and the second part 62.

[0109] In the extension direction of the gate line 2, the width w1 of the second part 62 is greater than the width w2 of the first part 61 and the third part 63;

[0110] Perpendicular to the substrate ( Figure 5 In the direction (not shown), the first part 61 and the third part 63 overlap with the first pole 41 connected to their respective adjacent second pixel electrode 12, and the second part 62 overlaps with the two gate lines 2 that are electrically connected to the first pixel switch 4.

[0111] The first conductive structure 6 can be set in the same layer as the common electrode 7. This way, the first conductive structure 6 can reduce the lateral coupling capacitance formed by the first electrode 41 of the first pixel switch 4 and the gate line 2, and the first conductive structure 6 can connect the pixel electrodes of two adjacent rows.

[0112] In some embodiments, the width w1 of the second part 62 is the same as the length difference between the first pole 41 and the third pole 51 in the extension direction of the gate line 2. In this way, the second part 62 can effectively eliminate the difference in lateral coupling capacitance between the first pole 41 and the gate line 2 caused by the length difference between the second pole 41 and the second pole 42, and prevent the appearance of head-shaking patterns.

[0113] In the embodiments provided in this disclosure, by connecting the first part 61 of the first conductive structure 6 between the common electrode 7 corresponding to the second pixel electrode 12 and the second part 62, and connecting the third part 63 between the common electrode 7 corresponding to the second pixel electrode 12 in adjacent rows and the second part 62, the first conductive structure 6 can be connected between the common electrode 7 corresponding to the two second pixel electrodes 12 in adjacent pixel pairs 1, reducing the lateral coupling capacitance generated between the first conductive structure 6 and the first electrode 41; and in the extension direction of the gate line 2, the width w1 of the second part 62 is greater than the width w2 of the first part 61 and the third part 63, and the second part 62 overlaps with the two gate lines 2 that are electrically connected to the first pixel switch 4, the second part 62 can effectively shield the lateral coupling capacitance generated between the second electrode 42 (the length of which is greater than the length of the third electrode 51) and the gate line 2, so that the lateral coupling capacitance between the first electrode 41 of the first pixel switch 4 and the gate line 2 is approximately the same as the coupling capacitance between the third electrode 51 of the second pixel switch 5 and the gate line 2, thereby preventing the appearance of head-shaking patterns.

[0114] In some embodiments, in the extension direction of the data line 3, the length L of the second part 62 is greater than or equal to the sum of the width w3 of the two gate lines 2 and the gap d between the two gate lines 2.

[0115] like Figure 5 As shown, L = 2w³ + d; Figure 6 The diagram shown is a schematic diagram of another first conductive structure provided in an embodiment of this disclosure, where L>2w3+d.

[0116] Please see Figure 7 Provided for the embodiments of this disclosure Figure 6 Cross-sectional view at position AA'.

[0117] A gate line 2 is disposed on one side of a substrate 0. A gate insulating layer GI is disposed on the side of the gate line 2 away from the substrate 0. A first electrode 41 is located on the side of the gate insulating layer GI away from the gate line 2 and does not overlap with the gate line 2. An interlayer dielectric layer IDL is disposed on the side of the first electrode 41 away from the substrate 0. A first conductive structure 6 is disposed on the side of the interlayer dielectric layer IDL away from the substrate 0, and the second part 62 of the first conductive structure 6 overlaps with the gate line 2. Figure 7 In the extension direction of the data line 3, since the length L of the second part 62 of the first conductive structure 6 is greater than or equal to the width w3 of the two gate lines 2 and the gap d between the two gate lines 2, in the process of manufacturing the array substrate, due to the deposition process of each film layer, the part of the second part 62 that exceeds the width of the gate line 2 will extend from the side to the gate line 2, thereby playing a better shielding role for the signal on the gate line 2, and thus better reducing the lateral coupling capacitance between the gate line 2 and the first electrode 41, preventing the appearance of head-shaking patterns.

[0118] In some embodiments, the first conductive structures 6 in the same row have the same extension direction, as shown in Figure 5 and Figure 6 .

[0119] In other embodiments, the first conductive structures 6 in adjacent rows have different extension directions.

[0120] It should be understood that the extension direction of the first part 61 or the third part 63 of the first conductive structure 6 is regarded as the extension direction of the first conductive structure 6.

[0121] In the embodiments provided in the present disclosure, by setting the extension direction of the first conductive structure 6 in the same row to be the same and setting the extension direction of the first conductive structure 6 in adjacent rows to be different, the arrangement mode of the first pixel electrode 11 and the second pixel electrode 12 in different pixel rows can be better adapted.

[0122] Please refer to Figure 8 for a structural schematic diagram of a second conductive structure provided in the embodiments of the present disclosure. The array substrate further comprises:

[0123] The second conductive structure 8 is located between two pixel pairs 1 corresponding to the second pixel switch pair 5D, and the extension direction of the second conductive structure 8 is parallel to the extension direction of the data line 3.

[0124] The second conductive structure 8 is electrically connected to the common electrodes 7 in adjacent rows. In the direction perpendicular to the substrate 0, the second conductive structure 8 overlaps the gate line 2, and in the extension direction of the gate line 2, the width of the second conductive structure 8 is smaller than the width of the first conductive structure 6.

[0125] When the first conductive structure 6 comprises the first part 61, the second part 62 and the third part 63, the width of the first conductive structure 6 in the extension direction of the gate line 2 is the width of the second part 62.

[0126] In the embodiments provided in the present disclosure, by setting the second conductive structure 8 between two pixel pairs 1 corresponding to each second pixel switch pair 5D to have the same extension direction as the data line 3, and connecting the second conductive structure 8 between the common electrodes 7 in adjacent rows, the connection points of the common electrodes 7 in adjacent rows can be increased, and the common electrodes 7 in different pixel pair 1 regions can be balanced.

[0127] As shown in Figure 8 , the width of the second conductive structure 8 at different positions can be different. The width of the position in the gate line 2 overlapping the wider second conductive structure 8 is greater than the width of the position overlapping the narrower second conductive structure 8.

[0128] By setting the position width of the gate line 2 overlapping with the wider second conductive structure 8 to be greater than the position width of the gate line 2 overlapping with the narrower second conductive structure 8, the resistance of the common electrode 7 to the different pixel pairs 1 can be optimized, and the resistance uniformity of the gate signal to the common electrode 7 can be provided.

[0129] Please refer to Figure 9 A structure diagram of a common electrode provided by the embodiments of the present disclosure is shown. The common electrode 7 in the array substrate includes a plurality of strip-shaped electrodes 71 with different extension directions, and the two ends of the plurality of strip-shaped electrodes 71 with different extension directions are connected to each other.

[0130] In the embodiments provided by the present disclosure, by setting a plurality of strip-shaped electrodes 71 with different extension directions in the common electrode 7, and connecting the two ends of the plurality of strip-shaped electrodes 71 with different extension directions to each other (i.e., the plurality of strip-shaped electrodes 71 are connected together by the electrodes extending along the extension direction of the gate line 2 near the gate line 2), the horizontal electric field for driving the liquid crystal to rotate can be generated between the common electrode 7 and the pixel electrode.

[0131] Please continue to refer to Figure 9 In the extension direction of the gate line 2, the width w4 of the strip-shaped electrode 71 overlapping with the data line 3 is greater than the width w5 of the data line 3.

[0132] In the embodiments provided by the present disclosure, by setting the width w4 of the strip-shaped electrode 71 overlapping with the data line 3 to be greater than the width w5 of the data line 3 in the extension direction of the gate line 2, the horizontal electric field affecting the data signal near the data line 3 can be prevented, and the electromagnetic interference on the data signal can be prevented.

[0133] The first pixel electrode 11 and the second pixel electrode 12 can adopt the same transparent conductive material as the data line 3, or the first pixel electrode 11 and the second pixel electrode 12 can adopt a transparent conductive material such as Indium Tin Oxides (ITO) material, and the data line 3 can adopt a non-transparent conductive material such as a metal material.

[0134] When the first pixel electrode 11 and the second pixel electrode 12 adopt the same material as the data line 3, one mask can be used to form the first pixel electrode 11 and the second pixel electrode 12, the data line 3, the first electrode 41 and the second electrode 42 of the first pixel switch 4, and the source and drain of the third pixel switch. At this time, the first electrode 41 is directly connected to the first pixel electrode 11.

[0135] When the first pixel electrode 11 and the second pixel electrode 12 adopt different materials from the data line 3, the first electrode 41 is connected to the first pixel electrode 11 by overlapping, and the overlapping position is located in the non-opening area of the pixel.

[0136] In the embodiments provided in the present disclosure, the first pixel electrode 11 and the second pixel electrode 12 can be arranged in the same layer as the data line 3, which can effectively reduce the film layers, make the array substrate more lightweight, and effectively save the process, improve the production efficiency, and reduce the production cost.

[0137] Please refer to Figure 10 Another schematic diagram of the structure of the array substrate provided in the embodiments of the present disclosure is provided. The array substrate further includes:

[0138] A plurality of common electrode lines 9 are arranged in the crossing direction of the row direction and the column direction, and the common electrode line 9 corresponds to a row of pixel pairs 1.

[0139] Please continue to refer to Figure 10 The common electrode line 9 includes:

[0140] The main trunk electrode line 91 is arranged in the region where the different strip-shaped electrodes 71 along the different extension directions intersect.

[0141] A plurality of branch electrode lines 92 are arranged between the first pixel electrode 11 and the second pixel electrode 12 in each pixel pair 1, the extension direction of the branch electrode line 92 is the same as the extension direction of the strip-shaped electrode 71, and the intersection point of the branch electrode line 92 and the main trunk electrode line 91 is arranged in the region where the different strip-shaped electrodes 71 along the different extension directions are connected.

[0142] In the embodiments provided in the present disclosure, by arranging the branch electrode line 92 with the same extension direction as the strip-shaped electrode 71 between the first pixel electrode 11 and the second pixel electrode 12 of the pixel pair 1, the branch electrode line 92 can be used to shield the backlight of the pixels of different colors in the pixel pair 1, so that even if there is a deviation in the alignment of the different film layers when manufacturing the array substrate, the branch electrode line 92 can be used to prevent the pixels in the pixel pair 1 from producing color mixing; and by arranging the main trunk electrode line 91 in the region where the different strip-shaped electrodes 71 along the different extension directions intersect, the main trunk electrode line 91 can be used to connect the branch electrode lines 92 in the same row to form a meshed common electrode line 9, thereby reducing the resistance of the common electrode line 9.

[0143] Please continue to refer to Figure 10 The common electrode line 9 is arranged in the same layer as the gate line 2, and the branch electrode line 92 is arranged in the gap between the gate lines 2 on both sides of the corresponding pixel pair 1.

[0144] In the embodiments provided in the present disclosure, by arranging the branch electrode line 92 and the gap between the gate lines 2 on both sides of the corresponding pixel pair 1, the common electrode line 9 and the gate line 2 can be arranged in the same film layer, and the common electrode line 9 and the gate line 2 can be formed by one mask plate, thereby effectively saving the process and material, improving the production efficiency, and reducing the production cost. At the same time, since the common electrode line 9 and the gate line 2 can be formed at the same time by using one mask plate, the alignment error generated when they are formed by using different mask plates can be reduced, and the product yield can be improved.

[0145] Please refer to Figure 11 and Figure 12 , Figure 11 The present disclosure provides an array substrate pixel corresponding color film arrangement diagram, Figure 12 The present disclosure provides another array substrate structure diagram. The branch electrode line 92 corresponding to the pixel pair 1 corresponding to the blue pixel further includes a protruding portion 921;

[0146] The protruding portion 921 is located at both ends of the corresponding branch electrode line 92, and protrudes towards the blue pixel area.

[0147] As Figure 11 The arrangement of the color resistance corresponding to each pixel pair 1 is shown, Figure 12 The arrangement of the color resistance corresponding to each pixel pair 1 is shown, Figure 11 The setting position of the protruding portion 921 in the corresponding array substrate is shown, that is, the protruding portion 921 is arranged at the end of the branch electrode line 92 of the pixel pair 1 corresponding to the blue pixel (that is, the B color resistance corresponding pixel in the array substrate) close to the gate line 2, and the protruding portion 921 protrudes towards the blue pixel. Figure 11

[0148] If the color resistance is directly arranged in the array substrate, the above-mentioned blue pixel is the pixel corresponding to the blue color resistance in the array substrate;

[0149] If the color resistance is not arranged in the array substrate, but is arranged in the color film substrate opposite to the array substrate, the above-mentioned blue pixel is the pixel corresponding to the blue color resistance in the array substrate and the color film substrate.

[0150] In the embodiments provided in the present disclosure, by arranging the protruding portion 921 at the end of the branch electrode line 92 close to the gate line 2, it is convenient to arrange the connecting hole connecting the common electrode line 9 and the common electrode 7 at the corresponding position of the protruding portion 921; and since the brightness of the blue pixel is usually smaller than that of the red pixel and the green pixel, arranging the protruding portion 921 on the branch electrode line 92 corresponding to the blue pixel pair 1 can minimize the influence of the connecting hole on the transmittance of the display panel.

[0151] It should be noted that, in Figure 10 and Figure 12 ​In order to facilitate observation of the relationship between the common electrode line 9 and the strip electrode 71 of the first pixel electrode 11, the second pixel electrode 12, and the common electrode 7, only the outline of the first pixel electrode 11, the second pixel electrode 12, and the common electrode 7 is retained.

[0152] Please see Figure 13 and Figure 14 , Figure 11 This is a schematic diagram showing the location of connection holes in an array substrate according to an embodiment of the present disclosure. Figure 14 Provided for the embodiments of this disclosure Figure 13 Cross-sectional view of the BB' position.

[0153] The array substrate also includes:

[0154] In the connection hole H, at least a portion of the common electrode 7 is electrically connected to the partially overlapping protrusion 921 in the connection hole H1 in a direction perpendicular to the substrate 0.

[0155] When the gate line 2 and the common electrode line 9 are arranged in the same layer, it is only necessary to... Figure 13 A connecting hole H is provided at the edge of the protrusion 921 shown, and the corresponding cross-sectional view is as follows. Figure 14 As shown, in Figure 14 There is also a buffer layer B between the film layer where the gate line 2 is located and the substrate 0.

[0156] When etching the connection hole H using a through-hole etching process, etching stops when the metal or substrate 0 is reached because their hardness differs from other film layers. Therefore, when forming the common electrode 7, half of the common electrode 7 in the connection hole H can overlap the protrusion 921 within the connection hole H, and the other half can overlap the substrate 0 (e.g., ...). Figure 14 (As shown).

[0157] In the embodiments provided in this disclosure, by providing a connection hole H in the array substrate in a direction perpendicular to the substrate 0, at least a portion of the common electrode 7 is electrically connected to the protrusion 921 in the connection hole H, which can reduce the impedance between the common electrode 7 and the common electrode line 9. In addition, since a portion of the common electrode 7 in the connection hole H is connected to the protrusion 921, and another portion of the common electrode 7 is in contact with the substrate 0, this via design with a stepped shape is conducive to the flow of the alignment liquid, thereby improving the alignment uniformity. The alignment film layer formed by the alignment liquid is disposed on the side of the common electrode 7 away from the substrate 0.

[0158] When the data line 3 is arranged in a layer different from the first pixel electrode 11 and the second pixel electrode 12, the connection hole for electrically connecting the first electrode 41 and the first pixel electrode 11 or the third electrode 51 and the second pixel electrode 12 can also be arranged in a similar manner as the connection hole H for electrically connecting the common electrode 7 and the common electrode line 9 as described above, which will not be described herein again.

[0159] Please continue to refer to Figure 13 The second conductive structure 8 corresponding to the two branch electrode lines 92 in different directions has different widths.

[0160] The width of the overlapping position of the gate line 2 and the wider second conductive structure 8 is greater than the width of the overlapping position of the gate line 2 and the narrower second conductive structure 8.

[0161] In the embodiments provided in the present disclosure, by setting the second conductive structure 8 corresponding to the two branch electrode lines 92 in different directions to have different widths, and setting the width of the overlapping position of the gate line 2 and the wider second conductive structure 8 to be greater than the width of the overlapping position of the gate line 2 and the narrower second conductive structure 8, the uniformity of the signal load on the gate line 2 and the impedance of the common electrode 7 can be improved, thereby improving the display effect.

[0162] Please refer to Figure 15 The first electrode structure provided in the embodiments of the present disclosure.

[0163] The first sub-portion 411, the second sub-portion 412, the third sub-portion 413, and the first sub-connection portion 414 are connected to the first sub-connection portion 414.

[0164] In the extension direction of the gate line 2, the second sub-portion 412 and the third sub-portion 413 are located on the side of the first sub-connection portion 414 away from the first sub-portion 411, and the first sub-portion 411 overlaps the first gate electrode 4g, the second sub-portion 412 does not overlap the corresponding gate line 2, and the third sub-portion 413 overlaps the corresponding gate line 2.

[0165] The second sub-portion 412 is connected to the corresponding first pixel electrode 11, and the length of the second sub-portion 412 is greater than the length of the third sub-portion 413.

[0166] In the embodiments provided in the present disclosure, by setting the first electrode 41 to be composed of the first sub-part 411, the second sub-part 412, the third sub-part 413, and the first sub-connection part 414, and connecting the first sub-part 411, the second sub-part 412, and the third sub-part 413 to the first sub-connection part 414, the first sub-part 411 overlaps the first gate 4g, the second sub-part 412 does not overlap the corresponding gate line 2, and the third sub-part 413 overlaps the corresponding gate line 2, the variation of the vertical coupling capacitance of the first electrode 41 and the gate in the direction perpendicular to the substrate 0 due to the alignment deviation when different film layers of the first pixel switch 4 are manufactured can be compensated by the third sub-part 413, so that the vertical coupling capacitance remains unchanged at all times.

[0167] Please refer to Figure 16 The structural schematic diagram of the second pixel switch provided in the embodiments of the present disclosure.

[0168] The second pixel switch 5 comprises:

[0169] The third electrode 51 is electrically connected to the second pixel electrode 12, and the second electrode 42 does not overlap the second conductive structure 8;

[0170] The fourth electrode 52 is electrically connected to the data line 3;

[0171] The second gate 5g is electrically connected to the gate line 2 closest to the second pixel switch 5. As Figure 16 The part of the gate line 2 overlapping the second pixel switch 5 is reused as the second gate.

[0172] In the embodiments provided in the present disclosure, by reusing the second gate as part of the gate line 2, the aperture ratio of the corresponding pixel of the second pixel electrode 12 can be improved.

[0173] Please refer to Figure 17 The structural schematic diagram of the third electrode provided in the embodiments of the present disclosure. The third electrode 51 comprises:

[0174] The fourth sub-part 511, the fifth sub-part 512, and the second sub-connection part 513 connecting the fourth sub-part 511 and the fifth sub-part 512; in the extension direction of the gate line 2, the fifth sub-part 512 is located on the side of the second sub-connection part 513 away from the fourth sub-part 511;

[0175] The fourth sub-part 511 overlaps the second gate, and the fifth sub-part 512 overlaps the corresponding gate line 2.

[0176] In the embodiments provided in the present disclosure, by overlapping the fifth sub-part 512 with the corresponding gate line 2, the variation of the vertical coupling capacitance of the third electrode 51 and the gate in the direction perpendicular to the substrate 0 due to the alignment deviation when different film layers of the second pixel switch 5 are manufactured can be compensated by the fifth sub-part 512, so that the vertical coupling capacitance remains unchanged at all times.

[0177] In some embodiments, the overlapping area of the fifth sub-portion 512 with the corresponding gate line 2 is substantially the same as the overlapping area of the third sub-portion 413 with the corresponding gate line 2.

[0178] Since there is a certain error in forming the gate line layer and the source-drain layer, such as an error of 1x1 um, the overlapping area of the fifth sub-portion 512 with the corresponding gate line 2 is substantially the same as the overlapping area of the third sub-portion 413 with the corresponding gate line 2, that is, the error of the overlapping area of both is within 1x1 um, which can be regarded as that the overlapping areas of both are substantially the same.

[0179] Generally, the overlapping area of the source-drain of the first pixel switch 4 with the gate line 2 and the overlapping area of the source-drain of the second pixel switch 5 with the gate line 2 are the same, but there is a registration error in forming the gate line 2 layer and the source-drain layer due to the use of different masks. In the design, the overlapping area of the fifth sub-portion 512 with the corresponding gate line 2 is set to be the same as the overlapping area of the third sub-portion 413 with the corresponding gate line 2, and the fifth sub-portion 512 and the third sub-portion 413 belong to the source-drain layer. Even if there is a registration error between the source-drain layer and the gate line 2 layer, the change amount of the overlapping area of the fifth sub-portion 512 and the third sub-portion 413 with the gate line 2 will be substantially the same, so that the overlapping area of the fifth sub-portion 512 with the corresponding gate line 2 is substantially the same as the overlapping area of the third sub-portion 413 with the corresponding gate line 2, thereby making the vertical coupling capacitances of the first pixel switch 4 and the second pixel switch 5 substantially the same.

[0180] Please refer to Figure 18 The length of the first electrode and the third electrode provided by the embodiment of the present disclosure is shown in the schematic diagram.

[0181] In the extension direction of the gate line 2, the length of the first electrode 41 is greater than the length of the third electrode 51; the extension direction of the first electrode 41 of the first pixel switch pair 4D is opposite.

[0182] As shown in the left lower corner Figure 18 As shown in the left lower corner of a pair of first pixel switches 4, in the extension direction of the data line 3, the extension direction of the first electrode 41 close to the second pixel electrode 12 is X', and the extension direction of the first electrode 41 away from the first pixel electrode 11 is X, and the extension directions of the two are opposite. Similarly, the extension directions of the first electrodes of the remaining pairs of first pixel switches 4 are also opposite.

[0183] As shown in the left lower corner Figure 18 As shown in the right lower corner, the length of the first electrode 41 is L1, and the length of the third electrode 51 is L2, L1>L2.

[0184] In the embodiments provided in this disclosure, by making the length of the first electrode 41 greater than the length of the third electrode 51 in the extension direction of the gate line 2, the lengths of the second electrode 42 of the first pixel switch 4 and the fourth electrode 52 of the second pixel switch 5 can be made approximately the same, thereby concentrating the length difference between the first pixel electrode 11 and the second pixel electrode 12 electrically connected to the same data line 3 on the length of the third electrode 51; at the same time, by setting the extension direction of the first electrode 41 of each pair of first pixel switches 4 to be the same, it is convenient to set the first conductive structure 6 between the first electrodes 41 of each pair of first pixel switches 4 in the extension direction of the data line 3, thereby using a first conductive structure 6 to simultaneously shield a portion of the gate line 2 between the first electrodes 41 of each pair of first pixel switches 4, thereby reducing the lateral coupling capacitance of the first pixel switch 4, and making the coupling capacitance of the first pixel switch 4 and the second pixel switch 5 approximately the same.

[0185] Please see Figure 19 This is a schematic diagram of an array substrate provided in an embodiment of the present disclosure. The pixels in the same column have the same color, and the pixel electrodes corresponding to blue and green are electrically connected to the same gate line 2.

[0186] like Figure 19 As shown, the pixel electrodes (including the first pixel electrode 11 and the second pixel) connected on the odd-numbered gate lines 2 are both blue and green pixel electrodes.

[0187] Please see Figure 20 A comparison image of pixel brightness and darkness for GB co-gate and RG co-gate pixels provided in this embodiment of the disclosure. Figure 20 The schematic diagram corresponding to the GB cogate is as follows Figure 19 The image corresponding to the RG gate is far away. Figure 1 .exist Figure 1 and Figure 19 In the schematic diagram shown, the data signal is a column-flipping signal, meaning that all data within a frame are of the same polarity, and the next frame has the opposite polarity. If... Figure 1 and Figure 19 If the gate signal has only one output time, then the charging for that row is entirely the data for that row, and there is no pre-charging. However, in the current display product driving method, the output time of a single row is longer than the output time of a single row. Before the data for the current row arrives, the driving transistor is in the on state, and the data from the previous row will be charged into the current row (i.e., pre-charging). If the pre-charging signals are of the same polarity, then pre-charging is effective; if they are of opposite polarity or the corresponding data from the previous row is not displayed, then there is no pre-charging. When displaying a sky-blue image, the R pixel is not displayed. According to the above rules, it can be determined that... Figure 19 In GB co-grid (i.e., all G pixels in a row are in the same grid, and all B pixels are in the same grid) and Figure 1 The image brightness comparison diagram corresponding to RG co-grating (i.e., all R pixels and all G pixels in a row are co-grating) is shown below. Figure 20As shown, Figure 20 In this method, setting the letter to a dark color indicates that the corresponding pixel has pre-charging, setting the letter to a light color indicates that the corresponding pixel does not have pre-charging, and pixels without a letter indicate that the corresponding pixel (R) is not displayed.

[0188] from Figure 20 As can be seen, the GB co-grid scheme, in most cases, has pre-charge in the GB pixels, resulting in more uniform brightness across the GB pixels and a better display of sky blue images. However, the RG co-grid scheme causes adjacent G and B column pixels to be either equally dark or equally bright, which will produce noticeable vertical stripes on the display panel when displaying sky blue images. Therefore, using the GB co-grid scheme can improve the display effect of sky blue images (i.e., Windows images).

[0189] Based on the same inventive concept, this disclosure provides a display panel, please refer to [link to relevant documentation]. Figure 21 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure. The display panel includes:

[0190] The array substrate 100 and the opposing substrate 200 are as described above; the specific structure of the array substrate 100 can be found in the description of the array substrate side above, and is not limited here.

[0191] The liquid crystal layer 300 is located between the array substrate 100 and the opposing substrate 200.

[0192] The display panel also includes a color filter layer, which includes multiple color filters arranged in an array. The color filter layer can be located in the array substrate 100 or in the opposing substrate 200.

[0193] This display panel can exist in display devices such as LCD monitors, LCD screens, and LCD TVs, as well as in mobile devices such as mobile phones, tablets, and laptops.

[0194] Based on the same inventive concept, embodiments of this disclosure provide a display device, including the display panel as described above.

[0195] Based on the same inventive concept, this disclosure provides a method for fabricating an array substrate as described above. Please refer to [link to relevant documentation]. Figure 22 This is a flowchart illustrating a method for fabricating an array substrate according to an embodiment of this disclosure. The structural form of the resulting array substrate can be found in the aforementioned description of the array substrate, and will not be repeated here. The fabrication method includes:

[0196] Step S10: Provide a substrate;

[0197] Step S11: On one side of the substrate, multiple gate lines and multiple data lines are formed. The multiple gate lines and multiple data lines define multiple pixel pairs distributed in the array. Two gate lines are provided between two adjacent rows of pixel pairs. The pixel pair includes a first pixel electrode and a second pixel electrode arranged in parallel. The first pixel electrode and the second pixel electrode are electrically connected to the same data line. The first pixel electrode is located on the side of the second pixel electrode away from the data line.

[0198] Step S12: On one side of the substrate, a first pixel switch and a second pixel switch are formed, which are electrically connected to the first pixel electrode and the second pixel electrode, respectively; in the extension direction of the data line, the first pixel switch and the second pixel switch are each distributed in pairs between two different pixel pairs, and the first pixel switch and the second pixel switch corresponding to the pixel pair are located on both sides of the pixel pair; the first pixel switch includes a first gate, a first electrode and a second electrode, the first gate is electrically connected to the gate line closest to the first pixel switch, the second electrode is electrically connected to the data line, the first electrode is electrically connected to the first pixel electrode, and in the extension direction of the data line, the first electrode and the second pixel electrode at least partially overlap;

[0199] Step S13: A first conductive structure is formed on the side of the multiple data lines away from the substrate, and at least part of the first conductive structure is located between two pixel pairs corresponding to each pair of first pixel switches; in the direction perpendicular to the substrate, the first conductive structure at least partially overlaps with the gate line, and in the extension direction of the data line, the first conductive structure at least partially overlaps with the first electrode.

[0200] Please see Figure 23 The fabrication provided for the embodiments of this disclosure Figure 18 The flowchart of the array substrate is shown.

[0201] Step S21: Form the gate line 2 and the common electrode line 9, that is, form the gate line 2 and the common electrode line 9 in the same layer and with the same material.

[0202] In the substrate ( Figure 23 On one side (not shown), gate line 2 and common electrode line 9 are formed. The structural forms of gate line 2 and common electrode line 9 can be found in the description of the array substrate side above, and will not be repeated here.

[0203] In this case, a portion of the gate line 2 is reused as the first gate 4g and the second gate 5g.

[0204] Step S22: Form an active layer for 4s / 5s.

[0205] On the side of the gate line 2 away from the substrate, an active layer 4s of the first pixel switch 4 and an active layer 5s of the second pixel switch 5 are formed. Optionally, the active layer 5s can be amorphous silicon, low-temperature polycrystalline silicon or oxide semiconductor layer, which is not limited here.

[0206] Step S23: forming the data line 3 and the first pixel electrode 11 and the second pixel electrode 12 and the source-drain layer.

[0207] On the side of the active layer 4s / 5s away from the substrate, the data line 3 and the first pixel electrode 11 and the second pixel electrode 12 and the source-drain layer are formed, the source-drain layer including the first pole and the second pole of the first pixel switch 4 and the third pole and the fourth pole of the second pixel switch, thus forming the first pixel switch 4 and the second pixel switch 5.

[0208] The materials used by the above-mentioned data line 3 and the source-drain layer and the first pixel electrode 11 and the second pixel electrode 12 can be the same or different.

[0209] When the materials used by them are the same, the data line 3 and the first pixel electrode 11 and the second pixel electrode 12 and the source-drain layer can be formed in sequence.

[0210] When the materials used by them are different, for example, the first pixel electrode and the second pixel electrode use ITO, and the data line and the source-drain layer use other conductive materials, such as metal materials, the first pixel electrode 11 is conductive with the first pole through overlapping, and the second pixel electrode 12 is conductive with the third pole through overlapping, and in the opening area corresponding to the pixel, the first pole and the second pole are both not overlapped with the respective corresponding opening area, and the first pixel electrode 11 and the second pixel electrode 12 can be overlapped with the first pole and the third pole by extending a connecting line in the direction of the first pole and the third pole, such as Figure 24 The figure shows the schematic diagram of forming the data line and the source-drain layer and the first pixel electrode and the second pixel electrode provided by the embodiment of the disclosure.

[0211] Step S24: forming an insulating layer on the side of the first pixel electrode 11 away from the substrate, and forming a connecting hole H on the insulating layer corresponding to the protruding part 921.

[0212] Step S25: forming a common electrode layer.

[0213] The common electrode layer includes the common electrode 7 covering each row of pixels and the first conductive structure 6 and the second conductive structure 8 connecting the common electrodes 7 of adjacent rows, at least part of the first conductive structure 6 is located between the two pixel pairs corresponding to each pair of first pixel switches 4; in the direction perpendicular to the substrate, the first conductive structure 6 at least partially overlaps with the gate line 2, and in the extension direction of the data line 3, the first conductive structure 6 at least partially overlaps with the first pole 41.

[0214] Although the preferred embodiments of the disclosure have been described, those skilled in the art can make further changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be interpreted as including all changes and modifications falling within the scope of the disclosure.

[0215] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed disclosure without departing from the spirit or scope of the disclosure. Thus, it is intended that the disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims and their equivalents.

Claims

1. An array substrate, comprising: a substrate; a plurality of pixel pairs arranged in an array, two adjacent rows of the pixel pairs being provided with two gate lines, each of the pixel pairs comprising a first pixel electrode and a second pixel electrode arranged side by side, the first pixel electrode and the second pixel electrode being electrically connected to a same data line, the first pixel electrode being arranged on a side of the second pixel electrode away from the data line; a first pixel switch and a second pixel switch electrically connected to the first pixel electrode and the second pixel electrode respectively, the first pixel switch and the second pixel switch being arranged in pairs respectively between different two pixel pairs in an extension direction of the data line, and the first pixel switch and the second pixel switch corresponding to the pixel pair being located on two sides of the pixel pair; the first pixel switch comprising a first gate, a first electrode and a second electrode, the first gate being electrically connected to the gate line closest to the first pixel switch, the second electrode being electrically connected to the data line, and the first electrode being electrically connected to the first pixel electrode; a first conductive structure, at least part of the first conductive structure being located between two pixel pairs corresponding to each pair of the first pixel switches; the first conductive structure at least partially overlapping the gate line in a direction perpendicular to the substrate, and the first conductive structure at least partially overlapping the first electrode in the extension direction of the data line; a common electrode at least partially covering the pixel pairs in the same row; the first conductive structure in the same row being electrically connected to the common electrodes in adjacent rows; the first conductive structure comprising: a first portion, a second portion and a third portion connected in sequence, the first portion being connected between the common electrode corresponding to the second pixel electrode and the second portion, and the third portion being connected between the common electrode corresponding to the second pixel electrode in the adjacent row and the second portion; the second portion having a width greater than that of the first portion and the third portion in the extension direction of the gate line; the first portion and the third portion respectively overlapping the first electrode connected to the second pixel electrode in the direction perpendicular to the substrate, and the second portion partially overlapping the two gate lines electrically connected to the first pixel switch corresponding to the pair in the direction perpendicular to the substrate; the second portion having a length greater than or equal to a width of the two gate lines and a gap between the two gate lines in the extension direction of the data line. 3.The array substrate of claim 1 or 2, wherein the first conductive structure in the same row has the same extension direction. The extension directions of the first conductive structure in two adjacent rows are different. The array substrate further comprises: a second conductive structure located between two pixel pairs corresponding to the second pixel switch pair, and the second conductive structure being parallel to the extension direction of the data line; the second conductive structure being electrically connected to the common electrodes in adjacent rows, the second conductive structure overlapping the gate line in the direction perpendicular to the substrate, and the second conductive structure having a width smaller than that of the first conductive structure in the extension direction of the gate line. The common electrode comprises: ​ ​ ​ ​ ​ ​ ​ 2. The array substrate of claim 1, wherein, ​ ​ 4. The array substrate of claim 3, wherein, ​ 5. The array substrate of claim 1 or 2, wherein, ​ ​ ​ 6. The array substrate of claim 5, wherein, ​ A plurality of strip electrodes having different extension directions, both ends of the plurality of strip electrodes having different extension directions being connected to each other.

7. The array substrate of claim 6, wherein, In an extension direction of the gate lines, a width of the strip electrode overlapping the data line is greater than a width of the data line.

8. The array substrate of claim 6, wherein, The array substrate further comprises: A plurality of common electrode lines extending in a row direction and a column direction and being arranged at intersections of the common electrode lines and the pixel pairs, the common electrode lines corresponding to a row of the pixel pairs.

9. The array substrate of claim 8, wherein, The common electrode line comprises: A trunk electrode line in a straight line shape, arranged at a region of intersections of the strip electrodes having different extension directions; A plurality of branch electrode lines, the branch electrode lines being located between the first pixel electrode and the second pixel electrode in each pixel pair, the branch electrode lines having the same extension direction as the strip electrodes, and intersections of the branch electrode lines and the trunk electrode line being arranged at a region of connection of the strip electrodes having different extension directions.

10. The array substrate of claim 9, wherein, The common electrode line is arranged in the same layer as the gate line, and the branch electrode line is arranged in a gap between the gate lines on both sides of the corresponding pixel pair.

11. The array substrate of claim 9, wherein, The branch electrode line corresponding to the pixel pair with the blue pixel further comprises a protruding portion; The protruding portion is located at both ends of the corresponding branch electrode line and protrudes towards a region of the blue pixel.

12. The array substrate of claim 11, wherein, The array substrate further comprises: A first connection hole, in a direction perpendicular to the substrate, a protruding portion of at least part of the common electrode partially overlapping the first connection hole is electrically connected.

13. The array substrate of claim 11, wherein, Widths of the second conductive structures corresponding to the two branch electrode lines with different orientations of the protruding portion are different; In a position overlapping the wider one of the gate line and the second conductive structure, a width is greater than a width in a position overlapping the narrower one of the gate line and the second conductive structure.

14. The array substrate of claim 5, wherein, The first electrode comprises: A first sub-portion, a second sub-portion, a third sub-portion, and a first sub-connection portion, the first sub-portion, the second sub-portion, and the third sub-portion being connected to the first sub-connection portion; In an extension direction of the gate line, the second sub-portion and the third sub-portion are located on a side of the first sub-connection portion away from the first sub-portion, the first sub-portion overlaps the first gate electrode, the second sub-portion does not overlap the corresponding gate line, and the third sub-portion overlaps the corresponding gate line; The second sub-portion is connected to the corresponding first pixel electrode, and a length of the second sub-portion is greater than a length of the third sub-portion.

15. The array substrate of claim 14, wherein, The second pixel switch comprises: A third electrode electrically connected to the second pixel electrode, and the second electrode does not overlap the second conductive structure; A fourth electrode electrically connected to the data line; A second gate electrode electrically connected to the gate line closest to the second pixel switch.

16. The array substrate of claim 15, wherein, The third electrode comprises: A fourth sub-portion, a fifth sub-portion, and a second sub-connection portion connecting the fourth sub-portion and the fifth sub-portion; in an extension direction of the gate line, the fifth sub-portion is located on a side of the second sub-connection portion away from the fourth sub-portion; The fourth sub-portion overlaps the second gate electrode, and the fifth sub-portion overlaps the corresponding gate line.

17. The array substrate of claim 16, wherein, An overlapping area of the fifth sub-portion and the corresponding gate line is substantially the same as an overlapping area of the third sub-portion and the corresponding gate line.

18. The array substrate of claim 15, wherein, The length of the first electrode is greater than the length of the third electrode in the extending direction of the gate line; and the extending directions of the first electrodes of the first pixel switch pair are opposite.

19. The array substrate of claim 1 or 2, wherein, The pixels in the same column have the same color; The pixel electrodes corresponding to the blue color and the green color are electrically connected to the same gate line.

20. The array substrate of claim 1 or 2, wherein, The data line is arranged in the same layer as the first pixel electrode and the second pixel electrode.

21. A display panel, comprising: The array substrate and the counter substrate according to any one of claims 1-20; A liquid crystal layer between the array substrate and the counter substrate.

22. A method for manufacturing the array substrate according to any one of claims 1-20, comprising: providing a substrate; forming a plurality of gate lines and a plurality of data lines on one side of the substrate, the plurality of gate lines and the plurality of data lines defining a plurality of pixel pairs arranged in an array, two gate lines being arranged between two adjacent rows of the pixel pairs; each pixel pair comprising a first pixel electrode and a second pixel electrode arranged side by side, the first pixel electrode and the second pixel electrode being electrically connected to the same data line, the first pixel electrode being arranged on the side of the second pixel electrode away from the data line; forming a first pixel switch and a second pixel switch on the same side of the substrate, the first pixel switch and the second pixel switch being electrically connected to the first pixel electrode and the second pixel electrode respectively; in the extending direction of the data line, the first pixel switch and the second pixel switch are each arranged between two different pixel pairs, and the first pixel switch and the second pixel switch corresponding to the pixel pair are arranged on the two sides of the pixel pair; the first pixel switch comprises a first gate electrode, a first electrode and a second electrode, the first gate electrode being electrically connected to the gate line closest to the first pixel switch, the second electrode being electrically connected to the data line, and the first electrode being electrically connected to the first pixel electrode; in the extending direction of the data line, the first electrode at least partially overlaps the second electrode; forming a first conductive structure on the side of the plurality of data lines away from the substrate, at least part of the first conductive structure being arranged between the two pixel pairs corresponding to the first pixel switch pair; in the direction perpendicular to the substrate, the first conductive structure at least partially overlaps the gate line, and in the extending direction of the data line, the first conductive structure at least partially overlaps the first electrode.

Images