Data access system, method, and program product for heterogeneous multi-core processors

Abstract

The present invention relates to the field of data access technology, and in particular to a data access system, method, and program product for a heterogeneous multi-core processor. The present invention provides a data access system for a heterogeneous multi-core processor, comprising: a heterogeneous multi-core processor, a target storage block, and a register module. The present invention introduces a register module comprising a counting unit, a register unit, and a lock status unit, which provides a hardware basis for the heterogeneous multi-core processor to access the target storage block, and can support the rapid response and atomicity of the lock operation. The present invention takes into account the possible data competition and data dependency of the processing core, and by assigning a line program number to the processing core and designing management logic in combination with the register module, it can effectively adapt to data competition and data dependency, avoid unnecessary time consumption, and ensure that the processing core efficiently completes data access.

Description

Technical Field

[0001] The present invention relates to the field of data access technology, and more specifically, to: 1. a data access system for a heterogeneous multi-core processor; 2. a data access method for a heterogeneous multi-core processor; 3. a computer program product. Background Art

[0002] As the number of processing cores increases, heterogeneous multi-core CPUs can process more tasks in parallel, significantly improving processor performance and efficiency.

[0003] However, multiple processing cores need to access a shared memory block (generally set in the NPU, i.e., the target memory block) to achieve data exchange and communication. Since the processing cores are executed in parallel, if there is no effective synchronization mechanism, problems such as data competition and deadlock may occur, resulting in inconsistent data and system instability.

[0004] In addition, many synchronization mechanisms use a lock mechanism implemented purely in software, the purpose of which is to ensure that different processing cores access the target storage block in an orderly and mutually exclusive manner, reduce conflicts and waiting time between processing cores, and ensure data consistency and integrity. However, this approach will bring higher overhead, such as context switching and memory access delays. Summary of the invention

[0005] Based on this, it is necessary to provide a data access system, method, and program product for heterogeneous multi-core processors to address the problems of data inconsistency and system instability caused by the lack of an effective synchronization mechanism when existing heterogeneous multi-core CPUs access shared storage target storage blocks.

[0006] The present invention is implemented by the following technical solutions:

[0007] In a first aspect, the present invention discloses a data access system for a heterogeneous multi-core processor, comprising: a heterogeneous multi-core processor, a target storage block, and a register module. The heterogeneous multi-core processor is communicatively connected with the target storage block via the register module.

[0008] Wherein, the heterogeneous multi-core processor comprises N Processing cores CPU1~CPU N ; N ≥ 2; if the processing core CPU n Need to access the target storage block, CPU n Assigned line program ID n ;

[0009] The register module includes a counting unit, a register unit, and a lock state unit; the lock state unit is used to lock or unlock the target storage block; when the processing core CPU n When accessing the storage target storage block, the register is used to store the IDn The counting part is used to add its count value m ; m Is a positive integer.

[0010] The data access system for a heterogeneous multi-core processor implements the method or process according to the embodiment of the present disclosure.

[0011] In a second aspect, the present invention discloses a data access method for a heterogeneous multi-core processor, which is applied to the data access system for a heterogeneous multi-core processor disclosed in the first aspect;.

[0012] Data access methods for heterogeneous multi-core processors include:

[0013] Step 1, if the processing core CPU n If the target storage block needs to be accessed, the CPU n Assign line program ID n , proceed to step 2;

[0014] Step 2, CPU n Read the information of the lock status part to determine whether the target storage block is in a locked state;

[0015] If the storage target storage block is in a locked state, repeat step 2;

[0016] If the storage target storage block is in unlocked state, proceed to step 3;

[0017] Step 3, CPU n Determine whether the target storage block it accesses exists with Q processing cores Y1~Y Q Data dependence; among them, Y1~Y Q There is no data dependency between them; processing core Y q ∈[CPU1,…,CPU N ], and Y q ≠CPU n ;q∈[1,Q],n-1≥Q≥1;

[0018] If there are Q processing cores Y1~Y Q , then proceed to step 4;

[0019] If there are no Q processing cores Y1~Y P , then proceed to step 8;

[0020] Step 4: Towards Y1~Y Q Assign the same line program number ID z , proceed to step 5;

[0021] Step 5, CPU nRead the information in the register to determine whether the target storage block is Y q access;

[0022] If the information of the depository is ID z , then proceed to step 6;

[0023] If the information of the deposit department is not ID z , then repeat step 5;

[0024] Step 6, CPU n Read the count value of the counter to determine Y1~Y Q Whether all target storage blocks have been accessed;

[0025] If the counter value is not m Q, then repeat step 6;

[0026] If the counter value is m Q, then proceed to step 7;

[0027] Step 7, CPU n Repeat reading the information of the lock status part until the target storage block is unlocked, and then proceed to step 8;

[0028] Step 8, CPU n Start data access to the target storage block, and the register part is updated to the CPU n Line program ID n , the counting unit is reset to m , the lock status unit locks the target storage block;

[0029] Waiting for CPU n After the data access is completed, the lock status unit unlocks the target storage block.

[0030] This data access method for a heterogeneous multi-core processor implements a method or process according to an embodiment of the present disclosure.

[0031] In a third aspect, the present invention discloses a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the data access method for a heterogeneous multi-core processor disclosed in the second aspect are implemented.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. The present invention introduces a register module including a counting unit, a register unit, and a lock status unit, which provides a hardware basis for heterogeneous multi-core processors to access target storage blocks and can support fast response and atomicity of lock operations.

[0034] 2. The present invention takes into account possible data competition and data dependency in the processing core. By assigning a line program number to the processing core and designing management logic in combination with the register module, it can effectively adapt to data competition and data dependency, avoid unnecessary time consumption, and ensure that the processing core efficiently completes data access.

[0035] 3. The present invention provides a software method based on hardware foundation, realizes the collaborative work of software and hardware, can effectively improve system performance, ensure data consistency, optimize resource management, and simplify development complexity; the present invention has important practical application value in the use environment of heterogeneous multi-core processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0037] Figure 1 A first hardware configuration diagram of a data access system for a heterogeneous multi-core processor provided in Embodiment 1 of the present invention;

[0038] Figure 2 A second hardware configuration diagram of a data access system for a heterogeneous multi-core processor provided in Embodiment 1 of the present invention;

[0039] Figure 3 This is a flow chart of a data access method for a heterogeneous multi-core processor provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0043] Example 1

[0044] This embodiment 1 provides a data access system for a heterogeneous multi-core processor, which is the hardware design part of the present invention:

[0045] The data access system for a heterogeneous multi-core processor includes: a heterogeneous multi-core processor, a target storage block, and a register module. The heterogeneous multi-core processor is connected to the target storage block through the register module.

[0046] It should be noted that the target storage block can be set in the NPU (ie, the scenario mentioned in the background technology) or in other storage hardware.

[0047] Among them, heterogeneous multi-core processors include N Processing cores CPU1~CPU N ; N ≥ 2; if the processing core CPU n Need to access the target storage block, CPU n Assigned line program ID n ——This operation can be implemented at the software level (see the subsequent introduction to data access methods for heterogeneous multi-core processors).

[0048] The register module includes a counting unit, a storage unit, and a lock state unit.

[0049] When processing core CPU n When accessing the storage target storage block, the register is used to store the ID n The counting part is used to add its count value m ,The lock status part is used to lock the target storage block; m is a positive integer, generally, m Usually take 1.

[0050] When processing core CPU n After completing access to the storage target storage block, the lock state unit is used to unlock the target storage block.

[0051] For the lock state part, the following design can be adopted: when the lock state part writes a lock signal, the target storage block is locked accordingly; when the lock state part writes an unlock signal, the target storage block is unlocked accordingly. In other words, the CPU nWhen accessing the target storage block, the lock status unit will write a lock signal, so that the target storage block is locked accordingly; the CPU n After completing the access to the target storage block, the lock state unit will write the unlock signal, thereby unlocking the target storage block accordingly. In this embodiment 1, the lock signal can be a 0xff signal; the unlock signal can be a signal other than 0xff.

[0052] For the register module, it can adopt the following two hardware configurations:

[0053] 1. See Figure 1 The register module includes: an access register; a counting unit, a register unit, and a lock state unit are all arranged in the access register. That is, the counting unit, the register unit, and the lock state unit are all integrated into the same register.

[0054] Generally, the total bit width of the access register is [31:0], so the following configuration can be adopted: the counting part occupies the bit width [23:16], the register part occupies the bit width [15:0], and the lock state part occupies the bit width [31:24]. Of course, the bit widths occupied by the counting part, the register part, and the lock state part are customized according to actual needs and are not limited to the specific values ​​given above.

[0055] Case 1 can reduce the amount of hardware, but since the reserved bit width is small or even non-existent, the subsequent function expandability is weak.

[0056] 2. See Figure 2 The register module includes: a thread register and a lock register; the counter and the register unit are both set in the thread register, and the lock state unit is set in the lock register. That is, the counter and the register unit are integrated into one register, and the lock state unit is integrated into another register.

[0057] Generally, the total bit width of the access register is [31:0], and the following configuration can be adopted: the counting part occupies the bit width [23:16], the register part occupies the bit width [15:0], and other bit widths are reserved; the total bit width of the register is [31:0], and the following configuration can be adopted: the lock status part occupies the bit width [7:0], and other bit widths are reserved.

[0058] Similarly, the widths occupied by the counting unit, the register unit, and the lock status unit are customized according to actual needs and are not limited to the specific values ​​given above.

[0059] Compared with Case 1, Case 2 only adds one hardware, but since a certain bit width can be reserved, the subsequent functional expandability is greatly increased.

[0060] It should be noted that the subsequent functional extensibility mentioned above is intended to solve other data access problems that may arise in the future and will not be explained in detail here.

[0061] This embodiment 1 also provides a data access method for a heterogeneous multi-core processor, which is the software design part of the present invention:

[0062] The data access method for a heterogeneous multi-core processor is applied to the above-mentioned data access system for a heterogeneous multi-core processor, that is, the two constitute a combination of software and hardware.

[0063] See also Figure 3 ,Data access methods for heterogeneous multi-core processors include:

[0064] Step 1, if the processing core CPU n If the target storage block needs to be accessed, the CPU n Assign line program ID n , proceed to step 2.

[0065] Step 2, CPU n Read the information of the lock status part to determine whether the target storage block is in a locked state;

[0066] If the storage target storage block is in a locked state (i.e., the information in the lock state portion is a locked signal), repeat step 2;

[0067] If the storage target storage block is in the unlocked state (ie, the information of the lock state portion is a non-locked signal), proceed to step 3.

[0068] Step 3, CPU n Determine whether the target storage block it accesses exists with Q processing cores Y1~Y Q Data dependence (i.e. Y1~Y Q When accessing the target storage block, the data of the target storage block will be written and changed. n Need to wait for Y1~Y Q Access the target storage block only after all accesses to the target storage block are completed to ensure data consistency);

[0069] Among them, processing core Y q ∈[CPU1,…,CPU N ], and Y q ≠CPU n ;

[0070] q∈[1,Q], n-1≥Q≥1.

[0071] It should be noted that: Y1~Y Q There is no data dependency between them.

[0072] If there are Q processing cores Y1~Y Q , then proceed to step 4;

[0073] If there are no Q processing cores Y1~Y P , proceed to step 8.

[0074] Step 4: Towards Y1~Y Q Assign the same line program number ID z , proceed to step 5;

[0075] That is, Y q To access the target storage block, the thread signals are all ID z .

[0076] Step 5, CPU n Read the information in the register to determine whether the target storage block is Y q access;

[0077] If the information of the depository is ID z (i.e. the target storage block is being q Access), then proceed to step 6;

[0078] If the information of the deposit department is not ID z (i.e. the target storage block is not Y q access), repeat step 5.

[0079] Step 6, CPU n Read the count value of the counter to determine Y1~Y Q Whether all target storage blocks have been accessed;

[0080] If the counter value is not m Q (i.e. Y1~Y Q If the target storage block has not been accessed completely), repeat step 6;

[0081] If the counter value is m Q (i.e. Y1~Y Q If all target storage blocks have been accessed), proceed to step 7.

[0082] Step 7, CPU n Repeat reading the information of the lock status part until the target storage block is in the unlocked state, and then proceed to step 8.

[0083] Step 8, CPU n Start data access to the target storage block, and the register part is updated to the CPU n Line program ID n , the counting unit is reset to m , the lock status unit locks the target storage block;

[0084] Waiting for CPU n After the data access is completed, the lock status unit unlocks the target storage block.

[0085] The above data access method for heterogeneous multi-core processors provides an effective synchronization mechanism. By setting the rules of steps 1 to 7, Y1 to Y2 are synchronized according to the actual situation of data dependency. Q Access the target storage block in sequence, and use the counting unit, the register unit, and the linear sequence number to real-time Y1~Y Q The access progress so that the CPU n Determine the access timing and complete the access to the target storage block in the manner of step 8, thereby ensuring data consistency and system stability.

[0086] It should be noted that in step 3, if there are Q processing cores Y1~Y Q Data dependency, which is equivalent to CPU n 、Y1~Y Q A total of Q+1 processing cores need to access the target storage block, that is, the above method also covers the situation where multiple processing cores access the target storage block.

[0087] Example 2

[0088] This embodiment 2 discloses a computer device, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps of the data access method for a heterogeneous multi-core processor disclosed in embodiment 1 are implemented.

[0089] This embodiment 2 also discloses a readable storage medium, in which computer program instructions are stored. When the computer program instructions are read and executed by a processor, the steps of the data access method for a heterogeneous multi-core processor disclosed in embodiment 1 are executed.

[0090] This embodiment 2 also discloses a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the data access method for a heterogeneous multi-core processor disclosed in embodiment 1 are implemented.

[0091] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A data access method for a heterogeneous multi-core processor, characterized in that: Its application is to data access systems for heterogeneous multi-core processors; The data access system for a heterogeneous multi-core processor comprises: a heterogeneous multi-core processor, a target storage block, and a register module; the heterogeneous multi-core processor is connected to the target storage block through the register module; Wherein, the heterogeneous multi-core processor comprises N Processing cores CPU1~CPU N ; N ≥ 2; Wherein, the register module includes a counting unit, a storage unit, and a lock state unit; The data access method for a heterogeneous multi-core processor comprises: Step 1, if the processing core CPU n If the target storage block needs to be accessed, the CPU n Assign line program ID n , proceed to step 2; Step 2, CPU n Read the information of the lock status part to determine whether the target storage block is in a locked state; If the storage target storage block is in a locked state, repeat step 2; If the storage target storage block is in unlocked state, proceed to step 3; Step 3, CPU n Determine whether the target storage block to be accessed exists with Q processing cores Y1~Y Q Data dependence; among them, Y1~Y Q There is no data dependency between them; processing core Y q ∈[CPU1,…,CPU N ], and Y q ≠CPU n ;q∈[1,Q],n-1≥Q≥1; If there are Q processing cores Y1~Y Q , then proceed to step 4; If there are no Q processing cores Y1~Y P If the data is dependent on , proceed to step 8; Step 4: Towards Y1~Y Q Assign the same line program number ID z , proceed to step 5; Step 5, CPU n Read the information in the register to determine whether the target storage block is Y q access; If the information of the depository is ID z , then proceed to step 6; If the information of the deposit department is not ID z , then repeat step 5; Step 6, CPU n Read the count value of the counter to determine Y1~Y Q Whether all target storage blocks have been accessed; If the counter value is not m Q, then repeat step 6; m is a positive integer; If the counter value is m Q, then proceed to step 7; Step 7, CPU n Repeat reading the information of the lock status part until the target storage block is in the unlocked state, and then proceed to step 8; Step 8, CPU n Start data access to the target storage block, and the register part is updated to the CPU n Line program ID n , the counting unit is reset to m , the lock status unit locks the target storage block; Waiting for CPU n After the data access is completed, the lock status unit unlocks the target storage block.

2. A data access system for a heterogeneous multi-core processor, characterized in that: It uses the data access method for heterogeneous multi-core processors as claimed in claim 1; The data access system for a heterogeneous multi-core processor comprises: a heterogeneous multi-core processor, a target storage block, and a register module; the heterogeneous multi-core processor is connected to the target storage block through the register module; Wherein, the heterogeneous multi-core processor comprises N Processing cores CPU1~CPU N ; N ≥ 2; if the processing core CPU n Need to access the target storage block, CPU n Assigned line program ID n ; Wherein, the register module includes a counting unit, a storage unit, and a lock state unit; When processing core CPU n When accessing the storage target storage block, the register is used to store the ID n The counting part is used to add its count value m ,The lock status part is used to lock the target storage block; m is a positive integer; When processing core CPU n After completing access to the storage target storage block, the lock state unit is used to unlock the target storage block.

3. The data access system for heterogeneous multi-core processors according to claim 2, characterized in that: The register module comprises: an access register; a counting unit, a register unit and a lock state unit are all arranged in the access register.

4. The data access system for heterogeneous multi-core processors according to claim 3, characterized in that: The total bit width of the access register is [31:0], the counting part occupies the bit width [23:16], the register part occupies the bit width [15:0], and the lock state part occupies the bit width [31:24].

5. The data access system for heterogeneous multi-core processors according to claim 2, characterized in that: The register module comprises: a thread register and a lock register; a counter and a register part are both arranged in the thread register, and a lock state part is arranged in the lock register.

6. The data access system for heterogeneous multi-core processors according to claim 5, characterized in that: The total bit width of the thread register is [31:0], the counting part occupies the bit width [23:16], the register part occupies the bit width [15:0], and other bit widths are reserved; The total bit width of the lock register is [31:0], the lock status part occupies the bit width [7:0], and other bit widths are reserved.

7. The data access system for heterogeneous multi-core processors according to claim 2, characterized in that: When the lock state unit writes a lock signal, the target storage block is locked accordingly; When the unlock signal is written into the lock state part, the target storage block is unlocked accordingly.

8. The data access system for heterogeneous multi-core processors according to claim 7, characterized in that: The lock signal is 0xff signal; the unlock signal is a signal other than 0xff.

9. The data access system for heterogeneous multi-core processors according to claim 2, characterized in that: The target storage block is set in the NPU.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the data access method for a heterogeneous multi-core processor as claimed in claim 1 are implemented.

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