Method for evaluating performance of chip circuit design, and electronic device

Abstract

The present application relates to a method and electronic device for evaluating the performance of a chip circuit design, the method comprising: obtaining a first chip circuit design file, which is a file obtained by performing metal filling design on a target chip circuit; obtaining metal filling data of the circuit according to the circuit design file to form metal filling rules; performing performance evaluation based on various iterative optimization versions of the circuit, and simulating the circuit environment after metal filling based on the metal filling rules when extracting parasitic parameters during the performance evaluation process, as the circuit environment for extracting parasitic parameters. The technical solution of the present application, after obtaining the metal filling rules based on the circuit design file for the first time, the subsequent iterative evaluation can directly use the metal filling rules to simulate the circuit environment after metal filling, without the need to repeatedly perform metal filling design to obtain the circuit design file, effectively improving analysis efficiency, shortening the design cycle, and reducing development costs.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method, device, electronic device and storage medium for performing performance evaluation on a chip circuit design. Background Art

[0002] The dummy fill technique used in chip manufacturing is a technology that fills the voids in the chip circuit layout (i.e., areas without any metal interconnects) with metal to fill the uneven surface and improve the flatness of the metal layer. It can effectively reduce local over-polishing or under-polishing during the chemical mechanical polishing (CMP) process and improve the manufacturing quality and reliability of the chip.

[0003] Since metal fillers are real metal materials in chip circuits and have similar electrical and thermal properties to other parts of the chip, as the performance requirements of chip design at advanced process nodes become more stringent, it is necessary to correctly evaluate the impact of these metal fillers when iterating the design of chip circuits.

[0004] Traditionally, when inserting metal fillers for design iterations, metal filling design is required for the current iteration version of the circuit to obtain chip circuit design files (including metal filler graphics information files, generally of GDSII and OASIS types) during each iteration optimization, so as to update the circuit environment for extracting parasitic parameters, re-extract parasitic parameters for performance evaluation, until the evaluation passes. Since it is necessary to repeatedly perform metal filling design on circuits of different iteration versions to obtain chip circuit design files, a long design cycle is required both in the early and late stages of design, which increases development costs. Summary of the invention

[0005] In response to the above technical problems, the present application provides a method, device, electronic device and storage medium for performance evaluation of chip circuit design, which eliminates the need for repeated metal filling design to obtain chip circuit design files, effectively improves analysis efficiency, shortens the design cycle and reduces development costs.

[0006] In order to solve the above technical problems, the present application provides a method for evaluating the performance of a chip circuit design, the method comprising the following steps:

[0007] Acquire a first chip circuit design file corresponding to a target chip circuit, where the first chip circuit design file is a file obtained by performing metal filling design on the target chip circuit;

[0008] According to the first chip circuit design file, obtaining metal filling material data of the target chip circuit to form a metal filling rule;

[0009] Based on each iteratively optimized version of the target chip circuit, a performance evaluation is performed, wherein when extracting parasitic parameters during the performance evaluation process, the circuit environment after metal filling is simulated based on the metal filling rule to serve as the circuit environment for extracting parasitic parameters.

[0010] In some embodiments, acquiring metal filler data of the target chip circuit according to the first chip circuit design file to form a metal filling rule includes:

[0011] Scanning the target chip circuit after metal filling design according to the first chip circuit design file to obtain metal filling data corresponding to each metal filling pattern filled in the target chip circuit;

[0012] The metal filling data corresponding to each of the metal filling patterns are processed to determine the metal filling rule of the target chip circuit.

[0013] In some embodiments, simulating a circuit environment after metal filling based on the metal filling rule includes:

[0014] Determine a fillable area of ​​the current iteration version of the target chip circuit;

[0015] The metal filling is simulated in the fillable area according to the metal filling rule to obtain a circuit environment after the metal filling.

[0016] In some embodiments, when extracting parasitic parameters during the performance evaluation process, simulating a circuit environment after metal filling based on the metal filling rule as a circuit environment for extracting parasitic parameters includes:

[0017] When extracting parasitic parameters during performance evaluation, determine whether the current optimization is the first iteration;

[0018] If the current iteration is not the first optimization, the circuit environment after metal filling is simulated based on the metal filling rule to serve as the circuit environment for extracting parasitic parameters.

[0019] In some embodiments, the method further comprises:

[0020] If the current optimization is the first iteration, when extracting parasitic parameters, the circuit environment corresponding to the first chip circuit design file is used as the circuit environment for extracting parasitic parameters.

[0021] In some embodiments, the performance evaluation is performed based on each iteratively optimized version of the target chip circuit, wherein when extracting parasitic parameters during the performance evaluation process, the circuit environment after metal filling is simulated based on the metal filling rule as the circuit environment for extracting parasitic parameters, including:

[0022] Simulating a circuit environment after metal filling based on the metal filling rule to serve as a circuit environment for extracting parasitic parameters;

[0023] Extracting parasitic parameters corresponding to the current iteration version of the target chip circuit based on the circuit environment;

[0024] Performing performance evaluation analysis based on the parasitic parameters;

[0025] If the result of the performance evaluation is failure, when the next iteration version of the target chip circuit is obtained, the step of simulating the circuit environment after metal filling based on the metal filling rule is entered as a step of extracting the circuit environment of parasitic parameters.

[0026] In some embodiments, the target chip circuit is iteratively optimized until the performance evaluation is completed, and the method further includes:

[0027] Metal filling design is performed on the target chip circuit that has passed the performance evaluation result to obtain a second chip circuit design file.

[0028] The present application also provides a device for evaluating the performance of a chip circuit design, comprising:

[0029] A file acquisition module, used to acquire a first chip circuit design file corresponding to a target chip circuit, wherein the first chip circuit design file is a file obtained by performing metal filling design on the target chip circuit;

[0030] A rule acquisition module, used to acquire metal filling material data of the target chip circuit according to the first chip circuit design file, and form a metal filling rule;

[0031] An evaluation module is used to perform performance evaluation based on various iterative optimization versions of the target chip circuit. When extracting parasitic parameters during the performance evaluation process, the circuit environment after metal filling is simulated based on the metal filling rules to serve as the circuit environment for extracting parasitic parameters.

[0032] The present application also provides an electronic device, including a storage medium and a controller, characterized in that a computer program is stored on the storage medium, and when the computer program is executed by the controller, the steps of the method for performance evaluation of chip circuit design as described above are implemented.

[0033] The present application also provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method for performing performance evaluation on a chip circuit design as described above are implemented.

[0034] The present application discloses a method, electronic device, and storage medium for evaluating the performance of a chip circuit design. The method includes: obtaining a first chip circuit design file, the first chip circuit design file being a file obtained by performing metal filling design on a target chip circuit; obtaining metal filler data of the target chip circuit according to the first chip circuit design file to form metal filling rules; and performing performance evaluation based on each iterative optimization version of the target chip circuit, wherein when extracting parasitic parameters during the performance evaluation process, the circuit environment after metal filling is simulated based on the metal filling rules as the circuit environment for extracting parasitic parameters. The technical solution of the present application, after obtaining the metal filling rules based on the chip circuit design file for the first time, can directly use the metal filling rules to simulate the circuit environment after metal filling when performing performance evaluation during subsequent iterative optimization processes, without repeatedly performing metal filling design to obtain the chip circuit design file, effectively improving analysis efficiency, shortening the design cycle, and reducing development costs. On this basis, the technical solution of the present application does not need to repeatedly extract metal filling rules during the iteration process, further improving analysis efficiency and shortening the design cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The figure is a flow chart of a method for evaluating the performance of a chip circuit design according to an embodiment.

[0036] Figure 2 is a schematic diagram showing metal filler data according to an embodiment.

[0037] Figure 3 is a schematic diagram showing a circuit environment after simulating metal filling according to an embodiment.

[0038] Figure 4 The table is a comparison table of analysis accuracy of timing closure analysis based on chip circuit design files and timing closure analysis based on metal filling rule simulation circuit environment according to an embodiment.

[0039] Figure 5 It is a schematic structural diagram of a device for performing performance evaluation on a chip circuit design according to an embodiment. DETAILED DESCRIPTION

[0040] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thoroughly understood.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items. In the present invention, "each" includes one and more than two quantities.

[0042] Figure 1 FIG. 1 is a flow chart showing a method for evaluating the performance of a chip circuit design according to an embodiment. Figure 1 As shown, the method for evaluating the performance of a chip circuit design of the present application comprises the following steps:

[0043] S1, obtaining a first chip circuit design file corresponding to a target chip circuit, where the first chip circuit design file is a file obtained by performing metal filling design on the target chip circuit;

[0044] S2, acquiring metal filling material data of the target chip circuit according to the first chip circuit design file, and forming a metal filling rule;

[0045] S3, performing performance evaluation based on each iteratively optimized version of the target chip circuit, wherein when extracting parasitic parameters during the performance evaluation process, the circuit environment after metal filling is simulated based on the metal filling rule to serve as the circuit environment for extracting parasitic parameters.

[0046] The target chip circuit is the chip circuit (design) to be iteratively optimized. As the iterative optimization proceeds, the target chip circuit will have different iterative versions. The first chip circuit design file is a file obtained by metal filling design of the target chip circuit. It is used to characterize the target chip circuit after metal filling design, including the target chip circuit itself and the metal filler as a whole structure, and can be used as a design file for chip production.

[0047] In some embodiments, the first chip circuit design file includes layout and wiring data of the chip circuit and an information file including a metal filler graphic (i.e., metal filler data, generally of the type GDSII and OASIS). The information of the metal filler graphic may, for example, include the size of the metal fill graphic, the position of the graphic in the chip circuit layout, etc.

[0048] The metal filling rules of the target chip circuit are extracted based on the data in the first chip circuit design file. They are a set of parameter data that conform to circuit manufacturing rules and can characterize the distribution law of metal fillers in the target chip circuit. Therefore, the metal filling rules extracted based on the first chip circuit design file are universal for different iterative versions of the target chip circuit.

[0049] When iteratively optimizing the target chip circuit, the target chip circuit is subjected to performance analysis based on parasitic parameters to determine whether the iterative design of the target chip circuit meets the requirements. In some embodiments, the performance analysis may be a timing closure analysis, and may also be a power consumption analysis, a signal integrity analysis, an electromigration voltage drop analysis, a thermal effect analysis, etc. In some embodiments, when performing the timing closure analysis, the target chip circuit may be subjected to timing analysis in the form of a static timing analysis.

[0050] Parasitic parameters include capacitance information and resistance information. The circuit environment for extracting parasitic parameters includes the circuit structure of the current iteration version of the target chip circuit and the metal filler of the simulated filling. Therefore, it can more accurately reflect the impact of metal filling on resistance and capacitance and perform more accurate performance analysis.

[0051] Since the metal filling rules of the target chip circuit are universal for different iterative versions of the target chip circuit, during the iteration process, there is no need to repeatedly extract the metal filling rules before extracting the parasitic parameters, and there is no need to generate a file recording the metal filling rules. It is only necessary to simulate the circuit environment after metal filling according to the metal filling rules during parasitic parameter extraction, that is, there is no need to re-enter the file used to record the metal filling rules, thereby speeding up the iterative calculation process. At the same time, since the circuit environment after metal filling is simulated based on the metal filling rules as the circuit environment for extracting parasitic parameters, the simulated circuit environment can be directly stored in the cache during performance evaluation during the iterative optimization process, and there is no need to re-insert the metal filler design for the current iterative version of the target chip circuit, nor is there a need to repeatedly generate and input new chip circuit design files, which reduces the iteration steps, improves design efficiency, and shortens the design cycle.

[0052] In some embodiments, the first chip circuit design file may be a file obtained by performing metal filling design on the target chip circuit for the first time, which can reduce the number of times chip circuit design files are generated during the iteration process and improve efficiency. In some embodiments, the first chip circuit design file may also be a file obtained by performing metal filling design on the latest iteration version of the target chip circuit after optimizing the target chip circuit for a certain number of iterations, which can more accurately evaluate the impact of metal filling on circuit performance during the first few iterations. At the same time, it can also reduce the number of times chip circuit design files are generated during subsequent iterations, taking into account the efficiency of circuit iteration design.

[0053] In some embodiments, step S2, according to the first chip circuit design file, obtains metal filling material data of the target chip circuit to form a metal filling rule, including:

[0054] Scanning the target chip circuit after metal filling design according to the first chip circuit design file to obtain metal filling material data corresponding to each metal filling material pattern filled in the target chip circuit;

[0055] The metal filling data corresponding to each metal filling pattern is processed to determine the metal filling rule of the target chip circuit.

[0056] After the first chip circuit design file is imported, an environmental scan is performed on each metal filler in the target chip circuit to obtain metal filler data corresponding to the metal filler pattern. Figure 2 , is a schematic diagram of metal filler data according to an embodiment, wherein F represents metal filler, P represents power line, S represents signal line, 1 represents the width of metal filler, 2 represents the length of metal filler, 3 represents the horizontal distance between metal fillers, 4 represents the vertical distance between metal fillers, 5 represents the horizontal spacing between metal filler and signal line, 6 represents the vertical spacing between metal filler and signal line, 7 represents the horizontal spacing between metal filler and power line, 8 represents the vertical spacing between metal filler and power line, 9 represents the horizontal spacing between metal filler and blocking area, 10 represents the vertical spacing between metal filler and blocking area, 11 represents the horizontal spacing between metal filler and circuit boundary, 12 represents the vertical spacing between metal filler and circuit boundary, and 13 represents the reference direction. It can be understood that the metal filler data is not limited to the above-mentioned ones and can be adjusted as needed.

[0057] Next, the metal filler data corresponding to each metal filler pattern is processed to determine the metal filling rule of the target chip circuit. In some embodiments, the metal filler data can be processed in the same manner throughout the entire circuit, or in different regions of the target chip circuit according to the distribution characteristics of the circuit, so that the metal filling rule is closer to the effect of the metal filling design. In some embodiments, the processing method can be, for example, directly taking an average value or taking a weighted average value.

[0058] In some embodiments, in step S3, simulating the circuit environment after metal filling based on the metal filling rule includes:

[0059] Determine a fillable area of ​​a current iteration version of a target chip circuit;

[0060] According to the metal filling rules, metal filling is simulated in the fillable area to obtain the circuit environment after metal filling.

[0061] Among them, after obtaining the metal filling rules, the metal filling rules are used to simulate the insertion of metal fillers in the current iteration version of the target chip circuit. This step is performed in the early stage of the parasitic parameter extraction process. In the data preparation stage of the parasitic parameter extraction process, the circuit without metal fillers is scanned layer by layer to obtain the fillable area. Then, the fillable area is simulated and filled according to the direction, spacing, length and width requirements contained in the metal filling rules, and then the entire circuit is filled to obtain the circuit environment for extracting parasitic parameters, such as Figure 3 shown. Figure 3 The circuit data of the circuit environment shown can be directly cached without generating and outputting files before performance evaluation. Then, parasitic parameters are extracted based on this to obtain resistor and capacitor parasitic parameters reflecting the metal filling effect.

[0062] In some embodiments, in step S3, when extracting parasitic parameters during the performance evaluation process, simulating the circuit environment after metal filling based on the metal filling rule as the circuit environment for extracting parasitic parameters includes:

[0063] When extracting parasitic parameters during performance evaluation, determine whether the current optimization is the first iteration;

[0064] If the current is not the first iteration optimization, the circuit environment after metal filling is simulated based on the metal filling rule as the circuit environment for extracting parasitic parameters. In some embodiments, determining whether the current is the first iteration optimization may determine whether the metal filling rule already exists or determine the number of recorded iteration optimizations.

[0065] In some embodiments, the method further comprises:

[0066] If the current optimization is the first iteration, when extracting parasitic parameters, the circuit environment corresponding to the first chip circuit design file is used as the circuit environment for extracting parasitic parameters.

[0067] Among them, when it is the first iteration optimization, the circuit environment corresponding to the first chip circuit design file can be directly used as the circuit environment for extracting parasitic parameters, without repeatedly simulating metal filling using the extracted metal filling rules for the first iteration version, which can further speed up the iteration speed. In the subsequent performance evaluation process, the circuit environment after metal filling is simulated based on the metal filling rules as the circuit environment for extracting parasitic parameters, without repeatedly generating chip circuit design files, which speeds up the iteration speed.

[0068] Since the metal filling rule may not be used to simulate the circuit environment during the first iteration optimization, the step of extracting the metal filling rule may be performed before extracting the parasitic parameters, may be performed after extracting the parasitic parameters, or may be performed simultaneously.

[0069] In some embodiments, step S3, based on each iteratively optimized version of the target chip circuit, a performance evaluation is performed, wherein when extracting parasitic parameters during the performance evaluation process, a circuit environment after metal filling is simulated based on a metal filling rule as a circuit environment for extracting parasitic parameters, including:

[0070] Simulating the circuit environment after metal filling based on the metal filling rule to serve as the circuit environment for extracting parasitic parameters;

[0071] Extracting parasitic parameters corresponding to the current iteration version of the target chip circuit based on the circuit environment;

[0072] Performance evaluation based on parasitic parameters;

[0073] If the result of the performance evaluation is failed, when the next iteration version of the target chip circuit is obtained, the circuit environment after metal filling is simulated based on the metal filling rule as a step for extracting the circuit environment of parasitic parameters.

[0074] Among them, after obtaining the metal filling rules, iterative optimization begins. If the result of the performance evaluation of this iterative version is failed, for example, the timing has not converged, the designer can redesign and optimize the circuit to generate the next iterative version. After obtaining the next iterative version of the target chip circuit, a new round of analysis begins. The circuit environment after metal filling is simulated based on the metal filling rules as the circuit environment for extracting parasitic parameters. At this time, there is no need to regenerate the chip circuit design file or re-extract the metal filling rules, which effectively speeds up the iteration speed.

[0075] In some embodiments, the method further comprises:

[0076] Metal filling design is performed on the target chip circuit whose performance evaluation result is passed to obtain a second chip circuit design file.

[0077] Among them, when the result of the performance evaluation of the latest iteration version of the target chip circuit is passed, the metal filling design is performed on the latest iteration version to obtain the second chip circuit design file. In this way, the present application realizes the use of simulated metal filling to replace the metal filling design in the early and middle stages of the design, so that the iterations in the early and middle stages are accelerated, and it can smoothly transition to the metal filling design when the performance evaluation passes in the later stage. Compared with performing metal filling design in the early, middle and late stages, the iteration cycle is shortened. Compared with performing metal filling design in the later stage, the difference in the results of performance evaluation before and after the metal filling design is avoided. The later design does not need to spend extra time and resources to readjust the design, which reduces the risk and time cost of the later design, and can help the design team complete performance evaluation and optimize the design more quickly.

[0078] Figure 4 The comparison table of analysis accuracy of timing closure analysis based on chip circuit design files and timing closure analysis based on metal filling rule simulation circuit environment is shown. It can be seen that when the method of the present application is used in timing closure evaluation, the error between the analysis accuracy of timing closure analysis based on chip circuit design files and the analysis accuracy of timing closure analysis based on metal filling rule simulation circuit environment can be controlled within 1%. In terms of accuracy, the error between the two is very small, indicating that the method of simulating metal filling in the present application can be equivalent to replacing metal filling design, accelerating timing convergence without affecting accuracy, and accelerating the design iteration process.

[0079] When iterating the chip circuit design in actual applications, first perform layout and routing based on the chip design Netlist file and the chip process technology file (Tech file). Layout and routing can be completed using a layout and routing tool (PR tool) to generate a file containing physical layout and routing information (such as a DEF file). Next, use the PR tool to perform metal filling and generate a file containing metal filling information (such as a GDSII file). It should be noted that GDSII is a graphic file format that is used in many stages of chip design, but it has different uses in different stages.

[0080] After generating a file containing metal filling information, combined with a file containing physical layout and routing information, a parasitic parameter extraction tool (such as an RC tool) can be used to extract metal filling rules, and then the parasitic parameters such as resistance and capacitance parameters of the chip circuit can be extracted in combination with the physical layout and routing information or the iterated physical layout and routing information to obtain a netlist file containing parasitic parameter information such as parasitic resistance and capacitance (such as a SPEF netlist file), and then based on the netlist file containing parasitic parameter information, a performance evaluation is performed. Taking timing closure analysis as an example, a timing tool is used to perform static timing analysis to obtain a timing analysis report (Final Timing Report). According to the results of the performance evaluation report, if the performance evaluation passes (such as timing convergence), the graphic file (which can be a GDSII file) containing the final version of the physical layout and routing information and metal filling information is used for tape-out and production. If (timing is not converged), the chip circuit continues to be iterated.

[0081] In this application, the GDSII file of the metal filler is required to generate the metal fill rule during the first iteration. In all subsequent iterations, there is no need to use the PR tool for metal filling again. Instead, the circuit environment after metal filling is directly simulated based on the metal filling rule, and there is no need to generate the GDSII file containing the metal filling information again before the performance evaluation result is passed. It can be seen that since there is no need to repeatedly perform metal filling design to obtain the circuit design file, the analysis efficiency can be effectively improved, the design cycle can be shortened, and the development cost can be reduced.

[0082] like Figure 5 As shown, the present application also provides a device for evaluating the performance of a chip circuit design, comprising:

[0083] A file acquisition module 51 is used to acquire a first chip circuit design file corresponding to a target chip circuit, where the first chip circuit design file is a file obtained by performing metal filling design on the target chip circuit;

[0084] A rule acquisition module 52 is used to acquire metal filling material data of a target chip circuit according to a first chip circuit design file to form a metal filling rule;

[0085] The evaluation module 53 is used to perform performance evaluation based on each iterative optimization version of the target chip circuit. When extracting parasitic parameters during the performance evaluation process, the circuit environment after metal filling is simulated based on the metal filling rule to serve as the circuit environment for extracting parasitic parameters.

[0086] In some embodiments, the rule acquisition module 52 is used to:

[0087] Scanning the target chip circuit after metal filling design according to the first chip circuit design file to obtain metal filling material data corresponding to each metal filling material pattern filled in the target chip circuit;

[0088] The metal filling data corresponding to each metal filling pattern is processed to determine the metal filling rule of the target chip circuit.

[0089] In some embodiments, when simulating the circuit environment after metal filling based on the metal filling rule, the evaluation module 53 is used to:

[0090] Determine a fillable area of ​​a current iteration version of a target chip circuit;

[0091] According to the metal filling rules, metal filling is simulated in the fillable area to obtain the circuit environment after metal filling.

[0092] In some embodiments, when extracting parasitic parameters during the performance evaluation process, when simulating the circuit environment after metal filling based on the metal filling rule as the circuit environment for extracting parasitic parameters, the evaluation module 53 is used to:

[0093] When extracting parasitic parameters during performance evaluation, determine whether the current optimization is the first iteration;

[0094] If the current process is not the first iteration optimization, the circuit environment after metal filling is simulated based on the metal filling rule to serve as the circuit environment for extracting parasitic parameters.

[0095] In some embodiments, the evaluation module 53 is further configured to:

[0096] If the current optimization is the first iteration, when extracting parasitic parameters, the circuit environment corresponding to the first chip circuit design file is used as the circuit environment for extracting parasitic parameters.

[0097] In some embodiments, performance evaluation is performed based on each iteratively optimized version of the target chip circuit. When extracting parasitic parameters during the performance evaluation process, the circuit environment after metal filling is simulated based on the metal filling rule as the circuit environment for extracting parasitic parameters. The evaluation module 53 is used to:

[0098] Simulating the circuit environment after metal filling based on the metal filling rule to serve as the circuit environment for extracting parasitic parameters;

[0099] Extracting parasitic parameters corresponding to the current iteration version of the target chip circuit based on the circuit environment;

[0100] Performance evaluation based on parasitic parameters;

[0101] If the result of the performance evaluation is failed, when the next iteration version of the target chip circuit is obtained, the circuit environment after metal filling is simulated based on the metal filling rule as a step for extracting the circuit environment of parasitic parameters.

[0102] In some embodiments, the apparatus further comprises a file generation module for:

[0103] Metal filling design is performed on the target chip circuit whose performance evaluation result is passed to obtain a second chip circuit design file.

[0104] For the specific implementation process of the steps executed by each module in the device for performing performance evaluation on chip circuit design, please refer to the description of the method embodiment, which will not be repeated here.

[0105] The present application also provides an electronic device, including a storage medium and a controller, wherein the storage medium stores a computer program, and when the computer program is executed by the controller, the steps of the method for performance evaluation of chip circuit design as described in the above embodiment are implemented.

[0106] The present application also provides a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the method for performance evaluation of chip circuit design as described in the above embodiment are implemented.

[0107] The present application discloses a method, electronic device, and storage medium for evaluating the performance of a chip circuit design. The method includes: obtaining a first chip circuit design file, the first chip circuit design file being a file obtained by performing metal filling design on a target chip circuit; obtaining metal filling rules for the target chip circuit according to the first chip circuit design file; and performing performance evaluation based on each iteratively optimized version of the target chip circuit, wherein when extracting parasitic parameters during the performance evaluation process, the circuit environment after metal filling is simulated based on the metal filling rules as the circuit environment for extracting parasitic parameters. The technical solution of the present application, after obtaining the metal filling rules based on the chip circuit design file for the first time, can directly use the metal filling rules to simulate the circuit environment after metal filling when performing performance evaluation during subsequent iterative optimization processes, without repeatedly performing metal filling design to obtain the chip circuit design file, effectively improving analysis efficiency, shortening the design cycle, and reducing development costs. On this basis, the technical solution of the present application does not need to repeatedly extract metal filling rules during the iteration process, further improving analysis efficiency and shortening the design cycle.

[0108] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for evaluating the performance of a chip circuit design, characterized in that: The method comprises the following steps: Acquire a first chip circuit design file corresponding to a target chip circuit, where the first chip circuit design file is a file obtained by performing metal filling design on the target chip circuit; According to the first chip circuit design file, obtaining metal filling material data of the target chip circuit to form a metal filling rule; Based on each iteratively optimized version of the target chip circuit, a performance evaluation is performed, wherein when extracting parasitic parameters during the performance evaluation process, a circuit environment after metal filling is simulated based on the metal filling rule to serve as a circuit environment for extracting parasitic parameters; When extracting parasitic parameters in the performance evaluation process, simulating the circuit environment after metal filling based on the metal filling rule as the circuit environment for extracting parasitic parameters includes: When extracting parasitic parameters during performance evaluation, determine whether the current optimization is the first iteration; If the current iteration is not the first optimization, the circuit environment after metal filling is simulated based on the metal filling rule to serve as the circuit environment for extracting parasitic parameters.

2. The method according to claim 1, characterized in that The step of acquiring metal filling material data of the target chip circuit according to the first chip circuit design file and forming a metal filling rule comprises: Scanning the target chip circuit after metal filling design according to the first chip circuit design file to obtain metal filling data corresponding to each metal filling pattern filled in the target chip circuit; The metal filling data corresponding to each of the metal filling patterns are processed to determine the metal filling rule of the target chip circuit.

3. The method according to claim 1, characterized in that: The simulating the circuit environment after metal filling based on the metal filling rule includes: Determine a fillable area of ​​the current iteration version of the target chip circuit; The metal filling is simulated in the fillable area according to the metal filling rule to obtain a circuit environment after the metal filling.

4. The method according to claim 1, characterized in that The method further comprises: If the current optimization is the first iteration, when extracting parasitic parameters, the circuit environment corresponding to the first chip circuit design file is used as the circuit environment for extracting parasitic parameters.

5. The method according to claim 1, characterized in that The method of performing performance evaluation based on each iteratively optimized version of the target chip circuit, wherein when extracting parasitic parameters during the performance evaluation process, simulating the circuit environment after metal filling based on the metal filling rule as the circuit environment for extracting parasitic parameters, includes: Simulating a circuit environment after metal filling based on the metal filling rule to serve as a circuit environment for extracting parasitic parameters; Extracting parasitic parameters corresponding to the current iteration version of the target chip circuit based on the circuit environment; performing performance evaluation according to the parasitic parameters; If the result of the performance evaluation is failure, when the next iteration version of the target chip circuit is obtained, the step of simulating the circuit environment after metal filling based on the metal filling rule is entered as a step of extracting the circuit environment of parasitic parameters.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: Metal filling design is performed on the target chip circuit that has passed the performance evaluation result to obtain a second chip circuit design file.

7. A device for evaluating the performance of a chip circuit design, characterized in that: include: A file acquisition module, used to acquire a first chip circuit design file corresponding to a target chip circuit, wherein the first chip circuit design file is a file obtained by performing metal filling design on the target chip circuit; A rule acquisition module, used to acquire metal filling material data of the target chip circuit according to the first chip circuit design file, and form a metal filling rule; An evaluation module, configured to perform performance evaluation based on each iteratively optimized version of the target chip circuit, wherein when extracting parasitic parameters during the performance evaluation process, a circuit environment after metal filling is simulated based on the metal filling rule to serve as a circuit environment for extracting parasitic parameters; When extracting parasitic parameters during performance evaluation, the evaluation module is used to simulate the circuit environment after metal filling based on the metal filling rule as the circuit environment for extracting parasitic parameters: When extracting parasitic parameters during performance evaluation, determine whether the current optimization is the first iteration; If the current process is not the first iteration optimization, the circuit environment after metal filling is simulated based on the metal filling rule to serve as the circuit environment for extracting parasitic parameters.

8. An electronic device, comprising a storage medium and a controller, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the controller, the steps of the method for performance evaluation of chip circuit design according to any one of claims 1 to 6 are implemented.

9. A storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the steps of the method for performance evaluation of chip circuit design according to any one of claims 1 to 6.

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