Method for preparing IGBT wafer and IGBT wafer

Abstract

The present invention provides a method for manufacturing an IGBT wafer and an IGBT wafer, belonging to the field of semiconductors. The method for manufacturing the IGBT wafer includes providing a wafer and performing a first film pasting on the front side of the wafer. After the first film pasting, the wafer is successively subjected to film planarization treatment and back thinning treatment of the wafer, and then the first film pasting is subjected to a first film peeling treatment. The front side of the wafer after the first film peeling treatment is subjected to a second film pasting. The back side of the wafer after the second film pasting is successively subjected to ion implantation and thermal annealing treatment. The wafer after the thermal annealing treatment is subjected to a second film peeling treatment. By performing a second film pasting on the back side of the wafer after the back thinning treatment and film peeling treatment of the wafer, the present invention can avoid scratches, residual central imprints, etc. on the front side of the wafer, play a role in protecting the front side of the wafer, improve the overall appearance performance of the IGBT wafer, and improve the qualification rate of the wafer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a method for preparing an IGBT wafer and an IGBT wafer. Background Art

[0002] Insulated Gate Bipolar Transistor (IGBT) is a new type of composite power device developed on the basis of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and Bipolar transistor, and has MOS input and bipolar output functions. IGBT combines the advantages of small on-state voltage drop, large current density, high breakdown voltage of bipolar devices and small drive power, fast switching speed, high input impedance, and good thermal stability of power MOSFET, and is widely used in fields such as AC motors, frequency converters, switching power supplies, lighting circuits, and traction drives. As the core device of power electronic converters, it lays the foundation for the high-frequency, miniaturization, high performance, and high reliability of application devices.

[0003] Currently, for the process of preparing IGBT wafers, in the back-end process of the wafers, processes such as wafer thinning, ion implantation, and laser thermal annealing (LTA) need to be carried out in sequence. In the traditional back-end process of wafers, first, a film is pasted on the front surface of the wafer for protection, then the film is planarized, secondly, the back grinding and thinning process of the wafer is started, and finally, the film is removed and processes such as ion implantation and laser thermal annealing are entered. Refer Figures 1 to 4 as shown Figure 1 is a schematic diagram of the fixed-point structure on the front surface of the wafer during ion implantation. Among them, 10 - fixed-point structure. Figure 2 is Figure 1 a schematic diagram of a scratch formed at the fixed-point structure in Figure 2 It can be seen that an obvious scratch 20 is formed in the fixed-point structure 10. Figure 3 is a simple schematic diagram of a central imprint formed on the surface of the wafer. Figure 4 is an electron scan of a central imprint formed on the surface of the wafer. Among them, 30 - central imprint. From Figure 4 it can be seen that a central imprint 30 is formed in the b area. From Figures 1 to 4 it can be known that when using the traditional method for preparing wafers, it is easy to generate defects such as scratches 20, central imprints 30 on the front surface of the wafer, and black dot residual glue generated during the LTA process, which damage the wafer and reduce the qualified rate of the wafer.

[0004] It should be noted that the information disclosed in the background art part of this invention is only intended to deepen the understanding of the general background technology of this invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0005] The object of the present invention is to provide a method for preparing an IGBT wafer, so as to solve the problem that in the existing wafer preparation method, when performing processes such as ion implantation and thermal annealing on the back surface of the wafer after film removal, defects such as scratches and residual imprints are likely to occur on the front surface of the wafer, damaging the wafer and reducing the qualified rate of the wafer.

[0006] To solve the above technical problems, the present invention provides a method for preparing an IGBT wafer, including:

[0007] Providing a wafer and performing a first film lamination on the front surface of the wafer;

[0008] After the first film lamination, the wafer is successively subjected to film planarization treatment and back thinning treatment of the wafer, and then the first film lamination is subjected to a first film removal treatment;

[0009] Performing a second film lamination on the front surface of the wafer after the first film removal treatment;

[0010] Performing ion implantation and thermal annealing treatments on the back surface of the wafer after the second film lamination in sequence;

[0011] Performing a second film removal treatment on the wafer after the thermal annealing treatment.

[0012] Preferably, the wafer after the second film lamination is placed in an annealing machine for laser thermal annealing treatment. The annealing machine includes a carrier table, and the surface of the film lamination in contact with the carrier table has a step, and a channel for air flow is formed between the step and the carrier table.

[0013] Preferably, the Taiko process is used to perform back thinning treatment on the wafer.

[0014] Preferably, chemical mechanical polishing is used to perform planarization treatment on the first film lamination.

[0015] Preferably, during the process of the first film lamination, the pressure setting range of the roller is 0.295 Mpa to 0.305 Mpa, and the peeling speed of the first film lamination is 0.5 mm / s to 2.5 mm / s.

[0016] Preferably, during the process of the second film lamination, the pressure setting range of the roller is 0.295 Mpa to 0.305 Mpa, and the peeling speed of the second film lamination is 0.5 mm / s to 2.5 mm / s.

[0017] Preferably, ion implantation on the back surface of the wafer includes boron ion implantation, and the depth of boron ion implantation is 0.1 μm to 0.25 μm.

[0018] Preferably, the ion implantation on the back side of the wafer includes phosphorus ion implantation, and the depth of the phosphorus ion implantation is 0.6 μm to 0.8 μm, or 1.6 μm - 1.8 μm.

[0019] Preferably, the thermal annealing treatment is laser thermal annealing treatment, the wavelength of the laser is 500 nm to 600 nm, and the surface transient laser annealing temperature is 1400 °C to 1600 °C.

[0020] Based on the same inventive concept, the present invention also provides an IGBT wafer, which is manufactured by using the manufacturing method of the above IGBT wafer.

[0021] Compared with the prior art, the manufacturing method of the IGBT wafer of the present invention has the following advantages:

[0022] In the manufacturing method of the IGBT wafer provided by the present invention, after the back side of the wafer is thinned and the film is removed, a second film is attached to the back side of the wafer. When ion implantation and thermal annealing treatment are performed on the back side of the wafer, defects such as scratches and residual central imprints on the front side of the wafer can be avoided, which plays a role in protecting the front side of the wafer, improves the overall appearance performance of the IGBT wafer, and increases the qualified rate of the wafer.

[0023] The IGBT wafer provided by the present invention and the manufacturing method of the IGBT wafer provided by the present invention belong to the same inventive concept. Therefore, the front side of the IGBT wafer provided by the present invention is protected by the second film attachment, and no defects such as scratches and residual central imprints are generated, which improves the overall appearance performance of the IGBT wafer and has a high qualified rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic structural diagram of a fixed point on the front side of the wafer during ion implantation.

[0025] Figure 2 It is at Figure 1 A schematic diagram showing a scratch formed at the fixed point structure.

[0026] Figure 3 It is a simple schematic structural diagram showing a central imprint formed on the surface of the wafer.

[0027] Figure 4 It is an electron scanning image showing a central imprint formed on the surface of the wafer.

[0028] Figure 5 It is a flowchart of the manufacturing method of the IGBT wafer provided in an embodiment of the present invention.

[0029] Figure 6 It is a schematic structural diagram formed by attaching a first film to the front side of the wafer in an embodiment of the present invention.

[0030] Figure 7 It is a schematic structural diagram after the planarization treatment of the first film pasting in an embodiment of the present invention.

[0031] Figure 8 It is a schematic structural diagram after the thinning treatment of the back surface of the wafer using this embodiment of the present invention.

[0032] Figure 9 It is a schematic structural diagram after the first film peeling treatment of the wafer in an embodiment of the present invention.

[0033] Figure 10 It is a schematic structural diagram after the second film pasting treatment of the front surface of the wafer in an embodiment of the present invention.

[0034] Figure 11 It is a schematic structural diagram of loading the wafer into the ion implantation machine in an embodiment of the present invention.

[0035] Figure 12 It is a schematic structural diagram of the IGBT wafer manufactured by using the manufacturing method of the IGBT wafer provided by the present invention in an embodiment of the present invention.

[0036] In the figure, 10 - fixed point structure; 20 - scratch; 30 - central imprint; 100 - film pasting; 110 - step; 120 - channel; 200 - wafer; 210 - back surface; 220 - front surface; 300 - carrier table. Detailed implementation manners

[0037] To make the objectives, advantages and features of the present invention clearer, the manufacturing method of the IGBT wafer and the IGBT wafer proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions and shapes, will be partially determined by the specific application and usage environment. Also, in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to represent the same part or parts having the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in the subsequent drawings.

[0038] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0039] In the description of this specification, descriptions with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0040] The core idea of the present invention is to provide a method for preparing an IGBT wafer, which can avoid defects such as scratches and residual central imprints on the front side of the wafer, so as to protect the front side of the wafer and improve the qualification rate of the wafer.

[0041] To achieve the above idea, the present invention provides a method for preparing an IGBT wafer, referring to Figures 5 to 12 a specific implementation manner of a method for preparing an IGBT wafer disclosed. The method for preparing an IGBT wafer includes the following steps S1 to step S5.

[0042] Step S1: Provide a wafer 200 and perform a first film pasting on the front side 220 of the wafer 200.

[0043] Specifically, referring to Figure 5 、 Figure 6 and Figure 9As shown, a wafer 200 is provided, and the front process of the IGBT on the wafer 200 has been completed. Then, the front side 220 of the wafer is subjected to the first film pasting by a film pasting device to protect the front side 220 of the wafer. The film pasting device includes a roller. During the first film pasting process, the pressure setting range of the roller is 0.295 Mpa to 0.305 Mpa. That is, during the first film pasting, the pressure of the roller can be 0.295 Mpa, 0.300 Mpa, 0.305 Mpa, or any value within the range of 0.295 Mpa to 0.305 Mpa. The film 100 can be a blue film, a UV film, etc., and no specific limitation is made here, as long as it can adhere to the front side 220 of the wafer 200 and play a role in protecting the front side 220 of the wafer. By performing the first film pasting on the front side 220 of the wafer 200, a structure as shown in Figure 6 is formed. As can be seen from Figure 6 and Figure 9 , the wafer 200 has a front side 220 and a back side 210. In this step, only the front side 220 of the wafer 200 is film pasted.

[0044] Step S2: After the wafer 200 after the first film pasting is successively subjected to film planarization treatment and thinning treatment of the back side 210 of the wafer 200, the first film pasting is subjected to the first film peeling treatment.

[0045] Specifically, as shown in Figures 5 to 9 , after the first film pasting, the back side 210 of the wafer 200 is loaded onto the machine for thinning treatment. As can be seen from Figure 6 , the surface of the film 100 in contact with the machine is uneven. In order to keep the back side 210 of the wafer 200 flat after the thinning treatment, before the back side 210 of the wafer 200 is thinned, the film 100 needs to be planarized. For example, the first film pasting can be planarized by chemical mechanical polishing to form a structure as shown in Figure 7 . After the planarization treatment, the flatness of the surface of the film 100 in contact with the machine meets the design requirements. In this embodiment, preferably, the Taiko process is used to thin the back side 210 of the wafer to form a structure as shown in Figure 8 .

[0046] Then, the first film 100 is peeled off by a film peeling device. The peeling speed of the first film pasting is 0.5 mm / s to 2.5 mm / s. That is, the peeling speed of the first film pasting can be 0.5 mm / s, 1.0 mm / s, 1.5 mm / s, 2.0 mm / s, 2.5 mm / s, or any value within the range of 0.5 mm / s to 2.5 mm / s. After the film peeling treatment, a structure as shown in Figure 9 is formed.

[0047] Step S3: Perform a second film pasting on the front side 220 of the wafer 200 after the first film peeling process.

[0048] Specifically, referring Figure 5 to Figure 10 as shown, after the first film peeling process, the front side 220 of the wafer is subjected to a second film pasting through a film pasting device to form a structure as Figure 10 shown. During the second film pasting process, the pressure setting range of the roller is 0.295 Mpa to 0.305 Mpa. That is, the pressure setting range of the roller is 0.295 Mpa to 0.305 Mpa. That is, during the second film pasting, the pressure of the roller can be 0.295 Mpa, 0.300 Mpa, 0.305 Mpa, or any value within the range of 0.295 Mpa to 0.305 Mpa. It should be noted that during the first film pasting and the second film pasting, the pressure of the roller can be equal or not equal, and no specific requirements are made here. Similarly, the film 100 can be a blue film, a UV film, etc., and no specific restrictions are made here, as long as it can adhere to the front side 220 of the wafer and play a role in protecting the front side 220 of the wafer 200.

[0049] Step S4: Perform ion implantation and thermal annealing processes on the back side 210 of the wafer 200 after the second film pasting.

[0050] Specifically, referring Figure 5 to Figure 11 as shown, the wafer 200 after the second film pasting process is placed in an ion implantation machine tool to perform an ion implantation process to form an N-type buffer region and a collector on the back side 210 of the wafer. The ion implantation of the back side 210 of the wafer includes boron ion implantation or phosphorus ion implantation. The depth of phosphorus ion implantation is 0.6 μm to 0.8 μm, or 1.6 μm - 1.8 μm. That is, the depth of phosphorus ion implantation can be 0.6 μm, 0.7 μm, 0.8 μm, 1.6 μm, 1.7 μm, 1.8 μm, or any value within the range of 0.6 μm to 0.8 μm, or alternatively within the range of 1.6 μm - 1.8 μm. The depth of boron ion implantation is 0.1 μm to 0.25 μm. That is, the depth of boron ion implantation can be 0.1 μm, 0.2 μm, 0.25 μm, or any value within the range of 0.1 μm to 0.25 μm.

[0051] Next, a thermal annealing treatment is performed on the back surface 210 of the wafer 200, so that the doping ion implantation damage within this depth is ideally repaired, and the implanted ions are fully activated, in order to form a back surface 210 collector junction with high injection efficiency. The thermal annealing is performed by laser thermal annealing. The wavelength range of the laser is 500 nm to 570 nm, that is, the wavelength of the laser can be 500 nm, 520 nm, 525 nm, 550 nm, 570 nm, or any value within the range of 500 nm to 570 nm. In this embodiment, preferably, the wavelength of the laser is 525 nm. The surface transient temperature of the laser annealing is 1400 °C to 1600 °C. That is, the surface transient temperature of the laser annealing can be 1400 °C, 1500 °C, 1600 °C, or any value within the range of 1400 °C to 1600 °C.

[0052] The wafer 200 after the second film pasting is placed in an annealing machine for laser thermal annealing treatment. The annealing machine includes a carrier table 300. One surface of the film 100 in contact with the carrier table 300 has a step 110. A channel 120 for the airflow to pass through is formed between the step 110 and the carrier table 300, enabling the gas to flow rapidly between the wafer 200 and the carrier table 300, constituting an airflow circuit, and further enhancing the heat dissipation capacity.

[0053] Step S5: Perform a second film peeling treatment on the wafer 200 after the thermal annealing treatment.

[0054] Specifically, refer Figure 5 as shown. The wafer after the thermal annealing treatment is subjected to a second film peeling treatment for subsequent processes of the wafer. The peeling speed of the second film pasting is 0.5 mm / s to 2.5 mm / s. That is, the peeling speed of the second film pasting can be 0.5 mm / s, 1.0 mm / s, 1.5 mm / s, 2.0 mm / s, 2.5 mm / s, or any value within the range of 0.5 mm / s to 2.5 mm / s. It should be noted that when performing the second film peeling, the peeling speed of the film can be equal to or different from that of the first film peeling, and no specific requirements are made here.

[0055] Refer Figure 12 as shown, Figure 12 is an IGBT wafer manufactured by using the method for manufacturing an IGBT wafer provided in this embodiment. From Figure 12It can be seen from the center of the chip at position a that there are no defects such as a central imprint 30 or a scratch 20. In the method for manufacturing an IGBT wafer provided in this embodiment, after thinning and film peeling treatments are performed on the back surface 210 of the wafer 200, a second film is attached to the back surface 210 of the wafer 200. When ion implantation and thermal annealing treatments are performed on the back surface 210 of the wafer 200, defects such as scratches 20 and residual central imprints 30 can be avoided on the front surface 220 of the wafer 200. This plays a role in protecting the front surface 220 of the wafer 200, improves the overall appearance of the IGBT wafer, and increases the qualified rate of the wafer 200.

[0056] To implement the above idea, this embodiment also discloses an IGBT wafer, including: manufactured by using the method for manufacturing an IGBT wafer described above.

[0057] The IGBT wafer provided in this embodiment and the method for manufacturing an IGBT wafer provided in this embodiment belong to the same inventive concept. Therefore, the front surface 220 of the IGBT wafer provided in this embodiment is protected by the second film attachment, and no defects such as scratches 20 and residual central imprints 30 are generated, improving the overall appearance of the IGBT wafer and having a high qualified rate.

[0058] In summary, the above embodiments have described in detail the method for manufacturing an IGBT wafer and different configurations of the IGBT wafer. Of course, the above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the content of the above embodiments. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the claims.

Claims

1. A method for preparing an IGBT wafer, characterized in that, Including: Provide a wafer and perform the first film pasting on the front side of the wafer; After the first film pasting, the wafer is successively subjected to film planarization treatment and back thinning treatment of the wafer, and then the first film pasting is subjected to the first film peeling treatment; Perform the second film pasting on the front side of the wafer after the first film peeling treatment; Successively perform ion implantation and thermal annealing treatment on the back side of the wafer after the second film pasting; Perform the second film peeling treatment on the wafer after the thermal annealing treatment; Place the wafer after the second film pasting on an annealing machine for laser thermal annealing treatment. The annealing machine includes a carrier table, and the surface of the film pasting in contact with the carrier table has steps, and a channel for air flow is formed between the steps and the carrier table.

2. The manufacturing method of the IGBT wafer according to claim 1, wherein, The back side of the wafer is thinned by Taiko process.

3. The manufacturing method of the IGBT wafer according to claim 1, wherein, The first film pasting is planarized by chemical mechanical polishing.

4. The method for preparing an IGBT wafer according to claim 1, characterized in that, During the first film pasting process, the pressure setting range of the roller is 0.295 Mpa to 0.305 Mpa, and the peeling speed of the first film pasting is 0.5 mm / s to 2.5 mm / s.

5. The manufacturing method of the IGBT wafer according to claim 1, characterized in that, During the second film pasting process, the pressure setting range of the roller is 0.295 Mpa to 0.305 Mpa, and the peeling speed of the second film pasting is 0.5 mm / s to 2.5 mm / s.

6. The manufacturing method of the IGBT wafer according to claim 1, characterized in that, Ion implantation on the back side of the wafer includes boron ion implantation, and the depth of boron ion implantation is 0.1 μm to 0.25 μm.

7. The manufacturing method of the IGBT wafer according to claim 6, characterized in that, Ion implantation on the back side of the wafer includes phosphorus ion implantation, and the depth of phosphorus ion implantation is 0.6 μm to 0.8 μm, or 1.6 μm - 1.8 μm.

8. The method for preparing an IGBT wafer according to claim 1, wherein, The thermal annealing treatment is laser thermal annealing treatment, the wavelength of the laser is 500 nm to 600 nm, and the surface transient laser annealing temperature is 1400 °C to 1600 °C.

9. An IGBT wafer, characterized in that, Including: Manufactured by using the method for manufacturing an IGBT wafer according to any one of claims 1 - 8.

Images