A flip chip manufacturing method and flip chip

Abstract

The application discloses a flip chip preparation method and a flip chip, and belongs to the flip chip technical field. The flip chip preparation method provided by the application forms a first interconnection element on a first substrate, forms a first sub-interconnection element on a first surface of an intermediate substrate and forms a second sub-interconnection element and an action surface limiting element on a second surface of the intermediate substrate, and the height of the second sub-interconnection element is not higher than that of the action surface limiting element; a second interconnection element is formed on a second substrate; and when the first surface of the intermediate substrate is welded and interconnected with the first substrate, since the height of the second sub-interconnection element is not higher than that of the action surface limiting element, the action surface limiting element can bear the pressure applied in the flip welding process, which helps to avoid the circuit structure on the second surface from being damaged or destroyed due to the pressure.

Description

Technical Field

[0001] The present application belongs to the field of flip chip technology, especially the field of superconducting quantum chip technology. In particular, the present application relates to a method for preparing a flip chip and a flip chip. Background Art

[0002] Flip chip welding technology is a microelectronic circuit interconnection technology that interconnects the circuit structure located on the lower surface of a substrate with the circuit structure located on the upper surface of another substrate using solder to form a stable and reliable mechanical and electrical connection. The main process method for flip chip welding is hot pressing welding.

[0003] The qubits (qubits) on quantum chips are the fundamental units for performing quantum computing. To achieve large-scale qubit expansion, quantum circuits located on substrates typically need to be stacked and interconnected using flip-chip bonding technology. For flip-chip bonding with three or more substrates, the middle substrate requires two soldering steps to connect to the adjacent substrates. Because circuit structures are formed on both surfaces of the middle substrate, applying pressure during the flip-chip bonding process while avoiding impact on the circuits presents an urgent challenge. Invention content

[0004] The purpose of this application is to provide a method for preparing a flip chip and a flip chip to solve the deficiencies in the prior art.

[0005] One embodiment of the present application provides a method for preparing a flip chip, comprising:

[0006] forming a first interconnection element on a first substrate;

[0007] forming a first sub-interconnection element on the first surface of the intermediate substrate, and forming a second sub-interconnection element and an active surface defining element on the second surface of the intermediate substrate, wherein the height of the second sub-interconnection element does not exceed that of the active surface defining element;

[0008] forming a second interconnection element on the second substrate;

[0009] placing the first interconnection sub-element opposite the first interconnection element and engaging the first interconnection element with the first interconnection sub-element based on applying a force to the first substrate and a surface defined by the active surface defining element;

[0010] The second sub-interconnection element and the second interconnection element are opposed to each other and are joined based on applying a force to the first substrate and the second substrate.

[0011] In some embodiments of the method described above, the step of placing the second interconnection sub-element and the second interconnection element opposite to each other and joining the second interconnection sub-element and the second interconnection element by applying force to the first substrate and the second substrate comprises:

[0012] heating the second interconnection element at a first temperature and heating the second sub-interconnection element at a second temperature, wherein the first temperature is higher than the second temperature and the second temperature is more than 10° C. lower than the melting point of both the first sub-interconnection element and the first interconnection element;

[0013] Applying a force engages the second sub-interconnection element and the second interconnection element.

[0014] In the method described above, in some embodiments, the first temperature is within 10° C. lower than the melting point of the second interconnection element.

[0015] In the above method, in some embodiments, the second temperature is at least 10° C. lower than the melting point of the second interconnection sub-element and the first temperature.

[0016] In some embodiments of the method described above, the second interconnection element, the second sub-interconnection element, the first sub-interconnection element, and the first interconnection element are all indium, and the first temperature is 150°C to 155°C, and the second temperature is 20°C to 30°C.

[0017] In some embodiments of the method described above, at least one of the following parameters of the first interconnection sub-element and the first interconnection element is greater than those of the second interconnection sub-element and the second interconnection element: cross-sectional area, quantity.

[0018] In some embodiments of the method described above, the step of placing the first interconnection sub-element opposite to the first interconnection element and joining the first interconnection element to the first interconnection sub-element by applying a force to the first substrate and the surface defined by the active surface defining element comprises:

[0019] heating the first sub-interconnection element and the first interconnection element at a third temperature;

[0020] A force is applied to engage the first sub-interconnection element and the first interconnection element.

[0021] In some embodiments of the method described above, the first interconnection sub-element and the first interconnection element have the same melting point, and the third temperature is within 10° C. lower than the melting point.

[0022] Another embodiment of the present application provides a flip chip prepared according to the above method, comprising:

[0023] a first substrate formed with a first interconnection element;

[0024] an intermediate substrate, wherein a first sub-interconnection element is formed on a first surface of the intermediate substrate, a second sub-interconnection element and an active surface defining element are formed on a second surface of the intermediate substrate, the height of the second sub-interconnection element does not exceed the active surface defining element, and the first sub-interconnection element is oppositely engaged with the first interconnection element;

[0025] The second substrate is formed with a second interconnection element, and the second interconnection element is oppositely coupled to the second sub-interconnection element.

[0026] Compared with the prior art, the flip chip preparation method provided by the present application is characterized in that the first substrate forms a first interconnection element, the first surface of the intermediate substrate forms a first sub-interconnection element, and the second surface of the intermediate substrate forms a second sub-interconnection element and an active surface defining element, and the height of the second sub-interconnection element does not exceed the active surface defining element. The second substrate forms a second interconnection element. When the first surface of the intermediate substrate is welded and interconnected with the first substrate, since the height of the second sub-interconnection element does not exceed the active surface defining element, the active surface defining element receives the pressure applied during the flip-chip welding process, which helps to prevent the circuit structure on the second surface from being damaged or destroyed by the pressure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic structural diagram of a three-layer substrate to be flip-chip bonded in one embodiment provided in the present application;

[0028] Figure 2 A schematic diagram of the first flip-chip bonding in an embodiment provided in this application;

[0029] Figure 3 A schematic diagram of the second flip-chip bonding in an embodiment provided in this application;

[0030] Figure 4 This is a structural diagram of a flip chip in an embodiment provided in this application.

[0031] Description of reference numerals:

[0032] 1-first substrate, 11-first interconnection element;

[0033] 2 - intermediate substrate, 21 - first sub-interconnection element, 22 - second sub-interconnection element, 23 - active surface defining element;

[0034] 3 - second substrate, 31 - second interconnection element. DETAILED DESCRIPTION

[0035] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0036] To make the purpose, technical solutions, and advantages of the embodiments of the present application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals are used throughout the text to refer to similar components. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it is obvious that in various cases, one or more embodiments can be practiced without these specific details, and the various embodiments can be combined and referenced with each other without contradiction.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] In addition, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be directly on another layer or substrate, and / or intervening layers can also be present. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or one or more intervening layers can also be present. In addition, references to being "on" and "under" various layers can be made based on the accompanying drawings.

[0039] A quantum chip is the processor that performs quantum computations in a quantum computer. The circuit structure that serves as the processing unit of the processor is often referred to as a qubit. A qubit can be understood as a two-level system that follows the laws of quantum mechanics and can exist in any superposition of 0 and 1. Surrounding the qubit are various circuit structures with different functions, such as the drive control signal lines (xy-control lines, also known as xy control lines or pulse control signal lines) for XY rotation of the qubit, the flux control signal lines (z-control lines, also known as z control signal lines or frequency control signal lines) for Z rotation of the qubit, the readout resonant cavity, and the couplers used for coupling between qubits. In a quantum chip, the circuit structures described above are generally referred to as quantum circuits.

[0040] Traditional quantum circuits are all prepared on the same substrate, which results in very limited space on the substrate for forming quantum bits, making it difficult to expand the number of quantum bits on a large scale. In order to achieve large-scale expansion of quantum bits, related technologies classify the quantum circuits located on the substrate and prepare them on different substrates, and then achieve stacking interconnection through flip-chip welding technology. Flip-chip welding technology is a microelectronic circuit interconnection technology that interconnects the circuit structure located on the lower surface of the substrate with the circuit structure located on the upper surface of another substrate with solder to form a stable and reliable mechanical and electrical connection. Compared with traditional wire bonding interconnection technology, flip-chip welding technology has higher density and can increase the number of I / Os per unit area. The preparation of flip-chip bumps is basically based on wafers and chips. Compared with wire bonding interconnection based on a single wire, it has high production efficiency and reduces the cost of batch packaging.

[0041] When using flip-chip welding technology to stack and interconnect three or more substrates to expand the number of quantum bits, it is generally necessary to perform multiple welding operations to sequentially realize the stacking and interconnection between different layers, and the substrate in the middle needs to be welded twice to achieve interconnection with the adjacent substrate. However, circuit structures are formed on both surfaces of the middle substrate. How to apply pressure during the flip-chip welding process while avoiding affecting the circuit, such as causing deformation of the interconnected components or damage to other circuit structures, etc. These influences will further change the chip performance parameters. Therefore, it is urgent for technical personnel in this field to solve this problem.

[0042] For chips stacked by flip-chip welding of three or more substrates, in order to ensure that the circuit on the middle substrate is not affected by the pressure applied during the flip-chip welding process, the present application provides a method for preparing a flip-chip and a flip-chip.

[0043] Figure 1 A schematic structural diagram of a three-layer substrate to be flip-chip bonded in one embodiment provided in the present application;

[0044] Figure 2 A schematic diagram of the first flip-chip bonding in an embodiment provided in this application;

[0045] Figure 3 A schematic diagram of the second flip-chip bonding in an embodiment provided in this application;

[0046] Figure 4 This is a structural diagram of a flip chip in an embodiment provided in this application.

[0047] Combine Figures 1 to 4 As shown, the embodiment of the present application provides a method for preparing a flip chip, comprising the following steps:

[0048] forming the first interconnection element 11 on the first substrate 1; forming the first sub-interconnection element 21 on the first surface of the intermediate substrate 2, and forming the second sub-interconnection element 22 and the action surface defining element 23 on the second surface of the intermediate substrate 2, and the height of the second sub-interconnection element 22 does not exceed that of the action surface defining element 23; forming the second interconnection element 31 on the second substrate 3; it should be noted that the substrates can be made of dielectric materials such as silicon or sapphire, and the interconnection elements can be directly formed on the surface of the substrate or the surface of the circuit structure on the substrate, and the first interconnection element 11 and the second interconnection element 31 can be connected by the first sub-interconnection element 21 and the second sub-interconnection element 22. Figure 1 As shown in the figure, the first interconnection element 11 is located on the top surface of the first substrate 11, the first sub-interconnection element 21 is located on the bottom surface of the intermediate substrate 2, the second sub-interconnection element 22 and the action surface defining element 23 are located on the top surface of the intermediate substrate 2, and the second interconnection element 31 is located on the bottom surface of the second substrate 3. It can be understood that the bottom and top here are relative to the drawings of the embodiments provided in the present application, the height of the second sub-interconnection element 22 does not exceed that of the action surface defining element 23, and the height of the action surface defining element 23 does not affect the joint of the second sub-interconnection element 22 and the second interconnection element 31, so that an action surface of the action surface defining element 23 can be defined, which is higher than the second sub-interconnection element 22; and,

[0049] First, the first sub-interconnection element 21 and the first interconnection element 11 are one-to-one opposed, and the first interconnection element 11 and the first sub-interconnection element 21 are jointed based on the force applied to the first substrate 1 and the surface defined by the action surface defining element 23; then, the second sub-interconnection element 22 and the second interconnection element 31 are one-to-one opposed, and the second sub-interconnection element 22 and the second interconnection element 31 are jointed based on the force applied to the first substrate 1 and the second substrate 3.

[0050] A flip chip is a device that uses flip-chip soldering technology to achieve stacked interconnection. It includes at least three layers of stacked interconnected substrates. The circuit structures on the two adjacent layers of substrates are interconnected by bonding interconnection elements. Therefore, the substrate in the middle position and the substrates above and below it all need to use interconnection elements to achieve circuit structure interconnection. The flip chip preparation method provided by this application is that the first substrate 1 forms a first interconnection element 11, the first surface of the intermediate substrate 2 (as shown in the figure, the bottom surface of the intermediate substrate 2) forms a first sub-interconnection element 21, and the second surface of the intermediate substrate 2 (as shown in the figure, the top surface of the intermediate substrate 2) forms a second sub-interconnection element 22 and an active surface defining element 23, and the height of the second sub-interconnection element 22 does not exceed the active surface defining element 23. The second substrate 3 forms a second interconnection element 31. When the first surface of the intermediate substrate 2 is soldered to the first substrate 1, since the height of the second sub-interconnection element 22 does not exceed the active surface defining element 23, the active surface defining element 23 receives the pressure applied during the flip-chip soldering process, which helps to prevent the circuit structure on the second surface from being damaged or destroyed by the pressure.

[0051] It should be noted that in the embodiments of the present application, to protect the second sub-interconnect element 22 from the pressure applied during the flip-chip bonding process, the height of the second sub-interconnect element 22 can be set lower than the height of the active surface defining element 23. Therefore, the active surface defining element 23 can be any type of raised structure. For example, the active surface defining element 23 can be a hole-shaped structure, with the second sub-interconnect element 22 formed in the hole, and the hole wall height being higher than the second sub-interconnect element 22. In a specific implementation, the hole can be formed by deep silicon etching of the silicon substrate, and then the second sub-interconnect element 22 is formed in the hole. The second sub-interconnect element 22 formed in the hole is not squeezed during the flip-chip bonding process, thereby maintaining the integrity of its morphology.

[0052] In some embodiments, the step of placing the second sub-interconnection element 22 and the second interconnection element 31 opposite to each other and bonding the second sub-interconnection element 22 and the second interconnection element 31 based on the force applied to the first substrate 1 and the second substrate 3 includes: heating the second interconnection element 31 at a first temperature and heating the second sub-interconnection element 22 at a second temperature, wherein the first temperature is higher than the second temperature, and the second temperature is lower than the melting point of the first sub-interconnection element 21 and the first interconnection element 11 by more than 10°C, for example, the second temperature is lower than the melting point by 10°C, 11°C, 12°C, 12.5°C, 14°C... and so on; applying force to bond the second sub-interconnection element 22 and the second interconnection element 31.

[0053] See also Figure 3 and compare Figure 2 、 Figure 1 As shown (relative to Figure 2 、 Figure 1 , Figure 3 The end of the second interconnection element 31 is wetted by the heat when heated at the first temperature (hence the distinction in the figure). The heat provided by the first temperature ensures that the second interconnection element 31 is wetted by the heat. This wetting causes a portion of the second interconnection element 31 near the end to melt, thereby imparting adhesion and atomic penetration, thereby enabling the second interconnection element 31 to bond with the second sub-interconnection element 22. Under the action of an external force, the ends of the second interconnection element 31 and the second sub-interconnection element 22 contact and generate friction. Due to the bonding ability described above, the second interconnection element 31 and the second sub-interconnection element 22 are bonded. During this process, the second temperature used is far from the melting point of the first interconnection element 11 and the first sub-interconnection element 21, being at least 10°C lower than the melting point. This ensures that the conducted heat does not cause the first interconnection element 11 and the first sub-interconnection element 21 to soften or deform, and the bonded structure between the first interconnection element 11 and the first sub-interconnection element 21 maintains a certain degree of rigidity. Therefore, the preparation method of this embodiment avoids changes in the morphology of the previously interconnected bonded structure during flip-chip bonding, which could affect the performance parameters of the chip.

[0054] It should be noted that the method for providing the first temperature or the second temperature can be ultrasonic heating, or flat plate heating, hot air heating, laser heating, etc. The specific implementation is not limited to the methods described above, as long as it can achieve heating the second interconnection element 31 at the required first temperature and heating the second sub-interconnection element 22 at the required second temperature.

[0055] A commonly used process for flip chip welding is hot pressing welding. Figure 2 、 Figure 3 As shown, the relative direction is applied by the wafer stage (such as Figure 2 、 Figure 3 The working principle of thermocompression flip-chip bonding is as follows: under certain pressure and temperature, ultrasonic energy is applied to the raised elements on one substrate (i.e., the interconnected elements described above). Within a certain period of time, the raised elements generate a binding force with the raised elements on the other substrate, thereby interconnecting the raised elements on the two substrates. The interface bonding of the raised elements in thermocompression bonding is a friction process. First, there is interface contact and pre-deformation, that is, under a given pressure, the raised elements contact and are flattened and deformed to a certain extent. Then, ultrasonic action is applied to remove the oxide and contamination layer on the surface of the raised elements. Then, the temperature rises sharply, the raised elements deform, and the atoms of the raised elements penetrate each other until they are within a certain range. Therefore, the key process parameters of thermocompression flip-chip bonding are pressure, temperature, ultrasonic power, and welding time.

[0056] The operation method of hot-press flip-chip welding is to place a substrate to be flip-chip welded on a wafer table, pick up another substrate with a protruding component with a pick-up welding head, and place the surface with the protruding component facing down to the other substrate, and adjust the position so that the two substrates are parallel to each other and the welding positions are aligned. During flip-chip welding, the parallelism between the substrates is very important. If they are not parallel, the deformation of the protruding components after welding will be large or small, resulting in high or low tensile strength, and some solder joints may not meet the use requirements. Therefore, parallelism is crucial to welding quality. During the ultrasonic hot pressing process, under the action of temperature and pressure, the protruding components tend to melt. The deformation that occurs in this process is very likely to tilt, which also causes the ultrasonic hot pressing flip-chip welding method to have a particularly serious impact on the consistency of the chip spacing.

[0057] To ensure effective wetting of the second interconnecting element 31 when receiving heat provided by the first temperature, in some embodiments of the present application, the first temperature is lower than the melting point of the second interconnecting element 31 and is within 10°C lower, for example, 10°C, 9°C, 8°C, 8.5°C, 7°C, etc., lower than the melting point. A temperature close to the melting point but not reaching the melting point can enable the second interconnecting element 31 to achieve wetting, tending to melt. It should be noted that wetting means that the portion close to the surface has melted and formed an adhesion layer on the surface of the parent material by capillary force, and the atoms of the melted portion and the parent material are close to each other and reach a distance where the atomic attraction takes effect.

[0058] In some embodiments, when the preparation method described above is implemented, the second temperature is lower than the melting point of the second sub-interconnection element 22 and the first temperature, and is lower by more than 10°C. In specific implementation, it can be 10°C, 11°C, 12°C, 12.5°C, 14°C... and so on, lower than the melting point and the first temperature of the second sub-interconnection element 22, thereby forming a sufficiently large temperature gradient in the direction from the second sub-interconnection element 22 to the first interconnection element 11. The sufficiently large temperature gradient further ensures that the bonding structure formed by the interconnection of the first interconnection element 11 and the first sub-interconnection element 21 does not deform.

[0059] In some embodiments, second interconnection element 31, second sub-interconnection element 22, first sub-interconnection element 21, and first interconnection element 11 are all superconductors. The superconductor can be formed of a superconducting material that exhibits superconducting properties at a temperature equal to or lower than a critical temperature, for example, approximately 10-100 millikelvin (mK) or approximately 4K, such as aluminum, niobium, tantalum, or titanium nitride. The specific implementation is not limited to these materials, and any material that exhibits superconducting properties at a temperature equal to or lower than the critical temperature can be used to form the superconductor. In some embodiments, the second interconnection element 31, the second sub-interconnection element 22, the first sub-interconnection element 21, and the first interconnection element 11 are all made of indium (which has a melting point of 157°C), and the first temperature is 150°C to 155°C (in a specific embodiment, one of 150°C, 151°C, 152°C, 153°C, 154°C, 155°C, etc. can be selected), and the second temperature is 20°C to 30°C (in a specific embodiment, one of 20°C, 21°C, 23°C, 25°C, 28°C, 30°C, etc. can be selected). In a preferred embodiment, the first temperature is 155°C and the second temperature is 20°C. In this case, the second sub-interconnection element 22 and the second interconnection element 31, both made of indium, can be bonded with high quality, and during this process, the bonded structure formed by the first interconnection element 11 and the first sub-interconnection element 21 does not deform.

[0060] In order to prevent the substrate from being tilted relative to each other due to the pressing force in the subsequent flip-chip welding process. In some embodiments, at least one of the following parameters of the first sub-interconnection element 21 and the first interconnection element 11 is greater than that of the second sub-interconnection element 22 and the second interconnection element 31: cross-sectional area, quantity. In one example, specifically, the cross-sectional area of ​​the first sub-interconnection element 21 and the first interconnection element 11 at any point is greater than that of the second sub-interconnection element 22 and the second interconnection element 31, so as to increase the compressive strength of the interconnection element previously joined. It should be noted that the cross section is perpendicular to the joining direction of the first interconnection element 11 and the first sub-interconnection element 21, combined with Figure 1 、 Figure 2 and Figure 3 As shown, the cross section described above is a transverse cross section. In one example, specifically, the number of first sub-interconnection elements 21 and first interconnection elements 11 is greater than the number of second sub-interconnection elements 22 and second interconnection elements 31, so as to increase the overall compressive strength of the previously joined interconnection elements and ensure a stable spacing between the first substrate 1 and the intermediate substrate 2.

[0061] In some embodiments, the step of placing the first interconnection element 21 and the first interconnection element 11 opposite each other and bonding the first interconnection element 11 and the first interconnection element 21 by applying a force to the first substrate 1 and the surface defined by the active surface defining element 23 is a prior flip-chip bonding step, which includes: heating the first interconnection element 21 and the first interconnection element 11 at a third temperature; and applying a force to bond the first interconnection element 21 and the first interconnection element 11. In the specific implementation of this prior flip-chip bonding step, the first interconnection element 21 and the first interconnection element 11 can be made of a material different from that of the second interconnection element 22 and the second interconnection element 31 to facilitate heating at a third temperature, different from the first temperature, during flip-chip bonding. This temperature can be lower than the melting point of the first interconnection element 21 and the first interconnection element 11 by no more than 10°C. In some embodiments, the first interconnection element 21 and the first interconnection element 11 have the same melting point.

[0062] Another embodiment of the present application provides a flip chip prepared according to the method described above, see Figure 4 The flip chip comprises: a first substrate 1, formed with a first interconnection element 11; an intermediate substrate 2, a first surface of which is formed with a first sub-interconnection element 21; a second surface of which is formed with a second sub-interconnection element 22 and an active surface defining element 23, wherein the height of the second sub-interconnection element 22 does not exceed the active surface defining element 23, and the first sub-interconnection element 21 is oppositely bonded to the first interconnection element 11; and a second substrate 3, formed with a second interconnection element 31, which is oppositely bonded to the second sub-interconnection element 22.

[0063] The above flip chip has multiple layers of stacked substrates with high consistency in the spacing between the substrates, stable chip performance parameters, and easy process preparation. It has the same or similar beneficial effects as the above-mentioned preparation method embodiments, so it will not be described in detail. For technical details not disclosed in the flip chip embodiments of this application, those skilled in the art should refer to the description of the above-mentioned preparation method for understanding. To save space, it will not be repeated here.

[0064] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the scope of protection of the present application.

Claims

1. A method for preparing a flip chip, characterized in that: include: forming a first interconnection element on a first substrate; forming a first sub-interconnection element on the first surface of the intermediate substrate, and forming a second sub-interconnection element and an active surface defining element on the second surface of the intermediate substrate, wherein the height of the second sub-interconnection element does not exceed that of the active surface defining element; forming a second interconnection element on the second substrate; placing the first interconnection sub-element opposite the first interconnection element and engaging the first interconnection element with the first interconnection sub-element based on applying a force to the first substrate and a surface defined by the active surface defining element; The second sub-interconnection element and the second interconnection element are opposed to each other and are joined based on applying a force to the first substrate and the second substrate.

2. The method according to claim 1, characterized in that The step of placing the second sub-interconnection element and the second interconnection element opposite to each other and bonding the second sub-interconnection element and the second interconnection element by applying force to the first substrate and the second substrate comprises: heating the second interconnection element at a first temperature and heating the second sub-interconnection element at a second temperature, wherein the first temperature is higher than the second temperature and the second temperature is more than 10° C. lower than the melting point of both the first sub-interconnection element and the first interconnection element; Applying a force engages the second sub-interconnection element and the second interconnection element.

3. The method according to claim 2, characterized in that The first temperature is within 10° C. lower than a melting point of the second interconnect element.

4. The method according to claim 2 or 3, characterized in that The second temperature is at least 10° C. lower than the melting point of the second interconnection sub-element and the first temperature.

5. The method according to claim 2 or 3, characterized in that The second interconnection element, the second sub-interconnection element, the first sub-interconnection element and the first interconnection element are all made of indium, and the first temperature is 150° C. to 155° C., and the second temperature is 20° C. to 30° C.

6. The method according to claim 1, characterized in that At least one of the following parameters of the first sub-interconnection element and the first interconnection element is greater than that of the second sub-interconnection element and the second interconnection element: cross-sectional area, quantity.

7. The method according to claim 1, characterized in that The step of placing the first interconnection sub-element opposite to the first interconnection element and joining the first interconnection element to the first interconnection sub-element based on applying a force to the first substrate and the surface defined by the active surface defining element comprises: heating the first sub-interconnection element and the first interconnection element at a third temperature; A force is applied to engage the first sub-interconnection element and the first interconnection element.

8. The method according to claim 7, characterized in that The first sub-interconnection element and the first interconnection element have the same melting point, and the third temperature is within 10° C. lower than the melting point.

9. A flip chip prepared according to the method according to any one of claims 1 to 8, characterized in that: include: a first substrate formed with a first interconnection element; an intermediate substrate, wherein a first sub-interconnection element is formed on a first surface of the intermediate substrate, a second sub-interconnection element and an active surface defining element are formed on a second surface of the intermediate substrate, the height of the second sub-interconnection element does not exceed the active surface defining element, and the first sub-interconnection element is oppositely engaged with the first interconnection element; The second substrate is formed with a second interconnection element, and the second interconnection element is oppositely coupled to the second sub-interconnection element.

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