Low voltage Micro-LED epitaxial wafer and preparation method thereof, Micro-LED

Abstract

The present invention discloses a low-voltage Micro-LED epitaxial wafer and a preparation method thereof, and Micro-LED, and relates to the field of semiconductor optoelectronic devices. The low-voltage Micro-LED epitaxial wafer comprises a substrate, a buffer layer, an undoped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type GaN layer, and a P-type contact layer in sequence; wherein the P-type contact layer comprises a porous AlInN layer, a two-dimensional P-type BGaN layer, an AlN roughening layer, a P-type BInGaN nanocluster layer, and a P-type AlInGaN roughening layer stacked in sequence on the P-type GaN layer; wherein the porous AlInN layer is formed by H 2 The AlInN layer is etched, and the P-type AlInGaN roughening layer is formed by N 2 The roughened P-type AlInGaN layer is obtained. The implementation of the present invention can reduce the operating voltage, improve the light extraction efficiency, and further improve the luminous efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic devices, and in particular to a low-voltage Micro-LED epitaxial wafer and a preparation method thereof, and a Micro-LED. Background Art

[0002] Micro-LEDs are superior to existing display technologies such as LCD and OLED in all aspects of performance, so they are considered to be the next generation display technology with the most competitive advantages. Based on the chip size, micro-LED displays are usually divided into two major areas: Mini-LEDs with chip sizes between 100μm and 200μm; Micro-LEDs with chip sizes below 100μm. Micro-LEDs have a smaller area and require higher current expansion. Otherwise, when an external current is applied, the chip voltage will easily increase or even burn out due to the current congestion effect, affecting the aging performance and luminous consistency of the Micro-LED. In addition, due to the low bandgap width of the traditional P-type contact layer, it is easier to absorb the light emitted by the Micro-LED, resulting in a lower light extraction efficiency for the Micro-LED. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a low-voltage Micro-LED epitaxial wafer and a preparation method thereof, which can reduce the operating voltage and improve the light extraction efficiency.

[0004] Another technical problem to be solved by the present invention is to provide a Micro-LED.

[0005] In order to solve the above problems, the present invention provides a low-voltage Micro-LED epitaxial wafer, which includes a substrate, a buffer layer, an undoped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type GaN layer and a P-type contact layer stacked on the substrate in sequence;

[0006] The P-type contact layer includes a porous AlInN layer, a two-dimensional P-type BGaN layer, an AlN roughening layer, a P-type BInGaN nanocluster layer and a P-type AlInGaN roughening layer sequentially stacked on the P-type GaN layer;

[0007] Wherein, the porous AlInN layer is formed by H 2 The AlInN layer is etched, and the P-type AlInGaN roughening layer is formed by N 2 The roughened P-type AlInGaN layer is obtained.

[0008] As an improvement of the above technical solution, the thickness of the AlInN layer is ≤10 nm, and the thickness of the two-dimensional P-type BGaN layer is ≥15 nm, so that the two-dimensional P-type BGaN layer can fill the holes in the porous AlInN layer.

[0009] As an improvement of the above technical solution, the thickness of the AlInN layer is 1 nm to 10 nm, and the In component ratio thereof is 0.01 to 0.1; and / or

[0010] The thickness of the two-dimensional P-type BGaN layer is 15nm~40nm, the B component ratio is 0.01~0.1, and the P-type doping concentration is 5×10 18 cm -3 ~5×10 19 cm -3 .

[0011] As an improvement of the above technical solution, the thickness of the AlN roughening layer is 0.5nm~5nm;

[0012] The AlN roughening layer is grown at a temperature of ≤1000° C. and a pressure of ≥400 torr to form a roughening structure.

[0013] As an improvement of the above technical solution, the P-type doping concentration in the P-type BInGaN nanocluster layer is 5×10 19 cm -3 ~5×10 20 cm -3 , the B component accounts for 0.01~0.1, the In component accounts for 0.02~0.12, and the thickness is 2nm~5nm;

[0014] The growth temperature of the P-type BInGaN nanocluster layer is ≤1000° C. and the growth pressure is ≥400 torr to form nanoclusters.

[0015] As an improvement of the above technical solution, the thickness of the P-type AlInGaN layer is 5nm~10nm, the Al component accounts for 0.01~0.1, the In component accounts for 0.01~0.08, and the P-type doping concentration is 5×10 20 cm -3 ~5×10 21 cm -3 ;

[0016] After the growth of the P-type AlInGaN layer is completed, 2 The P-type AlInGaN roughened layer is formed by annealing at 700° C. to 800° C. for 5 min to 10 min in an atmosphere.

[0017] Correspondingly, the present invention also discloses a method for preparing a low-voltage Micro-LED epitaxial wafer, which is used to prepare the above-mentioned low-voltage Micro-LED epitaxial wafer, and comprises:

[0018] Providing a substrate, and sequentially growing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type GaN layer and a P-type contact layer on the substrate;

[0019] The P-type contact layer includes a porous AlInN layer, a two-dimensional P-type BGaN layer, an AlN roughening layer, a P-type BInGaN nanocluster layer and a P-type AlInGaN roughening layer sequentially stacked on the P-type GaN layer;

[0020] Wherein, the porous AlInN layer is formed by H 2 The AlInN layer is etched, and the P-type AlInGaN roughening layer is formed by N 2 The roughened P-type AlInGaN layer is obtained.

[0021] As an improvement of the above technical solution, the growth temperature of the AlInN layer is 800° C. to 900° C., and the growth pressure is 50 torr to 300 torr; and / or

[0022] The growth temperature of the two-dimensional P-type BGaN layer is 900° C. to 1000° C., and the growth pressure is 50 torr to 300 torr; and / or

[0023] The AlN roughening layer has a growth temperature of 800° C. to 950° C. and a growth pressure of 400 torr to 600 torr; and / or

[0024] The growth temperature of the P-type BInGaN nanocluster layer is 900° C. to 1000° C., and the growth pressure is 400 torr to 600 torr; and / or

[0025] The growth temperature of the P-type AlInGaN layer is 900° C. to 1000° C., and the growth pressure is 100 torr to 300 torr.

[0026] As an improvement of the above technical solution, after the AlInN layer is grown, 2 In the atmosphere, the etching process is carried out at 850℃~1050℃ for 10s~50s.

[0027] Correspondingly, the present invention also discloses a Micro-LED, which includes the above-mentioned low-voltage Micro-LED epitaxial wafer.

[0028] The implementation of the present invention has the following beneficial effects:

[0029] In the low-voltage Micro-LED epitaxial wafer in one embodiment of the present invention, the P-type contact layer includes a porous AlInN layer, a two-dimensional P-type BGaN layer, an AlN roughening layer, a P-type BInGaN nanocluster layer and a P-type AlInGaN roughening layer stacked in sequence. The porous structure of the porous AlInN layer can improve the light extraction efficiency; the two-dimensional P-type BGaN layer can improve the current expansion capability and reduce leakage; the AlN roughening layer is mainly used to form a roughening structure on the two-dimensional P-type BGaN layer to improve the light extraction efficiency. The multiple nanoclusters distributed in the P-type BInGaN nanocluster layer can serve as bridge points for current expansion, improve the current expansion capability, reduce current concentration, reduce resistance, and reduce the operating voltage. The P-type AlInGaN roughening layer not only further improves the light extraction efficiency, but also has a relatively low work function, which can form a good ohmic contact with the metal electrode and reduce the operating voltage. In summary, based on the P-type contact layer structure of this embodiment, the current expansion capability can be effectively improved, the operating voltage can be reduced, and the light extraction efficiency and luminous efficiency can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic structural diagram of a low-voltage Micro-LED epitaxial wafer in one embodiment of the present invention;

[0031] Figure 2 It is a flow chart of a method for preparing a low-voltage Micro-LED epitaxial wafer in one embodiment of the present invention.

[0032] Among them, 100 is a substrate, 200 is a buffer layer, 300 is an undoped GaN layer, 400 is an N-type GaN layer, 500 is a multiple quantum well layer, 600 is an electron blocking layer, 700 is a P-type GaN layer, 800 is a P-type contact layer, 810 is a porous AlInN layer, 820 is a two-dimensional P-type BGaN layer, 830 is an AlN roughening layer, 840 is a P-type BInGaN nanocluster layer, and 850 is a P-type AlInGaN roughening layer. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0034] See also Figure 1 The present invention discloses a low-voltage Micro-LED epitaxial wafer, which includes a substrate 100, a buffer layer 200, an undoped GaN layer 300, an N-type GaN layer 400, a multi-quantum well layer 500, an electron blocking layer 600, a P-type GaN layer 700 and a P-type contact layer 800 stacked in sequence on the substrate 100.

[0035] The P-type contact layer includes a porous AlInN layer 810 , a two-dimensional P-type BGaN layer 820 , an AlN roughening layer 830 , a P-type BInGaN nanocluster layer 840 and a P-type AlInGaN roughening layer 850 which are sequentially stacked on the P-type GaN layer 700 .

[0036] The porous AlInN layer 810 is formed by H 2 The AlInN layer is etched and provided with a plurality of holes, which will cause a change in the light transmission medium, thereby improving the light extraction efficiency and the luminous efficiency. Specifically, the thickness of the AlInN layer is 1nm to 15nm, and is exemplarily 2nm, 4nm, 6nm, 8nm, 10nm or 12nm, but is not limited thereto. Preferably, it is 1nm to 10nm.

[0037] The In component ratio in the AlInN layer is 0.01-0.2. If the In component ratio is too small, it is difficult to form a porous structure. If the In component ratio is too large, the crystal quality of the layer is poor and light will be absorbed, thereby reducing the light extraction efficiency. Exemplarily, the In component ratio in the AlInN layer is 0.02, 0.05, 0.08, 0.12, 0.15 or 0.18, but not limited thereto. Preferably, it is 0.01-0.1, and more preferably, it is 0.02-0.08.

[0038] The two-dimensional P-type BGaN layer 820 has a large bandgap and is doped with Mg, which can enhance the current expansion capability, reduce the operating voltage of the Micro-LED, and reduce leakage. Specifically, by controlling the growth pressure and growth temperature, the growth mode can be inclined to two-dimensional growth, and the two-dimensional P-type BGaN layer 820 can be obtained.

[0039] Specifically, the thickness of the two-dimensional P-type BGaN layer 820 is 10 nm to 40 nm, and is exemplarily 12 nm, 18 nm, 24 nm, 30 nm or 36 nm, but is not limited thereto. It is preferably 15 nm to 40 nm, and more preferably 15 nm to 30 nm.

[0040] The B component ratio in the two-dimensional P-type BGaN layer 820 is 0.01-0.12, exemplarily 0.02, 0.05, 0.08 or 0.11, but not limited thereto, preferably 0.01-0.1, and more preferably 0.01-0.05.

[0041] The P-type doping element in the two-dimensional P-type BGaN layer 820 is Mg, but is not limited thereto. The doping concentration of the two-dimensional P-type BGaN layer 820 is 1×10 18 cm -3 ~5×10 19 cm -3. An example is 3×10 18 cm -3 , 6×10 18 cm -3 ,9×10 18 cm -3 , 1×10 19 cm -3 or 3×10 19 cm -3 , but not limited thereto. Preferably 5×10 18 cm -3 ~5×10 19 cm -3 .

[0042] Preferably, in one embodiment, the thickness of the AlInN layer is ≤10nm, and the thickness of the two-dimensional P-type BGaN layer 820 is ≥15nm, so that the two-dimensional P-type BGaN layer 820 fills the holes in the porous AlInN layer 810; based on this structure, firstly, part of the two-dimensional P-type BGaN layer 820 is embedded in the hole, and the two-dimensional P-type BGaN layer 820 in the hole and the AlInN layer around it form an AlInN-P-type BGaN interface, which is conducive to changing the light transmission angle, forming a light extraction structure, and improving the luminous efficiency. Secondly, the two-dimensional P-type BGaN layer 820 is grown to obtain a flat surface, which can reduce the contact angle of the subsequently grown AlN roughening layer 830 on the two-dimensional P-type BGaN layer 820, improve the crystal quality of the AlN roughening layer 830, and further improve the light extraction efficiency.

[0043] Among them, the AlN roughening layer 830 can further improve the light extraction efficiency. Specifically, the preparation method of the AlN roughening layer 830 can be: growing a two-dimensional AlN layer, and forming a roughening structure by a dry etching or wet etching process, but is not limited thereto. Preferably, in one embodiment, the growth temperature of the AlN roughening layer 830 is ≤1000°C, and the growth pressure is ≥400torr to form a roughening structure.

[0044] Specifically, the thickness of the AlN roughening layer 830 is 0.5 nm to 10 nm, and is exemplarily 0.8 nm, 1.5 nm, 4 nm, 6.5 nm, 8 nm or 9.5 nm, but is not limited thereto, preferably 0.5 nm to 5 nm, and more preferably 1 nm to 5 nm.

[0045] Among them, the multiple nanoclusters distributed in the P-type BInGaN nanocluster layer 840 can serve as bridge points for current expansion, improve current expansion capability, reduce current concentration, reduce resistance, and reduce operating voltage. Specifically, the nanoclusters in the P-type BInGaN nanocluster layer 840 can be formed by first growing a two-dimensional P-type BInGaN layer and then by dry etching or wet etching, but is not limited to this. Preferably, in one embodiment, the growth temperature of the P-type BInGaN nanocluster layer 840 is ≤1000°C and the growth pressure is ≥400torr to form nanoclusters.

[0046] Specifically, the B component ratio in the P-type BInGaN nanocluster layer 840 is 0.01-0.12, exemplarily 0.03, 0.06, 0.09 or 0.11, but not limited thereto, preferably 0.01-0.1.

[0047] The In component ratio in the P-type BInGaN nanocluster layer 840 is 0.01-0.15, and is 0.02, 0.05, 0.08, 0.12 or 0.14, but not limited thereto. It is preferably 0.02-0.12, and more preferably 0.05-0.1.

[0048] The P-type doping element in the P-type BInGaN nanocluster layer 840 is Mg, but is not limited thereto. The doping concentration of the P-type BInGaN nanocluster layer 840 is 5×10 19 cm -3 ~1×10 21 cm -3 , exemplarily 6×10 19 cm -3 ,9×10 19 cm -3 , 2×10 20 cm -3 , 5×10 20 cm -3 or 8×10 20 cm -3 , but not limited thereto. Preferably 5×10 19 cm -3 ~5×10 20 cm -3 .

[0049] The thickness of the P-type BInGaN nanocluster layer 840 is 2 nm to 10 nm, exemplarily 3 nm, 5 nm, 8 nm or 9 nm, but not limited thereto, preferably 2 nm to 5 nm.

[0050] The roughened structure of the P-type AlInGaN roughened layer 850 changes the light emission angle, further improving the light extraction efficiency. The work function of the P-type AlInGaN roughened layer 850 is relatively low, and it can form a good ohmic contact with the metal electrode, thereby reducing the operating voltage of the Micro-LED. 2 The roughened P-type AlInGaN layer is obtained. The roughened structure obtained by this structure is evenly distributed, which can improve the light extraction efficiency. In addition, the roughening process can also decompose the part with more defects in the P-type AlInGaN layer, improve the crystal quality of the layer, and improve the ohmic contact with the metal electrode. If the process of forming the roughened structure by etching or controlling the growth conditions is adopted, it is often difficult to simultaneously improve the light extraction efficiency and optimize the ohmic contact. More specifically, in one embodiment, after the growth of the P-type AlInGaN layer is completed, the N 2 The P-type AlInGaN roughened layer 850 is formed by annealing at 700° C. to 800° C. for 5 min to 10 min in an atmosphere.

[0051] Specifically, the thickness of the P-type AlInGaN layer is 5 nm to 15 nm, exemplarily 8 nm, 10 nm, 12 nm or 14 nm, but not limited thereto, preferably 5 nm to 10 nm.

[0052] The Al component ratio in the P-type AlInGaN layer is 0.01-0.12, exemplarily 0.03, 0.05, 0.07 or 0.09, but not limited thereto, preferably 0.01-0.1, and more preferably 0.01-0.06.

[0053] The In component ratio of the P-type AlInGaN layer is 0.01-0.1, exemplarily 0.02, 0.04, 0.06, 0.09, but not limited thereto, preferably 0.01-0.08.

[0054] The P-type doping element in the P-type AlInGaN layer is Mg, but is not limited thereto. The doping concentration of the P-type AlInGaN layer is 3×10 20 cm -3 ~5×10 21 cm -3 ; An exemplary value is 4×10 20 cm -3 , 6×10 20 cm -3 , 8×10 20 cm -3 , 1×10 21 cm -3 or 3×10 21 cm -3, but not limited thereto. Preferably 5×10 20 cm -3 ~5×10 21 cm -3 .

[0055] The substrate 100 is a sapphire substrate or a silicon substrate, but is not limited thereto.

[0056] The buffer layer 200 is an AlN layer or an AlGaN layer, but is not limited thereto. The buffer layer 200 has a thickness of 10 nm to 50 nm.

[0057] The thickness of the non-doped GaN layer 300 is 1 μm-5 μm.

[0058] The doping element of the N-type GaN layer 400 is Si, but not limited thereto. The doping concentration of Si in the N-type GaN layer 400 is 1×10 19 cm -3 ~5×10 19 cm -3 , and its thickness is 1μm~3μm.

[0059] The multi-quantum well layer 500 is a periodic structure with a period number of 3 to 15, and each period includes sequentially stacked InGaN quantum well layers and AlGaN quantum barrier layers. The In component of the InGaN quantum well layer accounts for 0.1 to 0.3, and its thickness is 2 nm to 5 nm. The Al component of the AlGaN quantum barrier layer accounts for 0.01 to 0.1, and its thickness is 5 nm to 15 nm.

[0060] The electron blocking layer 600 is an AlGaN layer or an AlInGaN layer, but is not limited thereto. Preferably, in one embodiment, the electron blocking layer 600 is an AlInGaN layer, wherein the Al component accounts for 0.01-0.05, the In component accounts for 0.01-0.05, and the thickness is 10nm-40nm.

[0061] The thickness of the P-type GaN layer 700 is 50 nm to 100 nm, and the Mg doping concentration is 1×10 19 cm -3 ~5×10 20 cm -3 .

[0062] Accordingly, see Figure 2 The present invention also provides a method for preparing a low-voltage Micro-LED epitaxial wafer, which is used to prepare the above-mentioned low-voltage Micro-LED epitaxial wafer, and specifically comprises the following steps:

[0063] S1: providing a substrate;

[0064] S2: sequentially growing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type GaN layer and a P-type contact layer on the substrate;

[0065] Specifically, in some embodiments of the present invention, step S2 includes:

[0066] S21: growing a buffer layer on the substrate;

[0067] Specifically, in one embodiment of the present invention, an AlN layer is grown by PVD as a buffer layer.

[0068] S22: growing a non-doped GaN layer on the buffer layer;

[0069] Specifically, in one embodiment of the present invention, the non-doped GaN layer is grown by MOCVD, the growth temperature is 1000° C. to 1200° C., and the growth pressure is 100 torr to 500 torr.

[0070] S23: growing an N-type GaN layer on the non-doped GaN layer;

[0071] Specifically, in one embodiment of the present invention, an N-type GaN layer is grown by MOCVD, and the growth temperature is 1100° C. to 1200° C. and the growth pressure is 100 torr to 500 torr.

[0072] S24: growing a multi-quantum well layer on the N-type GaN layer;

[0073] Specifically, in one embodiment, an InGaN quantum well layer and an AlGaN quantum barrier layer are periodically grown on an N-type GaN layer by MOCVD until a multi-quantum well layer is obtained.

[0074] The growth temperature of the InGaN quantum well layer is 760°C to 850°C, and the growth pressure is 50 torr to 300 torr. The growth temperature of the AlGaN quantum barrier layer is 850°C to 950°C, and the growth pressure is 50 torr to 300 torr.

[0075] S25: growing an electron blocking layer on the multi-quantum well layer;

[0076] Specifically, in one embodiment, an AlInGaN layer is grown by MOCVD as an electron blocking layer, and the growth temperature is 900° C. to 1000° C. and the growth pressure is 100 torr to 300 torr.

[0077] S26: growing a P-type GaN layer on the electron blocking layer;

[0078] Specifically, in one embodiment, the P-type GaN layer is grown by MOCVD, the growth temperature is 900° C. to 1050° C., and the growth pressure is 100 torr to 500 torr.

[0079] S27: growing a P-type contact layer on the P-type GaN layer;

[0080] Specifically, in one embodiment, step S27 includes:

[0081] S271: growing an AlInN layer on the P-type GaN layer;

[0082] In one embodiment, the AlInN layer is grown by MOCVD, the growth temperature is 800° C. to 900° C., and the growth pressure is 50 torr to 300 torr.

[0083] The thickness of the AlInN layer is 1 nm to 15 nm, exemplarily 2 nm, 4 nm, 6 nm, 8 nm, 10 nm or 12 nm, but not limited thereto, preferably 1 nm to 10 nm.

[0084] The In component ratio in the AlInN layer is 0.01-0.2, and illustratively, the In component ratio in the AlInN layer is 0.02, 0.05, 0.08, 0.12, 0.15 or 0.18, but not limited thereto, preferably 0.01-0.1, and more preferably 0.02-0.08.

[0085] S272: Using H 2 Etching the AlInN layer to form a porous AlInN layer;

[0086] In one embodiment, after the AlInN layer is grown, the temperature is raised by 50°C to 150°C, that is, at 850°C to 1050°C. 2 After etching in the atmosphere for 10s to 50s, a porous AlInN layer can be obtained.

[0087] S273: growing a two-dimensional P-type BGaN layer on the porous AlInN layer;

[0088] In one embodiment, a two-dimensional P-type BGaN layer is grown by MOCVD, and the growth temperature is 900°C~1000°C and the growth pressure is 50torr~300torr; by adopting a relatively high growth temperature and a low growth pressure, the growth mode can be made two-dimensional growth.

[0089] The thickness of the two-dimensional P-type BGaN layer is 10 nm to 40 nm, exemplarily 12 nm, 18 nm, 24 nm, 30 nm or 36 nm, but not limited thereto, preferably 15 nm to 40 nm, and more preferably 15 nm to 30 nm.

[0090] The B component ratio in the two-dimensional P-type BGaN layer is 0.01-0.12, exemplarily 0.02, 0.05, 0.08 or 0.11, but not limited thereto, preferably 0.01-0.1, and more preferably 0.01-0.05.

[0091] The P-type doping element in the two-dimensional P-type BGaN layer is Mg, but is not limited thereto. The doping concentration of the two-dimensional P-type BGaN layer is 1×10 18 cm -3 ~5×10 19 cm -3 . An example is 3×10 18 cm -3 , 6×10 18 cm -3 ,9×10 18 cm -3 , 1×10 19 cm -3 or 3×10 19 cm -3 , but not limited thereto. Preferably 5×10 18 cm -3 ~5×10 19 cm -3 .

[0092] Preferably, in one embodiment, the thickness of the AlInN layer is ≤10nm, and the thickness of the two-dimensional P-type BGaN layer is ≥15nm, so that the two-dimensional P-type BGaN layer fills the holes in the porous AlInN layer; based on this structure, firstly, part of the two-dimensional P-type BGaN layer is embedded in the hole, and the two-dimensional P-type BGaN layer in the hole and the AlInN layer around it form an AlInN-P-type BGaN interface, which is conducive to changing the light transmission angle, forming a light extraction structure, and improving the luminous efficiency. Secondly, a flat surface is obtained after the two-dimensional P-type BGaN layer grows, which can reduce the contact angle of the subsequently grown AlN roughening layer on the two-dimensional P-type BGaN layer, improve the crystal quality of the AlN roughening layer, and further improve the light extraction efficiency.

[0093] S274: growing an AlN roughening layer on the two-dimensional P-type BGaN layer;

[0094] In one embodiment, the AlN roughened layer is grown by MOCVD, the growth temperature is 800° C. to 950° C., and the growth pressure is 400 torr to 600 torr.

[0095] The thickness of the AlN roughening layer is 0.5 nm to 10 nm, and is exemplarily 0.8 nm, 1.5 nm, 4 nm, 6.5 nm, 8 nm or 9.5 nm, but is not limited thereto, preferably 0.5 nm to 5 nm, and more preferably 1 nm to 5 nm.

[0096] S275: growing a P-type BInGaN nanocluster layer on the AlN roughened layer;

[0097] In one embodiment, a P-type BInGaN nanocluster layer is grown by MOCVD, and its growth temperature is 900°C~1000°C and the growth pressure is 400torr~600torr; by adopting a relatively low growth temperature and a relatively high growth pressure, the growth mode can be made three-dimensional, thereby obtaining a nanocluster structure.

[0098] The B component ratio in the P-type BInGaN nanocluster layer is 0.01-0.12, exemplarily 0.03, 0.06, 0.09 or 0.11, but not limited thereto, preferably 0.01-0.1.

[0099] The In component ratio in the P-type BInGaN nanocluster layer is 0.01-0.15, and is exemplarily 0.02, 0.05, 0.08, 0.12 or 0.14, but is not limited thereto. It is preferably 0.02-0.12, and more preferably 0.05-0.1.

[0100] The P-type doping element in the P-type BInGaN nanocluster layer is Mg, but is not limited thereto. The doping concentration of the P-type BInGaN nanocluster layer 840 is 5×10 19 cm -3 ~1×10 21 cm -3 , exemplarily 6×10 19 cm -3 ,9×10 19 cm -3 , 2×10 20 cm -3 , 5×10 20 cm -3 or 8×10 20 cm -3 , but not limited thereto. Preferably 5×10 19 cm -3 ~5×10 20 cm -3.

[0101] The thickness of the P-type BInGaN nanocluster layer is 2 nm to 10 nm, exemplarily 3 nm, 5 nm, 8 nm or 9 nm, but not limited thereto, preferably 2 nm to 5 nm.

[0102] S276: growing a P-type AlInGaN layer on the P-type BInGaN nanocluster layer;

[0103] In one embodiment, the P-type AlInGaN layer is grown by MOCVD, the growth temperature is 900° C. to 1000° C., and the growth pressure is 100 torr to 300 torr.

[0104] The thickness of the P-type AlInGaN layer is 5 nm to 15 nm, exemplarily 8 nm, 10 nm, 12 nm or 14 nm, but not limited thereto, preferably 5 nm to 10 nm.

[0105] The Al component ratio in the P-type AlInGaN layer is 0.01-0.12, exemplarily 0.03, 0.05, 0.07 or 0.09, but not limited thereto, preferably 0.01-0.1, and more preferably 0.01-0.06.

[0106] The In component ratio of the P-type AlInGaN layer is 0.01-0.1, exemplarily 0.02, 0.04, 0.06, 0.09, but not limited thereto, preferably 0.01-0.08.

[0107] The P-type doping element in the P-type AlInGaN layer is Mg, but is not limited thereto. The doping concentration of the P-type AlInGaN layer is 3×10 20 cm -3 ~5×10 21 cm -3 ; An exemplary value is 4×10 20 cm -3 , 6×10 20 cm -3 , 8×10 20 cm -3 , 1×10 21 cm -3 or 3×10 21 cm -3 , but not limited thereto. Preferably 5×10 20 cm -3 ~5×10 21 cm -3 .

[0108] S277: In N 2Annealing in an atmosphere to transform the P-type AlInGaN layer into a P-type AlInGaN coarsening layer;

[0109] Specifically, in one embodiment, in N 2 The P-type AlInGaN roughening layer is formed by annealing at 700°C to 800°C for 5min to 10min in a vacuum atmosphere.

[0110] The present invention will be further described below with specific embodiments:

[0111] Example 1

[0112] This embodiment provides a low-voltage Micro-LED epitaxial wafer, which includes a substrate, a buffer layer, an undoped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type GaN layer and a P-type contact layer stacked on the substrate in sequence;

[0113] The substrate is a sapphire substrate, the buffer layer is an AlN layer with a thickness of 45 nm, and the thickness of the undoped GaN layer is 3 μm. The Si doping concentration in the N-type GaN layer is 3×10 19 cm -3 , with a thickness of 2μm. The multi-quantum well layer includes alternately stacked InGaN quantum well layers and AlGaN quantum barrier layers, with a period number of 10. Among them, the In component in the InGaN quantum well layer accounts for 0.18, and its thickness is 3nm, and the Al component in the AlGaN quantum barrier layer accounts for 0.05, and its thickness is 10nm. The electron blocking layer is an AlInGaN layer, with an Al component ratio of 0.02, an In component ratio of 0.03, and a thickness of 20nm.

[0114] The P-type contact layer includes a porous AlInN layer, a two-dimensional P-type BGaN layer, an AlN roughening layer, a P-type BInGaN nanocluster layer and a P-type AlInGaN roughening layer stacked on the P-type GaN layer in sequence; the porous AlInN layer is formed by H 2 The AlInN layer is formed by etching. The thickness of the AlInN layer is 15 nm, and the In component accounts for 0.15. The thickness of the two-dimensional P-type BGaN layer is 10 nm, and the B component accounts for 0.05. The Mg doping concentration is 8.5×10 18 cm -3 The thickness of the AlN roughening layer is 2 nm. The Mg doping concentration in the P-type BInGaN nanocluster layer is 3×10 20 cm -3 The B component accounts for 0.03, the In component accounts for 0.08, and the thickness is 4nm. The P-type AlInGaN roughening layer is formed by N 2The thickness of the P-type AlInGaN layer is 8 nm, the Al component accounts for 0.02, the In component accounts for 0.08, and the Mg doping concentration is 1×10 21 cm -3 .

[0115] The method for preparing a low-voltage and high-light-efficiency Micro-LED epitaxial wafer in this embodiment includes the following steps:

[0116] (1) Providing a substrate;

[0117] (2) growing a buffer layer on the substrate;

[0118] Specifically, an AlN layer is grown by PVD to serve as a buffer layer.

[0119] (3) growing a non-doped GaN layer on the buffer layer;

[0120] Specifically, the non-doped GaN layer is grown by MOCVD, with a growth temperature of 1080° C. and a growth pressure of 300 torr.

[0121] (4) growing an N-type GaN layer on the undoped GaN layer;

[0122] Specifically, MOCVD is used to grow the N-type GaN layer, with a growth temperature of 1150° C. and a growth pressure of 300 torr.

[0123] (5) Growing a multi-quantum well layer on the N-type GaN layer;

[0124] Specifically, InGaN quantum well layers and AlGaN quantum barrier layers are alternately grown on the N-type GaN layer by MOCVD until a multi-quantum well layer is obtained. The growth temperature of the InGaN quantum well layer is 780°C and the growth pressure is 200 torr. The growth temperature of the AlGaN quantum barrier layer is 910°C and the growth pressure is 200 torr.

[0125] (6) growing an electron blocking layer on the multi-quantum well layer;

[0126] Specifically, an AlInGaN layer is grown by MOCVD as an electron blocking layer, and the growth temperature is 920° C. and the growth pressure is 300 torr.

[0127] (7) Growing a P-type GaN layer on the electron blocking layer;

[0128] Specifically, the P-type GaN layer is grown by MOCVD, with a growth temperature of 980° C. and a growth pressure of 200 torr.

[0129] (8) Growing an AlInN layer on the P-type GaN layer;

[0130] Specifically, the AlInN layer is grown by MOCVD at a growth temperature of 830° C. and a growth pressure of 100 torr;

[0131] (9) Using H 2 Etching the AlInN layer to form a porous AlInN layer;

[0132] Specifically, the temperature was raised to 930°C under H 2 After etching for 30 seconds in the atmosphere, a porous AlInN layer can be obtained.

[0133] (10) Growing a two-dimensional P-type BGaN layer on the porous AlInN layer;

[0134] Specifically, a two-dimensional P-type BGaN layer is grown by MOCVD at a growth temperature of 990° C. and a growth pressure of 100 torr.

[0135] (11) Growing an AlN roughening layer on a two-dimensional P-type BGaN layer;

[0136] Specifically, the AlN roughened layer is grown by MOCVD at a growth temperature of 820° C. and a growth pressure of 500 torr.

[0137] (12) growing a P-type BInGaN nanocluster layer on the AlN roughened layer;

[0138] Specifically, the P-type BInGaN nanocluster layer is grown by MOCVD at a growth temperature of 920° C. and a growth pressure of 550 torr.

[0139] (13) growing a P-type AlInGaN layer on the P-type BInGaN nanocluster layer;

[0140] Specifically, the P-type AlInGaN layer is grown by MOCVD at a growth temperature of 930° C. and a growth pressure of 150 torr.

[0141] (14) In N 2 Annealing in an atmosphere to transform the P-type AlInGaN layer into a P-type AlInGaN coarsening layer;

[0142] Specifically, in N 2 The P-type AlInGaN roughened layer was formed by annealing at 730°C for 6 minutes in a silicon-free atmosphere.

[0143] Example 2

[0144] This embodiment provides a low-voltage Micro-LED epitaxial wafer, which is different from the embodiment 1 in that:

[0145] The thickness of the AlInN layer is 8nm, and its In component ratio is 0.05. The thickness of the two-dimensional P-type BGaN layer is 30nm.

[0146] The rest are the same as in Example 1.

[0147] Comparative Example 1

[0148] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0149] The P-type contact layer is a P-type InGaN layer with a thickness of 10 nm, an In component ratio of 0.05, and a Mg doping concentration of 5×10 20 cm -3 The growth temperature is 650°C and the growth pressure is 300 torr.

[0150] The rest are the same as in Example 1.

[0151] Comparative Example 2

[0152] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0153] The porous AlInN layer is not included, and the rest is the same as in Example 1.

[0154] Comparative Example 3

[0155] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0156] The two-dimensional P-type BGaN layer is not included, and the rest is the same as in Example 1.

[0157] Comparative Example 4

[0158] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0159] The AlN roughened layer is not included, and the rest is the same as in Example 1.

[0160] Comparative Example 5

[0161] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0162] The P-type BInGaN nanocluster layer is not included, and the rest is the same as in Example 1.

[0163] Comparative Example 6

[0164] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0165] The P-type AlInGaN roughening layer is not included, and the rest is the same as that of the first embodiment.

[0166] Comparative Example 7

[0167] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0168] The growth temperature of the P-type BInGaN nanocluster layer is 1100°C and the growth pressure is 100 torr. It is a two-dimensional planar structure with no nanoclusters on the surface.

[0169] The rest are the same as in Example 1.

[0170] Comparative Example 8

[0171] This comparative example provides a Micro-LED epitaxial wafer, which is different from Example 1 in that:

[0172] The growth temperature of the P-type AlInGaN roughened layer is 1050° C. and the growth pressure is 600 torr. Its surface is relatively rough, but the degree of roughening is less than that of Example 1.

[0173] The rest are the same as in Example 1.

[0174] The micro-LED epitaxial wafers obtained in Examples 1 to 2 and Comparative Examples 1 to 8 were prepared into micro-LEDs with a size of 50 μm×50 μm and a horizontal structure. 2 The brightness was tested at a current density of , and the brightness improvement rate was calculated based on the data of Comparative Example 1. The operating voltage of Micro-LED was tested. The specific results are shown in the following table:

[0175]

[0176] It can be seen from the table that the low-voltage Micro-LED epitaxial wafer in the present invention can effectively improve the luminous efficiency and reduce the operating voltage.

[0177] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A low voltage Micro-LED epitaxial wafer, characterized in that: It includes a substrate, a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type GaN layer and a P-type contact layer stacked in sequence on the substrate; The P-type contact layer includes a porous AlInN layer, a two-dimensional P-type BGaN layer, an AlN roughening layer, a P-type BInGaN nanocluster layer and a P-type AlInGaN roughening layer sequentially stacked on the P-type GaN layer; Wherein, the porous AlInN layer is obtained by etching the AlInN layer with H2, and the P-type AlInGaN roughening layer is obtained by roughening the P-type AlInGaN layer with N2; The thickness of the AlInN layer is ≤10 nm, and the thickness of the two-dimensional P-type BGaN layer is ≥15 nm, so that the two-dimensional P-type BGaN layer can fill the holes in the porous AlInN layer.

2. The low voltage Micro-LED epitaxial wafer according to claim 1, characterized in that: The thickness of the AlInN layer is 1 nm to 10 nm, and the In component ratio is 0.01 to 0.1; and / or The thickness of the two-dimensional P-type BGaN layer is 15nm~40nm, the B component ratio is 0.01~0.1, and the P-type doping concentration is 5×10 18 cm -3 ~5×10 19 cm -3 .

3. The low voltage Micro-LED epitaxial wafer according to claim 1, characterized in that: The thickness of the AlN roughening layer is 0.5 nm to 5 nm; The AlN roughening layer is grown at a temperature of ≤1000° C. and a pressure of ≥400 torr to form a roughening structure.

4. The low voltage Micro-LED epitaxial wafer according to claim 1, wherein: The P-type doping concentration in the P-type BInGaN nanocluster layer is 5×10 19 cm -3 ~5×10 20 cm -3 , the B component accounts for 0.01~0.1, the In component accounts for 0.02~0.12, and the thickness is 2nm~5nm; The growth temperature of the P-type BInGaN nanocluster layer is ≤1000° C. and the growth pressure is ≥400 torr to form nanoclusters.

5. The low voltage Micro-LED epitaxial wafer according to claim 1, wherein: The thickness of the P-type AlInGaN layer is 5nm~10nm, the Al component accounts for 0.01~0.1, the In component accounts for 0.01~0.08, and the P-type doping concentration is 5×10 20 cm -3 ~5×10 21 cm -3 ; After the growth of the P-type AlInGaN layer is completed, annealing is performed in a N2 atmosphere at 700° C. to 800° C. for 5 min to 10 min to form the P-type AlInGaN roughened layer.

6. A method for preparing a low-voltage Micro-LED epitaxial wafer, used for preparing the low-voltage Micro-LED epitaxial wafer as claimed in any one of claims 1 to 5, characterized in that: include: Providing a substrate, and sequentially growing a buffer layer, a non-doped GaN layer, an N-type GaN layer, a multi-quantum well layer, an electron blocking layer, a P-type GaN layer and a P-type contact layer on the substrate; The P-type contact layer includes a porous AlInN layer, a two-dimensional P-type BGaN layer, an AlN roughening layer, a P-type BInGaN nanocluster layer and a P-type AlInGaN roughening layer sequentially stacked on the P-type GaN layer; The porous AlInN layer is obtained by etching the AlInN layer with H2, and the P-type AlInGaN roughening layer is obtained by roughening the P-type AlInGaN layer with N2.

7. The method for preparing a low voltage Micro-LED epitaxial wafer according to claim 6, wherein: The AlInN layer is grown at a temperature of 800° C. to 900° C. and a pressure of 50 torr to 300 torr; and / or The growth temperature of the two-dimensional P-type BGaN layer is 900° C. to 1000° C., and the growth pressure is 50 torr to 300 torr; and / or The AlN roughening layer has a growth temperature of 800° C. to 950° C. and a growth pressure of 400 torr to 600 torr; and / or The growth temperature of the P-type BInGaN nanocluster layer is 900° C. to 1000° C., and the growth pressure is 400 torr to 600 torr; and / or The growth temperature of the P-type AlInGaN layer is 900° C. to 1000° C., and the growth pressure is 100 torr to 300 torr.

8. The method for preparing a low voltage Micro-LED epitaxial wafer according to claim 6, characterized in that: After the AlInN layer is grown, it is etched in a H2 atmosphere at 850°C to 1050°C for 10s to 50s.

9. A Micro-LED, characterized in that: Comprising the low-voltage Micro-LED epitaxial wafer as described in any one of claims 1 to 5.

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