A reconfigurable and priority-controllable port control circuit integrated in MCU

Abstract

The present invention belongs to the technical field of integrated circuit MCU chip design, and particularly relates to a reconfigurable and priority-controllable port control circuit integrated in the MCU. It includes: a port register read-write module REG; a port function mapping control module MAPCTRL; a port enable control module PADCTRL, whose input end is respectively connected to the output end of the drive register pndc, the direction register pnio and the pull-up register pnpu; a port analog channel control module ANACTRL, whose input end is respectively connected to the output end of the AD channel control register adancr, the touch channel control register tkcr and the LCD com port control register comcr. The introduction of the priority control register of the present invention enables MCU solution developers to configure the port output priority according to their own needs, greatly improving the flexibility of MCU use.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit MCU chip design, and in particular relates to a reconfigurable and priority-controllable port control circuit integrated in the MCU. Background Art

[0002] With the rapid development of electronic technology and the increasing market demand in application fields such as home appliance control, motors, and consumer electronics, the market demand for MCU chips has also grown rapidly. In the current increasingly fierce competition, the integration of MCUs is getting higher and higher, which leads to the complexity of MCU port control circuits. For example, the I / O port circuit with patent document publication number CN201465099U only describes that when the port multiplexing circuit does not map any function, it defaults to the GPIO function. Although it improves the efficiency of IO use, it does not explain how to integrate the ports and how to configure the priority when multiple functions are mapped on the same pin. The patent document publication number CN105446929A is a port multiplexing circuit that supports SPI, I2C, I2CL, and UART protocols. This patent only describes that multiple peripheral functions are integrated on 4 ports for selective multiplexing, but does not explain how to select multiplexing when multiple peripheral functions are integrated on the same port.

[0003] In view of the above situation, the main defects of the existing technology are as follows: 1. Its integration efficiency is low for MCUs with higher integration; 2. Its priority for multiplexing of port functions is relatively fixed, so that it is not flexible to use.

[0004] Therefore, under this premise, how to design a port control circuit that is more efficiently integrated and more flexible to use is a problem that needs to be solved urgently. Summary of the invention

[0005] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art. The present invention provides a reconfigurable and priority-controllable port control circuit integrated in an MCU, which improves the integration efficiency of the MCU port peripheral functions under the premise of a highly integrated MCU; when multiple peripheral functions are mapped to the same pin, the output priority of the port function can be configured through a priority control register.

[0006] In order to solve the above technical problems, the present invention provides a reconfigurable and priority-controllable port control circuit integrated in an MCU, comprising:

[0007] The port register read-write module REG, whose output end is respectively connected to the mapping control registers lcmcr0~lcmcr1, the port priority control register priorcr, the drive register pndc, the direction register pnio, the pull-up register pnpu, the AD channel control register adancr, the touch channel control register tkcr and the LCD com port control register comcr; wherein the port priority control register priorcr includes: by default, the SPI output priority is the highest, when the port priority control register priorcr is configured to be 2'b01, the I2C output priority is set to the highest, when the three peripheral SPI, I2C, UART are enabled at the same time, the I2C data is output first; when the port priority control register priorcr is configured to be 2'b1x, the UART output priority is set to the highest, when the three peripheral SPI, I2C, UART are enabled at the same time, the UART data is output first;

[0008] A port function mapping control module MAPCTRL, whose input end is respectively connected to the output ends of the mapping control registers lcmcr0-lcmcr1 and the port priority control register priorcr;

[0009] A port enable control module PADCTRL, whose input end is respectively connected to the output ends of the drive register pndc, the direction register pnio and the pull-up register pnpu;

[0010] The port analog channel control module ANACTRL has its input end connected to the output ends of the AD channel control register adancr, the touch channel control register tkcr and the LCD com port control register comcr respectively.

[0011] Preferably, the port function mapping control module MAPCTRL further includes:

[0012] Output data portno, as the output data of the default port when the port function is not multiplexed, comes from the MCU core and can be read and written by the CPU; when the MCU port is output, the internal bus data will be written to the output data portno; when the MCU port is input, the external port data is input to the MCU and stored in the output data portno;

[0013] Output enable signal pn_outen, used as output enable of the pin function when the port function is multiplexed; and connected to the port enable control module PADCTRL;

[0014] The output data pn_dout is used as the output data of the pin when the port function is multiplexed.

[0015] Preferably, the output end of the port enable control module PADCTRL also includes a connected output enable signal pnoe_enh, an input enable signal pnie_enh, a pull-up enable signal pnpu_enh, an n-transistor drive control signal pndrn and a p-transistor drive control signal pndrp.

[0016] Preferably, the output end of the port analog channel control module ANACTRL also includes a connected control touch channel enable signal tk_ch_enh, an AD channel enable signal ad_ch_enh, an LCD channel enable signal com_ch_enh and a port analog enable control signal pnain_enh; the port analog enable control signal pnain_enh is connected to the port enable control module PADCTRL. When the port analog enable control signal pnain_enh is high, it indicates that the port analog channel control module ANACTRL, as an analog function, will shield all digital functions and make the output enable signal pnoe_enh invalid.

[0017] Preferably, the port function mapping control module MAPCTRL also includes a reconfigurable output model PRIMUX, and the reconfigurable output model PRIMUX is a priority selector with two 4-bit inputs and two single-bit outputs; wherein the input signal is the output enable and data of the peripheral function, and the output signal is the enable and data after priority selection; the input signals are arranged from left to right in columns, and the output priority of the left column is greater than the output priority of the right column; for the output pin, only one peripheral function is valid at the same time; the peripheral functions are SPI, I2C and UART integrated simultaneously in the internal port of the MCU.

[0018] Preferably, the specific circuit of the reconfigurable output model PRIMUX includes: inverters INV1~INV2, AND gates AND1~AND4, NAND gate NAND, OR gate OR and NOR gates NOR1~NOR3; two input ends of the AND gate AND1 are respectively input with data data_s[1] and data data_i[1], and the other input end is connected to the output end of the inverter INV1; the input end of the inverter INV1 inputs data data_s[2] and is connected to one of the input ends of the AND gate AND2; the other input end of the AND gate AND2 inputs data data_i[2]; the output ends of the AND gates AND1 and AND2 are respectively connected to the two input ends of the NOR gate NOR1; the output end of the NOR gate NOR1 is connected to one of the input ends of the OR gate OR; the data data_s[3] is connected to the other input end of the OR gate OR; the output end of the OR gate OR is connected to the NAND gate NA One of the input ends of the AND gate NAND, the other input end of the NAND gate NAND is connected to the output end of the NOR gate NOR2, the two input ends of the NOR gate NOR1 are respectively connected to the output ends of the AND gate AND3 and the AND gate AND4, the two input ends of the AND gate AND3 are respectively input with data data_i[3] and data data_s[3], one of the input ends of the AND gate AND4 is input with data data_i[0], the other input end of the AND gate AND4 is connected to the input end of the inverter INV2 and the output end of the NOR gate NOR3, the three input ends of the NOR gate NOR3 are respectively input with data data_s[3], data_s[2] and data_s[1], the output end of the inverter INV2 is a data output enable port doe, which is used to output a data enable signal data_enh, and the output end of the NAND gate NAND is a data output port do, which is used to output data data_o.

[0019] Preferably, when data data_s[3] is 1, the reconfigurable output model PRIMUX will automatically invalidate data data_s[2] and data data_s[1]; when data data_s[2] is valid, data data_s[1] will be invalidated; when data data_s[3], data data_s[2] and data_s[1] are all invalid, the data output enable port doe output is 0, that is, the port output enable is turned off, and the default is input function.

[0020] Preferably, it also includes a priority control circuit, which uses a selector MUX with register control, and the control end of the selector MUX is the lower two bits of the priority control register priorcr, which controls a total of four decodings 00, 01, 10 and 11; the default value is 00, that is, the default priority of the port output; when the priority control register priorcr is configured to 01, the data selection signal ds[3:0] and the data input signal di[3:0] are shifted, and the data selection signal ds[1] and the data input signal di[1] are moved to the first column on the left, and the low priority is arranged thereafter; when the priority control register priorcr is configured to 10 and 11, the data selection signal ds[2] and the data input signal di[2] are moved to the first column on the left, so as to change the priority of the port output.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] 1. The reconfigurable priority output model of the present invention is characterized in that each port inside the MCU can call it, and when calling, it only needs to be arranged in columns, without the need to specially design a multiplexer, thereby greatly improving the efficiency of port function integration.

[0023] 2. The introduction of the priority control register of the present invention enables MCU solution developers to configure the port output priority according to their own needs, greatly improving the flexibility of MCU use. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is the internal logic block diagram of the MCU port of the present invention.

[0025] Figure 2 It is the overall block diagram of the reconfigurable selection circuit of the present invention.

[0026] Figure 3 It is a specific circuit diagram of the reconfigurable output model PRIMUX of the present invention.

[0027] Figure 4 It is a priority control circuit diagram of the present invention.

[0028] Figure 5 It is the port output waveform diagram of the present invention. DETAILED DESCRIPTION

[0029] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0030] like Figure 1~Figure 5 As shown, an embodiment of the present invention discloses a reconfigurable and priority-controllable port control circuit integrated in an MCU, comprising:

[0031] The port register read-write module REG, whose output end is respectively connected to the mapping control registers lcmcr0~lcmcr1, the port priority control register priorcr, the drive register pndc, the direction register pnio, the pull-up register pnpu, the AD channel control register adancr, the touch channel control register tkcr and the LCD com port control register comcr; wherein the port priority control register priorcr includes: by default, the SPI output priority is the highest, when the port priority control register priorcr is configured to be 2'b01, the I2C output priority is set to the highest, when the three peripheral SPI, I2C, UART are enabled at the same time, the I2C data is output first; when the port priority control register priorcr is configured to be 2'b1x, the UART output priority is set to the highest, when the three peripheral SPI, I2C, UART are enabled at the same time, the UART data is output first;

[0032] A port function mapping control module MAPCTRL, whose input end is respectively connected to the output ends of the mapping control registers lcmcr0-lcmcr1 and the port priority control register priorcr;

[0033] A port enable control module PADCTRL, whose input end is respectively connected to the output ends of the drive register pndc, the direction register pnio and the pull-up register pnpu;

[0034] The port analog channel control module ANACTRL has its input end connected to the output ends of the AD channel control register adancr, the touch channel control register tkcr and the LCD com port control register comcr respectively.

[0035] The port function mapping control module MAPCTRL also includes:

[0036] Output data portno, as the output data of the default port when the port function is not multiplexed, comes from the MCU core and can be read and written by the CPU; when the MCU port is output, the internal bus data will be written to the output data portno; when the MCU port is input, the external port data is input to the MCU and stored in the output data portno;

[0037] Output enable signal pn_outen, used as output enable of the pin function when the port function is multiplexed; and connected to the port enable control module PADCTRL;

[0038] The output data pn_dout is used as the output data of the pin when the port function is multiplexed.

[0039] The output end of the port enable control module PADCTRL also includes a connected output enable signal pnoe_enh, an input enable signal pnie_enh, a pull-up enable signal pnpu_enh, an n-transistor drive control signal pndrn and a p-transistor drive control signal pndrp.

[0040] The output end of the port analog channel control module ANACTRL also includes a connected control touch channel enable signal tk_ch_enh, an AD channel enable signal ad_ch_enh, an LCD channel enable signal com_ch_enh and a port analog enable control signal pnain_enh; the port analog enable control signal pnain_enh is connected to the port enable control module PADCTRL. When the port analog enable control signal pnain_enh is high, it indicates that the port analog channel control module ANACTRL, as an analog function, will shield all digital functions and make the output enable signal pnoe_enh invalid.

[0041] When the MCU integrates more peripheral functions, for example, the MCU integrates SPI, I2C, and UART peripherals at the same time. Its internal port has the above three peripheral functions at the same time. It only needs to adjust the reconfigurable output model PRIMUX inside MAPCTRL. The reconfigurable output model PRIMUX is a priority selector with two 4-bit inputs and two single-bit outputs; the input signal is the output enable and data of the peripheral function, and the output signal is the enable and data after priority selection; the input signals are arranged from left to right in columns, and the output priority of the left column is greater than the output priority of the right column; specifically, Figure 2As shown, the splicing symbol integrates 4 columns of content. The output priority of the first column is the highest, followed by the second column, and then the third column, that is, the left side has the highest output priority. For the reconfigurable output model PRIMUX, it has two inputs and two outputs, the two inputs are 4 bits, and the output is single bit. There are many ports inside the MCU, and each port can be instantiated. The first is the instantiation of enable, and the various enables are connected together through the splicing symbol, such as: {spi_data_enh, i2c_data_enh, uart_data_enh, 1'b0}. Then the data is instantiated, which is also operated through the splicing symbol, such as: {spi_data_o, i2c_data_o, uart_data_o, default}. For the output pin, only one peripheral function is valid at the same time; the peripheral functions are SPI, I2C and UART integrated simultaneously in the internal port of the MCU.

[0042] If the integrator wants to integrate more peripheral functions, he only needs to splice more peripheral functions to the input signal. Figure 2 As shown in the figure, taking one of the MCU ports as an example, it integrates SPI, UART and I2C functions. When none of these three functions are output, the port defaults to input function. When SPI and I2C are output at the same time, SPI data will be output first because the first column has the highest output priority.

[0043] like Figure 3As shown, the specific circuit of the reconfigurable output model PRIMUX includes: inverters INV1~INV2, AND gates AND1~AND4, NAND gate NAND, OR gate OR and NOR gates NOR1~NOR3; two input ends of the AND gate AND1 are respectively input with data data_s[1] and data data_i[1], and the other input end is connected to the output end of the inverter INV1, the input end of the inverter INV1 inputs data data_s[2] and is connected to one of the input ends of the AND gate AND2, and the other input end of the AND gate AND2 inputs data data_i[2], the output ends of the AND gates AND1 and AND2 are respectively connected to the two input ends of the NOR gate NOR1, the output end of the NOR gate NOR1 is connected to one of the input ends of the OR gate OR, data data_s[3] is connected to the other input end of the OR gate OR, and the output end of the OR gate OR is connected to the NAND gate NA One of the input ends of the AND gate NAND, the other input end of the NAND gate NAND is connected to the output end of the NOR gate NOR2, the two input ends of the NOR gate NOR1 are respectively connected to the output ends of the AND gate AND3 and the AND gate AND4, the two input ends of the AND gate AND3 are respectively input with data data_i[3] and data data_s[3], one of the input ends of the AND gate AND4 is input with data data_i[0], the other input end of the AND gate AND4 is connected to the input end of the inverter INV2 and the output end of the NOR gate NOR3, the three input ends of the NOR gate NOR3 are respectively input with data data_s[3], data_s[2] and data_s[1], the output end of the inverter INV2 is a data output enable port doe, which is used to output a data enable signal data_enh, and the output end of the NAND gate NAND is a data output port do, which is used to output data data_o.

[0044] The specific circuit of the reconfigurable output model PRIMUX is as follows Figure 3 As shown, the highest bit has the highest priority, followed by the second highest bit. When data_s[3] is 1, the circuit will automatically invalidate the data of data_s[2] and data_s[1]; when data_s[2] is valid, the data of data_s[1] will be invalidated; when data_s[3], data_s[2] and data_s[1] are all invalid, the doe output is 0, that is, the port output enable is turned off, and the default is input function.

[0045] In order to make the MCU more flexible in use, a port priority control register is added, that is, in actual use, users can flexibly configure the priority of peripheral output. By default, the output priority is: SPI>I2C>UART. When the port priority control register is configured, the user can adjust the I2C priority to the highest or the UART priority to the highest, and the second highest priority can be ignored, because the actual user only cares about which peripheral has the highest priority, so it can reduce additional circuit overhead.

[0046] like Figure 4 As shown, for the priority control circuit, essentially, a selector MUX with register control is added to the reconfigurable priority model. The selector control end is the lower two bits of the priority control register priorcr. The two bits control a total of four decoding conditions, namely 00 / 01 / 10 / 11. The default value is 00, which is the default priority of the port output. When priorcr is configured to 01, the data selection signal ds[3:0] and the data input signal di[3:0] are shifted, and ds[1] and di[1] are moved to the first column on the left, and the low priority is arranged behind them. When priorcr is configured to 10 / 11, ds[2] and di[2] are moved to the first column on the left. In this way, the priority of the port output is changed; wherein the above ds = {spi_data_enh, i2c_data_enh, uart_data_enh, 1'b0}, di = {spi_data_o, i2c_data_o,uart_data_o,default}.

[0047] like Figure 5 As shown, the port priority control register priorcr includes: by default, the SPI output priority is the highest. When the port priority control register priorcr is configured to 2'b01, the I2C output priority is set to the highest. When the three peripheral SPI, I2C, and UART are enabled and valid at the same time, the I2C data is output first; when the port priority control register priorcr is configured to 2'b1x, the UART output priority is set to the highest. When the three peripheral SPI, I2C, and UART are enabled and valid at the same time, the UART data is output first.

[0048] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A reconfigurable and priority-controllable port control circuit integrated in an MCU, characterized in that: include: The port register read-write module REG, whose output end is respectively connected to the mapping control registers lcmcr0~lcmcr1, the port priority control register priorcr, the drive register pndc, the direction register pnio, the pull-up register pnpu, the AD channel control register dancr, the touch channel control register tkcr and the LCD com port control register comcr; The port priority control register priorcr includes: by default, the SPI output priority is the highest. When the port priority control register priorcr is configured as 2'b01, the I2C output priority is set to the highest. When the three peripheral SPI, I2C, and UART are enabled and valid at the same time, the I2C data is output first; when the port priority control register priorcr is configured as 2'b1x, the UART output priority is set to the highest. When the three peripheral SPI, I2C, and UART are enabled and valid at the same time, the UART data is output first; A port function mapping control module MAPCTRL, whose input end is respectively connected to the output ends of the mapping control registers lcmcr0-lcmcr1 and the port priority control register priorcr; A port enable control module PADCTRL, whose input end is respectively connected to the output ends of the drive register pndc, the direction register pnio and the pull-up register pnpu; A port analog channel control module ANACTRL, whose input end is respectively connected to the output ends of the AD channel control register adancr, the touch channel control register tkcr and the LCD com port control register comcr; The port function mapping control module MAPCTRL also includes a reconfigurable output model PRIMUX, which is a priority selector with two 4-bit inputs and two single-bit outputs; the input signal is the output enable and data of the peripheral function, and the output signal is the enable and data after priority selection; the input signals are arranged from left to right in columns, and the output priority of the left column is greater than the output priority of the right column; for the output pin, only one peripheral function is valid at the same time; the peripheral function is SPI, I2C and UART integrated simultaneously in the internal port of the MCU; The specific circuit of the reconfigurable output model PRIMUX includes: inverters INV1~INV2, AND gates AND1~AND4, NAND gate NAND, OR gate OR and NOR gates NOR1~NOR3; two input ends of the AND gate AND1 are respectively input with data data_s[1] and data data_i[1], and the other input end is connected to the output end of the inverter INV1; the input end of the inverter INV1 inputs data data_s[2] and is connected to one of the input ends of the AND gate AND2; the other input end of the AND gate AND2 inputs data data_i[2]; the output ends of the AND gates AND1 and AND2 are respectively connected to the two input ends of the NOR gate NOR1; the output end of the NOR gate NOR1 is connected to one of the input ends of the OR gate OR; the data data_s[3] is connected to the other input end of the OR gate OR; the output end of the OR gate OR is connected to the NAND gate NAND One of the input ends of the NAND gate NAND, the other input end of the NAND gate NAND is connected to the output end of the NOR gate NOR2, the two input ends of the NOR gate NOR1 are respectively connected to the output ends of the AND gate AND3 and the AND gate AND4, the two input ends of the AND gate AND3 are respectively input with data data_i[3] and data data_s[3], one of the input ends of the AND gate AND4 is input with data data_i[0], the other input end of the AND gate AND4 is connected to the input end of the inverter INV2 and the output end of the NOR gate NOR3, the three input ends of the NOR gate NOR3 are respectively input with data data_s[3], data_s[2] and data_s[1], the output end of the inverter INV2 is a data output enable port doe, which is used to output a data enable signal data_enh, and the output end of the NAND gate NAND is a data output port do, which is used to output data data_o.

2. A reconfigurable and priority-controllable port control circuit integrated in an MCU as claimed in claim 1, characterized in that: The port function mapping control module MAPCTRL also includes: Output data portno, as the output data of the default port when the port function is not multiplexed, comes from the MCU core and can be read and written by the CPU; when the MCU port is output, the internal bus data will be written to the output data portno; when the MCU port is input, the external port data is input to the MCU and stored in the output data portno; Output enable signal pn_outen, used as output enable of the pin function when the port function is multiplexed; and connected to the port enable control module PADCTRL; The output data pn_dout is used as the output data of the pin when the port function is multiplexed.

3. A reconfigurable and priority-controllable port control circuit integrated in an MCU as claimed in claim 1, characterized in that: The output end of the port enable control module PADCTRL also includes a connected output enable signal pnoe_enh, an input enable signal pnie_enh, a pull-up enable signal pnpu_enh, an n-transistor drive control signal pndrn and a p-transistor drive control signal pndrp.

4. A reconfigurable and priority-controllable port control circuit integrated in an MCU as claimed in claim 1, characterized in that: The output end of the port analog channel control module ANACTRL also includes a connected control touch channel enable signal tk_ch_enh, an AD channel enable signal ad_ch_enh, an LCD channel enable signal com_ch_enh and a port analog enable control signal pnain_enh; the port analog enable control signal pnain_enh is connected to the port enable control module PADCTRL. When the port analog enable control signal pnain_enh is high, it indicates that the port analog channel control module ANACTRL, as an analog function, will shield all digital functions and make the output enable signal pnoe_enh invalid.

5. A reconfigurable and priority-controllable port control circuit integrated in an MCU as claimed in claim 1, characterized in that: When data data_s[3] is 1, the reconfigurable output model PRIMUX will automatically invalidate data data_s[2] and data data_s[1]; when data data_s[2] is valid, data data_s[1] will be invalidated; when data data_s[3], data data_s[2] and data_s[1] are all invalid, the data output enable port doe output is 0, that is, the port output enable is turned off, and the default is input function.

6. A reconfigurable and priority-controllable port control circuit integrated in an MCU as claimed in claim 1, characterized in that: It also includes a priority control circuit, which uses a selector MUX with register control. The control end of the selector MUX is the lower two bits of the priority control register priorcr. The lower two bits of the priority control register priorcr control a total of four decodings 00, 01, 10 and 11; the default value is 00, that is, the default priority of the port output; when the priority control register priorcr is configured to 01, the data selection signal ds[3:0] and the data input signal di[3:0] are shifted, and the data selection signal ds[1] and the data input signal di[1] are moved to the first column on the left, and the low priority is arranged behind them; when the priority control register priorcr is configured to 10 and 11, the data selection signal ds[2] and the data input signal di[2] are moved to the first column on the left, so as to change the priority of the port output.

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