Fault identification method and device before through silicon via bonding of three-dimensional integrated circuit

Abstract

The present invention provides a method and device for fault identification before through silicon via binding of a three-dimensional integrated circuit. The method includes testing a plurality of through silicon vias through a detection circuit, obtaining the parasitic resistance value of each through silicon via respectively, judging whether the through silicon via has a void fault or an open circuit fault according to the parasitic resistance value; dividing the through silicon via into a plurality of grid points, subjecting the plurality of grid points of the through silicon via to cutting magnetic field movement, calculating the potential difference generated by each grid point when the through silicon via moves in the cutting magnetic field according to the magnetic field strength, effective length and movement speed of the through silicon via when the cutting magnetic field moves, and determining whether each grid point has an abnormality according to the potential difference of each grid point; recording the position of the grid point with abnormality, and determining whether the through silicon via has a pinhole fault according to the distribution of the grid points with abnormality, thereby identifying the fault type of the through hole. The device can implement the above method. The present invention can realize fault identification before through silicon via binding of a three-dimensional integrated circuit at low cost and high precision.

Description

Technical Field

[0001] The present invention relates to the technical field of through silicon via failure analysis of a system-level chip, and in particular to a method for identifying failures of through silicon vias of a three-dimensional integrated circuit before binding, and a device for implementing the method. Background Art

[0002] With the development of integrated circuit technology, three-dimensional integrated circuits are widely used in large-capacity storage and high-speed signal processors due to their advantages of high density, high speed, multi-function and low power consumption. Three-dimensional integrated circuits (3D ICs) based on through-silicon vias (TSVs) vertically interconnect multi-layer chips through the through-silicon via structure. With its higher integration, smaller size, lower latency and lower power consumption, it has become the development trend of the next generation of integrated circuits.

[0003] In three-dimensional integrated core or chiplet technology, the interconnection of chips is mainly achieved through silicon vias, so design for testability (DFT) for silicon vias is an important consideration to improve the reliability and testability of the system. However, the main reasons that affect the yield of a single silicon via include deep silicon etching, hole isolation, seed layer deposition, electroplating filling, planarization, wafer thinning and other previous processes. Among them, the common types of failures of silicon vias mainly include void failures, pinhole failures and short circuits to the substrate.

[0004] Since the bonded TSV combination and its quality need to be determined before TSV bonding, this is the key to improving the yield of the entire TSV manufacturing and reducing costs. If the failure and yield problems of a TSV in a bond are found before bonding, the bonding cost can be saved and the loss caused by the failure of a TSV bonding combination can be avoided. However, before bonding, since the TSV is still a blind hole, there are great limitations in testing the TSV.

[0005] As shown in FIG. 1(a), before the TSV is bound, the TSV is usually tested by on-chip testing. For example, a TSV 15 is formed in a non-conductive substrate 14, the TSV 15 is filled with metal, an insulating layer 16 is formed on the periphery of the TSV 15, and a filled metal object 13 is provided above the TSV 15. When on-chip testing is used, a testability design structure embedded in the wafer is used to detect faults in the TSV. However, the TSV 15 before binding is in a blind hole state, and the test stimulus and test response can only be input and captured from the active layer end of the TSV 15. The test difficulty is relatively large, and the interconnection test method in the planar integrated circuit cannot be used.

[0006] If the wafer substrate has been thinned, the buried end of the TSV will be exposed. In this case, a special probe can be used to test the TSV. Although this method can solve the problem of limited test resources and test access in on-chip test methods, it still faces the high cost of special probe manufacturing and the inevitable TSV probing damage.

[0007] Another existing method for detecting silicon vias is to use scanning transmission electron microscope X-ray fluoroscopy to detect silicon via faults. The advantage of this method is high flexibility and no need for on-chip resource support. The disadvantage is low detection accuracy and is only suitable for preliminary screening of large-sized silicon via faults.

[0008] Therefore, most of the current testing methods for TSVs are performed after the TSVs are bound. Although there are more abundant fault detection resources and means after binding, and the test is more accurate and covers more comprehensive types, once a fault in the TSV is detected after the TSVs are bound, for chips with multiple chips interconnected, this fault is irreversible, and the chip production cost is doubled. In addition, because the TSV detection process after binding needs to increase the location of which process has a problem, it brings difficulties to fault analysis and improving manufacturing process efficiency.

[0009] Common faults of the existing through silicon vias 15 include pinholes in the through silicon vias 15, such as Figure 1 (b) shows the pinhole situation. The pinhole 21 is usually formed on the insulating layer 16 and penetrates the insulating layer. Another common situation is that a micro hole 22 is formed in the silicon through hole 15. Figure 1 As shown in (c), the micropore 22 is not formed on the insulating layer 16, but is formed in the silicon through-hole 15. Figure 1 As shown in (d), a truncation 23 is formed in the TSV 15 , and no metal is filled in the truncation 23 , which will cause the TSV 15 to be disconnected.

[0010] It can be seen that the current fault detection method for through silicon vias has problems such as high testing cost and low testing efficiency. Summary of the invention

[0011] The first object of the present invention is to provide a method for fault identification before through silicon via binding of a three-dimensional integrated circuit with high detection efficiency and low cost.

[0012] A second object of the present invention is to provide a three-dimensional integrated circuit through silicon via (TSV) fault identification device before bonding, which implements the above-mentioned three-dimensional integrated circuit through silicon via (TSV) fault identification method before bonding.

[0013] To achieve the first objective of the present invention, the present invention provides a fault identification method for through silicon vias before binding of a three-dimensional integrated circuit, comprising testing a plurality of through silicon vias through a detection circuit, obtaining a parasitic resistance value of each through silicon via respectively, and judging whether the through silicon via has a void fault or an open circuit fault according to the parasitic resistance value; dividing the through silicon via into a plurality of grid points, subjecting the plurality of grid points of the through silicon via to a cutting magnetic field movement, calculating the potential difference generated by each grid point when the cutting magnetic field moves according to the magnetic field strength, effective length and movement speed of the through silicon via when the cutting magnetic field moves, and determining whether each grid point has an abnormality according to the potential difference of each grid point; recording the position of the grid point with the abnormality, and determining whether the through silicon via has a pinhole fault according to the distribution of the grid points with the abnormality, thereby identifying the grid point fault defect and the fault type.

[0014] As can be seen from the above scheme, the present invention can test and analyze the faults of the silicon vias before the silicon vias are bound, especially by calculating the parasitic resistance value of the silicon vias in combination with the equivalent circuit of the silicon vias, and calculating the potential difference of each grid point by cutting the magnetic field, thereby analyzing the fault type and degree of the silicon vias, and accurately analyzing the fault type and degree of the silicon vias. Since the fault detection of the silicon vias is performed before binding, the cost of detection can be reduced, and the detection process is not complicated, which can improve the detection efficiency.

[0015] A preferred solution is that the filler of the silicon via is cut and moved at a uniform speed in a uniform field strength; determining whether each grid point has an abnormality based on the potential difference of each grid point includes: calculating the theoretical potential difference generated by each grid point when the cutting magnetic field moves based on the magnetic field strength, effective length and movement speed of the silicon via when the cutting magnetic field moves, and obtaining the actual potential difference of each grid point, and determining whether each grid point has an abnormality based on the theoretical potential difference and the actual potential difference.

[0016] A further solution is to determine whether there is an abnormality at each grid point based on the theoretical potential difference and the actual potential difference, including: calculating the ratio of the actual potential difference to the theoretical potential difference, and judging whether the ratio is within a preset range. If it exceeds the preset range, it is determined that there is an abnormality at the grid point.

[0017] It can be seen that by presetting a threshold range and comparing the ratio of the actual potential difference to the theoretical potential difference with the threshold range, it is possible to quickly determine whether each grid point has an abnormality.

[0018] An optional solution is that the filler of the silicon via performs nonlinear cutting motion in a magnetic field; when the silicon via is divided into multiple grid points, the multiple grid points of the silicon via are grouped using a binary search method, and when it is identified that there is an abnormality in the grouping of a certain grid point, a recursive method is used to detect the abnormal grid point grouping.

[0019] It can be seen that dividing the TSV into multiple grid points and using the binary method for detection can quickly detect the specific locations of abnormal grid points and improve detection efficiency.

[0020] A further solution is that dividing the through silicon via into a plurality of grid points includes: dividing the through silicon via into a plurality of grid points according to a preset size, and the grid points are regular hexahedrons.

[0021] In this way, by presetting the size of the divided grid points, the potential difference of each grid point can be easily calculated, thereby reducing the complexity of the calculation.

[0022] A further solution is to determine whether the TSV has a pinhole fault based on the distribution of abnormal grid points, including: judging whether the abnormal grid points are distributed in the insulating area, and if so, determining that the TSV has a pinhole fault.

[0023] It can be seen that since pinhole faults usually occur in the insulating region, whether the through silicon via has a pinhole fault can be determined by judging whether the abnormal grid points are distributed in the insulating region.

[0024] A further solution is to determine the void fault of the TSV based on the parasitic resistance value and then determine the extent of the void fault of the TSV based on the parasitic resistance value and a preset threshold value.

[0025] It can be seen that different void failure degrees have a direct impact on the parasitic resistance value of the TSV. Therefore, judging the void failure degree of the TSV by the obtained parasitic resistance value can quickly make a preliminary analysis of the TSV air conditioning failure degree.

[0026] A further solution is to test multiple silicon vias through a detection circuit, including: obtaining a layout file of the silicon via chip design to be tested, modeling the silicon via to be tested to obtain an equivalent circuit of the silicon via, and using the equivalent circuit to simulate to obtain the parasitic resistance value of the silicon via.

[0027] Since the equivalent circuit of the through silicon via is obtained by modeling, and the parasitic resistance value of the through silicon via is calculated based on the equivalent circuit, the calculation of the parasitic resistance value of the through silicon via can be realized quickly.

[0028] A further solution is that when the multiple grid points of the silicon via are cut and the magnetic field is moved, the angle and direction between the magnetic field and the silicon via chip remain fixed.

[0029] In this way, the accuracy of the calculated actual potential difference data can be ensured, thereby accurately judging whether the through silicon via is abnormal.

[0030] To achieve the above-mentioned second purpose, the present invention provides a fault identification device for silicon vias of a three-dimensional integrated circuit before binding, including: a parasitic resistance value calculation module, which is used to model the silicon vias and generate an equivalent circuit of the silicon vias, and calculate the parasitic resistance value of each silicon via according to the equivalent circuit; a fault analysis and classification module, which is used to determine whether the silicon via has a void fault or an open circuit fault according to the parasitic resistance value; and, the silicon vias are divided into a plurality of grid points, and the plurality of grid points of the silicon vias are subjected to a cutting magnetic field movement, and the potential difference generated by each grid point during the cutting magnetic field movement is calculated according to the magnetic field strength, effective length and movement speed of the silicon via during the cutting magnetic field movement, and whether each grid point is abnormal is determined according to the potential difference of each grid point; the position of the grid point with abnormality is recorded, and whether the silicon via has a pinhole fault is determined according to the distribution of the abnormal grid points, thereby identifying the grid point fault defect and the fault type; a fault display module, which is used to display the fault information of the silicon via.

[0031] As can be seen from the above scheme, the present invention combines circuit simulation and cutting magnetic field to generate electromagnetic induction potential difference to perform fault analysis on TSVs before binding. Different from the traditional redundant circuit test or probe test method, the present invention uses the principle of electromagnetic induction to test TSVs in a non-contact manner, solving the problem of large testing limitations of traditional test methods when TSVs are in a blind hole state, and enriching the TSV testing methods. Since the test is performed before the TSVs are bound, the fault analysis cost of the TSVs can be reduced, and the testing efficiency of the TSVs can be improved.

[0032] A preferred solution is that when calculating the parasitic resistance value of each TSV, a detection circuit is used to detect the parasitic resistance value of the TSV, and the detection circuit has a four-wire resistance measurement circuit.

[0033] It can be seen that the detection circuit is implemented using a commonly used four-wire resistance measurement circuit, which does not require the setting of a complex detection circuit and does not increase the hardware cost of the test, thereby achieving low-cost detection and analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Schematic diagram of no failure and multiple failure scenarios of TSV chip.

[0035] Figure 2 It is a structural block diagram of an embodiment of a fault identification device before through silicon via binding of a three-dimensional integrated circuit of the present invention.

[0036] Figure 3 It is a schematic diagram of the connection between the through silicon via and the outside in an embodiment of the method for fault identification before through silicon via binding of a three-dimensional integrated circuit of the present invention.

[0037] Figure 4It is a flow chart of an embodiment of a method for fault identification before through silicon via bonding of a three-dimensional integrated circuit of the present invention.

[0038] Figure 5 It is an electrical schematic diagram of a resistance measurement circuit used in an embodiment of a fault identification device before through silicon via binding of a three-dimensional integrated circuit of the present invention.

[0039] Figure 6 It is the equivalent circuit diagram of the through silicon via chip under no fault and multiple fault conditions.

[0040] Figure 7 It is a schematic diagram of implementing grid point division of through silicon vias in a fault identification method before through silicon via binding of a three-dimensional integrated circuit of the present invention.

[0041] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0042] The present invention analyzes the failure of silicon vias of three-dimensional integrated circuits, and the present application mainly analyzes the failure of silicon vias before they are bound, especially analyzing whether the silicon vias have various failure types such as void failures and pinhole failures, and can also identify the degree of the failure.

[0043] Embodiment of a fault identification device before through silicon via bonding of a three-dimensional integrated circuit:

[0044] See also Figure 2 , this embodiment has a parasitic resistance value calculation module 31, a fault analysis and classification module 32, and a fault display module 33, wherein the parasitic resistance value calculation module 31 is used to model the through silicon via, obtain the equivalent circuit of the through silicon via, and calculate the parasitic resistance value of the through silicon via. The fault analysis and classification module 32 is used to analyze the fault type and fault degree of the through silicon via. Preferably, the parasitic resistance value calculated by the parasitic resistance value calculation module 31 can be used for preliminary judgment and analysis. In addition, the fault analysis and classification module 32 will further analyze the fault type of the through silicon via in combination with the parameters generated by the movement process of the through silicon via cutting magnetic field. The fault display module 33 is used to display the fault information of the through silicon via, for example, by graphically displaying the abnormal situation of the through silicon via, that is, which position of the through silicon via has an abnormality, and can also display the fault degree of the through silicon via.

[0045] Embodiment of a method for identifying faults before through silicon via bonding of a three-dimensional integrated circuit:

[0046] When the above-mentioned fault identification device before through silicon via binding of a three-dimensional integrated circuit is used to identify the fault of the through silicon via of the three-dimensional integrated circuit, it is first necessary to make a connection before the through silicon via binding, such as Figure 3As shown, metal doping regions 11 and 12 are connected to the overfilled metal object 13, and are connected to the circuit for testing the through silicon via 15 through the metal doping regions 11 and 12. In order to test the through silicon via through an off-chip circuit, the present embodiment uses the overfilled metal object 13 to interconnect the through silicon via 15 and the metal doping regions 11 and 12, which has a low manufacturing cost, and after flattening and thinning and binding, the external circuit can be removed, reducing the damage caused by the probe to the through silicon via. In addition, the two metal doping regions 11 and 12 can be connected to the test circuit or test equipment through the test access port (TAP) controller routing based on the silicon substrate for parallel test verification. Then, the detection circuit for detecting the through silicon via is bound to the through silicon via to be tested through the routing switch.

[0047] Next, see Figure 4 , execute step S11, obtain the layout file of the silicon via chip to be tested, model the silicon via to be tested, for example, use the method introduced in the invention patent application CN118709618A to model, simulate based on the silicon via model, obtain the equivalent circuit of the silicon via, and thereby obtain various electrical parameters of the silicon via to be tested, such as the inductance (L), capacitance (C), resistance (R) and conductance (G) of the silicon via. Based on the simulation of the equivalent circuit of the silicon via, the theoretical value of the parasitic resistance value of each silicon via can be calculated.

[0048] Then, step S12 is performed to detect the through silicon via using a resistance measurement circuit to obtain the parasitic resistance value of the through silicon via. Figure 5 The detection circuit of this embodiment has a four-wire resistance measurement circuit, which has a current source Is and a voltage source Vm, and is provided with four resistors R1, R2, R3 and R4. The parasitic resistance of the silicon through via to be detected is Rx, and the circuit includes excitation input points 41, 44 and measurement points 42, 43. The excitation signal can be loaded to the silicon through via through the excitation input points 41, 44, and the response signal of the silicon through via to the input excitation signal is detected through the measurement points 42, 43. The actual value of the parasitic resistance value of the silicon through via to be detected is measured by the circuit.

[0049] Next, execute step S13 to quickly identify whether there is a void fault in the TSV based on the theoretical value of the parasitic resistance of the TSV obtained by simulation calculation and the actual value of the parasitic resistance measured, and mark and classify the TSV with void fault. With the improvement of process accuracy, the radius of the TSV can generally reach 3 nanometers to 100 microns. Due to the size of the TSV, the resistance is also relatively large. If a void appears in the TSV, and the void accounts for more than a certain proportion of the cross-sectional area, there will be a significant difference between the actual value and the theoretical value of the parasitic resistance of the TSV. At this time, it can be determined that a similar Figure 1 (d) shows the case of truncation 23. If this happens, the equivalent circuit of the through silicon via is as follows: Figure 6 (d) shows the situation, that is, a capacitor C43 is formed between capacitor C41 and capacitor C42. Through the above method, the fault type of the silicon via can be quickly judged, and even the filling depth of each silicon via can be measured to see whether it meets the actual requirements, thereby determining whether there is a problem with the filling process.

[0050] Preferably, after measuring the parasitic resistance value of each through silicon via, the through silicon via with void problems can be classified according to the actual value of the parasitic resistance value of each through silicon via, and multiple thresholds can be pre-set, and the actual value of the parasitic resistance value of the through silicon via is compared with the pre-set threshold to identify the severity of the void fault of the through silicon via. For example, the void fault is divided into an open circuit fault, a major void fault, a moderate void fault and a minor void fault. An open circuit fault is a void in the through silicon via that runs through the entire through silicon via, causing the central conductor of the through silicon via to be completely disconnected and unable to transmit signals. This situation will cause the circuit to fail completely and the signal cannot be transmitted. A major void fault is a large void in the through silicon via, which seriously affects the integrity and quality of signal transmission, causing a significant decrease in circuit performance, serious signal distortion, and failure to meet design requirements. The void size of the through silicon via with a moderate void fault is moderate, which has a certain impact on signal transmission, but has not yet reached a serious level. This situation will cause the quality of signal transmission to decline, but the circuit can still basically work normally, and needs to be closely monitored and measures taken to prevent deterioration. A minor void fault is a small void in the TSV, which has limited impact on signal transmission and will cause a slight decrease in signal transmission quality, but generally does not affect the normal operation of the circuit. By identifying the void situation of the TSV, the void situation in the TSV can be accurately identified and targeted treatment can be carried out.

[0051] For example, if the TSV has no anomaly, its equivalent circuit is as follows: Figure 6 As shown in (a), the TSV is equivalent to a capacitor C11; if a pinhole fault occurs in the TSV, Figure 1 (b) The equivalent circuit is as follows: Figure 6As shown in (b), the TSV will equivalently form a resistor R21 and a capacitor C21; if a void appears in the TSV but does not cause the TSV to be completely open, its equivalent circuit is as follows Figure 6 As shown in (c), the equivalent circuit of the through silicon via includes capacitors C31 and C32 at both ends, and a resistor R31 is formed between the two capacitors C31 and C32. The above method can preliminarily analyze the fault type and fault degree of the through silicon via.

[0052] However, since TSVs may have both pinhole and void faults, and these two fault conditions may be coupled to a certain extent at certain times, if a TSV has a pinhole fault, the position of the pinhole needs to be located. Since traditional detection methods cannot quickly locate pinhole faults, traditional TSV fault detection methods cannot accurately detect and analyze solid TSV fault types.

[0053] In case of pinhole failure in silicon via, this embodiment adopts electromagnetic measurement to detect, that is, the silicon via is divided into multiple grid points, and the silicon via is subjected to cutting magnetic field movement. The parameters formed during the cutting magnetic field movement are used to determine whether the silicon via has a field effect pinhole failure, and the location of the pinhole failure is identified.

[0054] Specifically, step S14 is performed to divide the through silicon via to be detected into a plurality of grid points, such as Figure 7 As shown in (a), for example, the size of each grid point 51 is preset, and the through silicon via is divided into a plurality of grid points 51 according to the preset size. Preferably, the divided grid points 51 are regular hexahedrons as much as possible. Of course, the grid points located at the edge may also be irregular in shape, for example, the divided grid points have irregular and rough micro-particles, which does not affect the test results and calibration results.

[0055] Then, step S15 is executed to perform cutting magnetic field movement on different grid points of the silicon through hole, and the detection circuit is used to identify whether there are abnormalities in each grid point of the silicon through hole, and the position of the grid point with abnormalities is recorded. Since the silicon through hole is filled with metal to form a metal rod, according to Faraday's law of electromagnetic induction, when the metal rod cuts the induction line in the magnetic field, an electric potential difference will be generated at both ends of the metal rod. The electric potential difference generated by the metal rod can be calculated by the following formula: E=BLv. Among them, E is the electromotive force generated at both ends of the metal rod; B is the magnetic induction intensity of the magnetic field, the unit is Tesla; L is the effective length of the metal rod cutting the magnetic induction line in the magnetic field, usually the length of the metal rod in the direction of movement in the magnetic field, the unit is meter; v is the speed of the metal rod moving in the magnetic field, the unit is meter per second.

[0056] In actual application, considering the external magnetic field of uniform field strength and the small size of silicon via, the cost of implementing the step-by-step uniform motion of cutting the magnetic field after dividing into grid points is relatively high. This embodiment can be implemented by two fault analysis methods: uniform speed cutting motion of the silicon via filler in uniform field strength and nonlinear cutting motion of the silicon via filler in the magnetic field.

[0057] In this embodiment, the uniform speed cutting magnetic field motion of each grid point in uniform field strength means that the magnetic field strength distribution at each position is uniform and of the same magnitude, and the object is performing uniform speed cutting magnetic field motion at a certain angle. When each grid point performs nonlinear cutting magnetic field motion in the magnetic field, the magnetic field in the magnetic field may be non-uniform, but the magnetic field strength distribution is stable, and it is only required that when the object moves with the same motion trajectory in different magnetic field strengths, the motion angle and speed of each grid point are consistent.

[0058] For the fault analysis method of the uniform speed cutting movement of the silicon via filler in the uniform field strength, it is first necessary to calculate the theoretical potential difference E_Theoretical_Value generated by the grid points of the silicon via when the cutting magnetic field moves according to the above formula E=BLv, and assuming that there is no abnormality at each grid point, the potential difference generated by each grid point is the theoretical potential difference E_ Theoretical_Value. In practical applications, the calculated theoretical potential difference E_Theoretical_Value can be used as a charging voltage to charge the detection circuit to simulate the movement of the silicon via cutting magnetic field. After the detection circuit is charged, the charging time and discharge time of a certain grid point of the silicon via to be detected in response to the charging voltage are obtained, and the actual potential difference E_ Real_Value_x of the grid point is calculated according to the charging time and discharge time. Then, the ratio between the actual potential difference E_ Real_Value_x of the grid point and the theoretical potential difference E_ Theoretical_Value is calculated. Next, it is determined whether the ratio is within a preset range. If it exceeds the preset range, for example, the ratio is greater than a set threshold, it is determined that there is an abnormality in the grid points of the through silicon via.

[0059] In practical applications, the actual potential difference E_ Real_Value_x can be calculated using the RC discharge principle instead of calculation. For example, the load of the circuit can be detected by the discharge and charge object, or the electrical parameters of charging and discharging can be obtained through the waveform of the input signal and output signal of the oscillation circuit.

[0060] Assuming that the detection circuit is charged and discharged with the theoretical potential difference E_ Theoretical_Value, according to the RC charging principle, during the charging process, the relationship between the voltage V across the capacitor and the time t can be expressed by the following formula: V = V0 × (1 - e^ (-t / RC)). Among them, V is the voltage across the capacitor, V0 is the power supply voltage, t is time, R is the resistance of the resistor, and C is the capacitance of the capacitor. The time constant τ = RC describes the time required for the capacitor to charge to 63.2% of the power supply voltage (i.e., V = 0.632V0). During the detection, it is only necessary to record the charging time and discharging time under the preset charging voltage. According to the actual charging time and discharging time, it can be judged whether a certain grid point has an abnormality. If there is no abnormality at the grid point, the actual charging time and discharging time should meet the requirements of the theoretical calculation value, that is, within a certain range of the theoretical calculation value. If it does not meet the requirements of the theoretical calculation value, it can be considered that the grid point has an abnormality, so that the grid point with an abnormality can be found.

[0061] The following steps are used to analyze the failure of TSV filler in nonlinear cutting motion in a magnetic field:

[0062] First, a magnetic field is applied outside the TSV chip. Preferably, the magnetic field needs to be a stable magnetic field, even if the magnetic field strength of the magnetic field may be unevenly distributed in the overall relative area. In addition, the angle and direction between the magnetic field direction and the movement direction of the TSV chip should remain fixed. Preferably, the angle between the magnetic field direction and the movement direction of the TSV chip is 90°.

[0063] Then, the silicon through hole is divided into a plurality of grid points. Preferably, the size of each grid point is as equal as possible, and these grid points cut the magnetic field along the same trajectory in the magnetic field. In order to quickly locate the approximate position of the abnormal grid point, the binary method is preferably used to divide each grid point and detect it. Then, recursive detection is performed and gradually refined to each grid point. In other words, the plurality of grid points in the silicon through hole are first grouped, divided into two groups according to the position of each grid point, and then the two groups of grid points are detected. If the detection finds that a group of grid points is abnormal, the group of grid points is further divided into two groups, and the detection is continued until the abnormal grid point is detected.

[0064] After the silicon through hole is divided into grid points, all grid points are set to cut the magnetic field according to the preset motion trajectory and speed, and complete the same trajectory motion within the specified time interval. During each detection process, it is necessary to record the motion trajectory of the grid points, the actual potential difference of the grid points, the current, the discharge time and other electrical parameters. At the same time, according to demand, the parasitic information generated in the detection circuit each time the magnetic field is cut can also be recorded, such as resistance, capacitance, inductance and conductance data. Since the motion trajectory, magnetic field area distribution intensity and movement speed of each silicon through hole remain unchanged, the grid size of the silicon through hole becomes the only variable. By collecting a large number of data samples, not only can the optimal silicon through hole after the fault has been troubleshooted be used as a standard, but the fault standard can also be determined based on the calculation results. In the absence of errors caused by contact circuits in the circuit, experiments can be carried out under relatively stable temperature conditions, thereby significantly improving the accuracy of the data.

[0065] By controlling the size of the grid points, the grid points can be divided into nanometer-scale grid points and thus fault detection can be performed. Since the size of each grid point is small, a binary method can be used for testing to control the feasibility of relative motion, which not only improves the accuracy and feasibility, but also reduces the detection cost of constant-speed relative motion.

[0066] Although the silicon through via is a whole piece of metal conductor, since the silicon through via is divided into multiple grid points, when these grid points cut the magnetic field with the same speed, motion trajectory, time and field strength distribution, if the metal distribution of each grid point is consistent, the errors of multiple electrical parameters that can be calculated, such as motion trajectory, potential difference, current, discharge time and parasitic information, will be very small. Therefore, when the detection circuit remains unchanged, it is only necessary to consider the circuit differences caused by the metal quality and position of the grid point filling. The circuit differences caused by the position of each grid point can not only be calculated using an equivalent circuit, but also can be identified according to the fault type and fault degree of the parasitic resistance value obtained in step S13, combined with the results of electromagnetic analysis, to quickly identify whether a certain grid point is abnormal, and thereby identify the position of the grid point with the abnormality, that is, execute step S16.

[0067] Since the pinhole fault of silicon via usually occurs in the insulating area, if the grid points of storage anomaly obtained by the above steps are distributed in the insulating area, it can be preliminarily determined that the silicon via has a pinhole fault. Since the potential difference generated by different materials cutting the magnetic field is different, it is easier to determine the pinhole fault if the abnormal grid point is located in the insulating area. If there is a pinhole in the insulating area of ​​the silicon via, the insulating silicon bottom can be further tested. For example, the insulating silicon bottom is also divided into grid points, and the above-mentioned steps are used to detect whether each grid point has an abnormality, that is, to determine whether a certain grid point has an abnormality based on the actual value of the electromotive force obtained.

[0068] Finally, step S17 is executed to determine the abnormal type and degree of the TSV according to the distribution of the abnormal grid points in the TSV. Since step S16 can calculate the abnormal grid points, that is, the position of each abnormal grid point can be obtained, by analyzing the distribution of each abnormal grid point, it can be determined whether the TSV to be detected has a void fault or a pinhole fault. If it is a void fault, it can also be identified whether the TSV is truncated, or the size of the micropore can be identified, and then the degree of fault of the TSV to be detected can be identified.

[0069] like Figure 7 As shown in (b), if the abnormal grid point 52 is identified to be located in the insulating region 16, it can be determined that the silicon through hole has a pinhole 21; Figure 7 As shown in (c), if it is identified that the abnormal grid point 53 is located inside the silicon via 15, according to the respective conditions of the plurality of abnormal grid points 53, it can be determined that a microhole 22 is formed inside the silicon via 15; Figure 7 As shown in (d), if the abnormal grid point 54 is identified to be located in the through silicon via 15 and occupies a large cross-sectional area, it is determined that a truncation 23 is formed inside the through silicon via 15.

[0070] This embodiment divides the silicon through via into multiple small grid points and uses the binary search method to test the multiple grid points, so as to quickly detect the positions of abnormal grid points. Since the number of abnormal grid points is usually small, the binary search method can avoid testing, calculating and analyzing each grid point one by one. Compared with the traditional fault sample calibration method, this embodiment can improve the detection efficiency and reduce the detection cost.

[0071] Since the present embodiment tests the TSVs before binding, in addition to calculating the parasitic resistance value of each TSV, the TSVs are also subjected to cutting magnetic field movement, and the generated potential difference is calculated to determine whether there is an abnormality in the TSV. This method is not only highly accurate and low-cost, but also can bring additional benefits to improving the yield of TSVs by adopting a cutting motion fault analysis method that utilizes the nonlinearity of the TSV filler.

[0072] Since the basic principle of cutting the magnetic field is to use the magnetic field to regulate the electron spin, under the action of the magnetic field, the electron spin in the silicon via will be affected by the Lorentz force, thereby changing its arrangement state. Using the magnetic field to make the electron spin arrangement more orderly may reduce electron scattering, thereby improving the electron mobility and conductivity. This embodiment can improve the manufacturing quality of each silicon via.

[0073] This embodiment can use electromagnetic fields and detection circuits to achieve passive circuit testing and contactless testing. This testing method has the advantages of low power consumption and low cost. During large-scale testing, it avoids energy waste caused by testing. In addition, this embodiment enriches the method for detecting through silicon vias, improves the detection accuracy, and can achieve nano-scale fault detection, analysis and display of through silicon vias. In addition, since through silicon vias do not need to be processed using a magnetizing circuit before binding, and through silicon vias use copper as a filler, copper is a non-magnetic material and will not cause magnetization. Therefore, this embodiment is a non-destructive detection method for through silicon vias.

[0074] With the popularization of high-precision magnetic fields such as nanomagnetic fields and micron magnetic fields, the present invention is not limited to the motion cutting of magnetic flux lines, but can also control the linear change of the intensity of the magnetic field to detect the fault defects of the silicon via when the silicon via and the magnetic field space are relatively static. Therefore, the present invention is not limited to the above method, but can also use the distributed magnetic field changes in a fixed space to test the fault conditions of the silicon via before binding when it is static.

[0075] Finally, it should be emphasized that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for identifying faults before through silicon via bonding of a three-dimensional integrated circuit, comprising: Testing a plurality of through silicon vias by means of a detection circuit, obtaining a parasitic resistance value of each of the through silicon vias, and determining whether the through silicon via has a void fault or an open circuit fault according to the parasitic resistance value; Features: Dividing the through silicon via into a plurality of grid points, subjecting the plurality of grid points of the through silicon via to cutting magnetic field movement, calculating the potential difference generated by each grid point when the cutting magnetic field moves according to the magnetic field strength, effective length and movement speed of the through silicon via when the cutting magnetic field moves, and determining whether each grid point has an abnormality according to the potential difference of each grid point; The positions of the abnormal grid points are recorded, and whether the through silicon via has a pinhole fault is determined according to the distribution of the abnormal grid points, so as to identify the grid point fault defect and the fault type.

2. The method for fault identification before through silicon via bonding of a three-dimensional integrated circuit according to claim 1, characterized in that: The filler of the through silicon via is cut and moved at a uniform speed in a uniform field strength; Determining whether each of the grid points has an abnormality according to the potential difference of each of the grid points comprises: The theoretical potential difference generated by each grid point when the cutting magnetic field moves is calculated based on the magnetic field strength, effective length and movement speed of the silicon through hole when the cutting magnetic field moves, and the actual potential difference of each grid point is obtained, and whether there is an abnormality at each grid point is determined based on the theoretical potential difference and the actual potential difference.

3. The method for fault identification before through silicon via bonding of a three-dimensional integrated circuit according to claim 2, characterized in that: Determining whether each of the grid points has an abnormality according to the theoretical potential difference and the actual potential difference comprises: The ratio of the actual potential difference to the theoretical potential difference is calculated to determine whether the ratio is within a preset range. If the ratio exceeds the preset range, it is determined that an abnormality exists at the grid point.

4. The method for fault identification before through silicon via bonding of a three-dimensional integrated circuit according to claim 1, characterized in that: The filler of the through silicon via performs nonlinear cutting motion in the magnetic field; When the through silicon via is divided into a plurality of grid points, the plurality of grid points of the through silicon via are grouped by using a binary search method. When it is identified that a certain grid point group is abnormal, a recursive method is used to detect the abnormal grid point group.

5. The method for fault identification before through silicon via bonding of a three-dimensional integrated circuit according to any one of claims 1 to 4, characterized in that: Dividing the through silicon via into a plurality of grid points includes: dividing the through silicon via into a plurality of grid points according to a preset size, wherein the grid points are regular hexahedrons.

6. The method for fault identification before through silicon via bonding of a three-dimensional integrated circuit according to any one of claims 1 to 4, characterized in that: Determining whether the through silicon via has a pinhole fault according to the distribution of the abnormal grid points includes: judging whether the abnormal grid points are distributed in an insulating region, and if so, determining that the through silicon via has a pinhole fault.

7. The method for fault identification before through silicon via bonding of a three-dimensional integrated circuit according to any one of claims 1 to 4, characterized in that: After determining that the TSV has a void fault according to the parasitic resistance value, the degree of the void fault of the TSV is determined according to the parasitic resistance value and a preset threshold value.

8. The method for fault identification before through silicon via bonding of a three-dimensional integrated circuit according to any one of claims 1 to 4, characterized in that: Testing of multiple TSVs with inspection circuits includes: The layout file of the through silicon via chip design to be tested is obtained, a model is built for the through silicon via to be tested to obtain an equivalent circuit of the through silicon via, and the equivalent circuit is used to perform simulation to obtain the parasitic resistance value of the through silicon via.

9. A fault identification device before through silicon via bonding of a three-dimensional integrated circuit, characterized in that: include: A parasitic resistance value calculation module, used to generate an equivalent circuit of the through silicon via by modeling the through silicon via, and calculate the parasitic resistance value of each through silicon via according to the equivalent circuit; A fault analysis and classification module is used to determine whether the silicon through via has a void fault or an open circuit fault according to the parasitic resistance value; and divide the silicon through via into a plurality of grid points, subject the plurality of grid points of the silicon through via to a cutting magnetic field movement, calculate the potential difference generated by each grid point when the cutting magnetic field moves according to the magnetic field strength, effective length and movement speed of the silicon through via when the cutting magnetic field moves, and determine whether each grid point has an abnormality according to the potential difference of each grid point; Recording the location of the abnormal grid points, and determining whether the through silicon via has a pinhole fault according to the distribution of the abnormal grid points, thereby identifying the grid point fault defect and the fault type; A fault display module is used to display the fault information of the through silicon via.

10. The device for identifying faults before through silicon via bonding of a three-dimensional integrated circuit according to claim 9, characterized in that: When calculating the parasitic resistance value of each of the through silicon vias, a detection circuit is used to detect the parasitic resistance value of the through silicon via, and the detection circuit has a four-wire resistance measurement circuit.

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