Address translation caching method, translation buffer, processor and computer storage medium

Abstract

The embodiment of the invention provides an address translation caching method, a translation cache, a processor and a computer storage medium. The address translation caching method comprises the steps that a plurality of hit states of a virtual address in an address translation request to a plurality of cache lines are determined, the cache lines have different page granularities by being divided into a plurality of cache groups respectively, and the hit state of each cache line indicates that the cache line is in a valid hit state, an invalid hit state or a miss state; combining the plurality of hit states to obtain a combined hit state; and if the combined hit state indicates that the effective hit is preferential, determining the backfill address table entry of the cache line of which the hit state is the effective hit as the cache table entry of the virtual address.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and in particular to an address translation cache method, a translation cache, a processor, and a computer storage medium. Background Art

[0002] In existing computer systems, processor applications generally use the virtual address (VA) of virtual memory to call related resources and use the virtual address to manage the virtual storage space of the computer system. For example, an application applies for a larger continuous physical space, and the application data subsequently fills the applied physical space, which is conducive to improving hardware compatibility.

[0003] In the memory access process, the virtual address needs to be translated into a physical address (PA). In order to achieve the translation between virtual addresses and physical addresses, the computer system needs to store a large number of backfill address table entries, each of which is used to translate a specified range of virtual addresses into corresponding physical addresses.

[0004] Translation buffers such as the Translation Look Aside Buffer (TLB) are used to cache a portion of the backfill address table entries stored in the computer system to avoid the need to search from the backfill address table entries stored in the computer system memory for each address translation process. If the virtual address to be translated matches one of the backfill address table entries cached by the TLB (also known as a hit), the memory management unit (MMU) can directly use the matching table entries cached in the TLB to implement address translation without searching in the storage device outside the TLB. If none of the cached entries in the TLB can match the virtual address to be translated, it is a miss.

[0005] If the TLB misses, the Page Table Walker (PTW) accesses the table entries stored in the computer system memory as backfill entries to complete the translation between the virtual address and the physical address. Existing processors need to support table entries of multiple page granularities (e.g., 4K, 64K, 2M, etc.). For a TLB that caches a single page granularity, caching table entries with a smaller page granularity (4K) will cause a large number of unnecessary misses, and caching table entries with a larger page granularity (64K) will occupy a larger storage space, and the utilization rate of the cache table entries is low, so it is impossible to take into account both the hit rate of the cache line and the utilization rate of the cache space. Summary of the invention

[0006] In view of this, an embodiment of the present invention provides an address translation cache method, a translation cache, a processor, and a computer storage medium to solve the above problems.

[0007] According to a first aspect of an embodiment of the present invention, there is provided a method for determining multiple hit states of a virtual address in an address translation request for multiple cache lines, wherein the multiple cache lines have different page granularities by being respectively divided into multiple cache groups, and the hit state of each cache line indicates that the cache line is in a valid hit, an invalid hit or a miss; the multiple hit states are merged to obtain a merged hit state; if the merged hit state indicates that a valid hit takes priority, a backfill address table entry of the cache line whose hit state is a valid hit is determined as the cache table entry of the virtual address.

[0008] In another implementation of the present invention, the method further includes: deleting the remaining cache lines other than the cache lines whose hit status is a valid hit among the multiple cache lines.

[0009] In another implementation of the present invention, the multiple hit states are merged to obtain a merged hit state, including: if there is a valid hit among the multiple hit states, the multiple hit states are merged into a merged hit state indicating that the valid hit is prioritized.

[0010] In another implementation of the present invention, the method further includes: if the merged hit status indicates miss priority, then according to the page granularity of the cache group whose hit status is miss, reading the backfill address table entry corresponding to the virtual address, and determining the backfill address table entry as a cache table entry.

[0011] In another implementation of the present invention, the multiple hit states are merged to obtain a merged hit state, including: if there is a miss and no valid hit in the multiple hit states, the multiple hit states are merged into a merged hit state indicating miss priority.

[0012] In another implementation of the present invention, the method further includes: associating the cache entry with the created cache line, and generating a response to the address translation request.

[0013] In another implementation of the present invention, the method also includes: if the merged hit status indicates that invalid hits take priority, then when a cache entry is read, the cache line corresponding to the cache entry is changed from an invalid hit to a valid hit, and when the cache entry is not read, the cache line corresponding to the cache entry is changed from an invalid hit to a miss.

[0014] In another implementation of the present invention, the multiple hit states are merged to obtain a merged hit state, including: if the multiple hit states are all invalid hits, merging the multiple hit states into a merged hit state indicating that invalid hits are given priority.

[0015] According to a second aspect of an embodiment of the present invention, a translation cache is provided, comprising: a hit status judgment unit, determining multiple hit statuses of a virtual address in an address translation request for multiple cache lines, the multiple cache lines having different page granularities by being respectively divided into multiple cache groups, and the hit status of each cache line indicating that the cache line is in a valid hit, an invalid hit or a miss; a hit status management unit, merging the multiple hit statuses to obtain a merged hit status; and an entry cache unit, determining the backfill address entry of the cache line with a hit status of a valid hit as the cache entry of the virtual address if the merged hit status indicates that a valid hit takes priority.

[0016] According to a third aspect of an embodiment of the present invention, a processor is provided, comprising the translation buffer according to the second aspect.

[0017] According to a fourth aspect of an embodiment of the present invention, a translation cache is provided, comprising: a processing unit, a storage unit, a communication interface and a communication bus, wherein the processing unit, the storage unit and the communication interface communicate with each other via the communication bus; the storage unit is used to store at least one executable instruction, and the executable instruction enables the processing unit to execute the method described in the first aspect.

[0018] According to a fifth aspect of an embodiment of the present invention, there is provided a computer storage medium on which a computer program is stored. When the program is executed by a processing unit, the method described in the first aspect is implemented.

[0019] In the solution of the embodiment of the present invention, multiple cache lines are divided into multiple cache groups with different page granularities, thereby improving the hit rate of the cache lines. In addition, when the combined hit state obtained by combining multiple hit states indicates that valid hits are prioritized, a cache line with a hit state of valid hits can be selected from multiple cache lines, and then the backfill address table entry of the cache line is determined as a cache table entry of the virtual address, thereby improving the utilization of the cache space, thereby taking into account both the hit rate of the cache line and the utilization of the cache space as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0021] Figure 1A A schematic diagram of the structure of a computer system applicable to some embodiments of the present invention.

[0022] Figure 1B for Figure 1A A schematic diagram of the structure of some example processors in the embodiments.

[0023] Figure 2 Schematic diagrams of the structures of some example translation buffers.

[0024] Figure 3 FIG. 4 is a schematic diagram of the structure of the translation buffer according to some embodiments of the present invention.

[0025] Figure 4 for Figure 3 A structural diagram of a further example of a translation buffer.

[0026] Figure 5 The following is a flowchart of the address translation cache method according to some other embodiments of the present invention.

[0027] Figure 6 Schematic diagram of the structure of the translation buffer according to some other embodiments of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in the field based on the embodiments in the embodiments of the present invention should fall within the scope of protection of the embodiments of the present invention.

[0029] In order to better understand the present invention, some terms used in the present invention are explained as follows.

[0030] Computer system, which can mean a desktop, server, general purpose embedded system, or other data processing system.

[0031] Memory can refer to the storage device in a computer system, and can also be called memory or main memory.

[0032] Physical Address (PA), also known as actual address, is used to provide to the address bus to access memory.

[0033] Virtual Address (VA), also known as logical address, is an abstract address used by programs. The virtual address space can be larger than the physical address space, and the virtual address can be mapped to the corresponding physical address.

[0034] Page refers to dividing the virtual address space into multiple parts, each part as a virtual page, and dividing the physical address space into multiple parts, each part as a physical page.

[0035] The root page table is stored in the memory and is used to represent the correspondence between virtual pages and physical pages. It usually includes multiple table entries, each of which includes the mapping relationship from virtual page to physical page and some attribute information, so that it can be used to translate the virtual address in the virtual page into the physical address in the corresponding physical page.

[0036] The Translation Look-aside Buffer (TLB) is used to cache some entries in the root page table that may be frequently used, so that they can be quickly called during the address translation process. It can also be called a fast table, which can speed up the address translation process.

[0037] The cache entry defines the entry stored in the translation buffer TLB as a cache entry.

[0038] Backfill entry: The entry obtained from the root page table based on the TLB miss information needs to be rewritten into the translation buffer TLB, so it is called a backfill entry.

[0039] The specific implementation of the embodiment of the present invention is further described below in conjunction with the accompanying drawings of the embodiment of the present invention.

[0040] Figure 1A 1 is a schematic diagram of the structure of a computer system of some embodiments of the present invention. The computer system 100 includes one or more processors 110. The processor 110 may be, for example, an independent processor or a processing circuit in a system on chip (SoC), including a microprocessor, a computing processing unit, a digital signal processing unit, a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a graphics processing unit (GPU), a neural network processing unit (NPU), a dedicated data processing unit (DPU) or any other type of processor or processing circuit that can be implemented by an integrated circuit.

[0041] Specifically, Figure 1AAs shown, in the computer system 100, the processor 110 transmits signals with other devices through the bus 120, and can transmit, for example, addresses, data or control signals. The bus 120 can be a processor bus, such as a Direct Media Interface (DMI) bus, a bus based on the Peripheral Component Interconnect (PCI) standard, a memory bus or other types of buses.

[0042] Other devices may be, for example, a memory 130 , a display device 140 , an input device 150 , a network device 160 , and a data acquisition device 170 .

[0043] The memory 130 serves as the main memory of the computer system 100 and may be a dynamic random access memory (DRAM), a static random access memory (SRAM) or other types of memory.

[0044] The display device 140 is used to display the interface or information that the processor needs to display to the user.

[0045] The input device 150 , such as a keyboard, a mouse, a touch panel, etc., is used to transmit the user's operation to the corresponding processor 110 to control the computer system 100 .

[0046] The network device 160 is used to enable the computer system 100 to access the network, and may include a wireless network device and / or a wired network device.

[0047] The data acquisition device 170 is used to collect information such as images, sounds, temperature, etc., and can be, for example, a microphone, a video camera, a camera, a temperature sensor, etc.

[0048] It should be noted that Figure 1A Only one structure of the computer system 100 is shown. The computer system 100 may also include other devices, and the present invention is not limited thereto.

[0049] Figure 1B1 is a schematic diagram of the structure of the processor of some embodiments of the present invention. The processor 110 of the present invention may include at least one core 10, each core includes a processing unit 101, a first cache 102, a second cache 103, a memory management unit 104, and a translation cache 105. The third cache 106 is shared by multiple cores 10, the first cache 102 is close to the processing unit 101, and the second cache 103 is between the first cache 102 and the third cache 106. The present invention is only introduced by taking the three-level cache as an example, of course, other cache structures can also be used.

[0050] The processing unit 101 issues a memory access instruction, and the memory management unit 104 first queries the physical address corresponding to the virtual address from the translation buffer 105 according to the virtual address. If there is a cache entry matching the virtual address in the translation buffer 105, it is called a TLB hit, and the virtual address is converted into a physical address according to the cache entry in the translation buffer 105. If there is no cache entry matching the virtual address in the translation buffer 105, it is called a TLB miss (i.e., miss), and the memory management unit 104 accesses the root page table in the memory to obtain the corresponding entry. Therefore, the translation buffer 105 can reduce the number of times the memory management unit 104 accesses the memory, saving the time of address translation.

[0051] It should be noted that Figure 1B Only one composition architecture of the processor 110 is shown. The processor 110 may also include registers for storing different types of data and / or instructions, such as integer registers, floating-point registers, status registers, instruction registers, and pointer registers, but the present invention is not limited thereto.

[0052] In order to better manage the address space exclusively occupied by each process, the computer system can allocate independent virtual address space to some processes and provide a mapping relationship from virtual address to physical address to map or demap the virtual address space to the physical address space.

[0053] Since data is usually transmitted in a computer system in units of pages, the computer system and / or operating system usually manages the physical address space and the virtual address space in units of pages. The virtual address space can be larger than the physical address space, that is, a virtual page in the virtual address space can be mapped to a physical page in the physical address space, or it can be mapped to a swap file, or there may be no mapping content.

[0054] Based on the paging management mechanism, the mapping relationship between each virtual page in the virtual address space and each physical page in the physical address space can be stored in the root page table of the memory. The root page table generally includes many entries, each of which is used to provide a mapping relationship between a virtual page and a corresponding physical page, so that the virtual address in the virtual page matching the entry can be translated into the corresponding physical address according to the entry.

[0055] For a certain process, the virtual address range corresponding to each virtual page (which may be referred to as the page granularity of the virtual page) should be consistent with the page granularity of the corresponding physical page, such as but not limited to 4K, 64K, 2M, etc. It should be added that for different processes, the page granularity of the corresponding virtual page may be consistent or inconsistent; similarly, for different processes, the page granularity of the corresponding physical page may be consistent or inconsistent, and different embodiments have different choices.

[0056] Since existing processors need to support table entries of multiple page granularities (such as 4K, 64K, 2M, etc.), for a TLB that caches a single page granularity, for example, when caching table entries with a smaller page granularity (4K), a large number of unnecessary misses will be caused, resulting in a low cache line hit rate; for another example, when caching table entries with a larger page granularity (64K), the page granularity of the backfill table entry is 4K, resulting in an unreliable address translation process.

[0057] From the perspective of TLB performance, a TLB that supports multiple page granularities can cover a larger physical address space. Compared with a single page granularity of the same size, the TLB has a higher hit rate while ensuring the reliability of address translation.

[0058] According to the different cache structures of TLB, TLB can include cache structures such as Set-associative TLB (set-associative translation lookaside buffer) and Fully-associative TLB (fully associative TLB). Set-associative TLB consists of multiple cache groups (Sets), and each cache group has a fixed number of cache lines (Ways). Part of the virtual address in the address translation request is used to determine the cache group, and the cache lines within the cache group are selected according to the replacement policy. The fully associative TLB is a larger cache structure, in which any virtual address can be mapped to any cache line, and the VA of all cache lines can be compared with the address translation request, which can implement cache structures with multiple page granularities.

[0059] For a fully associative TLB, when comparing the VA of all cache lines with the address translation request, it is subject to timing constraints. In addition, the cache lines of a fully associative TLB are subject to timing constraints, and the cache line hit rate cannot be improved by increasing the number of cache lines.

[0060] For a set-associative TLB, the tag storage unit (tag storage) configured based on a single page granularity cannot divide different cache groups so that cache lines in different cache groups have different page granularities. Figure 2 As shown, the TLB obtains the virtual address (VA) in the address translation request from the upstream device (e.g., CPU or other cache level) 20, and then obtains the tags (tags) of a certain number of cache lines (way) corresponding to the cache set (set) from the tag storage unit (tag storage). Then, the tag of the cache line is compared with the virtual address through the hit status judgment unit 210 to determine whether there is a cache line with a valid hit. If there is a cache line with a valid hit (i.e., a hit), the hit response will enter the hit status management unit 230 such as the miss status register (MSHR), activate the index entry (entries) corresponding to the virtual address, and the MSHR reads the cache table entry corresponding to the index entry from the table entry cache unit 240 such as the data storage unit (datastorage), uses the cache page to translate the virtual address into a physical address, and returns the physical address to the upstream device (e.g., CPU or other cache level) 20 of the TLB.

[0061] If there is a cache line miss, the hit status management unit 230 generates an index entry corresponding to the virtual address, and obtains the backfill entry corresponding to the virtual address to the data storage unit (data storage) 240 as a cache entry through the page table walker (PTW) 30, and associates the cache entry with the index entry.

[0062] If there is a cache line with an invalid hit (hit on miss), the hit status management unit 230 waits for the downstream device 30 to obtain the cache entry to trigger a hit response, then searches the cache entry to obtain the physical address corresponding to the virtual address, and returns the physical address to the upstream device 20 of the TLB.

[0063] The following will be combined Figure 3 The translation buffer of some embodiments of the present invention is described in detail. Figure 3The translation cache 300 is configured with a set associative cache structure. Specifically, the translation cache 300 includes a hit status determination unit 310 , a hit status management unit 320 , and an entry cache unit 330 .

[0064] In addition, the hit status judgment unit 310 determines multiple hit statuses of the virtual address in the address translation request for multiple cache lines. The multiple cache lines have different page granularities by being divided into multiple cache groups respectively. The hit status of each cache line indicates whether the cache line is in a valid hit, invalid hit or miss.

[0065] It should be understood that multiple cache lines are divided into multiple cache groups respectively, and the multiple cache groups have their own page granularity, for example, the larger page granularity is 64K, the medium page granularity is 16K, and the smaller page granularity is 4K.

[0066] In addition, the hit status management unit 320 merges multiple hit statuses to obtain a merged hit status.

[0067] It should be understood that multiple hit states may be merged based on a preset merge rule. For example, the preset merge rule indicates that a valid hit has a higher priority than a miss, and a miss has a higher priority than an invalid hit.

[0068] In addition, if the merged hit status indicates that the valid hit is prioritized, the entry cache unit 330 determines the backfill address entry of the cache line whose hit status is the valid hit as the cache entry of the virtual address.

[0069] It should be understood that the backfill address table entry is a backfill table entry obtained from a page table walker (PTW) 30, indicating an address mapping relationship between a virtual address and a physical address.

[0070] In the solution of the embodiment of the present invention, multiple cache lines are divided into multiple cache groups with different page granularities, thereby improving the hit rate of the cache lines. In addition, when the combined hit state obtained by combining multiple hit states indicates that valid hits are prioritized, a cache line with a hit state of valid hits can be selected from multiple cache lines, and then the backfill address table entry of the cache line is determined as a cache table entry of the virtual address, thereby improving the utilization of the cache space, thereby taking into account both the hit rate of the cache line and the utilization of the cache space as a whole.

[0071] More specifically, if Figure 4As shown, the TLB obtains the virtual address (VA) in the address translation request from the upstream device (e.g., CPU or other cache level) 20, and then obtains multiple cache sets (sets) from the cache line management unit 350, each cache set corresponding to a certain number of cache lines (way) tags (tags). The cache line management unit 350 can manage multiple tag storage units (tag storage), each tag storage unit is used to store a cache set corresponding to a page granularity.

[0072] Cache lines in different cache groups have different page granularities. For example, multiple cache lines are divided into multiple cache groups, and the multiple cache groups have their own page granularities. For example, the larger page granularity is 64K, the medium page granularity is 16K, and the smaller page granularity is 4K.

[0073] Taking the above three page granularities as an example, the hit status judgment unit 310 compares the tags of cache lines of different page granularities with the same virtual address from the address translation request to determine the hit status of each cache line. Specifically, the hit status judgment unit 310 compares the virtual address with each cache line: if the comparison result matches and the cache entry is ready, the comparison result of the cache line is a valid hit; if the comparison result does not match, the comparison result of the cache line is a miss; if the comparison result matches and the cache entry is not ready, the comparison result of the cache line is an invalid hit. Then, the hit status judgment unit 310 sends the hit status of each cache line to the hit status management unit 320.

[0074] Furthermore, the hit state management unit 320 merges multiple hit states according to a preset merging rule to obtain a merged hit state. For example, the preset merging rule indicates that the priority of a valid hit is higher than that of a miss, and the priority of a miss is higher than that of an invalid hit.

[0075] Specifically, if there is a valid hit in multiple hit states, the merged hit state indicates that the valid hit is prioritized, that is, according to the behavior of the software to allocate the page table, there is no situation where multiple cache lines are valid hits. If one of the three hit states is a valid hit, the merged hit state is a valid hit, and then the hit response enters the MSHR to wait for the cache table entry to be read. In addition, the cache line management unit 350 deletes the remaining cache lines other than the cache lines whose hit states are valid hits in the multiple cache lines, thereby improving the utilization of the cache lines. More specifically, if there is a valid hit (i.e., hit) in the cache line, the hit response will enter the hit status management unit 330 such as the miss status register (MSHR), activate the index entry corresponding to the virtual address, and the MSHR reads the cache table entry corresponding to the index entry from the table entry cache unit 340 such as the data storage unit, uses the cache page to translate the virtual address into a physical address, and returns the physical address to the upstream device of the TLB (e.g., the CPU or other cache levels) 20.

[0076] In addition, if there is a miss in multiple hit states and there is no valid hit, the merged hit state indicates miss priority. That is, if one of the three hit states is a miss, the merged hit state indicates miss priority, and the request for the cache entry is sent to the downstream device. Without loss of generality, if the merged hit state indicates miss priority, the backfill address entry corresponding to the virtual address is read as the cache entry according to the page granularity of the cache group whose hit state is a miss. More specifically, if there is a cache line that misses, the hit state management unit 330 creates a cache line, for example, creates a tag for the cache line in the cache line management unit 350, generates an index entry for the cache line corresponding to the virtual address in the MSHR, and obtains the cache entry corresponding to the virtual address through the page table finder (Page Table Walker, PTW) 30 into the data storage unit (data storage) 340, and associates the cache entry with the created cache line, and generates a response to the address translation request. For example, the response to the address translation request is returned to the upstream device.

[0077] In addition, if the multiple hit states are all invalid hits, the merged hit state indicates that invalid hits take precedence. That is, if the three hit states are all invalid hits (hit on miss), the merged hit state indicates that invalid hits take precedence, indicating that the cache line management unit 350 has created a tag for the cache line, and then puts the merged hit state into the MSHR, creates an index entry for the cache line and waits for a hit response. Without loss of generality, if the merged hit state indicates that invalid hits take precedence, when the cache entry is read, the cache line corresponding to the cache entry is changed from an invalid hit to a valid hit. For example, the cache entry in the data storage unit 340 can be associated with the created cache line (including the tag and index entry of the cache line). It should be understood that reading the cache entry indicates that the virtual address of the miss of other address translation requests and the virtual address of the invalid hit are in the virtual address mapping range of the same cache line, and the cache line response to the virtual address of the miss is created. At this time, there is no cache entry corresponding to the virtual address of the invalid hit in the data storage unit 340.

[0078] More specifically, if there is a cache line with an invalid hit (hit on miss), the hit status management unit 330 waits for the downstream device 30 to obtain the cache entry and triggers a hit response, then searches the cache entry to obtain the physical address corresponding to the virtual address into the data storage unit 340, and returns the physical address to the upstream device 20 of the TLB.

[0079] In addition, if the merge hit status indicates that invalid hits take priority, when the cache entry is not read, the cache line corresponding to the cache entry is changed from invalid hit to miss. For example, the created cache line is deleted. It should be understood that the failure to read the cache entry indicates that the virtual address of the miss with other address translation requests and the virtual address of the invalid hit are in the virtual address mapping range of the same cache line, and the cache line is created in response to the virtual address of the miss. In some examples, the created cache line is subsequently deleted (i.e., recycled) due to a low hit rate or inconsistency between the page granularity and the granularity of the cache line of the valid hit, and the cache line is changed from an invalid hit to a miss.

[0080] The following will be combined Figure 5 The address translation cache methods according to other embodiments of the present invention are described. Figure 5 The address translation cache methods include:

[0081] S510: Determine multiple hit states of the virtual address in the address translation request for multiple cache lines, the multiple cache lines have different page granularities by being divided into multiple cache groups respectively, and the hit state of each cache line indicates whether the cache line is a valid hit, an invalid hit or a miss.

[0082] S520: Merge multiple hit states to obtain a merged hit state.

[0083] S530: If the merge hit status indicates that valid hit is prioritized, the backfill address table entry of the cache line whose hit status is valid hit is determined as the cache table entry of the virtual address.

[0084] In the solution of the embodiment of the present invention, multiple cache lines are divided into multiple cache groups with different page granularities, thereby improving the hit rate of the cache lines. In addition, when the combined hit state obtained by combining multiple hit states indicates that valid hits are prioritized, a cache line with a hit state of valid hits can be selected from multiple cache lines, and then the backfill address table entry of the cache line is determined as a cache table entry of the virtual address, thereby improving the utilization of the cache space, thereby taking into account both the hit rate of the cache line and the utilization of the cache space as a whole.

[0085] In some other embodiments, the address translation cache method further includes: deleting the remaining cache lines except the cache lines whose hit status is a valid hit among the plurality of cache lines.

[0086] In some other embodiments, the address translation cache method further includes: if there is a valid hit in the multiple hit states, the merged hit state indicates that the valid hit is prioritized. More specifically, if there is a cache line with a valid hit (i.e., hit), the hit response will enter a hit state management unit 330 such as a miss status register (MSHR), activate the index entry corresponding to the virtual address, and the MSHR reads the cache entry corresponding to the index entry from an entry cache unit 340 such as a data storage unit, uses a cache page to translate the virtual address into a physical address, and returns the physical address to the upstream device (e.g., CPU or other cache level) 20 of the TLB.

[0087] In some other embodiments, the address translation cache method further includes: if there is a miss in the multiple hit states and there is no valid hit, the merged hit state indicates that the miss is prioritized, and according to the page granularity of the cache group whose hit state is a miss, the backfill address table entry corresponding to the virtual address is read as a cache table entry. More specifically, if there is a cache line that misses, the hit state management unit 330 generates an index entry corresponding to the virtual address, and obtains the cache table entry corresponding to the virtual address into the data storage unit (data storage) 340 through the page table walker (PTW) 30, and associates the cache table entry with the index entry.

[0088] In some other embodiments, the address translation cache method further includes: if the multiple hit states are all invalid hits, the merged hit state indicates that the invalid hit takes priority, and when the cache entry is read, the cache line corresponding to the cache entry is changed from invalid hit to valid hit, and when the cache entry is not read, the cache line corresponding to the cache entry is changed from invalid hit to miss. More specifically, if there is an invalid hit (hit on miss) cache line, the hit state management unit 330 waits for the downstream device 30 to obtain the cache entry and trigger a hit response, then searches the cache entry to obtain the physical address corresponding to the virtual address, and returns the physical address to the upstream device 20 of the TLB.

[0089] It should be understood that the specific implementation of each step of the address translation cache method can refer to the corresponding description of each unit in the translation cache, and has corresponding beneficial effects, which will not be repeated here. A person skilled in the art can clearly understand that for the convenience and simplicity of description, each step of the address translation cache method can refer to the corresponding process description of each unit in the aforementioned translation cache, which will not be repeated here.

[0090] Reference Figure 6 , shows a schematic diagram of the structure of a translation buffer according to another embodiment of the present invention. The specific embodiment of the present invention does not limit the specific implementation of the translation buffer.

[0091] like Figure 6 As shown, the translation buffer may include: a processing unit (processor) 602 for executing a program 610 , a communication interface (Communications Interface) 604 , a storage unit (memory) 606 , and a communication bus 608 .

[0092] The processing unit, the communication interface, and the storage unit communicate with each other via a communication bus.

[0093] Communication interface, used to communicate with upstream or downstream devices.

[0094] The processing unit is used to execute the program, and specifically can execute the relevant steps in the above method embodiment.

[0095] Specifically, the program may include program codes including computer operation instructions.

[0096] The processing unit may be a CPU, or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0097] A storage unit used to store programs. The storage unit may include high-speed RAM, such as SRAM.

[0098] The program may include multiple computer instructions. Specifically, the program may enable the processing unit to execute the address translation cache method described in any one of the aforementioned method embodiments through the multiple computer instructions.

[0099] The specific implementation of each step in the program can refer to the corresponding description of the corresponding steps, modules or units in the above method embodiments, and has corresponding beneficial effects, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described device, equipment or module can refer to the corresponding process description in the above method embodiments, which will not be repeated here.

[0100] The embodiment of the present invention further provides a computer storage medium on which a computer program is stored, and when the program is executed by a processing unit, the method described in any of the above-mentioned multiple method embodiments is implemented. The computer storage medium includes, but is not limited to: a compact disc read-only memory (CD-ROM), a random access memory (RAM), a floppy disk, a hard disk or a magneto-optical disk, etc.

[0101] An embodiment of the present invention further provides a computer program product, including computer instructions, which instruct a computing device to execute the address translation cache method in the above-mentioned multiple method embodiments.

[0102] In addition, it should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used to train the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant regulations and standards, and corresponding operation entrances are provided for users to choose to authorize or refuse.

[0103] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present invention can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0104] The above-mentioned method according to the embodiment of the present invention can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as a computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and to be stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor or programmable or dedicated hardware (such as an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA)). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., a random access memory (RAM), a read-only memory (ROM), a flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method shown here, the execution of the code converts the general-purpose computer into a dedicated computer for executing the method shown here.

[0105] Those of ordinary skill in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present invention.

[0106] The above implementation methods are only used to illustrate the embodiments of the present invention, and are not limitations of the embodiments of the present invention. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of the present invention. The patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. An address translation cache method, comprising: Determine multiple hit states of a virtual address in an address translation request for multiple cache lines, wherein the multiple cache lines have different page granularities by being respectively divided into multiple cache groups, and the hit state of each cache line indicates whether the cache line is in a valid hit, an invalid hit, or a miss; Merging the multiple hit states to obtain a merged hit state; If the merged hit status indicates that valid hits are prioritized, the backfill address table entry of the cache line whose hit status is valid hit is determined as the cache table entry of the virtual address.

2. The address translation cache method according to claim 1, wherein: The method further comprises: The remaining cache lines except the cache lines whose hit status is a valid hit among the multiple cache lines are deleted.

3. The address translation cache method according to claim 1, wherein: Merging the multiple hit states to obtain a merged hit state includes: If there is a valid hit among the multiple hit states, the multiple hit states are merged into a merged hit state indicating that the valid hit is prioritized.

4. The address translation cache method according to claim 1, wherein: The method further comprises: If the merged hit status indicates miss priority, then according to the page granularity of the cache group whose hit status is miss, a backfill address table entry corresponding to the virtual address is read, and the backfill address table entry is determined as a cache table entry.

5. The address translation cache method according to claim 4, wherein: Merging the multiple hit states to obtain a merged hit state includes: If there is a miss and no valid hit in the multiple hit states, the multiple hit states are merged into a merged hit state indicating miss priority.

6. The address translation cache method according to claim 4, wherein: The method further comprises: The cache entry is associated with the created cache line, and a response to the address translation request is generated.

7. The address translation cache method according to claim 1, wherein: The method further comprises: If the merged hit status indicates that invalid hits are prioritized, then when a cache entry is read, the cache line corresponding to the cache entry is changed from invalid hit to valid hit, and when the cache entry is not read, the cache line corresponding to the cache entry is changed from invalid hit to miss.

8. The address translation cache method according to claim 7, wherein: Merging the multiple hit states to obtain a merged hit state includes: If the multiple hit states are all invalid hits, the multiple hit states are merged into a merged hit state indicating that invalid hits are prioritized.

9. A translation buffer, comprising: A hit status judgment unit, which determines multiple hit statuses of a virtual address in an address translation request for multiple cache lines, wherein the multiple cache lines have different page granularities by being respectively divided into multiple cache groups, and the hit status of each cache line indicates whether the cache line is in a valid hit, an invalid hit, or a miss; A hit status management unit, which merges the multiple hit statuses to obtain a merged hit status; The entry cache unit determines the backfill address entry of the cache line whose hit status is a valid hit as the cache entry of the virtual address if the merge hit status indicates that the valid hit is prioritized.

10. A processor, comprising: A translation buffer as claimed in claim 9.

11. A translation buffer, comprising: A processing unit, a storage unit, a communication interface and a communication bus, wherein the processing unit, the storage unit and the communication interface communicate with each other via the communication bus; The storage unit is used to store at least one executable instruction, and the executable instruction enables the processing unit to execute the method according to any one of claims 1-8.

12. A computer storage medium having a computer program stored thereon, wherein the program, when executed by a processing unit, implements the method according to any one of claims 1 to 8.

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