Tree-shaped nanosheet complementary field effect transistor

Abstract

The invention discloses a tree-shaped nanosheet complementary field effect transistor which comprises a tree-shaped channel formed by a silicon nanosheet and a germanium-silicon fin-shaped inter-bridge channel, a gate oxide wrapping the channel and composed of silicon dioxide and hafnium dioxide, a P-type work function liner only deposited outside the P-type gate oxide, a P-type power function liner deposited outside the P-type power function liner, a P-type power function liner deposited outside the P-type power function liner, and a P-type power function liner deposited outside the P-type power function liner. The dual-k side walls, the source end and the drain end are symmetrically deposited at the two ends of the channel, and N-type and P-type isolation and conduction are realized by adopting a common metal grid electrode, a source-drain metal electrode and an N / P isolation layer. The device is characterized in that the channel is composed of vertically stacked silicon nanosheets and germanium-silicon inter-bridge channels between the silicon nanosheets. Compared with a nano-sheet complementary field effect transistor (NS-CFET), a larger channel conduction area is provided under the condition that the occupied area is not increased, the conduction current is improved, and the additional process cost is relatively low. Under the same off-state leakage current, the N-type conduction current and the P-type conduction current are respectively improved by 24.20% and 43.00%, the on-off ratio is respectively improved by 23.64% and 43.32%, and the transconductance is respectively improved by 36.86% and 60.35%.

Description

Technical Field

[0001] The present invention belongs to the field of field effect transistors in semiconductor devices, and in particular relates to a tree-type nanosheet complementary field effect transistor (Tree-CFET). Background Art

[0002] With the rapid development of the integrated circuit industry, semiconductor devices are rapidly updated and iterated, from traditional planar MOSFET devices to fin field effect transistors (FinFET) and then to all-gate field effect transistors (GAAFET). GAAFET devices can adjust the device drive current by changing the number of channel stacks, and have a more flexible and adjustable channel width-to-length ratio than FinFET devices. According to the channel shape, GAAFET devices can be divided into nanowire field effect transistors (NWFET) and nanosheet field effect transistors (NSFET). By comparing NWFET with other transistor structures, it is found that vertically stacked ring-gate devices will become the best candidate device structure for process nodes below 5nm, but through layer-by-layer practical research, it is found that in actual processes, the larger width-to-length ratio of NWFET will bring great difficulties to the preparation of devices. At the same time, many researchers have chosen NSFET devices due to smaller short channel effects, better electrostatic control capabilities, smaller parasitic capacitance, flexibly adjustable channel width and higher device reliability.

[0003] As the size is further reduced, the limitations of feature size scaling have prompted technicians to explore other scaling methods, proposing device structures such as complementary field effect transistors (CFETs) and tree field effect transistors (TreeFETs). Due to the significant advantages of CFETs in area reduction, it has become a strong candidate for semiconductor device size miniaturization to break through inherent physical limits in just a few years. According to a microelectronics research center, the nanosheet complementary field effect transistor (NS-CFET), which combines the advantages of the nanosheet field effect transistor (NSFET) and CFET, may become the core device of the 1nm process node. Summary of the invention

[0004] The purpose of the present invention is to provide a tree-type nanosheet complementary field effect transistor (Tree-CFET), which combines the advantages of TreeFET and CFET, can provide additional channel conduction area without increasing the device footprint, improve the on-current, and have very little additional process cost. Under the simulation strategy of unifying the off-state leakage current benchmark, that is, unifying the off-state leakage current of NS-CFET and the present invention to 5 nA, compared with NS-CFET, the on-current of the N-type and P-type of the present invention is increased by 24.20% and 43.00%, respectively, the switch ratio is increased by 23.64% and 43.32%, respectively, and the transconductance is increased by 36.86% and 60.35%, respectively.

[0005] To achieve the above object, the present invention adopts the following technical solutions: A tree-shaped nanosheet complementary field effect transistor, characterized in that it comprises: N-type and P-type tree channels formed by silicon nanosheets and germanium silicon fin-type bridge channels; A gate oxide composed of silicon dioxide and hafnium dioxide that uniformly wraps the N-type and P-type tree channels; A P-type work function liner deposited only outside the P-type gate oxide; A common metal gate deposited outside the N-type gate oxide and the P-type work function pad; Symmetrical N-type source and drain (top), P-type source and drain (bottom) at both ends of the channel; Source and drain metal electrodes wrapping N-type and P-type source and drain terminals on three sides; In the vertical direction, an N / P isolation layer is used to insulate the source and drain of the N-type and P-type terminals; The high- k Sidewall and low- k Side walls; A substrate and a shallow trench isolation layer deposited on both sides of the substrate; The tree-shaped channel is a stack of silicon nanosheets and germanium silicon fin-type bridge channels (the impurity concentration of the tree-shaped channel is 1×10 15 cm -3 , where the proportion of germanium in germanium silicon is 30%); The gate oxide is silicon dioxide and hafnium dioxide; The P-type work function liner is titanium nitride; The common metal gate is tungsten; The N-type source and drain are heavily doped silicon (impurity concentration is 1×10 21 cm -3 ); The P-type source and drain are heavily doped germanium silicon (impurity concentration is 1×10 21 cm -3 , where the proportion of germanium in germanium silicon is 50%); The N-type and P-type source and drain metal electrodes are tungsten; The N / P isolation layer is nitride; The high- k The sidewall is made of hafnium dioxide, low- k The side walls are made of a material with a dielectric constant of 4.0; The substrate is silicon, and the shallow trench isolation layer is silicon dioxide.

[0006] The tree-shaped nanosheet complementary field effect transistor proposed in the present invention has the following advantages: Without increasing the device footprint, it is possible to provide additional channel conduction area, increase the on-current, and have very little additional process cost.

[0007] Under the simulation strategy of unifying the off-state leakage current benchmark, that is, unifying the off-state leakage current of NS-CFET and the present invention to 5 nA, compared with NS-CFET, the on-state current (I on ) were increased by 24.20% and 43.00% respectively, the switching ratio was increased by 23.64% and 43.32% respectively, and the transconductance (gm) was increased by 36.86% and 60.35% respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the three-dimensional structure of the present invention; Figure 2 is a schematic cross-sectional view of the center position of the device along the y direction of the present invention; Figure 3 It is a cross-sectional schematic diagram of the center position of the device along the z direction of the present invention; Figure 4 is a transfer characteristic curve diagram of the present invention and NS-CFET; Figure 5 It is a transconductance variation trend diagram of the present invention and NS-CFET; Figure 6 It is a preparation flow chart of the present invention. DETAILED DESCRIPTION

[0009] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0010] See also Figure 1-3 The present invention proposes a tree-type nanosheet complementary field effect transistor (Tree-CFET), whose channel consists of vertically stacked silicon nanosheets and a germanium-silicon fin-type bridge channel between the nanosheets. Figure 1 It is a schematic diagram of the three-dimensional structure of the present invention, in which the common metal gate, the N-type source metal electrode and the drain metal electrode, and the P-type source metal electrode and the drain metal electrode are made transparent so that the internal device structure can be viewed.

[0011] The tree-shaped nanosheet complementary field effect transistor comprises a tree-shaped channel composed of a silicon nanosheet 1 and a germanium silicon fin-type bridge channel 2; a gate oxide composed of silicon dioxide 3 and hafnium dioxide 4 that wraps the N-type and P-type tree-shaped channels; a P-type work function pad 5 that is deposited only outside the P-type gate oxide; a common metal gate 6 that wraps the N-type gate oxide and the P-type work function pad; an N-type source terminal 7 and a drain terminal 8, and a P-type source terminal 9 and a drain terminal 10 that are symmetrical at both ends of the channel; and a gate oxide that wraps the N-type gate oxide and the P-type work function pad. A source metal electrode 11 and a drain metal electrode 12 wrapping N-type source and drain; a source metal electrode 13 and a drain metal electrode 14 wrapping P-type source and drain on three sides; an N / P isolation layer 15 that insulates the N-type and P-type source and drain in the vertical direction; a high-k side wall 16 and a low-k side wall 17 that are in contact with the source and drain, wrap the N-type and P-type tree channels and are symmetrically distributed; a substrate 18 and a shallow trench isolation layer 19 deposited on both sides of the substrate.

[0012] The impurity concentration of the tree channel is 1×10 15 cm -3 , where the proportion of germanium in germanium silicon is 30%; The P-type work function pad 5 is titanium nitride; The common metal gate 6 is tungsten; The N-type source terminal 7 and drain terminal 8 are heavily doped silicon (impurity concentration is 1×10 21 cm -3 ); The P-type source terminal 9 and drain terminal 10 are heavily doped germanium silicon (impurity concentration is 1×10 21 cm -3 , where the proportion of germanium in germanium silicon is 50%); The N-type source metal electrode 11 and the drain metal electrode 12 are made of tungsten; The P-type source metal electrode 13 and the drain metal electrode 14 are made of tungsten; The N / P isolation layer 15 is nitride; The high- k The side wall 16 is made of hafnium dioxide, low- k The side wall 17 is made of a material with a dielectric constant of 4.0; The substrate 18 is made of silicon, and the shallow trench isolation layer 19 is made of silicon dioxide.

[0013] Figure 4The transfer characteristic curves of the present invention and NS-CFET are provided. For the upper NFET, the threshold voltages of the two are 0.131 V and 0.110 V, the on-currents are 124.7 μA and 100.4 μA, and the switch ratios are 24.94 and 20.17, respectively. For the lower PFET, the threshold voltages of the two are 0.162 V and 0.169 V, the on-currents are 73.86 μA and 51.65 μA, and the switch ratios are 14.78 and 10.31, respectively. Compared with NS-CFET, the on-currents of the NFET and PFET of the present invention are increased by 24.20% and 43.00%, respectively, and the switch ratios are increased by 23.64% and 43.32%, respectively. Figure 5 The figure is a transconductance variation trend diagram of the present invention and NS-CFET. Compared with NS-CFET, the transconductance of NFET and PFET of the present invention are increased by 36.86% and 60.35%, respectively.

[0014] See also Figure 6 , the production process of the present invention is as follows: On a clean bulk silicon (Bulk-Si) substrate 18, silicon 1 and germanium silicon 2 are epitaxially grown to form a stacked layer, silicon 1 and germanium silicon 2 "Fin" patterning is completed, and shallow trench isolation 19 is performed; Precisely and selectively etching the silicon nanosheet 1 and the germanium silicon fin bridge channel 2; Anisotropic and isotropic etching are used to prepare polysilicon dummy gates (Dummy Poly Gate), which are deposited and etched to form low- k Sidewall 17; The source and drain terminals are cut, and the lower P-type source terminal 9 and drain terminal 10, as well as the P-type source terminal metal electrode 13 and the drain terminal metal electrode 14 are prepared by chemical vapor deposition technology. Then, a dielectric is deposited to form an N / P isolation layer 15 to achieve insulation between the source and drain electrodes of the upper and lower devices, and then the upper N-type source terminal 7 and drain terminal 8, as well as the N-type source terminal metal electrode 11 and the drain terminal metal electrode 12 are prepared; The chemical mechanical polishing technology is used for planarization, the polysilicon pseudo-gate is removed by selective etching of polysilicon, and the sacrificial layer of germanium silicon is precisely and selectively etched; Using chemical vapor deposition technology to deposit silicon dioxide in the gate oxide3; Chemical vapor deposition is used to deposit the hafnium dioxide 4 in the gate oxide, as well as the dual- k The side wall is high- k Side wall 16; Using chemical vapor deposition technology, depositing a P-type work function pad 5; Using chemical vapor deposition technology to deposit a common metal gate 6; CFET adopts buried power rail (BPR) technology. Finally, the common metal gate 6, N-type source metal electrode 11 and drain metal electrode 12, P-type source metal electrode 13 and drain metal electrode 14 are led out through interconnection metal, and chemical mechanical polishing technology is used to flatten all electrodes.

Claims

1. A tree-shaped nanosheet complementary field effect transistor, characterized in that: The transistor comprises: N-type and P-type tree channels formed by silicon nanosheets (1) and germanium silicon fin-type bridge channels (2); A gate oxide composed of silicon dioxide (3) and hafnium dioxide (4) uniformly encapsulating the N-type and P-type tree channels; A P-type work function liner (5) deposited only outside the P-type gate oxide; A common metal gate (6) deposited outside the N-type gate oxide and the P-type work function pad; An N-type source terminal (7) and a drain terminal (8), and a P-type source terminal (9) and a drain terminal (10) symmetrically disposed at both ends of the channel; A source-end metal electrode (11) and a drain-end metal electrode (12) that wrap the N-type source and drain on three sides; A source-end metal electrode (13) and a drain-end metal electrode (14) that wrap the P-type source and drain on three sides; In the vertical direction, an N / P isolation layer (15) is used to insulate the source and drain terminals of the N-type and P-type; The high- k Sidewall (16) and low- k Sidewall (17); A substrate (18) and a shallow trench isolation layer (19) deposited on both sides of the substrate.

2. The tree-shaped nanosheet complementary field effect transistor according to claim 1, characterized in that: The P-type work function pad (5) is titanium nitride; The common metal gate (6) is tungsten; The N-type source terminal (7) and drain terminal (8) are heavily doped silicon; The P-type source terminal (9) and drain terminal (10) are heavily doped germanium silicon; The N-type source metal electrode (11) and the drain metal electrode (12) are tungsten; The P-type source metal electrode (13) and the drain metal electrode (14) are tungsten; The N / P isolation layer (15) is nitride; The high- k The side wall (16) is made of hafnium dioxide; The low- k The side wall (17) is made of a material with a dielectric constant of 4.0; The substrate (18) is silicon, and the shallow trench isolation layer (19) is silicon dioxide.

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