Test method and platform for chip and electronic equipment

Abstract

The invention relates to the technical field of chips, and discloses a test method and platform for a chip and electronic equipment. The test method comprises the following steps: generating an index data structure taking an instruction address as an index according to a pre-compiled test case; obtaining an accurate program counter signal in the process of executing the test case by the chip to be tested; according to the index data structure and the precise program counter signal, generating an actual instruction stream in the process of executing the test case by the chip to be tested; and testing the to-be-tested chip according to the actual instruction stream. The simulation test process of the chip can be simplified, the simulation test efficiency of the chip is improved, and the simulation test cost of the chip is reduced.

Description

Technical Field

[0001] The present application relates to the field of chip technology, for example, to a testing method, platform and electronic device for a chip. Background Art

[0002] Microcontroller Unit (MCU), also known as single-chip microcomputer, is a microcomputer integrated on a circuit chip, which is widely used in various electronic devices, such as automobiles, home appliances, communication equipment, etc. In the design and production process of MCU, comprehensive testing and verification work is required to ensure that its performance is stable and reliable and meets the actual application requirements.

[0003] At present, in the process of MCU development, software simulation test methods are mostly used to test and verify MCU. Specifically, computer software is used to simulate the operating environment of MCU and its peripherals, and the log tools provided by external IP (Intellectual Property) manufacturers are integrated into the operating environment to build a test platform, execute predefined test cases, capture signal waveforms and output log information. Technicians use the captured signal waveforms and generated log information to conduct comprehensive testing and evaluation of the functions, performance, reliability and other aspects of the MCU.

[0004] In the process of implementing the above embodiments, it is found that there are at least the following problems in the related technology: (1) Waveform analysis generates a large amount of data, resulting in a large loss of time and simulation hardware resources in generating dump waveform files; (2) It is highly dependent on third-party tools (log tools), which are often only applicable to specific scenarios or stages. Based on the above problems, the simulation test process of MCU is complicated and costly.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical elements or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0007] The embodiments of the present disclosure provide a test method, platform and electronic device for a chip, which can simplify the simulation test process of the chip, improve the simulation test efficiency of the chip, and reduce the simulation test cost of the chip.

[0008] In some embodiments, a testing method for a chip is provided, including: generating an index data structure indexed by instruction addresses based on pre-written test cases; obtaining a precise program counter signal during the execution of the test case by the chip to be tested; generating an actual instruction stream during the execution of the test case by the chip to be tested based on the index data structure and the precise program counter signal; and testing the chip to be tested based on the actual instruction stream.

[0009] Optionally, obtaining an accurate program counter signal during the execution of a test case by the chip to be tested includes: obtaining a key signal of the chip to be tested during the execution of the test case in response to a simulation instruction; tracing a flow path of the simulation instruction and extracting an initial program counter signal from the key signal; and obtaining an accurate program counter signal based on the initial program counter signal.

[0010] Optionally, key signals of the chip to be tested during the execution of test cases are obtained in the following manner: keywords represented by each communication signal of the chip to be tested during the execution of test cases are obtained; a global search is performed in the code library of the chip to be tested based on the keywords to obtain and save the complete path of each communication signal; and the saved communication signal is sampled using the clock edge to obtain key signals.

[0011] Optionally, the chip to be tested includes a sequential processor or an out-of-order processor; in the case where the chip to be tested includes a sequential processor, tracing the flow path of the simulation instructions and extracting the initial program counter signal from the key signal includes: tracing the flow path of the simulation instructions and extracting the initial program counter signal from the key signal in the execution unit; or, in the case where the chip to be tested includes an out-of-order processor, tracing the flow path of the simulation instructions and extracting the initial program counter signal from the key signal includes: tracing the flow path of the simulation instructions and extracting the initial program counter signal from the key signal in the retirement unit.

[0012] Optionally, the key signal includes a branch valid signal; obtaining an accurate program counter signal according to the initial program counter signal includes: correcting the branch valid signal; performing a logical operation on the corrected branch valid signal and the initial program counter signal to obtain an accurate program counter signal.

[0013] Optionally, the branch valid signal is corrected in the following manner: multiple branch instruction execution flows containing different timing errors are obtained; a target branch instruction execution flow that matches the benchmark instruction execution flow is determined from the multiple branch instruction execution flows; and the branch valid signal is corrected according to the timing error corresponding to the target branch instruction execution flow.

[0014] Optionally, an index data structure indexed by instruction addresses is generated based on pre-written test cases, including: disassembling the pre-written test cases to obtain instruction addresses, instruction codes and corresponding assembly statements in the test cases; using instruction addresses as indexes, saving instruction codes and corresponding assembly statements to obtain an index data structure.

[0015] Optionally, the chip to be tested is tested according to the actual instruction stream, including: obtaining the number of executions and execution time of each instruction in the actual instruction stream; obtaining the average execution time of each instruction based on the number of executions and the execution time; comparing the average execution time of each instruction with the expected execution time corresponding to each instruction, and testing the chip to be tested.

[0016] In some embodiments, a test platform for a chip is provided, including: a monitoring module, configured to generate an index data structure indexed by instruction addresses based on pre-written test cases; an analysis module, configured to obtain precise program counter signals during the execution of test cases by the chip to be tested; a generation module, configured to generate actual instruction streams during the execution of test cases by the chip to be tested based on the index data structure and the precise program counter signals; and a test module, configured to test the chip to be tested based on the actual instruction stream.

[0017] In some embodiments, an electronic device is provided, comprising: a processor; and a memory storing program instructions, wherein the processor is configured to execute the chip testing method as described in the above embodiments when running the program instructions.

[0018] The chip testing method, platform, and electronic device provided by the embodiments of the present disclosure can achieve the following technical effects: The test method for a chip provided by the embodiment of the present disclosure has test cases written in advance according to the functional specifications and design requirements of the chip to be tested. According to the written test cases, an index data structure with instruction addresses as indexes can be generated to quickly access the instruction information corresponding to each instruction address without traversing the entire program space, thereby improving the efficiency and accuracy of subsequent instruction stream acquisition. The program counter, as a register inside the CPU, stores the memory address of the instruction currently being executed. Whenever the CPU executes an instruction, the value of the program counter is automatically updated to the address of the next instruction to ensure that the program can be executed sequentially. By obtaining an accurate program counter signal, the instruction currently being executed by the CPU can be accurately obtained, and then the currently executed instruction information is obtained in combination with the index data structure, and it is output as an instruction stream to generate an actual instruction stream, and then the test of the chip to be tested is implemented according to the actual instruction stream.

[0019] The embodiment of the present disclosure performs simulation testing of the chip to be tested based on the actual instruction stream. The actual instruction stream can directly reflect the real state of the chip to be tested during the execution process, so as to accurately discover potential problems and defects and locate the problem. Compared with the related art, it avoids the generation of dump waveform files and the use of third-party tools to generate a large amount of log information for chip simulation testing, simplifies the simulation test process, reduces the test preparation time and the loss of simulation hardware resources, and reduces the simulation test cost by no longer relying on third-party tools. In addition, the test method provided by the embodiment of the present disclosure can be applied to various complex test scenarios, including multi-core processors, parallel processing units, etc. After the chip to be tested is replaced, there is no need to re-modify the test environment according to the method provided by the external IP manufacturer, and it has higher universal applicability and ease of use.

[0020] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein: Figure 1 is a schematic diagram of an electronic device provided by an embodiment of the present disclosure; Figure 2 is a schematic diagram of a chip testing method provided by an embodiment of the present disclosure; Figure 3 is a schematic diagram of a chip testing method provided by another embodiment of the present disclosure; Figure 4 is a schematic diagram of a chip testing method provided by another embodiment of the present disclosure; Figure 5 is a schematic diagram of a chip testing method provided by another embodiment of the present disclosure; Figure 6 is a schematic diagram of a chip testing platform provided by an embodiment of the present disclosure; Figure 7 It is a schematic diagram of a chip testing device provided by an embodiment of the present disclosure.

[0022] Reference numerals: 1 electronic device; 10 device body; 60 a test platform for a chip; 610 a monitoring module; 620 an analysis module; 630 a generation module; 640 a test module; 70 is a test device for a chip; 700 is a processor; 701 is a memory; 702 is a communication interface; 703 is a bus. DETAILED DESCRIPTION

[0023] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0024] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0025] Unless otherwise stated, the term "plurality" means two or more.

[0026] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0027] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A, B, A and B.

[0028] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0029] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0030] A microcontroller (MCU) is an integrated circuit that integrates multiple functional modules such as a processor core, memory, input / output interface, and timer. It not only includes a CPU (Central Processing Unit), but also integrates many peripherals and interfaces, and can independently implement the functions of various embedded systems.

[0031] The program counter (PC) is a key register in the CPU. It is mainly used to store the address of the unit where the next instruction is located. When the CPU executes an instruction, it first reads the address of the instruction from the program counter, then fetches the instruction corresponding to the address from the memory and sends it to the instruction register for decoding and execution. After execution, the program counter will automatically update to point to the address of the next instruction, thereby realizing the sequential execution of the program.

[0032] A test case is a description of a test task for a specific software or hardware product, including information such as test objectives, test environment, input data, test steps, expected results, etc. During chip testing, test cases are used to define specific test scenarios and conditions.

[0033] Combination Figure 1 As shown, the embodiment of the present disclosure provides an electronic device 1, comprising: a device body 10 and a chip testing device 70. The chip testing device is installed in the device body 10.

[0034] In the embodiment of the present disclosure, the chip test device 70 is installed in the device body 10. The installation relationship described here is not limited to being placed inside the device body 10, but also includes installation connections with other components of the electronic device 1, including but not limited to physical connection, electrical connection or signal transmission connection, etc. It can be understood by those skilled in the art that the chip test device 70 can be adapted to a feasible electronic device 1, thereby realizing other feasible embodiments.

[0035] Optionally, combined Figure 7 As shown, the test device 70 for a chip includes a processor 700. The processor 700 can generate an index data structure with instruction addresses as indexes according to a pre-written test case; can obtain an accurate program counter signal during the process of the chip to be tested executing the test case; can generate an actual instruction stream during the process of the chip to be tested executing the test case according to the index data structure and the accurate program counter signal; and can test the chip to be tested according to the actual instruction stream.

[0036] Combination Figure 1 and Figure 7 The electronic device shown in the figure, the embodiment of the present disclosure provides a testing method for a chip, such as Figure 2 As shown, the test methods include: S201, the processor generates an index data structure with instruction addresses as indexes according to a pre-written test case.

[0037] S202, the processor obtains an accurate program counter signal during the process of the chip to be tested executing the test case.

[0038] In this embodiment, the chip to be tested includes an MCU to be tested.

[0039] S203, the processor generates an actual instruction stream during the execution of the test case by the chip to be tested according to the index data structure and the precise program counter signal.

[0040] S204: The processor tests the chip to be tested according to the actual instruction stream.

[0041] The test method for a chip provided by the embodiment of the present disclosure has test cases written in advance according to the functional specifications and design requirements of the chip to be tested. According to the written test cases, an index data structure with instruction addresses as indexes can be generated to quickly access the instruction information corresponding to each instruction address without traversing the entire program space, thereby improving the efficiency and accuracy of subsequent instruction stream acquisition. The program counter, as a register inside the CPU, stores the memory address of the instruction currently being executed. Whenever the CPU executes an instruction, the value of the program counter is automatically updated to the address of the next instruction to ensure that the program can be executed sequentially. By obtaining an accurate program counter signal, the instruction currently being executed by the CPU can be accurately obtained, and then the currently executed instruction information is obtained in combination with the index data structure, and it is output as an instruction stream to generate an actual instruction stream, and then the test of the chip to be tested is implemented according to the actual instruction stream.

[0042] The embodiment of the present disclosure performs simulation testing of the chip to be tested based on the actual instruction stream. The actual instruction stream can directly reflect the real state of the chip to be tested during the execution process, so as to accurately discover potential problems and defects and locate the problem. Compared with the related art, it avoids the generation of dump waveform files and the use of third-party tools to generate a large amount of log information for chip simulation testing, simplifies the simulation test process, reduces the test preparation time and the loss of simulation hardware resources, and reduces the simulation test cost by no longer relying on third-party tools. In addition, the test method provided by the embodiment of the present disclosure can be applied to various complex test scenarios, including multi-core processors, parallel processing units, etc. After the chip to be tested is replaced, there is no need to re-modify the test environment according to the method provided by the external IP manufacturer, and it has higher universal applicability and ease of use.

[0043] Combination Figure 3 As shown, the embodiment of the present disclosure provides another testing method for a chip, comprising: S301, the processor disassembles the pre-written test case to obtain the instruction address, instruction code and corresponding assembly statement in the test case.

[0044] In this embodiment, the corresponding assembly statement refers to an assembly statement obtained by presenting the meaning of the instruction in the form of an assembly statement.

[0045] S302, the processor uses the instruction address as an index, saves the instruction code and the corresponding assembly statement, and obtains an index data structure.

[0046] S303, the processor obtains the precise program counter signal during the process of the chip to be tested executing the test case.

[0047] S304, the processor generates an actual instruction stream during the execution of the test case by the chip to be tested according to the index data structure and the precise program counter signal.

[0048] S305: The processor tests the chip to be tested according to the actual instruction stream.

[0049] In the test method for chips provided by the embodiment of the present disclosure, the test case can be disassembled by static analysis, such as using the open source objdump tool, to obtain the instruction address, instruction code and corresponding assembly statement therein, and generate a disassembly file. The test case is disassembled by static analysis to understand the execution process of the test case and reveal how the test case is executed at the bottom layer. The disassembly file is then read, and the instruction code and the corresponding assembly statement are saved in the form of an index with the instruction address as the index, and an index data structure is obtained to quickly find the instruction information at any given address later, thereby reducing the test preparation time and improving the efficiency of the simulation test. In addition, since the index data structure is constructed based on the parsed test case, the index data structure includes every instruction that needs to be executed by the chip to be tested, so that the actual instruction stream generated according to the index data structure and the precise program counter signal can cover the entire execution process of the chip to be tested.

[0050] Combination Figure 4 As shown, the embodiment of the present disclosure provides another testing method for a chip, comprising: S401, the processor generates an index data structure with instruction addresses as indexes according to a pre-written test case.

[0051] S402: The processor obtains key signals of the chip to be tested during the execution of the test case in response to the simulation instruction.

[0052] In this embodiment, the key signal may be all the signals generated by each component or module of the chip to be tested during the execution of the test case; or it may be the signal generated by a specific component or module preset by the technician. Among them, the key signal includes the program counter signal. Exemplarily, the key signal also includes the internal general register, special register, peripheral status and the signal on the storage access bus, etc.

[0053] Optionally, key signals of the chip to be tested during the execution of test cases are obtained in the following manner: keywords represented by each communication signal of the chip to be tested during the execution of test cases are obtained; a global search is performed in the code library of the chip to be tested based on the keywords to obtain and save the complete path of each communication signal; and the saved communication signal is sampled using the clock edge to obtain key signals.

[0054] Signals such as the chip's program counter, internal general registers, special registers, peripheral status, and storage access bus are often distributed in different levels and modules of the chip. The disclosed embodiment can perform a global search in the code library of the chip to be tested (such as source code, header files, register definition files, etc.) according to the keywords represented by each communication signal to obtain the complete path of each communication signal. The complete path corresponding to each communication signal describes the entire process from the generation to the use of each communication signal. The complete path of each communication signal can clarify the hierarchical path of each communication signal and the specific location and source of each signal.

[0055] Among them, the redevelopment and design of chips are often based on the original chips. For chips of the same type, they usually have the same components or modules, such as program counters, internal general registers, etc. The keywords corresponding to each component or module can be pre-edited, such as alm (interrupt alarm signal), addr (address signal), data (data signal), etc., and saved. During the test of the new chip to be tested, the code of the new chip to be tested is read to obtain the components or modules it includes, so as to automatically determine the keywords represented by each communication signal (component or module) of the chip to be tested during the execution of the test case, so as to further improve the simulation test efficiency and automation of the chip to be tested.

[0056] After obtaining the complete path of each communication signal, it can be saved in a data structure (such as a hash table or an associative array) so that each signal can be quickly located later. The clock edge (such as the rising edge or the falling edge) is the key moment of the signal state change. By sampling the saved communication signal using the clock edge, the accurate value or state change of the signal can be captured. At the same time, unnecessary signal sampling is avoided, further reducing the test time and improving the test efficiency.

[0057] In this embodiment, the complete path of each communication signal, that is, the hierarchical path, is first located to clarify the specific position and source of each signal, and then the signal is captured using the clock edge, thereby improving the efficiency, accuracy and reliability of signal capture.

[0058] S403, the processor traces the flow path of the simulation instruction and extracts the initial program counter signal from the key signal.

[0059] Optionally, the chip to be tested includes a sequential processor or an out-of-order processor. For different types of processors, the control logic for extracting the initial program counter signal is different.

[0060] In some embodiments, when the chip to be tested includes a sequential processor, the flow path of the simulation instructions is traced and the initial program counter signal is extracted from the key signal, including: tracing the flow path of the simulation instructions and extracting the initial program counter signal from the key signal in the execution unit.

[0061] In this embodiment, the processor of the chip to be tested is a sequential processor. In a sequential processor, instructions are executed in sequence according to the order of the program counter. The execution path of the instruction usually starts from the instruction cache (I-Cache), passes through the instruction decoder to the execution unit (such as the arithmetic logic unit ALU or floating point unit, etc.), and finally updates the program counter to point to the next instruction. Therefore, for a sequential processor, the initial program counter signal can be extracted from the key signal in the execution unit by parsing the driving logic of the instruction data.

[0062] In some embodiments, when the chip to be tested includes an out-of-order processor, the flow path of the simulation instructions is tracked and the initial program counter signal is extracted from the key signal, including: tracking the flow path of the simulation instructions and extracting the initial program counter signal from the key signal in the retirement unit.

[0063] In this embodiment, the processor of the chip to be tested is an out-of-order processor. The out-of-order processor adopts a complex instruction scheduling and execution strategy. The execution order of instructions in the execution stage is often out of order, but in the submission stage, it will be reconfirmed and submitted in sequence according to the order of the program counter in the retirement unit. Therefore, for the out-of-order processor, the initial program counter signal can be extracted from the key signal in the retirement unit by parsing the driving logic of the submission result.

[0064] S404, the processor obtains an accurate program counter signal according to the initial program counter signal.

[0065] Optionally, the key signal includes a branch valid signal; obtaining an accurate program counter signal according to the initial program counter signal includes: correcting the branch valid signal; performing a logical operation on the corrected branch valid signal and the initial program counter signal to obtain an accurate program counter signal.

[0066] MCUs usually have a branch prediction function to improve performance. When a branch prediction error occurs, the processor of the MCU needs to roll back the execution state, that is, a rollback phenomenon occurs, which affects the PC signal. In this embodiment, by finding a signal to determine whether the branch is valid from the captured key signal, extracting the branch valid signal, and ignoring the branch error signal, the invalid PC signal caused by the branch prediction error is filtered out. Furthermore, there may be a timing difference between the branch valid signal and the PC signal, so it is necessary to correct the branch valid signal and perform timing debugging to ensure that the branch valid signal and the PC signal are synchronized. Then, the corrected branch valid signal is logically operated (such as logical AND) with the initial PC signal to obtain an accurate program counter signal.

[0067] Optionally, the branch valid signal is corrected in the following manner: multiple branch instruction execution flows containing different timing errors are obtained; a target branch instruction execution flow that matches the benchmark instruction execution flow is determined from the multiple branch instruction execution flows; and the branch valid signal is corrected according to the timing error corresponding to the target branch instruction execution flow.

[0068] In this embodiment, the branch instruction execution flow refers to the instruction flow corresponding to the MCU executing the branch prediction function and the branch prediction is valid. It can be started from the timing error of 0 and incremented in sequence, and the branch instruction execution flow corresponding to the branch valid signal under each timing error condition can be traversed to obtain multiple branch instruction execution flows containing different timing errors. The benchmark instruction execution flow is an idealized or known correct instruction execution flow, which represents the execution order and results of the instructions in the branch prediction function without timing errors or other interference factors. By comparing multiple branch instruction execution flows with the benchmark instruction execution flow respectively, the branch instruction execution flow that matches the benchmark instruction execution flow (timing consistency) is determined as the target branch instruction execution flow to determine the correct timing difference, that is, the timing error corresponding to the target branch instruction execution flow. Then, according to the timing error corresponding to the target branch instruction execution flow, the branch valid signal is moved forward or backward to achieve the correction of the branch valid signal.

[0069] S405, the processor generates an actual instruction stream during the execution of the test case by the chip to be tested according to the index data structure and the precise program counter signal.

[0070] The instruction stream refers to the flow of information involved in the operation process, especially the data flow related to the execution of instructions. The instruction stream usually includes: instruction address, instruction content, instruction sequence, timing information and the like. In this embodiment, the index data structure includes the instruction address, instruction code and corresponding assembly statement. After each instruction is executed, the precise program counter signal is automatically updated to the address of the next instruction. Based on the current value (instruction address) of the precise program counter signal, the instruction information (instruction code and corresponding assembly statement) corresponding to the instruction address is obtained from the index data structure in real time, and the update time of each precise program counter signal is recorded as the timing information of the instruction stream, that is, the actual instruction stream in the process of executing the test case of the chip to be tested is generated.

[0071] S406: The processor tests the chip to be tested according to the actual instruction stream.

[0072] The test method for a chip provided by the embodiment of the present disclosure can start the chip to be tested and load the test case in response to the obtained simulation instruction, while capturing the key signals inside the chip to be tested. Then, the flow path of the simulation instruction inside the chip to be tested is tracked so as to understand the execution order and dependency of the instruction. During the tracing process, the initial program counter signal is extracted from the key signal to focus on how the instruction affects the value of the program counter (PC is a key register that controls the execution order of instructions). Since most current chips are integrated with complex execution technologies (such as multiple launches, branch prediction, out-of-order execution, etc.), the initial program counter signal extracted based on the captured key signal is mostly an inaccurate program counter signal. Therefore, based on the initial program counter signal, a precise program counter signal is further obtained to reflect the true state of the chip to be tested when executing the test case, thereby improving the accuracy of subsequent analysis and evaluation.

[0073] Combination Figure 5 As shown, the embodiment of the present disclosure provides another testing method for a chip, comprising: S501, the processor generates an index data structure with instruction addresses as indexes according to a pre-written test case.

[0074] S502, the processor obtains an accurate program counter signal during the process of the chip to be tested executing the test case.

[0075] S503, the processor generates an actual instruction stream in the process of executing the test case in the chip to be tested according to the index data structure and the precise program counter signal.

[0076] S504: The processor obtains the execution count and execution duration of each instruction in the actual instruction stream.

[0077] S505: The processor obtains an average execution time of each instruction according to the number of executions and the execution time.

[0078] S506: The processor compares the average execution time of each instruction with the expected execution time corresponding to each instruction, and tests the chip to be tested.

[0079] By using the chip testing method provided by the embodiment of the present disclosure, it is possible to obtain the number of executions and execution time of each instruction in the actual instruction stream, and calculate the average execution time of each instruction to eliminate deviations caused by individual execution differences and provide more stable performance indicators. The expected execution time refers to the expected execution time that should be spent on a specific instruction or instruction sequence under ideal conditions or preset standards. By comparing the average execution time with its corresponding expected execution time, based on the comparison results, it is possible to identify which instructions have an execution efficiency higher or lower than expected, so as to evaluate whether the performance of the chip to be tested meets expectations or standards, and realize simulation testing of the chip to be tested.

[0080] Optionally, the testing method further includes: outputting log information in response to a log output instruction; wherein the log information includes a test result.

[0081] In this embodiment, in response to a log output instruction, log information is output and the log information includes test results, so that technicians can know which instructions perform well and which need to be improved to debug the chip to be tested.

[0082] In some embodiments, the log information also includes actual instruction stream, index data structure, precise program counter signal, preliminary program counter signal, critical signal, state change of critical signal, etc.

[0083] Optionally, the testing method further includes: in response to a log information output level requirement, outputting log information corresponding to the required log information output level.

[0084] In this embodiment, multiple log information output levels are preset, such as LOW, MEDIUM, HIGH, FULL, etc., and the log information content corresponding to each level gradually increases. When obtaining each information content (such as actual instruction stream, index data structure, accurate program counter signal, etc.), each information content can be marked with priority in advance, and in response to the log information output level requirement, the content information whose priority meets the level requirement is output to achieve different levels of log information output. Compared with the related art, the log output information can be customized, which improves the flexibility of simulation testing.

[0085] When the log information includes the state change of the key signal, the change of the program counter signal can be accurately used as the time point, and the states of each key signal can be collected in sequence to obtain the state change of the key signal.

[0086] Combination Figure 6 As shown, the embodiment of the present disclosure provides a test platform 60 for a chip, including a monitoring module 610, an analysis module 620, a generation module 630 and a test module 640. The monitoring module 610 is configured to generate an index data structure with instruction addresses as indexes according to pre-written test cases; the analysis module 620 is configured to obtain the precise program counter signal during the execution of the test case by the chip to be tested; the generation module 630 is configured to generate the actual instruction stream during the execution of the test case by the chip to be tested according to the index data structure and the precise program counter signal; the test module 640 is configured to test the chip to be tested according to the actual instruction stream.

[0087] The chip test platform 60 provided in the embodiment of the present disclosure can execute the chip test method described in the above embodiment. The technical effects of the chip test method described in the above embodiment are all possessed by this embodiment and will not be described in detail here. The chip test platform 60 provided in the embodiment of the present disclosure is implemented based on SystemVerilog language.

[0088] Optionally, the monitoring module 610 is further configured to obtain key signals of the chip to be tested during the execution of the test case in response to the simulation instruction. The analysis module 620 is configured to track the flow path of the simulation instruction, extract the initial program counter signal from the key signal, and obtain the accurate program counter signal according to the initial program counter signal.

[0089] Optionally, the monitoring module 610 is also configured to obtain keywords represented by each communication signal of the chip to be tested during the execution of the test case; perform a global search in the code library of the chip to be tested based on the keywords to obtain and save the complete path of each communication signal; and use the clock edge to sample the saved communication signal to obtain the key signal.

[0090] Optionally, in the case where the chip to be tested includes a sequential processor, the analysis module 620 is further configured to trace the flow path of the simulation instructions and extract an initial program counter signal from the key signal in the execution unit.

[0091] Optionally, in the case where the chip to be tested includes an out-of-order processor, the analysis module 620 is further configured to trace the flow path of the simulation instructions and extract the initial program counter signal from the key signal in the retirement unit.

[0092] Optionally, the key signal includes a branch valid signal, and the analysis module 620 is further configured to modify the branch valid signal; perform a logic operation on the modified branch valid signal and the initial program counter signal to obtain an accurate program counter signal.

[0093] Optionally, the analysis module 620 is also configured to obtain multiple branch instruction execution flows containing different timing errors; determine a target branch instruction execution flow that matches the benchmark instruction execution flow from the multiple branch instruction execution flows; and correct the branch valid signal according to the timing error corresponding to the target branch instruction execution flow.

[0094] Optionally, the monitoring module 610 is also configured to disassemble the pre-written test case to obtain the instruction address, instruction code and corresponding assembly statement in the test case; use the instruction address as the index, save the instruction code and the corresponding assembly statement, and obtain the index data structure.

[0095] Optionally, the test module 640 is also configured to obtain the number of executions and execution time of each instruction in the actual instruction stream; obtain the average execution time of each instruction based on the number of executions and the execution time; compare the average execution time of each instruction with the expected execution time corresponding to each instruction, and test the chip to be tested.

[0096] Optionally, the generation module 630 is further configured to output log information in response to a log output instruction; wherein the log information includes a test result.

[0097] Optionally, the generation module 630 is further configured to output log information corresponding to the required log information output level in response to a log information output level requirement.

[0098] Combination Figure 7 As shown, the embodiment of the present disclosure provides a test device 70 for a chip, including a processor 700 and a memory 701. Optionally, the device 70 may also include a communication interface 702 and a bus 703. The processor 700, the communication interface 702, and the memory 701 may communicate with each other through the bus 703. The communication interface 702 may be used for information transmission. The processor 700 may call the logic instructions in the memory 701 to execute the test method for a chip of the above embodiment.

[0099] In addition, the logic instructions in the memory 701 described above may be implemented in the form of software functional units and when sold or used as independent products, may be stored in a computer-readable storage medium.

[0100] The memory 701 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the methods in the embodiments of the present disclosure. The processor 700 executes functional applications and data processing by running the program instructions / modules stored in the memory 701, that is, implementing the test method for the chip in the above-mentioned embodiment.

[0101] The memory 701 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 701 may include a high-speed random access memory and may also include a non-volatile memory.

[0102] An embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned test method for a chip.

[0103] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0104] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the presence of other identical elements in the process, method or device including the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0105] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0106] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0107] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A chip testing method, characterized in that: include: Generate an index data structure with instruction addresses as indexes based on pre-written test cases; Obtain the precise program counter signal during the execution of the test case by the chip under test; Generate the actual instruction flow of the chip under test during the execution of the test case according to the index data structure and the accurate program counter signal; The chip under test is tested according to the actual instruction stream.

2. The testing method according to claim 1, characterized in that: Obtain the precise program counter signal during the test case execution of the chip under test, including: In response to the simulation instruction, obtaining key signals of the chip to be tested during the execution of the test case; Trace the flow path of simulation instructions and extract the initial program counter signal from the key signals; Based on the initial program counter signal, a precise program counter signal is obtained.

3. The testing method according to claim 2, characterized in that: Obtain the key signals of the chip under test during the execution of the test case in the following way: Obtain keywords represented by each communication signal of the chip under test during the execution of the test case; Perform a global search in the code base of the chip to be tested based on the keywords to obtain and save the complete path of each communication signal; The stored communication signal is sampled using the clock edge to obtain the key signal.

4. The testing method according to claim 2, characterized in that: The chip to be tested includes an in-order processor or an out-of-order processor; In the case where the chip to be tested includes a sequential processor, tracing the flow path of the simulation instruction and extracting the initial program counter signal from the key signal includes: tracing the flow path of the simulation instruction and extracting the initial program counter signal from the key signal in the execution unit; or, In the case where the chip to be tested includes an out-of-order processor, the flow path of the simulation instructions is tracked and the initial program counter signal is extracted from the key signal, including: tracking the flow path of the simulation instructions and extracting the initial program counter signal from the key signal in the retirement unit.

5. The testing method according to claim 2, characterized in that: Key signals include branch valid signals; according to the initial program counter signal, the accurate program counter signal is obtained, including: Modify the branch effective signal; The corrected branch valid signal is logically operated with the initial program counter signal to obtain an accurate program counter signal.

6. The testing method according to claim 5, characterized in that: The branch valid signal is modified as follows: Obtaining a plurality of branch instruction execution flows including different timing errors; Determining a target branch instruction execution flow that matches a reference instruction execution flow from among a plurality of branch instruction execution flows; The branch valid signal is corrected according to the timing error corresponding to the target branch instruction execution flow.

7. The testing method according to any one of claims 1 to 6, characterized in that: Generate an index data structure indexed by instruction addresses based on pre-written test cases, including: Disassemble the pre-written test cases to obtain the instruction addresses, instruction codes and corresponding assembly statements in the test cases; Using the instruction address as the index, save the instruction code and the corresponding assembly statement to obtain the index data structure.

8. The testing method according to any one of claims 1 to 6, characterized in that: Test the chip under test according to the actual instruction stream, including: Get the execution times and execution time of each instruction in the actual instruction stream; According to the number of executions and execution time, the average execution time of each instruction is obtained; The average execution time of each instruction is compared with the expected execution time corresponding to each instruction, and the chip to be tested is tested.

9. A test platform for a chip, characterized in that: include: A monitoring module, configured to generate an index data structure indexed by instruction addresses according to pre-written test cases; An analysis module is configured to obtain an accurate program counter signal during the execution of a test case by the chip under test; A generation module is configured to generate an actual instruction flow during the execution of the test case by the chip to be tested according to the index data structure and the precise program counter signal; The test module is configured to test the chip to be tested according to the actual instruction stream.

10. An electronic device, characterized in that: include: processor; and A memory storing program instructions, wherein the processor is configured to execute the chip testing method according to any one of claims 1 to 8 when running the program instructions.

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