Packaging structure and manufacturing method thereof

Abstract

The invention provides a packaging structure and a manufacturing method thereof. The packaging structure comprises a circuit board, a packaging substrate, an electronic / photonic assembly, a thin film redistribution layer, a heat dissipation assembly and an optical fiber assembly. The package substrate is disposed on the circuit board and electrically connected to the circuit board. The electronic / photonic component comprises an application-specific integrated circuit component, an electronic integrated circuit component and a photonic integrated circuit component. The electronic integrated circuit component and the photonic integrated circuit component are stacked on the packaging substrate and are electrically connected with the packaging substrate through the thin film redistribution layer. The orthographic projection of the electronic integrated circuit component on the thin film redistribution layer is overlapped with the orthographic projection of the photonic integrated circuit component on the thin film redistribution layer. The heat dissipation assembly is disposed on the electron / photon assembly. The optical fiber assembly is disposed on the package substrate and optically connected to the photonic integrated circuit assembly. The packaging structure provided by the invention can have relatively low cost.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and in particular to a packaging structure and a manufacturing method thereof. Background Art

[0002] In recent years, high-performance computing (HPC) has become more popular and widely used in advanced network and server applications, especially in artificial intelligence (AI) related products that require high data rates, increasing bandwidth, and decreasing latency. People have more and more expectations and requirements for high-density (HD) packaging substrates used in packaging structures that include high-performance computing (HPC), such as the requirements for the line width and line spacing of the metal layer are getting finer, and the requirements for the thickness of the dielectric layer of the reconfiguration circuit layer are getting thinner. However, the current build-up package substrate cannot meet the above requirements. Therefore, in order to meet the above requirements, the industry currently proposes to place dedicated integrated circuit components, electronic integrated circuit components, and photonic integrated circuit components side by side on a thin film redistribution layer to electrically connect to each other through the thin film redistribution layer. However, because the dedicated integrated circuit components, electronic integrated circuit components, and photonic integrated circuit components are placed side by side, the area of ​​the thin film redistribution layer required is large, and the area of ​​the packaging substrate cannot be reduced. Furthermore, due to the above arrangement, the electrical transmission path is longer and cannot achieve better electrical performance. In addition, the industry has further proposed adding a through-silicon via (TSV)-interposer to the build-up packaging substrate, but the price of the through-silicon via interposer is very expensive. Summary of the invention

[0003] The present invention is directed to a packaging structure which can solve the problems of the prior art and has a lower cost.

[0004] The present invention also provides a method for manufacturing a packaging structure, which is used to manufacture the above packaging structure.

[0005] According to an embodiment of the present invention, a packaging structure includes a circuit board, a packaging substrate, an electronic / photonic component, a thin film redistribution layer (or an organic interposer), a heat dissipation component, and an optical fiber component. The packaging substrate is disposed on the circuit board and electrically connected to the circuit board. The electronic / photonic component includes a dedicated integrated circuit component, an electronic integrated circuit component, and a photonic integrated circuit component. The dedicated integrated circuit component is disposed on the packaging substrate and electrically connected to the packaging substrate. The electronic integrated circuit component and the photonic integrated circuit component are stacked and disposed on the packaging substrate and electrically connected to the packaging substrate. The thin film redistribution layer (or an organic interposer) is disposed between the electronic integrated circuit component and the photonic integrated circuit component. The electronic integrated circuit component and the photonic integrated circuit component are electrically connected to the packaging substrate through the thin film redistribution layer. The orthographic projection of the electronic integrated circuit component on the thin film redistribution layer overlaps the orthographic projection of the photonic integrated circuit component on the thin film redistribution layer. The heat dissipation component is disposed on the electronic / photonic component. The optical fiber component is disposed on the packaging substrate and optically connects the photonic integrated circuit component.

[0006] In the packaging structure according to the embodiment of the present invention, the above-mentioned photonic integrated circuit component is located between the thin film redistribution layer and the packaging substrate.

[0007] In the packaging structure according to the embodiment of the present invention, the above-mentioned packaging substrate includes a containing groove, and part of the photonic integrated circuit component is located in the containing groove.

[0008] In the packaging structure according to an embodiment of the present invention, the heat dissipation component includes a first heat sink, a second heat sink, a first thermoelectric cooling plate and a second thermoelectric cooling plate. The first heat sink is configured on the application-specific integrated circuit component. The second heat sink is configured on the electronic integrated circuit component. The first thermoelectric cooling plate is configured on the first heat sink and is located between the first heat sink and the application-specific integrated circuit component. The second thermoelectric cooling plate is configured on the second heat sink and is located between the second heat sink and the electronic integrated circuit component.

[0009] In the packaging structure according to an embodiment of the present invention, the heat dissipation component further comprises a plurality of first thermal interface materials and a plurality of second thermal interface materials. The first thermal interface materials are respectively arranged between the first thermoelectric cooling sheet and the first heat sink, and between the first thermoelectric cooling sheet and the dedicated integrated circuit component. The second thermal interface materials are respectively arranged between the second thermoelectric cooling sheet and the second heat sink, and between the second thermoelectric cooling sheet and the electronic integrated circuit component.

[0010] In the packaging structure according to the embodiment of the present invention, the above-mentioned electronic integrated circuit component is located between the thin film redistribution layer and the packaging substrate.

[0011] In the packaging structure according to the embodiment of the present invention, the packaging substrate comprises a receiving groove, and part of the electronic integrated circuit component is located in the receiving groove.

[0012] In the packaging structure according to an embodiment of the present invention, the heat dissipation component includes a first heat sink, a second heat sink, a first thermoelectric cooling plate and a second thermoelectric cooling plate. The first heat sink is configured on the application-specific integrated circuit component. The second heat sink is configured on the photonic integrated circuit component. The first thermoelectric cooling plate is configured on the first heat sink and is located between the first heat sink and the application-specific integrated circuit component. The second thermoelectric cooling plate is configured on the second heat sink and is located between the second heat sink and the photonic integrated circuit component.

[0013] In the packaging structure according to an embodiment of the present invention, the heat dissipation component further comprises a plurality of first thermal interface materials and a plurality of second thermal interface materials. The first thermal interface materials are respectively arranged between the first thermoelectric cooling sheet and the first heat sink, and between the first thermoelectric cooling sheet and the application-specific integrated circuit component. The second thermal interface materials are respectively arranged between the second thermoelectric cooling sheet and the second heat sink, and between the second thermoelectric cooling sheet and the photonic integrated circuit component.

[0014] In the packaging structure according to an embodiment of the present invention, the above-mentioned packaging structure also includes a plurality of first conductive members, a plurality of second conductive members, and a plurality of third conductive members. The first conductive member is arranged between the packaging substrate and the circuit board, wherein the packaging substrate is electrically connected to the circuit board through the first conductive member. The second conductive member is arranged between the thin film redistribution layer and the packaging substrate, between the thin film redistribution layer and the photonic integrated circuit component, and between the thin film redistribution layer and the electronic integrated circuit component. The electronic integrated circuit component and the photonic integrated circuit component are electrically connected to the thin film redistribution layer through the second conductive member. The thin film redistribution layer is electrically connected to the packaging substrate through the second conductive member. The third conductive member is arranged between the dedicated integrated circuit component and the packaging substrate. The dedicated integrated circuit component is electrically connected to the packaging substrate through the third conductive member. Each first conductive member, each second conductive member, and each third conductive member respectively include a solder ball or a C4 bump.

[0015] In the packaging structure according to the embodiment of the present invention, the packaging structure further includes a primer, which is disposed between the ASIC component and the packaging substrate and covers the third conductive element.

[0016] In the packaging structure according to an embodiment of the present invention, the optical fiber assembly includes an optical fiber connector, an optical coupler, and an optical fiber cable. The optical fiber connector is disposed on the packaging substrate and is electrically connected to the packaging substrate. The optical fiber cable passes through the optical fiber connector and is electrically connected to the photonic integrated circuit assembly through the optical coupler.

[0017] According to an embodiment of the present invention, a method for manufacturing a packaging structure includes the following steps. Provide wafer bumps of a dedicated integrated circuit component wafer and divide it into separate dedicated integrated circuit components. Use a temporary glass carrier to manufacture an organic interposer and divide the separate organic interposer. Provide wafer bumps of an electronic integrated circuit component wafer and wafer bumps of a photonic integrated circuit component wafer and divide them into separate electronic integrated circuit components and separate photonic integrated circuit components. Connect a separate electronic integrated circuit component or a separate photonic integrated circuit component to a separate organic interposer with a temporary glass carrier. Remove the temporary glass carrier and connect a separate electronic integrated circuit component or a separate photonic integrated circuit component to the bottom of the organic interposer, followed by electroplating copper pillars and welding caps. Connect the dedicated integrated circuit component and the electronic integrated circuit component or the photonic integrated circuit component to a packaging substrate with / without an accommodating groove in a three-dimensional stack, and then connect it to a circuit board using solder balls. Apply a thermal management system to the dedicated integrated circuit component and the electronic integrated circuit component or the photonic integrated circuit component.

[0018] Based on the above, in the design of the packaging structure of the present invention, the dedicated integrated circuit component of the electronic / photonic component is configured on the packaging substrate and electrically connected to the packaging substrate, and the electronic integrated circuit component and the photonic integrated circuit component of the electronic / photonic component are stacked and configured on the packaging substrate and electrically connected to the packaging substrate through a thin film redistribution layer. Compared with the prior art of using a build-up layer packaging substrate or a silicon through-via intermediate substrate, the packaging structure of the present invention not only meets people's expectations and requirements for high-density packaging structures, but also has lower costs, high performance, and can use smaller packaging substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a cross-sectional schematic diagram of a packaging structure according to an embodiment of the present invention;

[0020] Figure 2 is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention;

[0021] Figure 3 is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention;

[0022] Figure 4 is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention;

[0023] Figure 5 It is a schematic flow chart of a method for manufacturing a packaging structure according to an embodiment of the present invention.

[0024] Description of Reference Numerals

[0025] 100a, 100b, 100c, 100d: packaging structure;

[0026] 110: circuit board;

[0027] 120a, 120b: packaging substrate;

[0028] 122: accommodating groove;

[0029] 130a, 130b, 130c, 130d: electronic / photonic components;

[0030] 132: Application specific integrated circuit assembly;

[0031] 134a, 134b, 134c, 134d: electronic integrated circuit components;

[0032] 136a, 136b, 136c, 136d: photonic integrated circuit components;

[0033] 140: thin film heavy cloth layer;

[0034] 142: patterned circuit layer;

[0035] 144: dielectric layer;

[0036] 145: conductive blind via;

[0037] 146: first pad;

[0038] 148: second pad;

[0039] 149: solder mask;

[0040] 150a, 150b: heat dissipation components;

[0041] 151, 153: first thermal interface material;

[0042] 152: first radiator;

[0043] 154a, 154b: second radiator;

[0044] 156: a first thermoelectric cooling sheet;

[0045] 157, 159: second thermal interface material;

[0046] 158a, 158b: second thermoelectric cooling sheet;

[0047] 160: optical fiber assembly;

[0048] 162: optical fiber connector;

[0049] 164: Optical coupler;

[0050] 166: optical fiber cable;

[0051] 170: a first conductive member;

[0052] 175: second conductive member;

[0053] 180: a third conductive member;

[0054] 185: base glue;

[0055] E: electronic module;

[0056] S11, S12, S13, S20, S30, S40, S50: steps. DETAILED DESCRIPTION

[0057] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0058] The embodiment of the present invention can be used in conjunction with the attached Figure 1 It is also understood that the drawings of the present invention are also considered as part of the disclosure. It should be understood that the drawings of the present invention are not drawn according to scale, and in fact, the size of the elements may be arbitrarily enlarged or reduced to clearly show the features of the present invention.

[0059] Figure 1 is a cross-sectional schematic diagram of a packaging structure according to an embodiment of the present invention. Figure 1In this embodiment, the packaging structure 100a includes a circuit board 110, a packaging substrate 120a, an electronic / photonic component 130a, a thin film redistribution layer 140, a heat dissipation component 150a, and an optical fiber component 160. The packaging substrate 120a is disposed on the circuit board 110 and is electrically connected to the circuit board 110. The electronic / photonic component 130a includes an application-specific integrated circuit component 132, an electronic integrated circuit component 134a, and a photonic integrated circuit component 136a. The application-specific integrated circuit component 132 is disposed on the packaging substrate 120a and is electrically connected to the packaging substrate 120a. The electronic integrated circuit component 134a and the photonic integrated circuit component 136a are stacked and disposed on the packaging substrate 120a and are electrically connected to the packaging substrate 120a. The thin film redistribution layer 140 is disposed between the electronic integrated circuit component 134a and the photonic integrated circuit component 136a. The electronic integrated circuit component 134a and the photonic integrated circuit component 136a are electrically connected to the packaging substrate 120a through the thin film redistribution layer 140. The orthographic projection of the electronic integrated circuit component 134a on the thin film redistribution layer 140 overlaps the orthographic projection of the photonic integrated circuit component 136a on the thin film redistribution layer 140. The heat dissipation component 150a is disposed on the electronic / photonic component 130a. The optical fiber component 160 is disposed on the packaging substrate 120a and optically connected to the photonic integrated circuit component 136a. In one embodiment, the thin film redistribution layer 140 can also be replaced by an organic interposer, which still falls within the scope of the present invention.

[0060] In short, the ASIC component 132 of the present embodiment is disposed on the package substrate 120a and electrically connected to the package substrate 120a, while the electronic integrated circuit component 134a and the photonic integrated circuit component 136a are stacked and disposed on the package substrate 120a and electrically connected to the package substrate 120a through the thin film redistribution layer 140. Compared with the build-up layer package substrate or the through silicon via intermediate substrate in the prior art, the package structure 100a of the present embodiment can not only meet people's expectations and requirements for high-density package structures, but also has a lower cost than the through silicon via intermediate substrate in the prior art. Moreover, the thin film redistribution layer 140 is disposed between the electronic integrated circuit component 134a and the photonic integrated circuit component 136a, which can effectively reduce the area of ​​the package substrate 120a used, that is, a smaller package substrate 120a can be used, and has better electrical performance.

[0061] For more details, please refer to Figure 1In the present embodiment, the photonic integrated circuit component 136a is specifically located between the thin film redistribution layer 140 and the packaging substrate 120a. The thin film redistribution layer 140 includes a multi-layer patterned circuit layer 142, a multi-layer dielectric layer 144, a plurality of first pads 146, a plurality of second pads 148, a plurality of conductive blind vias 145 and a solder mask 149. The patterned circuit layer 142 and the dielectric layer 144 are alternately stacked, wherein the line width and line spacing of the patterned circuit layer 142 are, for example, 2 microns, 5 microns or 10 microns, which means that the patterned circuit layer 142 is a fine circuit layer. Preferably, the wiring density of the thin film redistribution layer 140 is greater than the wiring density of the packaging substrate 120a, and the wiring density of the packaging substrate 120a is greater than the wiring density of the circuit board 110. The material of the dielectric layer 144 may be, for example, an organic material, glass or ceramic, but is not limited thereto. The surface of the first pad 146 is exposed and aligned with the surface of the dielectric layer 144 closest to the electronic / photonic component 130a. The second pad 148 is directly electrically connected to the patterned circuit layer 142, wherein the surface of the second pad 148 is exposed and aligned with the surface of the solder mask 149. The conductive blind via 145 passes through the dielectric layer 144 and is electrically connected between the patterned circuit layers 142 and between the patterned circuit layers 142 and the first pad 146.

[0062] Furthermore, the heat dissipation component 150a of the present embodiment includes a first heat sink 152, a second heat sink 154a, a first thermoelectric cooling plate 156, and a second thermoelectric cooling plate 158a. The first heat sink 152 is disposed on the ASIC component 132. The second heat sink 154a is disposed on the electronic integrated circuit component 134a. The first thermoelectric cooling plate 156 is disposed on the first heat sink 152 and is located between the first heat sink 152 and the ASIC component 132. The second thermoelectric cooling plate 158a is disposed on the second heat sink 154a and is located between the second heat sink 154a and the electronic integrated circuit component 134a.

[0063] Furthermore, the heat dissipation component 150a of the present embodiment further includes a plurality of first thermal interface materials 151, 153 and a plurality of second thermal interface materials 157, 159. The first thermal interface material 151 is disposed between the first thermoelectric cooling sheet 156 and the first heat sink 152, and the first thermal interface material 153 is disposed between the first thermoelectric cooling sheet 156 and the ASIC component 132. The second thermal interface material 157 is disposed between the second thermoelectric cooling sheet 158a and the second heat sink 154a, and the second thermal interface material 159 is disposed between the second thermoelectric cooling sheet 158a and the ASIC component 134a.

[0064] Furthermore, the package structure 100a of the present embodiment further includes a plurality of first conductive members 170, a plurality of second conductive members 175, and a plurality of third conductive members 180. The first conductive member 170 is disposed between the package substrate 120a and the circuit board 110, wherein the package substrate 120a is electrically connected to the circuit board 110 through the first conductive member 170. The second conductive member 175 is disposed between the thin film redistribution layer 140 and the package substrate 120a, between the thin film redistribution layer 140 and the photonic integrated circuit component 136a, and between the thin film redistribution layer 140 and the electronic integrated circuit component 134a. The electronic integrated circuit component 134a and the photonic integrated circuit component 136a are electrically connected to the thin film redistribution layer 140 through the second conductive member 175. The thin film redistribution layer 140 is electrically connected to the package substrate 120a through the second conductive member 175. The third conductive member 180 is disposed between the dedicated integrated circuit component 132 and the package substrate 120a. The ASIC component 132 is electrically connected to the package substrate 120a through the third conductive member 180. Each of the first conductive members 170, each of the second conductive members 175, and each of the third conductive members 180 are, for example, solder balls or C4 bumps, which are not limited here. In addition, the package structure 100a of this embodiment further includes an underfill 185, which is disposed between the ASIC component 132 and the package substrate 120a and covers the third conductive member 180.

[0065] It should be noted that since the thermal expansion coefficients of the thin film redistribution layer 140, the packaging substrate 120a, the photonic integrated circuit component 136a and the electronic integrated circuit component 134a are comparable, there is no need to provide a primer between the thin film redistribution layer 140 and the packaging substrate 120a, between the thin film redistribution layer 140 and the photonic integrated circuit component 136a, and between the thin film redistribution layer 140 and the electronic integrated circuit component 134a.

[0066] In addition, please refer to Figure 1 The optical fiber assembly 160 of this embodiment includes an optical fiber connector 162, an optical coupler 164, and an optical fiber cable 166. The optical fiber connector 162 is disposed on the package substrate 120a and is electrically connected to the package substrate 120a. The optical fiber cable 166 passes through the optical fiber connector 162 and is electrically connected to the photonic integrated circuit assembly 136a through the optical coupler 164.

[0067] Figure 5 is a flow chart of a method for manufacturing a packaging structure according to an embodiment of the present invention. Figure 1 and Figure 5In the process of the package structure 100a, first, in step S11, wafer bumps of a ASIC component wafer are provided and separated into separate ASIC components; in step S12, an organic interposer (or a thin film redistribution layer) is manufactured using a temporary glass carrier and separate organic interposers are separated; in step S13, wafer bumps of an electronic integrated circuit component wafer and wafer bumps of a photonic integrated circuit component wafer are provided and separated into separate electronic integrated circuit components and separate photonic integrated circuit components. The above steps S11, S12 and S13 are not in any order.

[0068] Next, in step S20, the individual electronic integrated circuit component 134a or the individual photonic integrated circuit component 136a is connected to the individual organic interposer (or thin film redistribution layer 140) with the temporary glass carrier.

[0069] Next, in step S30, the temporary glass carrier is removed, and a separate electronic integrated circuit component 134a or a separate photonic integrated circuit component 136a is connected to the bottom of the organic interposer (or thin film redistribution layer 140), followed by electroplating of copper pillars and solder caps. The electronic integrated circuit component 134a and the photonic integrated circuit component 136a are respectively disposed on opposite sides of the thin film redistribution layer 140 to define an electronic module E. At this time, the orthographic projection of the electronic integrated circuit component 134a on the thin film redistribution layer 140 overlaps the orthographic projection of the photonic integrated circuit component 136a on the thin film redistribution layer 140.

[0070] Afterwards, in step S40, the ASIC component 132 and the electronic ASIC component 134a or the photonic ASIC component 136a are three-dimensionally stacked and connected to the package substrate 120a with or without the accommodating groove, and then connected to the circuit board 110 using solder balls (such as the first conductive member 170). The ASIC component 132 and the electronic module E are arranged on the package substrate 120a, wherein the ASIC component 132 and the electronic module E are electrically connected to the package substrate 120a respectively. In detail, the ASIC component 132 can be bonded to the package substrate 120a and electrically connected to the package substrate 120a through the third conductive member 180 formed between the ASIC component 132 and the package substrate 120a, wherein each third conductive member 180 can be, for example, a solder ball or a C4 bump. The electronic module E can be bonded to the package substrate 120a and electrically connected to the package substrate 120a through the second conductive member 175 formed between the thin film redistribution layer 140 and the package substrate 120a.

[0071] Finally, in step S50, a thermal management system is applied to the ASIC component 132 and the electronic IC component 134a or the photonic IC component 136a. That is, a heat dissipation component 150a is configured on the electronic / photonic component 130a. Next, an optical fiber component 160 is configured on the package substrate 120a, wherein the optical fiber component 160 is optically connected to the photonic IC component 136a. At this point, the production of the package structure 100a has been completed.

[0072] It must be noted that the following embodiments use the same component numbers and some contents of the previous embodiments, wherein the same number is used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can refer to the previous embodiments, and the following embodiments will not be repeated.

[0073] Figure 2 is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 1 and Figure 2 The package structure 100b of this embodiment is Figure 1 The present invention is similar to the packaging structure 100a of the embodiment, and the difference between the two is that in the present embodiment, the thickness of the photonic integrated circuit component 136b is greater than the thickness of the photonic integrated circuit component 136a of the previous embodiment, so the packaging substrate 120b may include an accommodating groove 122, and a portion of the photonic integrated circuit component 136b may be located in the accommodating groove 122. At this time, the electronic integrated circuit component 134b and the photonic integrated circuit component 136b of the electronic / photonic component 130b are still stacked and arranged on the packaging substrate 120b, and the orthographic projection of the electronic integrated circuit component 134b on the thin film redistribution layer 140 completely overlaps the orthographic projection of the photonic integrated circuit component 136b on the thin film redistribution layer 140.

[0074] Regarding the process, please also refer to Figure 2 as well as Figure 5 The manufacturing method of the packaging structure 100b of the present embodiment is similar to the manufacturing method of the packaging structure 100a described above, and the difference between the two is that in the present embodiment, in step S13, a packaging substrate 120b having an accommodating groove 122 can be directly provided to correspond to the subsequent photonic integrated circuit component 136b.

[0075] Figure 3 is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 1 and Figure 3 The package structure 100c of this embodiment is Figure 1The packaging structure 100a of the electronic / photonic component 130c is similar to the packaging structure 100a, and the difference between the two is that: in the present embodiment, the electronic integrated circuit component 134c of the electronic / photonic component 130c is located between the thin film redistribution layer 140 and the packaging substrate 120a. Furthermore, the second heat sink 154b of the heat dissipation component 150b is configured on the photonic integrated circuit component 136c. The second thermoelectric cooling plate 158b of the heat dissipation component 150b is configured on the second heat sink 154b and is located between the second heat sink 154b and the photonic integrated circuit component 136c. In addition, the second thermal interface material 157 of the heat dissipation component 150b is configured between the second thermoelectric cooling plate 158b and the second heat sink 154b, and the second thermal interface material 157 of the heat dissipation component 150b is configured between the second thermoelectric cooling plate 158b and the photonic integrated circuit component 13c.

[0076] Figure 4 is a cross-sectional schematic diagram of a packaging structure according to another embodiment of the present invention. Figure 3 and Figure 4 The packaging structure 100d of this embodiment is Figure 3 The present invention is similar to the packaging structure 100c of the present invention, and the difference between the two is that in the present embodiment, the thickness of the electronic integrated circuit component 134d is greater than the thickness of the electronic integrated circuit component 134c of the previous embodiment, so the packaging substrate 120b may include an accommodating groove 122, and part of the electronic integrated circuit component 134d may be located in the accommodating groove 122. At this time, the electronic integrated circuit component 134d and the photonic integrated circuit component 136d of the electronic / photonic component 130d are still stacked and arranged on the packaging substrate 120b, and the orthographic projection of the photonic integrated circuit component 136d on the thin film redistribution layer 140 completely overlaps the orthographic projection of the electronic integrated circuit component 134d on the thin film redistribution layer 140.

[0077] In summary, in the design of the packaging structure of the present invention, the dedicated integrated circuit component of the electronic / photonic component is configured on the packaging substrate and electrically connected to the packaging substrate, and the electronic integrated circuit component and the photonic integrated circuit component of the electronic / photonic component are stacked and configured on the packaging substrate and electrically connected to the packaging substrate through a thin film redistribution layer. Compared with the prior art of using a build-up layer packaging substrate or a silicon via intermediate substrate, the packaging structure of the present invention not only meets people's expectations and requirements for high-density packaging structures, but also has lower costs, high performance, and can use smaller packaging substrates.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging structure, characterized in that: include: Circuit boards; A packaging substrate, disposed on the circuit board and electrically connected to the circuit board; An electronic / photonic component, comprising an ASIC component, an electronic IC component and a photonic IC component, wherein the ASIC component is disposed on the packaging substrate and is electrically connected to the packaging substrate, and the electronic IC component and the photonic IC component are stacked and disposed on the packaging substrate and are electrically connected to the packaging substrate; a thin film redistribution layer, disposed between the electronic integrated circuit component and the photonic integrated circuit component, wherein the electronic integrated circuit component and the photonic integrated circuit component are electrically connected to the packaging substrate through the thin film redistribution layer, and an orthographic projection of the electronic integrated circuit component on the thin film redistribution layer overlaps an orthographic projection of the photonic integrated circuit component on the thin film redistribution layer; A heat dissipation component, configured on the electronic / photonic component; as well as The optical fiber component is disposed on the packaging substrate and optically connected to the photonic integrated circuit component.

2. The packaging structure according to claim 1, characterized in that: The photonic integrated circuit component is located between the thin film redistribution layer and the packaging substrate.

3. The packaging structure according to claim 2, characterized in that: The packaging substrate comprises a containing groove, and part of the photonic integrated circuit component is located in the containing groove.

4. The packaging structure according to claim 2, characterized in that: The heat dissipation component comprises: A first heat sink is disposed on the ASIC component; A second heat sink is disposed on the electronic integrated circuit assembly; A first thermoelectric cooling sheet is disposed on the first heat sink and located between the first heat sink and the ASIC component; and The second thermoelectric cooling sheet is disposed on the second heat sink and located between the second heat sink and the electronic integrated circuit component.

5. The packaging structure according to claim 4, characterized in that: The heat dissipation component also includes: A plurality of first thermal interface materials are respectively disposed between the first thermoelectric cooling sheet and the first heat sink, and between the first thermoelectric cooling sheet and the ASIC component; and A plurality of second thermal interface materials are respectively disposed between the second thermoelectric cooling sheet and the second heat sink, and between the second thermoelectric cooling sheet and the electronic integrated circuit component.

6. The packaging structure according to claim 1, characterized in that: The electronic integrated circuit component is located between the thin film redistribution layer and the packaging substrate.

7. The packaging structure according to claim 6, characterized in that: The packaging substrate comprises a containing groove, and part of the electronic integrated circuit component is located in the containing groove.

8. The packaging structure according to claim 6, characterized in that: The heat dissipation component comprises: A first heat sink is disposed on the ASIC component; A second heat sink is disposed on the photonic integrated circuit component; A first thermoelectric cooling sheet is disposed on the first heat sink and located between the first heat sink and the ASIC component; and The second thermoelectric cooling sheet is disposed on the second heat sink and located between the second heat sink and the photonic integrated circuit component.

9. The packaging structure according to claim 8, characterized in that: The heat dissipation component also includes: A plurality of first thermal interface materials are respectively disposed between the first thermoelectric cooling sheet and the first heat sink, and between the first thermoelectric cooling sheet and the ASIC component; and A plurality of second thermal interface materials are respectively disposed between the second thermoelectric cooling sheet and the second heat sink, and between the second thermoelectric cooling sheet and the photonic integrated circuit component.

10. The packaging structure according to claim 1, characterized in that: Also includes: A plurality of first conductive members are disposed between the packaging substrate and the circuit board, wherein the packaging substrate is electrically connected to the circuit board through the plurality of first conductive members; a plurality of second conductive members, disposed between the thin film redistribution layer and the packaging substrate, between the thin film redistribution layer and the photonic integrated circuit component, and between the thin film redistribution layer and the electronic integrated circuit component, wherein the electronic integrated circuit component and the photonic integrated circuit component are electrically connected to the thin film redistribution layer through the plurality of second conductive members, and the thin film redistribution layer is electrically connected to the packaging substrate through the plurality of second conductive members; as well as A plurality of third conductive members are disposed between the dedicated integrated circuit component and the packaging substrate, wherein the dedicated integrated circuit component is electrically connected to the packaging substrate through the plurality of third conductive members, and each of the plurality of first conductive members, each of the plurality of second conductive members, and each of the plurality of third conductive members respectively includes a solder ball or a C4 bump.

11. The packaging structure according to claim 10, characterized in that: Also includes: The bottom glue is arranged between the ASIC component and the packaging substrate, and covers the plurality of third conductive members.

12. The packaging structure according to claim 1, characterized in that: The optical fiber component includes an optical fiber connector, an optical coupler, and an optical fiber cable. The optical fiber connector is disposed on the packaging substrate and electrically connected to the packaging substrate. The optical fiber cable passes through the optical fiber connector and is electrically connected to the photonic integrated circuit component through the optical coupler.

13. A method for manufacturing a packaging structure, characterized in that: include: Providing wafer bumping of an ASIC wafer and singulating into individual ASICs; Manufacturing an organic interposer using a temporary glass carrier and separating individual organic interposers; Providing wafer bumps of electronic integrated circuit component wafers and wafer bumps of photonic integrated circuit component wafers, and dividing into individual electronic integrated circuit components and individual photonic integrated circuit components; connecting a single said electronic integrated circuit component or a single said photonic integrated circuit component to a single said organic interposer with said temporary glass carrier; Remove the temporary glass carrier and connect the individual electronic integrated circuit components or the individual photonic integrated circuit components to the bottom of the organic interposer, followed by electroplating copper pillars and solder caps; Connecting the ASIC component and the electronic IC component or the photonic IC component to a package substrate with or without an accommodating groove in a three-dimensional stack, and then connecting to a circuit board using solder balls; and A thermal management system is applied to the ASIC component and the electronic IC component or the photonic IC component.

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