Display module, manufacturing method and display device

Abstract

The invention discloses a display module, a manufacturing method and a display device. The display module of one embodiment comprises a substrate; the grid signal line is arranged on the substrate; the data signal lines are insulated from the grid signal lines, and orthographic projections of the grid signal lines and the data signal lines on the substrate intersect to form a plurality of pixel regions; the gate signal line comprises first conductive layers which extend along a first direction and are sequentially arranged in a second direction perpendicular to the first direction; the orthographic projection of the first oxide layer on the substrate is located in partial projection of the orthographic projection of the first conductive layer on the substrate; the data signal line comprises second conductive layers which extend in the second direction and are sequentially arranged in the first direction; the orthographic projection of the first oxide layer on the substrate is overlapped with the orthographic projection of the second conductive layer on the substrate, and the orthographic projection of the first oxide layer on the substrate is not overlapped with the orthographic projection of the second oxide layer on the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more specifically, to a display module, a manufacturing method and a display device. Background Art

[0002] In the related art, the contrast ratio (CR) of display products is affected by many factors, among which the metal reflection of the wiring layer is an important factor. The metal mainly used in the wiring layer is copper, which has strong reflectivity.

[0003] The light from the backlight source is incident on the metal wire through scattering, reflection, and refraction of other materials in the box, and then reflected to the front of the screen through the metal wire, reducing the contrast of the product. In addition, the display product also has uneven display of blue and red, which is mainly affected by film interference. For thin-film transistor liquid crystal displays (TFT-LCD displays), the backlight source needs to penetrate insulating films such as insulating layers and passivation layers. Due to the different refractive indices of different film layers to light, film interference is very likely to occur, which in turn causes uneven blue and red. Summary of the invention

[0004] An object of the present invention is to provide a display module, a manufacturing method and a display device to solve at least one of the problems existing in the prior art.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A first aspect of the present invention provides a display module, the display module comprising:

[0007] substrate;

[0008] A gate signal line disposed on the substrate;

[0009] A data signal line insulated from the gate signal line, wherein the gate signal line and the data signal line intersect each other on the substrate to form a plurality of pixel areas;

[0010] in,

[0011] The gate signal line comprises:

[0012] A first conductive layer extending along a first direction and arranged in sequence in a second direction perpendicular to the first direction; and

[0013] A first oxide layer, whose orthographic projection on the substrate is located in a partial projection of the orthographic projection of the first conductive layer on the substrate;

[0014] The data signal line comprises:

[0015] A second conductive layer extending along a second direction and arranged sequentially in the first direction; and

[0016] The orthographic projection of the second oxide layer on the substrate coincides with the orthographic projection of the second conductive layer on the substrate,

[0017] An orthographic projection of the first oxide layer on the substrate does not overlap with an orthographic projection of the second oxide layer on the substrate.

[0018] In an optional embodiment, the first oxide layer is obtained by oxidizing the first conductive layer, and the reflectivity of the first oxide layer is lower than the reflectivity of the first conductive layer;

[0019] The second oxide layer is obtained by oxidizing the second conductive layer, and the reflectivity of the second oxide layer is lower than the reflectivity of the second conductive layer.

[0020] In an optional embodiment, the display module further includes a driving transistor disposed on the substrate and located in the pixel area, and the driving transistor includes:

[0021] A gate layer disposed on the substrate;

[0022] A gate insulating layer covering the gate layer, the gate insulating layer is also used to insulate the gate signal line and the data signal line;

[0023] An active layer disposed on a side of the gate insulating layer away from the substrate;

[0024] A source-drain electrode layer covers the active layer and is at least partially disposed on a surface of the gate insulating layer away from the substrate.

[0025] In an optional embodiment, the source-drain electrode layer includes:

[0026] A source conductive layer connected to one end of the active layer and covering at least a portion of a surface of the active layer away from the substrate;

[0027] a drain conductive layer connected to the other end of the active layer and covering at least a portion of a surface of the active layer away from the substrate; and

[0028] A third oxide layer covers the surface of the source conductive layer and the drain conductive layer away from the substrate.

[0029] In an optional embodiment, the third oxide layer is obtained by oxidizing the source conductive layer and the drain conductive layer, and the reflectivity of the third oxide layer is lower than the reflectivity of the source conductive layer and the drain conductive layer.

[0030] In an optional embodiment, the orthographic projection of the gate insulating layer on the substrate covers the orthographic projection of the second conductive layer on the substrate, and covers the overlapping projections of the first conductive layer and the second conductive layer on the substrate. In the orthographic projection of the first conductive layer on the substrate, the gate insulating layer is not set at the non-overlapping position of the orthographic projection of the first conductive layer and the second conductive layer on the substrate.

[0031] In an optional embodiment, a surface of the gate layer away from the substrate is completely covered by the gate insulating layer;

[0032] The orthographic projection of the gate insulating layer on the substrate covers the orthographic projection of the gate layer on the substrate, and covers the combined orthographic projection of the source conductive layer and the drain conductive layer on the substrate.

[0033] The surface of the source conductive layer close to the substrate is completely disposed on the surface of the gate insulating layer away from the substrate;

[0034] A surface of the drain conductive layer close to the substrate is completely disposed on a surface of the gate insulating layer away from the substrate.

[0035] In an optional embodiment, in the orthographic projection of the first conductive layer on the substrate, the orthographic projection of the first oxide layer on the substrate is arranged at a non-overlapping position of the orthographic projection of the first conductive layer and the second conductive layer on the substrate;

[0036] The second oxide layer is arranged at the position of the orthographic projection of the second conductive layer on the substrate;

[0037] The third oxide layer covers a combined orthographic projection of the source conductive layer and the drain conductive layer on the substrate.

[0038] In an optional embodiment, the orthographic projection of the gate insulating layer on the substrate covers the overlapping projections of the first conductive layer and the second conductive layer on the substrate.

[0039] In the orthographic projection of the first conductive layer on the substrate, no gate insulating layer is provided at non-overlapping positions of the orthographic projections of the first conductive layer and the second conductive layer on the substrate;

[0040] In the orthographic projection of the second conductive layer on the substrate, no gate insulating layer is provided at non-overlapping positions of the orthographic projection of the first conductive layer and the second conductive layer on the substrate.

[0041] In an optional embodiment, a surface of the gate layer away from the substrate is completely covered by the gate insulating layer, and an orthographic projection of the gate insulating layer on the substrate covers an orthographic projection of the gate layer on the substrate.

[0042] The orthographic projection of the gate insulating layer on the substrate and the combined orthographic projection of the source conductive layer and the drain conductive layer on the substrate have overlapping projections,

[0043] The surface of the source conductive layer close to the substrate is partially disposed on the surface of the gate insulating layer away from the substrate, and partially disposed on the surface of the substrate;

[0044] A surface portion of the drain conductive layer close to the substrate is disposed on a surface of the gate insulating layer away from the substrate, and a portion of the drain conductive layer is disposed on a surface of the substrate.

[0045] In an optional embodiment, the display module includes:

[0046] In the orthographic projection of the first conductive layer on the substrate, the orthographic projection of the first oxide layer on the substrate is arranged at a non-overlapping position of the orthographic projection of the first conductive layer and the second conductive layer on the substrate;

[0047] The second oxide layer is arranged at the position of the orthographic projection of the second conductive layer on the substrate;

[0048] The third oxide layer covers the surface of the source conductive layer and the drain conductive layer away from the substrate.

[0049] A second aspect of the present invention provides a display device, comprising the display module described in the first aspect of the present invention.

[0050] A third aspect of the present invention provides a method for manufacturing the display module of the first aspect of the present invention, the method comprising:

[0051] A metal material layer of gate signal lines is formed on a substrate, extending along a first direction and arranged in sequence in a second direction perpendicular to the first direction;

[0052] forming a material layer of a gate insulating layer on the gate signal line;

[0053] A metal material layer of data signal lines is formed on the material layer of the gate insulating layer, extending along the second direction and arranged in sequence in the first direction, wherein the gate signal lines and the data signal lines intersect in a line with their orthographic projections on the substrate to form a plurality of pixel areas;

[0054] The metal material layers of the gate signal line and the data signal line are oxidized to form a first conductive layer, a second conductive layer, a first oxide layer and a second oxide layer,

[0055] Wherein, the step of oxidizing the metal material layer of the gate signal line and the data signal line further comprises:

[0056] The surface of the metal material layer of the gate signal line away from the substrate is treated with an oxidizing gas, the oxidized surface forms a first oxide layer, and the unoxidized metal layer material forms a first conductive layer.

[0057] The surface of the metal material layer of the data signal line away from the substrate is treated with an oxidizing gas, the oxidized surface forms a second oxide layer, and the unoxidized metal layer material forms a second conductive layer, and the orthographic projection of the first oxide layer on the substrate does not overlap with the orthographic projection of the second oxide layer on the substrate.

[0058] In an optional embodiment, before oxidizing the metal material layer of the gate signal line and the data signal line, the method further includes forming a driving transistor on the substrate in the pixel area, and further includes:

[0059] forming a gate layer on the substrate, wherein the gate layer is electrically connected to a gate signal line;

[0060] forming a material layer of a gate insulating layer covering the gate layer on the gate layer;

[0061] forming an active layer on a side of the material layer of the gate insulating layer away from the substrate;

[0062] forming a source-drain electrode layer on a side of the active layer away from the substrate, wherein the source-drain electrode layer covers the active layer and is at least partially disposed on a surface of the gate insulating layer away from the substrate;

[0063] The method also includes oxidizing the metal surface of the source-drain electrode layer away from the substrate, forming a third oxide layer on the surface of the oxidized source-drain electrode layer, forming a source conductive layer with a metal layer material connected to one end of the active layer that is not oxidized, and forming a drain conductive layer with a metal layer material connected to the other end of the active layer that is not oxidized.

[0064] In an optional embodiment, before oxidizing the metal material layer of the gate signal line and the data signal line, the method further comprises:

[0065] The material layer of the gate insulating layer in the pixel area is etched, and the gate signal line at a non-overlapping position of the gate signal line and the data signal line is etched,

[0066] The material layer of the gate insulating layer at the position corresponding to the second conductive layer is retained, the material layer of the gate insulating layer at the overlapping position of the first conductive layer and the second conductive layer is retained, and the material layer of the gate insulating layer at the corresponding positions of the source conductive layer, the drain conductive layer and the active layer is retained.

[0067] In an optional embodiment, before forming a metal material layer of a data signal line on the material layer of the gate insulating layer, the method further comprises:

[0068] The material layer of the gate insulating layer in the pixel area is etched, the gate signal line at a non-overlapping position of the gate signal line and the data signal line is etched, and the data signal line at a non-overlapping position of the gate signal line and the data signal line is etched, and the material layer of the gate insulating layer at the overlapping position of the gate signal line and the data signal line is retained,

[0069] The method of forming a material layer of a gate insulating layer covering the gate layer on the gate layer further includes etching the material layer of the gate insulating layer covering the gate layer to retain the material layer of the gate insulating layer at corresponding positions of the source conductive layer, the drain conductive layer and the active layer.

[0070] Forming a source-drain electrode layer on a side of the active layer away from the substrate further comprises:

[0071] A source conductive layer is formed on an end surface of the active layer away from a surface of one side of the substrate, on a surface of the gate insulating layer away from the substrate, and on a surface of the substrate; a source conductive layer is formed on an end surface of the active layer away from a surface of one side of the substrate, on a surface of the gate insulating layer away from the substrate, and on a surface of the substrate.

[0072] The beneficial effects of the present invention are as follows:

[0073] The display module of the embodiment of the present invention designs the layer structure of the gate signal line and the data signal line, sets the gate signal line to have a first conductive layer and a first oxide layer, and sets the data signal line to have a second conductive layer and a second oxide layer, oxidizes the signal line, and utilizes the weaker reflective performance of the oxidized first oxide layer and the second oxide layer to reduce metal reflection, thereby improving the contrast of the display module. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0075] Figure 1 A schematic diagram showing the arrangement of signal lines according to an embodiment of the present invention;

[0076] Figure 2 A schematic diagram showing the layer structure of a driving transistor according to an embodiment of the present invention;

[0077] Figure 3 A schematic diagram showing the layer structure of a driving transistor according to an optional embodiment of the present invention;

[0078] Figure 4 A schematic diagram showing the arrangement of signal lines of an optional embodiment of the present invention;

[0079] Figure 5 Show Figure 4 A schematic diagram of a layer structure where a cross section extending along a first direction is located at an overlapping position of a gate signal line and a data signal line;

[0080] Figure 6 Show Figure 4 A schematic diagram of a layer structure where a cross section extending along a second direction is located at an overlapping position of a gate signal line and a data signal line;

[0081] Figure 7 A schematic diagram showing the layer structure of a driving transistor according to another optional embodiment of the present invention;

[0082] Figure 8 A schematic diagram showing the arrangement of signal lines in another optional embodiment of the present invention;

[0083] Fig. 9 Shows Figure 8 A schematic diagram of a layer structure where a cross section extending along a first direction is located at an overlapping position of a gate signal line and a data signal line;

[0084] Fig.10 Shows Figure 8 A schematic diagram of a layer structure where a cross section extending along a second direction is located at an overlapping position of a gate signal line and a data signal line;

[0085] Fig.11 A schematic diagram showing a process of manufacturing a display module according to another embodiment of the present invention;

[0086] Fig.12a Shows Figure 3 The process flow chart of the driving transistor shown;

[0087] Figure 12b Shows Figure 4 The process flow chart of the signal line shown;

[0088] Fig.13a Shows Figure 7 The process flow chart of the driving transistor shown;

[0089] Fig.13b Shows Figure 8 The process flow chart of the signal line is shown. DETAILED DESCRIPTION

[0090] In order to explain the present invention more clearly, the present invention is further described below in conjunction with embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content specifically described below is illustrative rather than restrictive, and the protection scope of the present invention should not be limited thereto.

[0091] In the related art, the contrast ratio (CR) of display products is affected by many factors, among which the metal reflection of the wiring layer is an important factor. The metal mainly used in the wiring layer is copper, which has strong reflectivity.

[0092] The light from the backlight source is incident on the metal wire through scattering, reflection, and refraction of other materials in the box, and then reflected to the front of the screen through the metal wire, reducing the contrast of the product. In addition, the display product also has uneven display of blue and red, which is mainly affected by film interference. For thin-film transistor liquid crystal displays (TFT-LCD displays), the backlight source needs to penetrate insulating films such as insulating layers and passivation layers. Due to the different refractive indices of different film layers to light, film interference is very likely to occur, which in turn causes uneven blue and red.

[0093] In view of this, the present invention provides a display module, a manufacturing method and a display device to solve at least one of the above problems.

[0094] The embodiment of the present invention provides a display module, such as Figures 1 to 10 As shown, the display module includes:

[0095] Substrate 10,

[0096] A gate signal line 20 disposed on the substrate 10;

[0097] The data signal lines 30 are insulated from the gate signal lines 20 , and the gate signal lines 20 and the data signal lines 30 intersect each other on the substrate 10 to form a plurality of pixel areas Pix;

[0098] Wherein, the gate signal line 20 includes:

[0099] A first conductive layer 21 extending along a first direction and arranged in sequence in a second direction perpendicular to the first direction; and

[0100] The first oxide layer 22, whose orthographic projection on the substrate 10 is located in a partial projection of the orthographic projection of the first conductive layer 21 on the substrate 10;

[0101] The data signal line 30 includes:

[0102] A second conductive layer 31 extending along a second direction and arranged sequentially in the first direction; and

[0103] The orthographic projection of the second oxide layer 32 on the substrate 10 coincides with the orthographic projection of the second conductive layer 31 on the substrate 10.

[0104] The orthographic projection of the first oxide layer 22 on the substrate 10 does not overlap with the orthographic projection of the second oxide layer 32 on the substrate 10 .

[0105] The gate signal line 20 is closer to the substrate 10, and the data signal line 30 is farther away from the substrate 10 than the gate signal line 20. That is, in the stacking relationship of the layer structure, from bottom to top, there are the substrate 10, the gate signal line 20, and the data signal line 30. Figure 1 As shown, the gate signal line 20 and the data signal line 30 have overlapping projections in the projection direction. In combination with the structural design of the double-layered gate signal line 20 and the data signal line 30 of the embodiment of the present invention, the second oxide layer 32 of the data signal line 30 located above completely covers the second conductive layer 31, and the first oxide layer 22 is not provided at the overlapping position of the gate signal line 20 and the data signal line 30. That is, the first oxide layer 22 does not completely cover the first conductive layer 21, so as to improve the process efficiency.

[0106] The display module of the embodiment of the present invention designs the layer structure of the gate signal line 20 and the data signal line 30, sets the gate signal line 20 to have a first conductive layer 21 and a first oxide layer 22, and sets the data signal line 30 to have a second conductive layer 31 and a second oxide layer 32, oxidizes the signal line, and utilizes the weaker reflective performance of the oxidized first oxide layer 22 and the second oxide layer 32 to reduce metal reflection, thereby improving the contrast of the display module.

[0107] In an optional embodiment, the first oxide layer 22 is obtained by oxidizing the first conductive layer 21, and the reflectivity of the first oxide layer 22 is lower than the reflectivity of the first conductive layer 21; the second oxide layer 32 is obtained by oxidizing the second conductive layer 31, and the reflectivity of the second oxide layer 32 is lower than the reflectivity of the second conductive layer 31. The characteristic of weakened reflective performance after oxidation is utilized to weaken the metal reflection of the conductive layer, thereby improving the contrast of the display module.

[0108] In an optional embodiment, the material of the first conductive layer 21 and the second conductive layer 31 is copper, and the material of the first oxide layer 22 and the second oxide layer 32 is cuprous oxide. The reflectivity of cuprous oxide is lower than that of copper, which reduces the intensity of light reflected to the front of the screen, thereby improving the contrast of the display product.

[0109] In an alternative embodiment, Figure 1 and Figure 2As shown, the display module further includes a driving transistor 40 disposed on the substrate 10 and located in the pixel area Pix, and the driving transistor 40 is used to form a driving circuit for driving sub-pixels in the pixel area Pix. In this embodiment, the driving transistor 40 includes:

[0110] A gate layer 41 disposed on the substrate 10;

[0111] A gate insulating layer 42 covering the gate layer 41, wherein the gate insulating layer 42 is also used to insulate the gate signal line 20 and the data signal line 30;

[0112] An active layer 43 disposed on a side of the gate insulating layer 42 away from the substrate 10;

[0113] a source-drain electrode layer 44 covering the active layer 43 and at least partially disposed on a surface of the gate insulating layer 42 away from the substrate 10; and

[0114] A passivation layer 45 covers the side of the source-drain electrode layer 44 away from the substrate 10 .

[0115] In an optional embodiment, if Figure 3 and another embodiment Figure 7 As shown, the source-drain electrode layer 44 includes:

[0116] A source conductive layer 441 is connected to one end of the active layer 43 and covers at least a portion of a surface of the active layer 43 away from the substrate 10;

[0117] a drain conductive layer 442 connected to the other end of the active layer 43 and covering at least a portion of the surface of the active layer 43 away from the substrate 10; and

[0118] The third oxide layer 443 covers the surface of the source conductive layer 441 and the drain conductive layer 442 away from the substrate 10 .

[0119] The source-drain electrode layer 44 of this embodiment is designed to form a double-layer structure through oxidation, that is, a third oxide layer 443 is provided on the source conductive layer 441, a third oxide layer 443 is provided on the drain conductive layer 442, and the third oxide layer 443 is not provided on the active layer 43. In other words, the layer structure at the corresponding position of the source conductive layer 441 is a double-layer structure, the layer structure at the corresponding position of the drain conductive layer 442 is a double-layer structure, and the layer structure at the position of the active layer 43 is a single-layer structure.

[0120] In an optional embodiment, the third oxide layer 443 is obtained by oxidation treatment of the source conductive layer 441 and the drain conductive layer 442. The reflectivity of the third oxide layer 443 is lower than that of the source conductive layer 441 and the drain conductive layer 442. The characteristic of weakened reflective performance after oxidation is utilized to weaken the metal reflection of the conductive layer, thereby improving the contrast of the display module.

[0121] In an optional embodiment, the material of the source conductive layer 441 and the drain conductive layer 442 is copper, and the material of the third oxide layer 443 is cuprous oxide. The reflectivity of cuprous oxide is lower than that of copper, which reduces the intensity of light reflected to the front of the screen, thereby improving the contrast of the display product.

[0122] In this embodiment, in the process of oxidizing the surfaces of the source conductive layer 441 and the drain conductive layer 442 away from the substrate 10 using an oxidizing gas, oxygen is also added to the active layer 43 to prevent the surface of the active layer 43 from being oxidized.

[0123] The gate insulating layer 42 of the driving transistor 40 of the embodiment of the present invention has a different structural design.

[0124] In an optional embodiment, if Figure 3 As shown, the surface of the gate layer 41 away from the substrate 10 is completely covered by the gate insulating layer 42;

[0125] The orthographic projection of the gate insulating layer 42 on the substrate 10 covers the orthographic projection of the gate layer 41 on the substrate 10 , and covers the combined orthographic projection of the source conductive layer 441 and the drain conductive layer 442 on the substrate 10 .

[0126] The surface of the source conductive layer 441 close to the substrate 10 is completely disposed on the surface of the gate insulating layer 42 away from the substrate 10 , and the surface of the drain conductive layer 442 close to the substrate 10 is completely disposed on the surface of the gate insulating layer 42 away from the substrate 10 .

[0127] In other words, the length of the gate insulating layer 42 in the second direction of the present embodiment is greater than the length of the combined orthographic projection of the source conductive layer 441 , the drain conductive layer 442 and the active layer 43 on the substrate 10 along the second direction.

[0128] like Figure 3 As shown, the gate insulating layer 42 of this embodiment completely covers the gate layer 41 and provides a bearing surface for the source-drain electrode layer 44 and the active layer 43 , so that the source-drain electrode layer 44 and the active layer 43 are completely arranged on the surface of the gate insulating layer 42 away from the substrate 10 .

[0129] In this embodiment, in order to save process steps, the gate insulating layer 42 of the driving transistor 40 is not only arranged between the gate layer 41 and the active layer 43, but also arranged between the gate signal line 20 and the data signal line 30, that is, the gate insulating layer 42 is used to simultaneously achieve insulation between the gate signal line 20 and the data signal line 30. The gate insulating layer 42 of this embodiment can have different arrangements, which will be described in the following embodiments.

[0130] Regarding the design of the gate insulating layer 42 for insulating the gate signal line 20 and the data signal line 30, in an optional embodiment, as Figures 4 to 6 As shown,

[0131] The orthographic projection of the gate insulating layer 42 on the substrate 10 covers the orthographic projection of the second conductive layer 31 on the substrate 10 , and covers the overlapping projections of the first conductive layer 21 and the second conductive layer 31 on the substrate 10 .

[0132] In the orthographic projection of the first conductive layer 21 on the substrate 10 , the first conductive layer 21 and the second conductive layer 31 are at non-overlapping positions of the orthographic projection of the substrate 10 , and the gate insulating layer 42 is not provided.

[0133] That is to say, the gate insulating layer 42 of the present embodiment is not disposed in the non-pixel region, but is disposed under the entire data signal line 30. Figure 4 In addition, except for the overlapping position of the projections of the gate signal line 20 and the data signal line 30, the gate insulating layer 42 of this embodiment is not arranged above the gate signal line 20, that is, Figure 4 There is no dotted frame above the gate signal line 20 shown. Due to the position design of the gate insulating layer 42, the gate insulating layer 42 is not set in the pixel area Pix. Therefore, the pixel area Pix will not form a planar interference with the passivation layer 45 above the source and drain electrode layer 44, effectively improving the uneven blue and red color problem of the display module.

[0134] like Figure 4 and Figure 5 As shown, Figure 5 Shows Figure 4Schematic diagram of the layer structure at the cross-sectional position extending along the second direction at the position of the data signal line 30. In an optional embodiment, at the signal line position of the second conductive layer 31, the length of the gate insulating layer 42 in the second direction is greater than or equal to the length of the second conductive layer 31 in the second direction, that is, the gate insulating layer 42 is a strip structure arranged below the second conductive layer 31 of the data signal line 30, the length of the gate insulating layer 42 in the second direction is at least equal to or greater than the length of the second conductive layer 31 in the second direction, and the gate insulating layer 42 completely covers the second conductive layer 31 to completely insulate the gate signal line 20 from the second conductive layer 31.

[0135] At the overlapping position of the first conductive layer 21 and the second conductive layer 31, in an optional embodiment, the length of the gate insulating layer 42 in the second direction is greater than the length of the first conductive layer 21 in the second direction, that is, the length of the gate insulating layer 42 in the second direction at the overlapping position is greater than the overall width of the first conductive layer 21, and the gate insulating layer 42 completely insulates the second conductive layer 31 and the gate signal line 20 at the overlapping position.

[0136] like Figure 4 and Figure 6 As shown, Figure 6 Shows Figure 4 A schematic diagram of the layer structure of a cross section extending along the first direction at the overlapping position of the gate signal line 20 and the data signal line 30. In an optional embodiment, at the overlapping position of the first conductive layer 21 and the second conductive layer 31, the length of the gate insulating layer 42 along the first direction is greater than the length of the second conductive layer 31 along the first direction, that is, the length of the gate insulating layer 42 in the overlapping position in the first direction is greater than the overall width of the second conductive layer 31, and the gate insulating layer 42 completely insulates the second conductive layer 31 and the gate signal line 20 at the overlapping position.

[0137] In an optional embodiment, based on Figure 3 to Figure 6 As shown, under the structure of the signal line routing structure and the structure of the driving transistor 40, the positions of the first oxide layer 22, the second oxide layer 32 and the third oxide layer 443 are designed as follows:

[0138] In the orthographic projection of the first conductive layer 21 on the substrate 10, the orthographic projection of the first oxide layer 22 on the substrate 10 is arranged at a non-overlapping position of the orthographic projections of the first conductive layer 21 and the second conductive layer 31 on the substrate 10;

[0139] The second oxide layer 32 is arranged at the position of the orthographic projection of the substrate 10 of the second conductive layer 31;

[0140] The third oxide layer 443 covers the combined orthographic projection of the source conductive layer 441 and the drain conductive layer 442 on the substrate 10 .

[0141] That is, the first oxide layer 22 of the present embodiment covers the first conductive layer 21, the second oxide layer 32 covers the second conductive layer 31, and the third oxide layer 443 covers the source conductive layer 441 and the drain conductive layer 442. Based on the above structure, the present embodiment etches away the gate insulating layer 42 above the gate signal line 20 and in the pixel area Pix, and only retains the gate insulating layer 42 below the driving transistor 40 and the data signal line 30, so that the reflectivity of the surface of each signal line and the driving transistor 40 away from the side of the substrate 10 is reduced. In addition, the gate insulating layer 42 of the present embodiment is not set in the pixel area Pix, and will not form a planar interference with the passivation layer 45 on the side of the data signal line 30 away from the substrate 10. Therefore, the above setting can effectively improve the uneven cyan and red colors of the display state.

[0142] In an optional embodiment, if Figure 7 As shown, the surface of the gate layer 41 away from the substrate 10 is completely covered by the gate insulating layer 42, and the orthographic projection of the gate insulating layer 42 on the substrate 10 covers the orthographic projection of the gate layer 41 on the substrate 10.

[0143] The orthographic projection of the gate insulating layer 42 on the substrate 10 and the combined orthographic projection of the source conductive layer 441 and the drain conductive layer 442 on the substrate 10 have overlapping projections.

[0144] The surface of the source conductive layer 441 close to the substrate 10 is partially disposed on the surface of the gate insulating layer 42 away from the substrate 10 , and partially disposed on the surface of the substrate 10 ;

[0145] A surface portion of the drain conductive layer 442 close to the substrate 10 is disposed on a surface of the gate insulating layer 42 away from the substrate 10 , and a portion of the drain conductive layer 442 is disposed on a surface of the substrate 10 .

[0146] In other words, Figure 7 As shown, the length of the gate insulating layer 42 in the second direction of this embodiment is smaller than the length of the combined orthographic projection of the source conductive layer 441 , the drain conductive layer 442 and the active layer 43 on the substrate 10 along the second direction.

[0147] like Figure 7 As shown, the gate insulating layer 42 of this embodiment completely covers the gate layer 41 and provides a complete bearing surface for the active layer 43 , while the gate insulating layer 42 provides a partial bearing surface for the source conductive layer 441 and a partial bearing surface for the drain conductive layer 442 .

[0148] Exemplarily, the surface portion of the source conductive layer 441 close to the substrate 10 includes:

[0149] A first source portion located on the top surface of the gate insulating layer 42 away from the substrate 10 and covering a portion of the surface of the active layer 43 away from the substrate 10;

[0150] a second source portion located on an inclined surface of the gate insulating layer 42 away from the substrate 10; and a third source portion located on the substrate 10,

[0151] Exemplarily, the surface portion of the drain conductive layer 442 close to the substrate 10 includes:

[0152] A first drain portion located on the top surface of the gate insulating layer 42 away from the substrate 10 and covering a portion of the surface of the active layer 43 away from the substrate 10, wherein the first drain portion and the first source portion are located at two ends of the active layer 43;

[0153] a second drain portion located on an inclined surface of the gate insulating layer 42 on a side away from the substrate 10 ; and a third drain portion located on the substrate 10 .

[0154] Based on the above configuration, the source conductive layer 441 and the drain conductive layer 442 of this embodiment are not completely disposed on the gate insulating layer 42 . This structure can significantly reduce the occupied area of ​​the driving transistor 40 and improve the display performance.

[0155] Regarding the design of the gate insulating layer 42 for insulating the gate signal line 20 and the data signal line 30, in an optional embodiment, as Figure 7 to Figure 10 As shown:

[0156] The orthographic projection of the gate insulating layer 42 on the substrate 10 covers the overlapping projections of the first conductive layer 21 and the second conductive layer 31 on the substrate 10, that is, the gate insulating layer 42 completely insulates the overlapping position of the gate signal line 20 and the data signal line 30.

[0157] In the orthographic projection of the first conductive layer 21 on the substrate 10, the gate insulating layer 42 is not provided at the non-overlapping position of the orthographic projection of the first conductive layer 21 and the second conductive layer 31 on the substrate 10;

[0158] In the orthographic projection of the second conductive layer 31 on the substrate 10 , the first conductive layer 21 and the second conductive layer 31 are located at non-overlapping positions of the orthographic projection of the substrate 10 , and the gate insulating layer 42 is not provided.

[0159] That is, at the positions of the gate signal line 20 and the data signal line 30, the gate insulating layer 42 of the present embodiment is not arranged in the non-pixel region, nor is it arranged under the entire data signal line 30, but is only arranged at the overlapping position of the projections of the gate signal line 20 and the data signal line 30, that is, Figure 8 In the positions of the frame lines surrounded by the dotted lines shown in FIG. 1 , except for the overlapping positions of the data signal line 30 and the gate signal line 20, there is no dotted frame above the gate signal line 20 at the non-overlapping position, and there is no dotted frame above the data signal line 30 at the non-overlapping position. In addition, a gate insulating layer 42 is provided at the position of the driving transistor 40, that is, as shown in FIG. Figure 8 At the position of the frame line surrounded by the dotted line shown, the gate insulating layer 42 is not set in the pixel area Pix through the position design of the above-mentioned gate insulating layer 42. Therefore, the pixel area Pix will not form a planar interference with the passivation layer 45 above the source and drain electrode layer 44, effectively improving the problem of uneven blue and red colors of the display module.

[0160] In an optional embodiment, if Fig. 9 As shown, Fig. 9 Shows Figure 8 A schematic diagram of a layer structure of a cross section extending along a first direction at an overlapping position of a gate signal line 20 and a data signal line 30,

[0161] like Fig. 9 At the cross-sectional position shown, the extension length of the gate insulating layer 42 along the first direction is greater than the extension length of the second conductive layer 31 along the first direction, that is, the extension length of the gate insulating layer 42 along the first direction is greater than the overall width of the second conductive layer 31 .

[0162] In an optional embodiment, if Fig.10 As shown, Fig.10 Shows Figure 8 A schematic diagram of the layer structure of a cross section extending along the second direction at the overlapping position of the gate signal line 20 and the data signal line 30.

[0163] like Fig.10 At the cross-sectional position shown, the extension length of the gate insulation layer 42 along the second direction is greater than the extension length of the first conductive layer 21 along the first direction, that is, the gate insulation layer 42 covers the gate signal line 20 and the extension length of the gate insulation layer 42 along the second direction is greater than the overall width of the first conductive layer 21.

[0164] In an optional embodiment, the display module includes:

[0165] In the orthographic projection of the first conductive layer 21 on the substrate 10, the orthographic projection of the first oxide layer 22 on the substrate 10 is arranged at a non-overlapping position of the orthographic projections of the first conductive layer 21 and the second conductive layer 31 on the substrate 10, that is, the first oxide layer 22 covers the first conductive layer 21 of the gate signal line 20 at the non-overlapping projection position;

[0166] The second oxide layer 32 is arranged at the position of the orthographic projection of the second conductive layer 31 on the substrate 10, that is, the second oxide layer 32 covers the second conductive layer 31 of the entire data signal line 30, including the second conductive layer 31 at the overlapping projection position;

[0167] The third oxide layer 443 covers the surface of the source conductive layer 441 and the drain conductive layer 442 away from the substrate 10, that is, the third oxide layer 443 covers the entire source conductive layer 441 and the drain conductive layer 442. Through the above arrangement, the weaker reflective properties of the oxidized first oxide layer 22 and the second oxide layer 32 are utilized to weaken the metal reflection, thereby improving the contrast of the display module.

[0168] Therefore, based on the display module of the above embodiment, by designing the layer structure of the gate signal line 20 and the data signal line 30, the gate signal line 20 is set to have a first conductive layer 21 and a first oxide layer 22, and the data signal line 30 is set to have a second conductive layer 31 and a second oxide layer 32, and the signal line is oxidized, and the weaker reflective performance of the oxidized first oxide layer 22 and the second oxide layer 32 is used to reduce the metal reflection, thereby improving the contrast of the display module. In addition, the above embodiment also designs the position of the gate insulating layer 42, and does not set the gate insulating layer 42 in the pixel area Pix. Therefore, the pixel area Pix will not form a flat interference with the passivation layer 45 above the source and drain electrode layer 44, effectively improving the uneven blue and red color problem of the display module.

[0169] Another embodiment of the present invention provides a display device, which includes the display module of the above embodiment of the present invention. The display device can be applied to any product or component with a display function, such as electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators, and this embodiment does not limit this.

[0170] Another embodiment of the present invention provides a method for manufacturing the above display module, such as Fig.11 As shown, the method includes:

[0171] S10, forming a metal material layer of the gate signal line 20 on the substrate 10, extending along a first direction and arranged in sequence in a second direction perpendicular to the first direction;

[0172] S30, forming a material layer of a gate insulating layer 42 on the gate signal line 20;

[0173] S50, forming a metal material layer of the data signal line 30 on the material layer of the gate insulating layer 42, extending along the second direction and arranged in sequence in the first direction, wherein the orthographic projections of the gate signal line 20 and the data signal line 30 on the substrate 10 intersect to form a plurality of pixel areas Pix;

[0174] S70, oxidizing the metal material layer of the gate signal line 20 and the data signal line 30, so as to form a first conductive layer 21, a second conductive layer 31, a first oxide layer 22 and a second oxide layer 32,

[0175] The step S70 of “oxidizing the metal material layer of the gate signal line 20 and the data signal line 30” further includes:

[0176] S71, using an oxidizing gas to treat the surface of the metal material layer of the gate signal line 20 away from the substrate 10, the oxidized surface forms a first oxide layer 22, and the unoxidized metal layer material forms a first conductive layer 21,

[0177] S73. Use an oxidizing gas to treat the surface of the metal material layer of the data signal line 30 away from the substrate 10, and the oxidized surface forms a second oxide layer 32. The unoxidized metal layer material forms a second conductive layer 31. The orthographic projection of the first oxide layer 22 on the substrate 10 does not overlap with the orthographic projection of the second oxide layer 32 on the substrate 10.

[0178] In the process of forming the data signal line 30 and the gate signal line 20 in the embodiment of the present invention, the signal line is oxidized to form the gate signal line 20 having the first conductive layer 21 and the first oxide layer 22, and the gate signal line 20 having the second conductive layer 31 and the second oxide layer 32 is formed. The weaker reflective properties of the oxidized first oxide layer 22 and the second oxide layer 32 are used to reduce metal reflection, thereby improving the contrast of the display module.

[0179] In an optional embodiment, before the step S70 of “oxidizing the metal material layer of the gate signal line 20 and the data signal line 30”, the method further includes step S60: forming a driving transistor 40 on the substrate 10 in the pixel area Pix, and step S60 further includes:

[0180] S61, forming a gate layer 41 on the substrate 10, wherein the gate layer 41 is electrically connected to the gate signal line 20;

[0181] S63, forming a material layer of the gate insulating layer 42 covering the gate layer 41 on the gate layer 41;

[0182] S65, forming an active layer 43 on a side of the material layer of the gate insulating layer 42 away from the substrate 10;

[0183] S67, forming a source-drain electrode layer 44 on a side of the active layer 43 away from the substrate 10, wherein the source-drain electrode layer 44 covers the active layer 43 and is at least partially disposed on a surface of the gate insulating layer 42 away from the substrate 10;

[0184] The method also includes step S80 of "oxidizing the metal surface of the source-drain electrode layer 44 away from the substrate 10". Based on the oxidation step, a third oxide layer 443 is formed on the surface of the oxidized source-drain electrode layer 44, and the metal layer material connected to one end of the active layer 43 that is not oxidized is formed as a source conductive layer 441, and the metal layer material connected to the other end of the active layer 43 that is not oxidized is formed as a drain conductive layer 442.

[0185] In the process of manufacturing the driving transistor 40 of the display module in this step, the source-drain electrode layer 44 is oxidized, and a third oxide layer 443 is formed on the source conductive layer 441 and the drain conductive layer 442. The weaker reflective performance of the third oxide layer 443 formed after oxidation is utilized to reduce metal reflection, thereby improving the contrast of the display module.

[0186] When formed Figure 3 to Figure 6 In the structure of the signal line and the driving transistor 40 of the embodiment shown in the figure, in an optional embodiment, before the step S70 of "oxidizing the metal material layer of the gate signal line 20 and the data signal line 30", the method further includes:

[0187] S68. Etch the material layer of the gate insulating layer 42 in the pixel area Pix, and etch the gate signal line 20 at the non-overlapping position of the gate signal line 20 and the data signal line 30, retain the material layer of the gate insulating layer 42 at the corresponding position of the second conductive layer 31, retain the material layer of the gate insulating layer 42 at the overlapping position of the first conductive layer 21 and the second conductive layer 31, and retain the material layer of the gate insulating layer 42 at the corresponding positions of the source conductive layer 441, the drain conductive layer 442 and the active layer 43.

[0188] Production Figure 3 to Figure 6 The signal line and the method of driving the transistor 40 in the embodiment shown are exemplified as follows. Fig.12a and Figure 12b The schematic diagram shown:

[0189] First, the gate signal line 20, the data signal line 30 and the driving transistor 40 are formed according to normal process steps S10, S30, S50 and S60. For example, the metal circuits of each signal line can be formed by etching using a wet etching method.

[0190] For example, Fig.12a Shown and Figure 12b As shown, a gate layer 41 and a material layer of a gate signal line 20 are formed on a substrate 10 by the same process, a gate insulating layer 42 covering the entire surface is formed on the gate layer 41 and the material layer of the gate signal line 20, and then a material layer of the data signal line 30 is formed at a position of the gate insulating layer 42 corresponding to the data signal line 30, and an active layer 43 and a source-drain electrode layer 44 are formed at a position corresponding to the driving transistor 40, until step S67 is completed.

[0191] In the etching step of step S68, an insulating film mask is added, and the material layer of the gate insulating layer 42 on the gate signal line 20 and the pixel area Pix is ​​etched away through the process flow of coating photoresist, exposure, development, and dry etching, leaving only the device area of ​​the driving transistor 40 and the gate insulating layer 42 under the SD line.

[0192] Then, in step S70, the metal material layer of the gate signal line 20 and the data signal line 30 is oxidized to form Fig.12a and Figure 12b The first conductive layer 21 , the second conductive layer 31 , the first oxide layer 22 and the second oxide layer 32 are shown.

[0193] Exemplarily, in step S70, an oxidizing gas such as N2O is used to treat the metal material layer of the gate signal line 20, the metal material layer of the data signal line 30 and the surface of the source-drain electrode layer 44, so that the surface metal of the gate signal line 20, the data signal line 30 and the source-drain electrode layer 44 is completely oxidized to form a first oxide layer 22, a second oxide layer 32 and a third oxide layer 443. This can reduce metal reflection and improve the contrast of the display product. The pixel area Pix does not have a gate insulating layer 42, and will not form a flat interference with the passivation layer 45 above the source-drain electrode layer 44, which can effectively improve the problem of uneven cyan and red colors.

[0194] When formed Figure 7 to Figure 10 In the structure of the signal line and the driving transistor 40 of the embodiment shown, in an optional embodiment, before step S50 of "forming a metal material layer of the data signal line 30 on the material layer of the gate insulating layer 42", the method further includes:

[0195] S40, etching the material layer of the gate insulating layer 42 in the pixel area Pix, etching the gate signal line 20 at the non-overlapping position of the gate signal line 20 and the data signal line 30, and etching the data signal line 30 at the non-overlapping position of the gate signal line 20 and the data signal line 30, retaining the material layer of the gate insulating layer 42 at the overlapping position of the gate signal line 20 and the data signal line 30.

[0196] The step S63 of “forming a material layer of the gate insulating layer 42 covering the gate layer 41 on the gate layer 41” further includes etching the material layer of the gate insulating layer 42 covering the gate layer 41, and retaining the material layer of the gate insulating layer 42 at corresponding positions of the source conductive layer 441, the drain conductive layer 442 and the active layer 43.

[0197] The step S67 of “forming a source-drain electrode layer 44 on a side of the active layer 43 away from the substrate 10 ” further includes:

[0198] S671, forming a source conductive layer 441 on a surface of an end of the active layer 43 away from the substrate 10, on a surface of the gate insulating layer 42 away from the substrate 10, and on a surface of the substrate 10;

[0199] S673 , forming a source conductive layer 441 on the other end surface of the active layer 43 away from the surface of the substrate 10 , on the surface of the gate insulating layer 42 away from the substrate 10 , and on the surface of the substrate 10 .

[0200] Production Figure 7 to Figure 10 The signal line and the method of driving the transistor 40 in the embodiment shown are exemplified as follows. Fig.13a and Fig.13b The schematic diagram shown:

[0201] After first forming the material layer of the gate signal line 20 and the material layer of the gate insulating layer 42 according to the process steps S10 and S30, in step S40, an insulating film mask is added, and through the process of coating photoresist, exposing, developing, and dry etching, the material layer of the gate insulating layer 42 above the gate signal line 20 outside the preset overlapping position and the material layer of the gate insulating layer 42 of the pixel area Pix are etched away, leaving only the device area of ​​the driving transistor 40 and the gate insulating layer 42 at the overlapping position of the data signal line 30 and the gate signal line 20.

[0202] Then, according to the process of step S50, a data signal line 30 is formed on the material layer of the gate insulating layer 42. Fig.13a The second layer structure diagram shown in

[0203] According to the process of steps S61, S63, S65 and S67, various components of the driving transistor 40 are formed on the substrate 10 in the pixel area Pix. Fig.13b The second layer structure diagram shown in

[0204] Then, in step S70, the metal material layer of the gate signal line 20 and the data signal line 30 is oxidized. For example, the metal material layer of the gate signal line 20, the metal material layer of the data signal line 30 and the surface of the source-drain electrode layer 44 are treated with an oxidizing gas such as N2O to oxidize all the surface metals of the gate signal line 20, the data signal line 30 and the source-drain electrode layer 44 to form a Fig.13a and Fig.13b As shown in the schematic diagram of the layer structure, the first oxide layer 22, the second oxide layer 32 and the third oxide layer 443 can reduce metal reflection and improve the contrast of the display product. The pixel area Pix does not have a gate insulating layer 42, and will not form a planar interference with the passivation layer 45 above the source and drain electrode layer 44, and can effectively improve the problem of uneven blue and red colors.

[0205] It is worth noting that the specific embodiment of the method for manufacturing the display module of the embodiment of the present invention can refer to the display module of the aforementioned embodiment, which will not be described in detail here.

[0206] In the description of the present invention, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0207] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the embodiments here. All obvious changes or modifications derived from the technical solution of the present invention are still within the protection scope of the present invention.

Claims

1. A display module, It is characterized in that The display module comprises: substrate; A gate signal line disposed on the substrate; A data signal line insulated from the gate signal line, wherein the gate signal line and the data signal line intersect each other on the substrate to form a plurality of pixel areas; in, The gate signal line comprises: A first conductive layer extending along a first direction and arranged in sequence in a second direction perpendicular to the first direction; and A first oxide layer, whose orthographic projection on the substrate is located in a partial projection of the orthographic projection of the first conductive layer on the substrate; The data signal line comprises: A second conductive layer extending along a second direction and arranged sequentially in the first direction; and The orthographic projection of the second oxide layer on the substrate coincides with the orthographic projection of the second conductive layer on the substrate, An orthographic projection of the first oxide layer on the substrate does not overlap with an orthographic projection of the second oxide layer on the substrate.

2. The display module according to claim 1, It is characterized in that The first oxide layer is obtained by oxidizing the first conductive layer, and the reflectivity of the first oxide layer is lower than the reflectivity of the first conductive layer; The second oxide layer is obtained by oxidizing the second conductive layer, and the reflectivity of the second oxide layer is lower than the reflectivity of the second conductive layer.

3. The display module according to claim 1, It is characterized in that The display module further includes a driving transistor disposed on the substrate and located in the pixel area, wherein the driving transistor includes: A gate layer disposed on the substrate; A gate insulating layer covering the gate layer, the gate insulating layer is also used to insulate the gate signal line and the data signal line; An active layer disposed on a side of the gate insulating layer away from the substrate; A source-drain electrode layer covers the active layer and is at least partially disposed on a surface of the gate insulating layer away from the substrate.

4. The display module according to claim 3, It is characterized in that The source-drain electrode layer comprises: A source conductive layer connected to one end of the active layer and covering at least a portion of a surface of the active layer away from the substrate; a drain conductive layer connected to the other end of the active layer and covering at least a portion of a surface of the active layer away from the substrate; and A third oxide layer covers the surface of the source conductive layer and the drain conductive layer away from the substrate.

5. The display module according to claim 4, It is characterized in that The third oxide layer is obtained by oxidizing the source conductive layer and the drain conductive layer, and the reflectivity of the third oxide layer is lower than the reflectivity of the source conductive layer and the drain conductive layer.

6. The display module according to claim 4, It is characterized in that The orthographic projection of the gate insulating layer on the substrate covers the orthographic projection of the second conductive layer on the substrate, and covers the overlapping projections of the first conductive layer and the second conductive layer on the substrate. In the orthographic projection of the first conductive layer on the substrate, no gate insulating layer is provided at non-overlapping positions of the first conductive layer and the second conductive layer on the orthographic projection of the substrate.

7. The display module according to claim 6, It is characterized in that The surface of the gate layer away from the substrate is completely covered by the gate insulating layer; The orthographic projection of the gate insulating layer on the substrate covers the orthographic projection of the gate layer on the substrate, and covers the combined orthographic projection of the source conductive layer and the drain conductive layer on the substrate. The surface of the source conductive layer close to the substrate is completely disposed on the surface of the gate insulating layer away from the substrate; A surface of the drain conductive layer close to the substrate is completely disposed on a surface of the gate insulating layer away from the substrate.

8. The display module according to claim 7, It is characterized in that In the orthographic projection of the first conductive layer on the substrate, the orthographic projection of the first oxide layer on the substrate is arranged at a non-overlapping position of the orthographic projection of the first conductive layer and the second conductive layer on the substrate; The second oxide layer is arranged at the position of the orthographic projection of the second conductive layer on the substrate; The third oxide layer covers a combined orthographic projection of the source conductive layer and the drain conductive layer on the substrate.

9. The display module according to claim 4, It is characterized in that The orthographic projection of the gate insulating layer on the substrate covers the overlapping projections of the first conductive layer and the second conductive layer on the substrate, In the orthographic projection of the first conductive layer on the substrate, no gate insulating layer is provided at non-overlapping positions of the orthographic projections of the first conductive layer and the second conductive layer on the substrate; In the orthographic projection of the second conductive layer on the substrate, no gate insulating layer is provided at non-overlapping positions of the orthographic projection of the first conductive layer and the second conductive layer on the substrate.

10. The display module according to claim 9, It is characterized in that The surface of the gate layer away from the substrate is completely covered by the gate insulating layer, and the orthographic projection of the gate insulating layer on the substrate covers the orthographic projection of the gate layer on the substrate. The orthographic projection of the gate insulating layer on the substrate has an overlapping projection with the combined orthographic projection of the source conductive layer and the drain conductive layer on the substrate, The surface of the source conductive layer close to the substrate is partially disposed on the surface of the gate insulating layer away from the substrate, and partially disposed on the surface of the substrate; A surface portion of the drain conductive layer close to the substrate is disposed on a surface of the gate insulating layer away from the substrate, and a portion of the drain conductive layer is disposed on a surface of the substrate.

11. The display module according to claim 10, It is characterized in that The display module comprises: In the orthographic projection of the first conductive layer on the substrate, the orthographic projection of the first oxide layer on the substrate is arranged at a non-overlapping position of the orthographic projection of the first conductive layer and the second conductive layer on the substrate; The second oxide layer is arranged at the position of the orthographic projection of the second conductive layer on the substrate; The third oxide layer covers the surface of the source conductive layer and the drain conductive layer away from the substrate.

12. A display device, It is characterized in that The display device comprises the display module according to any one of claims 1 to 11.

13. A method for manufacturing the display module according to any one of claims 1 to 11, It is characterized in that The method comprises: A metal material layer of gate signal lines is formed on a substrate, extending along a first direction and arranged in sequence in a second direction perpendicular to the first direction; forming a material layer of a gate insulating layer on the gate signal line; A metal material layer of data signal lines is formed on the material layer of the gate insulating layer, extending along the second direction and arranged in sequence in the first direction, wherein the gate signal lines and the data signal lines intersect in a line with their orthographic projections on the substrate to form a plurality of pixel areas; The metal material layers of the gate signal line and the data signal line are oxidized to form a first conductive layer, a second conductive layer, a first oxide layer and a second oxide layer, Wherein, the step of oxidizing the metal material layer of the gate signal line and the data signal line further comprises: Using an oxidizing gas to treat the surface of the metal material layer of the gate signal line away from the substrate, the oxidized surface forms a first oxide layer, and the unoxidized metal layer material forms a first conductive layer; The surface of the metal material layer of the data signal line away from the substrate is treated with an oxidizing gas, the oxidized surface forms a second oxide layer, and the unoxidized metal layer material forms a second conductive layer, and the orthographic projection of the first oxide layer on the substrate does not overlap with the orthographic projection of the second oxide layer on the substrate.

14. The method according to claim 13, It is characterized in that Before oxidizing the metal material layer of the gate signal line and the data signal line, the method further includes forming a driving transistor on the substrate in the pixel area, and further includes: forming a gate layer on the substrate, wherein the gate layer is electrically connected to a gate signal line; forming a material layer of a gate insulating layer covering the gate layer on the gate layer; forming an active layer on a side of the material layer of the gate insulating layer away from the substrate; forming a source-drain electrode layer on a side of the active layer away from the substrate, wherein the source-drain electrode layer covers the active layer and is at least partially disposed on a surface of the gate insulating layer away from the substrate; The method also includes oxidizing the metal surface of the source-drain electrode layer away from the substrate, forming a third oxide layer on the surface of the oxidized source-drain electrode layer, forming a source conductive layer with a metal layer material connected to one end of the active layer that is not oxidized, and forming a drain conductive layer with a metal layer material connected to the other end of the active layer that is not oxidized.

15. The method according to claim 14, It is characterized in that Before oxidizing the metal material layer of the gate signal line and the data signal line, the method further comprises: The material layer of the gate insulating layer in the pixel area is etched, and the gate signal line at the non-overlapping position of the gate signal line and the data signal line is etched, and the material layer of the gate insulating layer at the corresponding position of the second conductive layer is retained, the material layer of the gate insulating layer at the overlapping position of the first conductive layer and the second conductive layer is retained, and the material layer of the gate insulating layer at the corresponding positions of the source conductive layer, the drain conductive layer and the active layer is retained.

16. The method according to claim 14, It is characterized in that Before forming a metal material layer of a data signal line on the material layer of the gate insulating layer, the method further comprises: Etching the material layer of the gate insulating layer in the pixel area, etching the gate signal line at a non-overlapping position of the gate signal line and the data signal line, and etching the data signal line at a non-overlapping position of the gate signal line and the data signal line, and retaining the material layer of the gate insulating layer at the overlapping position of the gate signal line and the data signal line; The step of forming a material layer of a gate insulating layer covering the gate layer on the gate layer further comprises etching the material layer of the gate insulating layer covering the gate layer to retain the material layer of the gate insulating layer at positions corresponding to the source conductive layer, the drain conductive layer and the active layer; Forming a source-drain electrode layer on a side of the active layer away from the substrate further comprises: A source conductive layer is formed on an end surface of the active layer away from a surface of one side of the substrate, on a surface of the gate insulating layer away from the substrate, and on a surface of the substrate; a source conductive layer is formed on an end surface of the active layer away from a surface of one side of the substrate, on a surface of the gate insulating layer away from the substrate, and on a surface of the substrate.

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