Power consumption management method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a power consumption management method and device, electronic equipment and a readable storage medium, the method is applied to a processor, and when a current sampling period starts, the memory access state of the processor is determined according to the memory access duration of a recorded historical sampling period; the memory access duration of one historical sampling period is determined according to the duration of the processor for executing the memory access task in the task queue in the historical sampling period; adjusting operation parameters of the processor according to the memory access state of the processor; the operation parameters comprise clock frequency and / or power supply voltage. Thus, the memory access state of the processor can be obtained through the recorded memory access duration of the historical sampling period, the problem of inaccuracy caused by evaluation of the state of the processor only according to the real-time operation data of the processor can be avoided, the accuracy of determining the memory access state of the processor is improved, and the memory access efficiency of the processor is improved. Therefore, the accuracy of operation parameter adjustment can be improved, and the accuracy of power consumption management can be improved.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and in particular relates to a power consumption management method, device, electronic equipment and readable storage medium. Background Art

[0002] In the field of computer technology, the performance of a computer system usually depends on the performance of a processor in the system, and the performance of a processor is related to the power consumption of the processor. This field usually manages the power consumption of a processor during its operation to adjust the processor performance according to the actual operation of the processor, for example, reducing the processor performance when the performance requirement is low, and increasing the processor performance when the performance requirement is high.

[0003] In the related art, power consumption is usually managed in real time by acquiring the processor's operating data in real time. However, the processor's operating data usually changes frequently, and the real-time acquired operating data has a certain degree of randomness, resulting in low accuracy of power consumption management and poor adjustment effect of processor performance. Summary of the invention

[0004] The present invention provides a power consumption management method, device, electronic device and readable storage medium to solve the problem of inaccurate power consumption management, which can more accurately manage the power consumption of a processor and further improve the adjustment effect of processor performance.

[0005] In order to solve the above-mentioned technical problems, the present invention is achieved as follows:

[0006] In a first aspect, the present invention provides a power consumption management method, which is applied to a processor, and the method comprises:

[0007] At the beginning of the current sampling cycle, the historical memory access state of the processor is determined according to the memory access duration of the recorded historical sampling cycle; the memory access duration of a historical sampling cycle is determined according to the duration of the processor executing the memory access task in the task queue within the historical sampling cycle;

[0008] According to the historical memory access state of the processor, the operating parameters of the processor are adjusted; the operating parameters include clock frequency and / or power supply voltage.

[0009] In a second aspect, the present invention provides a power consumption management device, which is applied to a processor, and includes:

[0010] A state determination module is used to determine the historical memory access state of the processor according to the memory access duration of the recorded historical sampling cycle at the beginning of the current sampling cycle; the memory access duration of a historical sampling cycle is determined according to the duration of the processor executing the memory access task in the task queue within the historical sampling cycle;

[0011] A parameter adjustment module is used to adjust the operating parameters of the processor according to the historical memory access state of the processor; the operating parameters include clock frequency and / or power supply voltage.

[0012] In a third aspect, the present invention provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned power consumption management method when executing the program.

[0013] In a fourth aspect, the present invention provides a readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to execute the above-mentioned power consumption management method.

[0014] The power consumption management method provided by the embodiment of the present invention is applied to a processor. At the beginning of the current sampling cycle, the memory access state of the processor is determined according to the memory access duration of the recorded historical sampling cycle, and the memory access duration of a historical sampling cycle is determined according to the duration of the memory access task in the task queue executed by the processor in the historical sampling cycle, and the memory access duration is related to the performance of the processor. Therefore, the state of the processor can be determined by the recorded historical memory access of the processor, avoiding the inaccurate problem caused by evaluating the state of the processor only according to the real-time operation data of the processor. Further, according to the memory access state of the processor, the operating parameters of the processor are adjusted; the operating parameters include clock frequency and / or power supply voltage. By adjusting the clock frequency and / or power supply voltage according to the memory access state determined by the memory access duration of the historical sampling cycle, the memory access state of the processor can be further refined, and the clock frequency and power supply voltage are no longer directly adjusted at the same time, so that the adjustment objects of different states are subdivided, that is, fine-grained power consumption management is realized, and the accuracy of adjusting the operating parameters can be improved, and the accuracy of power consumption management can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 is a flowchart of a power consumption management method provided by an embodiment of the present invention;

[0017] Figure 2 is a structural diagram of a power consumption management system provided by an embodiment of the present invention;

[0018] Figure 3 is a structural diagram of a power consumption management device provided by an embodiment of the present invention;

[0019] Figure 4 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] Figure 1 is a flowchart of a power consumption management method provided by an embodiment of the present invention, the method is applied to a processor, such as Figure 1 As shown, the method may include the following steps:

[0022] Step 101, at the beginning of the current sampling cycle, determine the memory access state of the processor according to the recorded memory access duration of the historical sampling cycle; the memory access duration of a historical sampling cycle is determined according to the duration of the processor executing the memory access task in the task queue within the historical sampling cycle.

[0023] Step 102: Adjust operating parameters of the processor according to the memory access status of the processor; the operating parameters include clock frequency and / or power supply voltage.

[0024] The processor may be a central processing unit (CPU) of a computer, or may be a graphics processing unit (GPU) or other processors, which are not limited in the embodiments of the present invention. The sampling period refers to the period of the sampling process for obtaining the memory access duration, and the duration of the sampling period may be set according to actual needs. For example, the duration of a sampling period may be set to 200 microseconds, or may be set to other values, which are not limited in the embodiments of the present invention.

[0025] The above-mentioned start of the current sampling cycle refers to the beginning of the current sampling cycle, at which time the memory access duration of the current sampling cycle has not yet been obtained. The above-mentioned historical sampling cycle refers to the sampling cycle before the current sampling cycle. Correspondingly, the memory access duration of the above-mentioned recorded historical sampling cycle refers to the memory access duration obtained in the sampling cycle before the current sampling cycle. Among them, one memory access duration can be obtained in one sampling cycle, so the number of the above-mentioned historical sampling cycles is consistent with the number of corresponding memory access durations. The above-mentioned historical sampling cycle can be one or more.

[0026] Optionally, the memory access task in the task queue refers to a memory access request whose memory access address does not hit the cache, and the number of the memory access tasks in the task queue is one or more.

[0027] The memory access duration refers to the time required for the processor to perform a memory access task within a sampling period, and the memory access task is used to indicate a memory access operation to the memory. The task queue refers to the cache queue in the processor, or the secondary cache invalidation status record table (MSHR, miss queue, miss buffer, etc.) of the processor. It should be noted that when the processor receives a memory access request, if the memory access address of the memory access request is an address in the cache, the execution time of the processor to execute the memory access request is short and can be ignored. When the memory access address of the memory access request is not an address in the cache, it indicates that the memory access address at this time is an address in the external memory, that is, the memory access address does not hit the cache. At this time, the execution time of the processor to execute the memory access request is long, and the memory access request will be recorded in the task queue until the processor completes the memory access request, and then delete the memory access request from the task queue. The memory access task refers to a memory access request whose memory access address does not hit the cache, that is, a request to perform a memory access operation on the external memory.

[0028] Optionally, if there are multiple memory access tasks in a task queue of a historical sampling period, the memory access duration of the historical sampling period is the execution duration of the memory access critical path within the historical sampling period, and the memory access critical path refers to the longest dependency chain between memory access tasks with dependencies in the task queue.

[0029] Further, in any sampling period, the number of memory access tasks in the task queue may be one or more, depending on the number of memory access requests received by the processor. Specifically, if in any sampling period, the number of memory access tasks in the task queue is more than one, the execution time of the critical path of memory access in the sampling period may be used as the memory access time of the sampling period. Among them, the critical path of memory access refers to the longest dependency chain between memory access tasks with dependency relationships. Having a dependency relationship means that the memory access result of another memory access task must be obtained before executing a memory access task. For example, the memory access result of memory access task B must be obtained before executing memory access task A, that is, memory access task B must be executed before memory access task A can be executed, so that a dependency chain is formed from B to A, that is, memory access task A and memory access task B have a dependency relationship. Correspondingly, there may be multiple dependency chains in the task queue in a sampling period, and of course there may be one dependency chain. When there is a dependency chain, the above memory access time is the time to execute the memory access tasks on the dependency chain. When there are multiple dependency chains, since the processor can execute multiple memory access tasks at the same time, the execution time of each dependency chain can be obtained separately, and the dependency chain with the longest execution time is taken as the above-mentioned memory access critical path. Accordingly, the execution time of the memory access critical path is taken as the memory access time of the sampling period.

[0030] For example, if there are five memory access tasks C, D, E, F, and G in a sampling cycle, G needs to execute 10 nanoseconds and depends on E; F needs to execute 5 nanoseconds and depends on E; E needs to execute 10 nanoseconds and depends on D; D needs to execute 5 nanoseconds and has no dependency; C needs to execute 30 nanoseconds and has no dependency. Then there will be three dependency chains: D to E to F, D to E to G, and C. The execution time of these three dependency chains is 20 nanoseconds, 25 nanoseconds, and 30 nanoseconds, respectively, so the critical path for memory access of these tasks is C. Since current processors can execute multiple memory access tasks at the same time, that is to say, the above three dependency chains can be executed at the same time. When the three dependency chains are executed at the same time, it takes at least 30 nanoseconds to complete the five memory access tasks, so 30 nanoseconds can be used as the memory access time of the sampling cycle.

[0031] It should be noted that the number of memory access tasks that the above-mentioned task queue can record is usually limited, and the number of memory access tasks in a sampling period is usually much larger than the maximum capacity of the task queue. Therefore, all memory access tasks in a sampling period enter the above-mentioned task queue in order. When there is a dependency relationship among several memory access tasks, these several memory access tasks enter the task queue in the order of the dependency chain. In any sampling period, the embodiment of the present invention can determine the memory access duration of this sampling period according to the duration of the memory access task in the above-mentioned task queue, that is, the time point at which the first memory access task is recorded in the queue is determined as the starting time point, and the time point at which the last memory access task is deleted is determined as the termination time point, thereby the memory access duration of this sampling period can be obtained according to the difference between the termination time point and the starting time point.

[0032] Among them, the above-mentioned clock frequency and power supply voltage are the operating parameters of the processor, and the size of the operating parameters is directly related to the performance and power consumption of the processor. It should be noted that the power consumption of the processor is proportional to the clock frequency and the power supply voltage, that is, the higher the clock frequency and the power supply voltage, the greater the power consumption of the processor. The performance of the processor is also related to the clock frequency. It is understandable that the higher the clock frequency, the higher the response efficiency of the processor, and thus the higher the performance. Therefore, during the operation of the processor, it is necessary to adjust the operating parameters according to the actual needs of the processor, while avoiding excessive power consumption of the processor and avoiding too low performance of the processor.

[0033] Among them, the above-mentioned memory access status can be used to indicate the frequency of the processor performing memory access tasks. It should be noted that the operating tasks of the processor may include computing tasks and memory access tasks. When the processor performs computing tasks more frequently, it indicates that the processor has higher requirements for operating performance, and a higher clock frequency should be maintained at this time. Correspondingly, when the processor performs memory access tasks more frequently, it indicates that the processor has lower requirements for operating performance, and a lower clock frequency and / or a lower power supply voltage can be maintained at this time to reduce the power consumption of the processor.

[0034] Specifically, the above memory access state can be determined by the proportion of the memory access duration of the historical sampling cycle in the historical sampling cycle. It should be noted that for the processor, the change of the memory access state within a period of time is small, so the embodiment of the present invention can use the memory access duration of the historical sampling cycle to predict the memory access state of the processor, and the memory access state in the historical sampling cycle can be used as the current memory access state of the processor, and then the operating parameters can be adjusted according to the memory access state.

[0035] It is understandable that the more the number of memory access durations of the recorded historical sampling cycles is, the higher the accuracy of the determined memory access state of the processor is. Therefore, in the embodiment of the present invention, a quantity threshold can be pre-set, and when the number of memory access durations of the recorded historical sampling cycles reaches the quantity threshold, the operation of the above step 101 is performed again. The quantity threshold can be set according to actual needs, and the embodiment of the present invention does not limit this.

[0036] In summary, at the beginning of the current sampling cycle, the embodiment of the present invention determines the memory access state of the processor according to the memory access duration of the recorded historical sampling cycle, and the memory access duration of a historical sampling cycle is determined according to the duration of the memory access task in the task queue executed by the processor in the historical sampling cycle, and the memory access duration is related to the performance of the processor, so the state of the processor can be determined by the recorded historical memory access of the processor, avoiding the inaccurate problem caused by evaluating the state of the processor only based on the real-time operation data of the processor. Further, according to the memory access state of the processor, the operating parameters of the processor are adjusted; the operating parameters include clock frequency and / or power supply voltage, and by adjusting the clock frequency and / or power supply voltage according to the memory access state determined by the memory access duration of the historical sampling cycle, the memory access state of the processor can be further refined, and the clock frequency and the power supply voltage are no longer directly adjusted at the same time, so that the adjustment objects of different states are subdivided, that is, fine-grained power consumption management is realized, and the accuracy of the adjustment of the operating parameters can be improved, and the accuracy of the power consumption management can be improved.

[0037] Optionally, in the embodiment of the present invention, adjusting the operating parameters of the processor according to the memory access state of the processor may include the following steps:

[0038] S21. If the memory access state of the processor is a continuous intensive memory access state, adjust the clock frequency and the power supply voltage.

[0039] S22: If the memory access state of the processor is a burst intensive memory access state, adjust the clock frequency.

[0040] Among them, the intensive memory access state refers to the state in which the processor performs memory access tasks more frequently. In the intensive memory access state, the performance requirements of the processor are low, and the power consumption of the processor can be reduced at this time. Furthermore, the above-mentioned continuous intensive memory access state refers to the intensive memory access lasting for a long time, that is, the processor has been in the intensive memory access state within the first preset time length, and the burst intensive memory access state refers to the intensive memory access lasting for a short time, that is, the processor is not in the intensive memory access state within the first preset time length, but is in the intensive memory access state within the second preset time length. It can be understood that the above-mentioned first preset time length is greater than the second preset time length, and both can be set according to actual needs.

[0041] Specifically, when the memory access state of the processor is a continuous intensive memory access state, it indicates that the intensive memory access state of the processor will continue for a long time, that is, the performance requirements of the processor are relatively low for a long time. At this time, the above-mentioned clock frequency and power supply voltage can be adjusted at the same time to minimize the power consumption of the processor. Specifically, the processor can be set to a P state at this time, wherein the P state refers to a control state that controls the performance of the processor by controlling power consumption, and power consumption is related to voltage and frequency. Therefore, by setting the P state, the clock frequency and power supply voltage can be adjusted at the same time. The setting of the above-mentioned P state can be implemented by a preset P state setting component or a P state setting device. When the processor is in a continuous intensive memory access state, a setting signal can be sent to the P state setting component or device to set the P state.

[0042] Accordingly, when the memory access state of the processor is a burst intensive memory access state, it indicates that the intensive memory access state of the processor will not last too long, and due to the limitation of the voltage regulator, the power supply voltage cannot be adjusted multiple times in a short time, and the adjustment interval of the power supply voltage of the processor is usually required to be more than 100 microseconds. Since the processor is in a burst intensive memory access state, if the processor is no longer in an intensive memory access state within 100 microseconds after the power supply voltage is adjusted, then adjusting the power supply voltage at this time will have a certain impact on the performance of the processor. Therefore, the embodiment of the present invention can only adjust the clock frequency when the memory access state of the processor is a burst intensive memory access state. Specifically, the processor can be set to an F state at this time, wherein the F state refers to a control state that controls the performance of the processor by controlling the clock frequency, and therefore, only the clock frequency can be adjusted by setting the F state. The above-mentioned setting of the F state can be implemented by a preset F state setting component or an F state setting device, and a setting signal can be sent to the F state setting component or device when the processor is in a burst intensive memory access state to set the F state.

[0043] Specifically, the setting of the above-mentioned F state can be performed through a frequency divider, and the clock frequency of the processor can be adjusted by inputting different frequency division coefficients into the frequency divider. In addition, since the conversion time of the frequency divider is short, usually in the nanosecond level, the adjustment period of the clock frequency is much shorter than the adjustment period of the power supply voltage, and sub-microsecond power consumption management can be achieved. The operation of adjusting the power supply voltage can be achieved by inputting different target voltages into the power supply device of the processor to adjust the power supply voltage to the target voltage. Among them, the above-mentioned frequency division coefficient and target voltage are determined according to the actual memory access state of the processor and the current operating parameters.

[0044] In an embodiment of the present invention, if the memory access state of the processor is a continuous intensive memory access state, the clock frequency and the power supply voltage are adjusted; if the memory access state of the processor is a burst intensive memory access state, the clock frequency is adjusted. In this way, the clock frequency and / or the power supply voltage can be selectively adjusted according to the actual memory access state of the processor. In the burst intensive memory access state, only the clock frequency needs to be adjusted, and it is no longer limited by the limitation of the voltage regulator, which greatly shortens the power consumption management cycle.

[0045] Optionally, the operation of adjusting the clock frequency in the embodiment of the present invention may specifically include the following steps:

[0046] S31. Determine a target frequency based on the recorded memory access duration of the historical sampling period and the current clock frequency of the processor.

[0047] S32. Determine a target frequency division coefficient based on the target frequency and the current clock frequency.

[0048] S33. Set the clock division factor of the processor to the target division factor, so as to set the clock frequency of the processor to the target frequency.

[0049] The above-mentioned current clock frequency refers to the clock frequency currently used by the processor, and the current clock frequency of the processor can be obtained through a performance monitoring tool (for example, perf). The memory access duration of the above-mentioned recorded historical sampling period can be the memory access duration of any N recorded historical sampling periods closest to the current moment, and the value of N can be set by itself, N is not less than 1, and N is not greater than the number of all recorded historical sampling periods.

[0050] Specifically, since the above-mentioned continuous intensive memory access state and the burst intensive memory access state are both intensive memory access states, in both memory access states, the power consumption of the processor needs to be reduced, that is, the power supply voltage and clock frequency need to be reduced. Therefore, when the clock frequency needs to be reduced, the target frequency is less than the current clock frequency. At this time, the above-mentioned target frequency can be determined by the following formula (1):

[0051]

[0052] After transformation, the following formula (2) can be obtained:

[0053]

[0054] Among them, the above t refers to the total duration of the above N historical sampling periods, that is, N*t s , t sRefers to the duration of a preset sampling cycle. Accordingly, the above cp refers to the memory access duration within the time t, that is, the total value of the memory access duration of the above N historical sampling cycles, the above f0 is the current clock frequency of the processor, f is the above target frequency, and the above x is a preset ratio threshold value, which is used to characterize the acceptable performance degradation ratio and can be set according to actual needs, for example, it can be set to 10%, 12%, 8%, etc., and the embodiment of the present invention does not limit this.

[0055] Specifically, in the above formula, since other parameters are known, the target frequency f can be obtained according to the above formula.

[0056] Furthermore, when the first memory access ratio does not exceed the preset threshold, and the second memory access ratio does not exceed the preset threshold, it indicates that the processor is not in an intensive memory access state at this time. At this time, the processor has a high demand for operating performance, so the performance of the processor should be improved. Accordingly, the operating parameters of the processor should be improved, that is, the power supply voltage and / or clock frequency should be increased. Therefore, when the clock frequency needs to be increased, the target frequency is greater than the current clock frequency. At this time, the target frequency can be determined by the following formula (3):

[0057]

[0058] After transforming formula (3), we can get formula (4):

[0059]

[0060] Among them, the above s is a predetermined memory access share threshold. Specifically, for the processor, the threshold when the processor is at different frequencies can be calculated in advance. Exemplarily, taking the processor containing 8 optional frequencies as an example, the above x can be taken as 10%. After the minimum value of the memory access time when the target frequency is lower than the current frequency is obtained by the above formula 2, the first share threshold is further obtained, as shown in the lower left triangle in the following table. Furthermore, in order to avoid frequent adjustment of the clock frequency, a threshold coefficient with a value range of (0~1) can be set, and the first share threshold obtained by formula (2) is multiplied by the threshold coefficient to obtain the above s. Furthermore, the second share threshold when the target frequency is greater than the current frequency can be calculated by formula (3), that is, the upper right triangle part in the following table.

[0061]

[0062] Among them, f in the above table max Indicates the maximum value of the processor clock frequency. With f0 = (6 / 8)f maxFor example, if the memory access ratio determined by the memory access duration is higher than 0.87 but lower than 0.92, the target frequency is set to (4 / 8)f max , if the memory access ratio determined by the memory access duration is higher than 0.52 but lower than 0.55, the target frequency is (7 / 8)f max , if the determined memory access ratio is between 0.55 and 0.79, the clock frequency remains unchanged.

[0063] Furthermore, the target frequency division coefficient can be determined based on the relationship between the target frequency and the current clock frequency. Specifically, the target frequency division coefficient is f / f0. Furthermore, by setting the clock frequency division coefficient of the digital frequency division component in the processor to the target frequency division coefficient, the clock frequency of the processor can be adjusted to the target frequency without changing the power supply voltage. Specifically, the determined target frequency division coefficient can be sent to the digital frequency division component, so that the digital frequency division component divides the current clock frequency according to the target frequency division coefficient, so that the clock frequency is adjusted to the target frequency.

[0064] Furthermore, when the clock frequency and the supply voltage need to be adjusted simultaneously, there is a correspondence between different clock frequencies and supply voltages, so after determining the target frequency, the target voltage corresponding to the target frequency can be obtained according to the correspondence. The correspondence can be obtained from the configuration file of the processor or a specified data table.

[0065] In the embodiment of the present invention, the target frequency is determined based on the access duration of the recorded historical sampling cycle and the current clock frequency of the processor; the target frequency division coefficient is determined based on the target frequency and the current clock frequency; the clock frequency division coefficient of the processor is set to the target frequency division coefficient to set the clock frequency of the processor to the target frequency. In this way, the clock frequency can be adjusted by the clock frequency division coefficient of the processor without changing the power supply voltage of the processor.

[0066] Optionally, the operation of determining the memory access state of the processor according to the recorded memory access duration of the historical sampling period may include the following steps in an embodiment of the present invention:

[0067] S41. Calculate a first memory access ratio based on the memory access duration of a historical sampling period under a first condition; the historical sampling period under the first condition refers to a continuous historical sampling period that meets a preset number.

[0068] S42: If the first memory access ratio exceeds a preset threshold, determine that the memory access state of the processor is a continuous intensive memory access state.

[0069] S43: If the first memory access ratio does not exceed the preset threshold, calculate the second memory access ratio based on the memory access duration of the historical sampling period of the second condition; the historical sampling period of the second condition refers to the historical sampling period that meets the preset time point.

[0070] S44: If the second memory access ratio exceeds the preset threshold, determine that the memory access state of the processor is a burst intensive memory access state.

[0071] Among them, the above-mentioned preset number can be the number of all historical sampling periods that have been recorded, and of course it can also be a number set by oneself, and the embodiment of the present invention does not limit this. The above-mentioned preset time point can be the most recent one, that is, the most recently recorded historical sampling period before the current sampling period, or it can also be the most recent 2 or 3, which can be set by oneself according to actual needs, and the embodiment of the present invention does not limit this. It should be noted that in order to ensure the timeliness of the determined memory access state, the historical sampling period of the above-mentioned first condition can be a historical sampling period whose recording time is close to the current moment and meets the preset number, that is, the most recently recorded preset number of historical sampling periods before the current sampling period. Correspondingly, the historical sampling period of the above-mentioned second condition can also be a historical sampling period whose recording time is close to the current moment and meets the preset time point, that is, the most recently recorded historical sampling period that meets the preset time point before the current sampling period.

[0072] Among them, the memory access ratio refers to the proportion of time occupied by executing memory access tasks during the operation of the processor. Correspondingly, the above-mentioned first memory access ratio refers to the proportion of time occupied by executing memory access tasks within the historical sampling period of the first condition. The above-mentioned second memory access ratio refers to the proportion of time occupied by executing memory access tasks within the historical sampling period of the second condition. The above-mentioned preset thresholds can be set by themselves. For example, the preset thresholds can be set to 70%, or 80%, of course, it can also be 75%, etc., and the embodiments of the present invention do not limit this.

[0073] Specifically, when the memory access ratio exceeds the preset threshold, it indicates that the memory access state of the processor is an intensive memory access state. Correspondingly, when the memory access ratio does not exceed the preset threshold, it indicates that the memory access state of the processor is not an intensive memory access state. Further, when the first memory access ratio obtained based on the historical sampling period of the first condition exceeds the preset threshold, it can be judged that the intensive memory access state of the processor lasts for a long time, and at this time, it can be determined that the memory access state of the processor is a continuous intensive memory access state. In the case where the first memory access ratio does not exceed the preset threshold, it can be determined that the intensive memory access state of the processor has not lasted for a long time. At this time, the second memory access ratio can be further obtained according to the historical sampling period that meets the preset time point, and the memory access state of the processor in the historical sampling period at the preset time point can be determined. In the case where the second memory access ratio exceeds the preset threshold, it indicates that the processor is in an intensive memory access state in the historical sampling period at the preset time point. At this time, it can be judged that the intensive memory access state of the processor is sudden, and the memory access state of the processor can be determined to be a sudden intensive memory access state.

[0074] The embodiment of the present invention calculates the first memory access ratio based on the memory access duration of the historical sampling cycle of the first condition; the historical sampling cycle of the first condition refers to the historical sampling cycle that continuously meets the preset number; if the first memory access ratio exceeds the preset threshold, it is determined that the memory access state of the processor is a continuous intensive memory access state; if the first memory access ratio does not exceed the preset threshold, the second memory access ratio is calculated based on the memory access duration of the historical sampling cycle of the second condition; the historical sampling cycle of the second condition refers to the historical sampling cycle that meets the preset time point; if the second memory access ratio exceeds the preset threshold, it is determined that the memory access state of the processor is a burst intensive memory access state. In this way, through the memory access duration of the historical sampling cycles of different conditions, the memory access state of the processor can be judged more finely, and the accuracy of power consumption management is further improved.

[0075] Optionally, the embodiment of the present invention may calculate the target memory access ratio through the following steps:

[0076] S51. Based on the memory access duration of the historical sampling period of the target condition, obtain a target memory access duration corresponding to the target condition.

[0077] S52: Determine the target historical duration corresponding to the target condition based on the target quantity of the historical sampling period corresponding to the target condition and the duration of the sampling period.

[0078] S53. Determine the ratio of the target memory access duration to the target historical duration as the target memory access ratio corresponding to the target condition; wherein, the target condition is the first condition, and the target memory access ratio is the first memory access ratio; or, the target condition is the second condition, and the target memory access ratio is the second memory access ratio.

[0079] Wherein, when the target condition is the first condition, the target quantity is the preset quantity, and the target memory access ratio corresponding to the target condition is the first memory access ratio. Correspondingly, when the target condition is the second condition, the target quantity is the number of historical sampling cycles that meet the preset time point, and the target memory access ratio corresponding to the target condition is the second memory access ratio.

[0080] Among them, the above-mentioned target memory access duration refers to the total value of the memory access duration of the historical sampling period of the target condition, that is, the memory access duration of the historical sampling period of the target condition is added to obtain the total duration of the processor executing the memory access task within the historical sampling period of the target condition. Correspondingly, the above-mentioned target historical duration refers to the total duration of the historical sampling period of the target condition. Specifically, since the duration of each sampling period is pre-set and fixed, the embodiment of the present invention can multiply the target number corresponding to the target condition and the duration of the pre-set sampling period to obtain the target historical duration corresponding to the target condition.

[0081] Furthermore, the memory access ratio refers to the proportion of the time required for the processor to perform memory access tasks during the running process. Therefore, the embodiment of the present invention can directly determine the ratio of the above-mentioned target memory access duration to the target historical duration as the target memory access ratio.

[0082] Among them, the above S51~S53 can be implemented through a sliding filter, and the memory access duration of the historical sampling period of the target condition can be used as a sample point. The sliding filter can accumulate data for all sample points and perform average calculation to obtain the above target memory access ratio.

[0083] The embodiment of the present invention obtains the target memory access duration corresponding to the target condition by the memory access duration of the historical sampling cycle based on the target condition; determines the target historical duration corresponding to the target condition based on the target number of the historical sampling cycle corresponding to the target condition and the duration of the sampling cycle; determines the ratio of the target memory access duration to the target historical duration as the target memory access ratio corresponding to the target condition; wherein, if the target condition is the first condition, the target memory access ratio is the first memory access ratio; or, if the target condition is the second condition, the target memory access ratio is the second memory access ratio. In this way, the target memory access ratios corresponding to different conditions can be obtained according to the memory access durations of the historical sampling cycles of different conditions.

[0084] Optionally, the embodiment of the present invention may specifically include the following content: determining the memory access duration of the current sampling period, and recording the memory access duration of the current sampling period.

[0085] The sampling period in the embodiment of the present invention may be continuous or intermittent. That is, after obtaining the memory access duration of a sampling period in the embodiment of the present invention, the memory access duration of the next sampling period may be obtained immediately, or, after a sampling period ends, the next sampling period may be continued after a period of time. The setting may be made according to actual needs, and the embodiment of the present invention does not limit this.

[0086] Among them, the above-mentioned determination of the memory access duration of the current sampling cycle can be performed by hardware counting, or can also be performed by software, and the embodiment of the present invention does not limit this. The above-mentioned operation of recording the memory access duration of the current sampling cycle can be to pre-set a record data table, and the record data table can record the memory access time of each determined sampling cycle in chronological order. It can be understood that after the memory access duration of the current sampling cycle is recorded, at the beginning of the next sampling cycle, the recorded "memory access duration of the current sampling cycle" will be determined as the memory access duration of the recorded historical sampling cycle, and the next sampling cycle will be determined as the new "current sampling cycle".

[0087] In the embodiment of the present invention, the memory access duration of the current sampling cycle is determined and recorded. In this way, the acquired memory access duration of the current sampling cycle can be recorded, and then the memory access duration of the recorded historical sampling cycle can be updated, ensuring that the memory access duration of the recorded historical sampling cycle is synchronized with the operation process of the processor in real time, thereby ensuring the timeliness and accuracy of power consumption management.

[0088] Optionally, the embodiment of the present invention further includes: determining the execution time of the critical memory access path of each sampling period. The embodiment of the present invention may specifically include the following steps:

[0089] S61. Acquire a task queue within the current sampling period; the task queue includes a plurality of queue items.

[0090] S62. When there is a memory access task for any queue item among the multiple queue items, start counting according to the clock cycle of the processor through a first counter corresponding to the queue item until there is no memory access task for the queue item, then stop counting, and use the current value of the first counter as the first duration corresponding to the queue item.

[0091] S63: When there is no memory access task for any queue item among the multiple queue items, determine the maximum value of the first durations corresponding to the queue items as the second duration.

[0092] S64: Determine the second duration at the end of the current sampling period as the execution duration of the memory access critical path of the current sampling period.

[0093] The task queue mentioned above refers to the Cache queue, which records the memory access tasks currently being processed by the update processor in real time, and there are usually several queue items in the queue, and the memory access tasks of different queue items can be performed simultaneously. The number of queue items in the queue is fixed. If there is a task in each queue item in the queue, it means that the current queue is full. At this time, only when any memory access task is completed and the corresponding queue item is empty, a new memory access task will be added to the queue.

[0094] Specifically, the embodiment of the present invention can allocate a local counter (Local_Counter) to each queue item of the Cache queue, which can be called the first counter. It can be understood that the initial value of the first counter can be 0. In the current sampling period, the embodiment of the present invention can obtain the queue content in real time from the storage location of the Cache queue. When there is a memory access task in any queue item, it indicates that the processor is executing the memory access task. At this time, the first counter corresponding to the queue item starts counting and increases by 1 in each clock cycle. When there is no more memory access task in the queue item, it indicates that the memory access task has been completed. At this time, the first counter stops counting, so that the first duration of the queue item can be obtained, that is, the memory access duration of the memory access task on the queue item.

[0095] It should be noted that each queue item in the task queue has a first counter, and the memory access duration of the memory access task of each queue item is usually inconsistent, that is, the time when the first counter corresponding to each queue item stops counting is not uniform. The embodiment of the present invention can obtain the first duration corresponding to each queue item when any first counter stops counting, that is, when any queue item does not have a memory access task, and select the maximum value, that is, the value with the longest memory access duration, as the above-mentioned second duration. It can be understood that step S63 needs to be executed once when any first counter stops counting to realize the update of the second duration. At each update, the determined second duration is the execution duration of the current critical dependency path.

[0096] Furthermore, at the end of the current sampling period, the current second duration is the key dependency path within the current sampling period, that is, the memory access duration of the longest dependency chain. At this time, the current second duration can be directly determined as the memory access duration of the current sampling period.

[0097] Optionally, the power consumption management method provided by the embodiment of the present invention may further include the following operations:

[0098] Before the end of the current sampling period, if there is a new task in any queue item in the task queue, the initial value of the first counter corresponding to the queue item is set to the current second duration, and the first counter starts counting according to the clock cycle of the processor.

[0099] Among them, after the memory access task enters the task queue, it is randomly assigned to any queue item, and the above-mentioned newly added task refers to the memory access task newly added to the task queue. It can be understood that before the newly added task enters the task queue, the above-mentioned second duration has usually been obtained in the current sampling period. At this time, the execution duration of the newly added task should be added to the total memory access duration in the current sampling period. Therefore, the embodiment of the present invention can use the current second duration as the initial value of the first counter corresponding to the queue item when there is a newly added task in any queue item, so that the first counter starts counting based on the current second duration, thereby realizing the accumulation of memory access duration.

[0100] Furthermore, when the newly added task is completed, that is, there is no memory access task in the queue item of the newly added task, the above step S63 can be re-executed to update the second duration again.

[0101] Optionally, after the first counter corresponding to the queue item starts counting according to the clock cycle of the processor, the embodiment of the present invention may further include the following operations:

[0102] At the end of each of the clock cycles, if the current value of the first counter corresponding to any queue item is greater than the current second time length, the current value of the second counter is increased by 1.

[0103] The above-mentioned determining the second duration at the end of the current sampling period as the memory access duration of the current sampling period may specifically include:

[0104] At the end of the current sampling period, the current value of the second counter is determined as the memory access duration of the current sampling period.

[0105] Among them, the above-mentioned second counter can be pre-allocated for the task queue, and can be called a global counter (Critical_Path). Specifically, since the first counter starts counting according to the clock cycle, that is, the first counter is incremented by 1 at the end of each clock cycle, the embodiment of the present invention can compare the value of each first counter with the size of the current second duration at the end of each clock cycle. When the current value of any first counter is larger than the second duration, it indicates that the memory access task of the queue item corresponding to the first counter has not been completed. At this time, the second duration will not be updated according to the value of the first counter, that is, the second duration at this time cannot represent the duration spent on the current execution of the memory access task. In the case of an unfinished memory access task, the embodiment of the present invention can make the current value of the second counter plus 1, so that the duration of the second counter can include the memory access duration of the completed memory access task and the memory access duration of the unfinished memory access task, and keep consistent with the actual memory access duration. By setting a second counter, the embodiment of the present invention can obtain the memory access time spent by the memory access task in the current sampling period in real time by reading the value of the second counter during the current sampling period. There is no need to wait until the end of the current sampling period to obtain the memory access time, thereby improving the flexibility of obtaining the memory access time.

[0106] Furthermore, since the value of the second counter can be consistent with the actual memory access duration, in the embodiment of the present invention, when the current sampling period ends, the current value of the second counter can be determined as the memory access duration of the current sampling period.

[0107] Exemplarily, an embodiment of the present invention shows an implementation method for determining the memory access duration of the current sampling period:

[0108]

[0109]

[0110] Among them, the above sampling means sampling is in progress, that is, within the current sampling period; the above entry() is used to determine whether an item in the task queue has just entered the queue, that is, whether there is a new task for a certain item; the above active() is used to determine whether there is a memory access task for a certain item in the task queue; correspondingly, the above finish() is used to determine whether an item in the task queue has been completed, that is, whether there is no memory access task. The above Local_Counter represents the above first counter, and Global_Counter is used to represent the above second duration; the above Critical_Path is used to represent the above second counter; the initial values ​​of the above second duration and the second counter are both 0. The above i is used to represent the i-th queue item in the task queue, and the above QUEUE is used to represent the number of queue items in the task queue.

[0111] It can be seen from the above content that the embodiment of the present invention allocates a first counter to each queue item. When there is a memory access task in any queue item, the corresponding first counter is incremented by 1, and if there is a new task in a queue item, the current Global_Counter is assigned to the Local_Counter corresponding to the queue item, so as to realize the accumulation of memory access time. In each clock cycle, the size of each Local_Counter and Global_Counter is compared. If there is a Local_Counter greater than the Global_Counter, the Critical_Path is incremented by 1. The memory access time of the completed memory access task and the memory access time of the unfinished memory access task can be obtained through Critical_Path, and then at the end of the sampling period, the total time required for the processor to perform the memory access task during the sampling period can be obtained by returning Critical_Path.

[0112] In an embodiment of the present invention, by acquiring the task queue within the current sampling period; when any of the multiple queue items in the task queue has a memory access task, the first counter corresponding to the queue item starts counting according to the clock cycle of the processor until the queue item does not have a memory access task, stops counting, and uses the current value of the first counter as the first duration corresponding to the queue item. In the case that any of the queue items does not have a memory access task, the maximum value of the first durations corresponding to the queue items is determined as the second duration; the second duration at the end of the current sampling period is determined as the memory access duration of the current sampling period. In this way, in an embodiment of the present invention, a counter can be set for the queue items in the task queue, that is, the memory access duration within a sampling period can be determined by hardware, without the need to implement it by software methods such as an operating system. The speed of determining the memory access duration by a hardware counter is faster than that by a software method, thereby improving the efficiency of determining the memory access state of the processor and further shortening the cycle of power consumption management.

[0113] Figure 2 is a structural diagram of a power consumption management system provided by an embodiment of the present invention, such as Figure 2 As shown, the system may include a load sensing component, a load analysis component, an F state setting component, and a P state setting component. Among them, the P state setting component can adjust the clock device and the power supply device at the same time. The power supply device is used to provide a power supply voltage to the CPU. The clock device can send a signal to the device in the computer (including the CPU) according to a certain period. The period of the signal sent by the clock device is the clock period of the processor. Correspondingly, the frequency of the signal sent is the clock frequency.

[0114] The load sensing component can be arranged in the memory access component in the CPU, and the load sensing component can be used to determine the memory access duration of the sampling cycle at the beginning of a sampling cycle, and send the determined memory access duration to the load analysis component at the end of the sampling cycle, so that it records the memory access duration. Correspondingly, the load analysis component can receive the memory access duration sent by the load sensing component, record it, and when the load sensing component starts a new round of sampling cycle, determine the memory access state of the processor according to the memory access duration of the recorded historical sampling cycle, and send the operating parameter adjustment signal to the P state setting component or the F state setting component according to the memory access state. Specifically, when the memory access state is a continuous intensive memory access state, the adjustment signal can be sent to the P state setting component, so that it adjusts the power supply voltage and clock frequency at the same time, and when the memory access state is a burst intensive memory access state, the adjustment signal can be sent to the F state setting component, so that it adjusts the clock frequency of the CPU through the clock division coefficient. Wherein, when the memory access state is a continuous intensive memory access state, the division coefficient set by the F state setting component can be kept as 1.

[0115] Figure 3 is a structural diagram of a power consumption management device provided by an embodiment of the present invention, the device is applied to a processor, and the device 20 may include:

[0116] The state determination module 201 is used to determine the memory access state of the processor according to the memory access duration of the recorded historical sampling cycle at the beginning of the current sampling cycle; the memory access duration of a historical sampling cycle is determined according to the duration of the processor executing the memory access task in the task queue within the historical sampling cycle;

[0117] The parameter adjustment module 202 is used to adjust the operating parameters of the processor according to the memory access state of the processor; the operating parameters include clock frequency and / or power supply voltage.

[0118] Optionally, the parameter adjustment module 202 includes:

[0119] A first adjustment submodule, configured to adjust the clock frequency and the supply voltage if the memory access state of the processor is a continuous intensive memory access state;

[0120] The second adjustment submodule is used to adjust the clock frequency if the memory access state of the processor is a burst intensive memory access state.

[0121] Optionally, the second adjustment submodule is specifically used to:

[0122] Determining a target frequency based on the memory access duration of the recorded historical sampling period and the current clock frequency of the processor;

[0123] Determining a target frequency division coefficient based on the target frequency and the current clock frequency;

[0124] The clock frequency division factor of the processor is set to the target frequency division factor, so as to set the clock frequency of the processor to the target frequency.

[0125] Optionally, the state determination module 201 includes:

[0126] A first calculation submodule, configured to calculate a first memory access ratio based on a memory access duration of a historical sampling period of a first condition; the historical sampling period of the first condition refers to a historical sampling period that continuously meets a preset number;

[0127] A first determining submodule, configured to determine that the memory access state of the processor is a continuous intensive memory access state if the first memory access ratio exceeds a preset threshold;

[0128] A second calculation submodule is configured to calculate a second memory access ratio based on the memory access duration of a historical sampling period of a second condition if the first memory access ratio does not exceed the preset threshold; the historical sampling period of the second condition refers to a historical sampling period that meets a preset time point;

[0129] The second determining submodule is configured to determine that the memory access state of the processor is a burst intensive memory access state if the second memory access proportion exceeds the preset threshold.

[0130] Optionally, the device 20 further includes:

[0131] A memory access duration acquisition module, used to acquire a target memory access duration corresponding to the target condition based on the memory access duration of a historical sampling period of the target condition;

[0132] A historical duration acquisition module, used to determine the target historical duration corresponding to the target condition based on the target quantity of the historical sampling period corresponding to the target condition and the duration of the sampling period;

[0133] A ratio determination module, used to determine the ratio of the target memory access duration to the target historical duration as the target memory access ratio corresponding to the target condition;

[0134] Among them, the target condition is the first condition, and the target memory access ratio is the first memory access ratio; or, the target condition is the second condition, and the target memory access ratio is the second memory access ratio.

[0135] Optionally, the memory access task in the task queue refers to a memory access request whose memory access address does not hit the cache, and the number of the memory access tasks in the task queue is one or more.

[0136] Optionally, if there are multiple memory access tasks in a task queue of a historical sampling period, the memory access duration of the historical sampling period is the execution duration of the memory access critical path within the historical sampling period, and the memory access critical path refers to the longest dependency chain between memory access tasks with dependencies in the task queue.

[0137] Optionally, the device is further used to: determine the execution time of the memory access critical path of each sampling cycle; the device 20 also includes:

[0138] A queue acquisition submodule is used to acquire the task queue within the current sampling period; the task queue includes multiple queue items;

[0139] a counting submodule, configured to, when any queue item among the multiple queue items has a memory access task, start counting according to the clock cycle of the processor through a first counter corresponding to the queue item until there is no memory access task for the queue item, stop counting, and use the current value of the first counter as the first duration corresponding to the queue item;

[0140] a maximum determination submodule, configured to determine, when there is no memory access task for any queue item among the plurality of queue items, a maximum value among the first durations corresponding to the queue items as a second duration;

[0141] The end determination submodule is used to determine the second duration at the end of the current sampling period as the execution duration of the memory access critical path of the current sampling period.

[0142] In summary, the power consumption management device provided by the embodiment of the present invention determines the memory access state of the processor according to the memory access duration of the recorded historical sampling cycle at the beginning of the current sampling cycle, and the memory access duration of a historical sampling cycle is determined according to the duration of the memory access task in the task queue executed by the processor in the historical sampling cycle, and the memory access duration is related to the performance of the processor, so the state of the processor can be determined by the recorded historical memory access of the processor, avoiding the inaccurate problem caused by evaluating the state of the processor only according to the real-time operation data of the processor. Further, according to the memory access state of the processor, the operating parameters of the processor are adjusted; the operating parameters include clock frequency and / or power supply voltage, and by adjusting the clock frequency and / or power supply voltage according to the memory access state determined by the memory access duration of the historical sampling cycle, the memory access state of the processor can be further refined, and the clock frequency and the power supply voltage are no longer directly adjusted at the same time, so that the adjustment objects of different states are subdivided, that is, fine-grained power consumption management is realized, and the accuracy of adjusting the operating parameters can be improved, and the accuracy of power consumption management can be improved.

[0143] The present invention also provides an electronic device, see Figure 4 , including: a processor 701, a memory 702, and a computer program 7021 stored in the memory and executable on the processor, wherein the processor implements the power consumption management method of the aforementioned embodiment when executing the program.

[0144] The present invention also provides a readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the power consumption management method of the aforementioned embodiment.

[0145] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0146] The algorithm and display provided herein are not inherently related to any particular computer, virtual system or other device. Various general purpose systems can also be used together with the teachings based on this. According to the above description, it is obvious that the structure required for constructing such systems. In addition, the present invention is not directed to any specific programming language either. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the description of the above specific languages ​​is for disclosing the best mode of the present invention.

[0147] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0148] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than the features explicitly recited in each claim. More specifically, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Therefore, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, with each claim itself serving as a separate embodiment of the present invention.

[0149] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0150] The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention may also be implemented as a device or apparatus program for executing part or all of the methods described herein. Such a program for implementing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0151] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0152] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0153] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

[0154] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A power consumption management method, characterized in that: Applied to a processor, the method comprises: At the beginning of the current sampling cycle, the memory access state of the processor is determined according to the memory access duration of the recorded historical sampling cycle; the memory access duration of a historical sampling cycle is determined according to the duration of the processor executing the memory access task in the task queue within the historical sampling cycle; According to the memory access state of the processor, the operating parameters of the processor are adjusted; the operating parameters include clock frequency and / or power supply voltage.

2. The method according to claim 1, characterized in that: The step of adjusting the operating parameters of the processor according to the memory access state of the processor includes: If the memory access state of the processor is a continuous intensive memory access state, adjusting the clock frequency and the power supply voltage; If the memory access state of the processor is a burst intensive memory access state, the clock frequency is adjusted.

3. The method according to claim 2, characterized in that: The adjusting the clock frequency comprises: Determining a target frequency based on the memory access duration of the recorded historical sampling period and the current clock frequency of the processor; Determining a target frequency division coefficient based on the target frequency and the current clock frequency; The clock frequency division factor of the processor is set to the target frequency division factor, so as to set the clock frequency of the processor to the target frequency.

4. The method according to claim 1, characterized in that: The determining the memory access state of the processor according to the recorded memory access duration of the historical sampling cycle includes: Calculate the first memory access ratio based on the memory access duration of the historical sampling period of the first condition; the historical sampling period of the first condition refers to a historical sampling period that continuously meets a preset number; If the first memory access ratio exceeds a preset threshold, determining that the memory access state of the processor is a continuous intensive memory access state; If the first memory access ratio does not exceed the preset threshold, the second memory access ratio is calculated based on the memory access duration of the historical sampling period of the second condition; the historical sampling period of the second condition refers to the historical sampling period that meets the preset time point; If the second memory access ratio exceeds the preset threshold, it is determined that the memory access state of the processor is a burst intensive memory access state.

5. The method according to claim 4, characterized in that: The target memory access ratio is calculated by the following steps: Based on the memory access duration of the historical sampling period of the target condition, obtaining the target memory access duration corresponding to the target condition; Determine the target historical duration corresponding to the target condition based on the target quantity of the historical sampling period corresponding to the target condition and the duration of the sampling period; Determine the ratio of the target memory access duration to the target historical duration as the target memory access ratio corresponding to the target condition; Among them, the target condition is the first condition, and the target memory access ratio is the first memory access ratio; or, the target condition is the second condition, and the target memory access ratio is the second memory access ratio.

6. The method according to claim 1, characterized in that: The memory access task in the task queue refers to a memory access request whose memory access address does not hit the cache, and the number of the memory access tasks in the task queue is one or more.

7. The method according to claim 1, characterized in that: If there are multiple memory access tasks in a task queue of a historical sampling period, the memory access duration of the historical sampling period is the execution duration of the memory access critical path within the historical sampling period, and the memory access critical path refers to the longest dependency chain between memory access tasks with dependencies in the task queue.

8. The method according to claim 7, characterized in that: Determine the execution time of the critical path of memory access in each sampling cycle, including: Acquire a task queue within the current sampling period; the task queue includes a plurality of queue items; When any queue item among the multiple queue items has a memory access task, count the first counter corresponding to the queue item according to the clock cycle of the processor until the queue item has no memory access task, stop counting, and use the current value of the first counter as the first duration corresponding to the queue item; In the case that there is no memory access task for any queue item among the multiple queue items, determining a maximum value among the first durations corresponding to the queue items as the second duration; The second duration at the end of the current sampling period is determined as the execution duration of the memory access critical path of the current sampling period.

9. A power consumption management device, characterized in that: Applied to a processor, the device comprises: A state determination module is used to determine the memory access state of the processor according to the memory access duration of the recorded historical sampling cycle at the beginning of the current sampling cycle; the memory access duration of a historical sampling cycle is determined according to the duration of the processor executing the memory access task in the task queue within the historical sampling cycle; A parameter adjustment module is used to adjust the operating parameters of the processor according to the memory access state of the processor; the operating parameters include clock frequency and / or power supply voltage.

10. The device according to claim 9, characterized in that: The parameter adjustment module comprises: A first adjustment submodule, configured to adjust the clock frequency and the supply voltage if the memory access state of the processor is a continuous intensive memory access state; The second adjustment submodule is used to adjust the clock frequency if the memory access state of the processor is a burst intensive memory access state.

11. The device according to claim 10, characterized in that: The second adjustment submodule is specifically used for: Determining a target frequency based on the memory access duration of the recorded historical sampling period and the current clock frequency of the processor; Determining a target frequency division coefficient based on the target frequency and the current clock frequency; The clock frequency division factor of the processor is set to the target frequency division factor, so as to set the clock frequency of the processor to the target frequency.

12. The device according to claim 9, characterized in that: The state determination module comprises: A first calculation submodule, configured to calculate a first memory access ratio based on a memory access duration of a historical sampling period of a first condition; the historical sampling period of the first condition refers to a historical sampling period that continuously meets a preset number; A first determining submodule, configured to determine that the memory access state of the processor is a continuous intensive memory access state if the first memory access ratio exceeds a preset threshold; A second calculation submodule is configured to calculate a second memory access ratio based on the memory access duration of a historical sampling period of a second condition if the first memory access ratio does not exceed the preset threshold; the historical sampling period of the second condition refers to a historical sampling period that meets a preset time point; The second determining submodule is configured to determine that the memory access state of the processor is a burst intensive memory access state if the second memory access proportion exceeds the preset threshold.

13. The device according to claim 12, characterized in that: The device also includes: A memory access duration acquisition module, used to acquire a target memory access duration corresponding to the target condition based on the memory access duration of a historical sampling period of the target condition; A historical duration acquisition module, used to determine the target historical duration corresponding to the target condition based on the target quantity of the historical sampling period corresponding to the target condition and the duration of the sampling period; A ratio determination module, used to determine the ratio of the target memory access duration to the target historical duration as the target memory access ratio corresponding to the target condition; Among them, the target condition is the first condition, and the target memory access ratio is the first memory access ratio; or, the target condition is the second condition, and the target memory access ratio is the second memory access ratio.

14. The device according to claim 9, characterized in that: The memory access task in the task queue refers to a memory access request whose memory access address does not hit the cache, and the number of the memory access tasks in the task queue is one or more.

15. The device according to claim 9, characterized in that: If there are multiple memory access tasks in a task queue of a historical sampling period, the memory access duration of the historical sampling period is the execution duration of the memory access critical path within the historical sampling period, and the memory access critical path refers to the longest dependency chain between memory access tasks with dependencies in the task queue.

16. The device according to claim 15, characterized in that: The device is also used to: determine the execution time of the memory access critical path of each sampling cycle; the device also includes: A queue acquisition submodule is used to acquire the task queue within the current sampling period; the task queue includes multiple queue items; a counting submodule, configured to, when any queue item among the multiple queue items has a memory access task, start counting according to the clock cycle of the processor through a first counter corresponding to the queue item until there is no memory access task for the queue item, stop counting, and use the current value of the first counter as the first duration corresponding to the queue item; a maximum determination submodule, configured to determine, when there is no memory access task for any queue item among the plurality of queue items, a maximum value among the first durations corresponding to the queue items as a second duration; The end determination submodule is used to determine the second duration at the end of the current sampling period as the execution duration of the memory access critical path of the current sampling period.

17. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 8 when executing the program.

18. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method according to any one of claims 1 to 8.

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