Access control method of memory device, memory controller, memory device and electronic device

Abstract

The invention provides a method for access control of a memory device with aid of interrupt management and a related apparatus. The method may include receiving, using a memory controller, a set of commands from a host device via a transmission interface circuit within the memory controller; and in response to the set of commands, using the memory controller to perform a set of access operations on a non-volatile memory for the host device, and returning a single message signaling interrupt corresponding to the set of commands to the host device via the transmission interface circuit, the memory device is coupled to the host device for informing the host device of completion of device-side access control of the memory device for the set of commands to allow the host device to complete host-side access control of the host device for the set of commands. For example, the memory controller may dynamically perform configuration adjustments.

Description

Technical Field

[0001] The present invention relates to memory control, and more particularly to a method for performing access control of a memory device by means of interrupt management and related apparatus such as a memory controller of the memory device, the memory device and an electronic device including the memory device. Background Art

[0002] According to the related art, a memory device can be designed to have the ability to simultaneously access the respective storage cells of multiple flash memory chips therein to improve the throughput of data access. However, improper control can reduce the above throughput. For example, if the transmission interface circuit in the memory device is not properly configured, a host accessing the memory device may not be able to complete certain access operations at ideal time points, which may increase the total access time. Therefore, a novel method and related architecture are needed to solve these problems without introducing any side effects or in a way that is unlikely to introduce side effects. Summary of the invention

[0003] Therefore, one of the objects of the present invention is to provide a method for performing access control of a memory device by means of interrupt management and related equipment such as a memory controller of the memory device, the memory device and an electronic device including the memory device to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a method for controlling access to a memory device by means of interrupt management, wherein the method can be applied to a memory controller of the memory device. The memory device can include the memory controller and a non-volatile (NV) memory, the non-volatile memory can include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element can include multiple blocks. The method may include: using the memory controller to receive a set of commands from a host device through a transmission interface circuit in the memory controller, wherein the command count of the set of commands is greater than one, and any command in the set of commands indicates a request to access the memory device; and in response to the set of commands, using the memory controller to perform a set of access operations on the non-volatile memory for the host device, and returning a single message signaled interrupt (MSI) corresponding to the set of commands to the host device through the transmission interface circuit for notifying the host device of completion of device side access control of the memory device for the set of commands, so as to allow the host device to complete the host side access control of the host device for the set of commands, wherein the set of access operations includes a corresponding access operation performed by the memory controller in response to any command in the set of commands.

[0005] In addition to the above method, the present invention further provides a memory controller of a memory device, wherein the memory device may include the memory controller and a non-volatile memory. The non-volatile memory may include at least one non-volatile memory element (e.g., one or more non-volatile memory elements), and the at least one non-volatile memory element may include multiple blocks. In addition, the memory controller includes a processing circuit, which is used to control the memory controller according to multiple host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, wherein the processing circuit is used to perform access control of the memory device by means of interrupt management. The memory controller also includes a transmission interface circuit, and the transmission interface circuit is used to communicate with the host device. For example, the memory controller receives a set of commands from the host device through the transmission interface circuit in the memory controller, wherein the number of commands in the set of commands is greater than one, and any command in the set of commands indicates a request to access the memory device; and in response to the set of commands, the memory controller performs a set of access operations on the non-volatile memory for the host device, and transmits a single message signaling interrupt corresponding to the set of commands back to the host device through the transmission interface circuit to notify the host device of the completion of the device-side access control of the memory device for the set of commands, so as to allow the host device to complete the host-side access control of the host device for the set of commands, wherein the set of access operations includes a corresponding access operation performed by the memory controller in response to any command in the set of commands.

[0006] In addition to the above method, the present invention further provides the memory device including the above memory controller, wherein the memory device includes the non-volatile memory and the memory controller. The non-volatile memory is used to store information. The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

[0007] In addition to the above method, the present invention further provides a related electronic device. The electronic device may include the above memory device, and may further include: the host device, which is coupled to the memory device. The host device may include: at least one processor, which is used to control the operation of the host device; and a power supply circuit, which is coupled to the at least one processor and is used to provide power to the at least one processor and the memory device. In addition, the memory device can provide storage space for the host device.

[0008] According to certain embodiments, the device may include at least a portion (e.g., a portion or all) of the electronic device. For example, the device may include the memory controller in the memory device. For another example, the device may include the memory device. As another example, the device may include the host device. In some examples, the device may include the electronic device.

[0009] According to some embodiments, the memory controller in the memory device may control the operation of the memory device according to the method, and the memory device may be disposed in the electronic device. In addition, the memory device may store data for the host device. The memory device may read the stored data in response to a host command from the host device, and provide the data read from the non-volatile memory to the host device.

[0010] The method and related apparatus of the present invention can ensure that the memory device can operate properly in different situations. In particular, the configuration of the memory device can be dynamically adjusted to optimize host-side access control. For example, by dynamically adjusting aggregation parameters such as aggregation threshold and aggregation time, access control is performed in response to the latest state of the electronic device (or the host device and / or the memory device therein) to improve the throughput (regarding data access). In addition, the method and apparatus of the present invention can solve the problems of the related art without introducing any side effects or in a manner that is unlikely to introduce side effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0012] Figure 2A FIG. 4 is a schematic diagram of an interrupt coalescing controller according to an embodiment of the present invention.

[0013] Figure 2B Draw Figure 2A An example of implementation details of the circuit architecture is shown.

[0014] Figure 2C Draw Figure 2A Another example of implementation details of the circuit architecture is shown.

[0015] Figure 3 The right half thereof shows a dynamically optimized access control scheme according to an embodiment of the present invention, wherein Figure 3 A non-optimized access control scheme is shown on the left half for easier understanding.

[0016] Figure 4 The flowchart is a method for controlling access to a memory device by means of interrupt management according to an embodiment of the present invention.

[0017] Figure 5 Some examples of timing diagrams related to access control are shown.

[0018] Figure 6 Another example of a timing diagram regarding access control is shown.

[0019] Figure 7 Some other examples of timing diagrams related to access control are shown.

[0020] Figure 8 Some more examples of timing diagrams for access control are shown.

[0021] Fig.9A According to an embodiment of the present invention, a workflow of a serving I / O command routine involved in the method is described.

[0022] Fig. 9B Draw Fig.9A The illustrated service I / O command routine involves a workflow of an interrupt service routine (ISR).

[0023] Fig. 10A An example of access control involved in the method is shown. Fig. 10B Another example of access control involved in the method is shown.

[0024]

Explanation of symbols

[0025] 10: Electronic devices

[0026] 50: Host device

[0027] 50B: Host buffer

[0028] 52: Processor

[0029] 54: Power supply circuit

[0030] 58: Transmission interface circuit

[0031] 100: memory device

[0032] 110: memory controller

[0033] 112: Microprocessor

[0034] 112C: Program code

[0035] 112M: Read-only memory

[0036] 114: Control logic circuit

[0037] 116: Random Access Memory 116AM: Temporary Logical to Physical (L2P) Address Mapping Table

[0038] 118: Transmission interface circuit

[0039] 118B: Bottom Circuit

[0040] 118P: Parameter Controller

[0041] 120: Non-volatile (NV) memory 120AM: Global logical to physical (L2P) address mapping table

[0042] 122-1~122-N E :Non-volatile (NV) memory devices

[0043] 200: Interrupt aggregation controller

[0044] 210,220,250: Arithmetic processing circuit

[0045] 230: parameter generation circuit

[0046] 240,256: Adder

[0047] 212,222,252: Multiplier

[0048] 254: Divider

[0049] REG0~REG3: register circuit

[0050] SQ(i): Submission Queue (SQ)

[0051] CQ(i): Completion Queue (CQ)

[0052] QC(i): Queue Circuit

[0053] QUEUE_ID(i): queue identification code (ID)

[0054] QD,QD(i),QD k (i): queue depth

[0055] THR,THR(i),THR k (i),THR k-1 (i): Aggregation threshold

[0056] TIME,TIME(i): aggregation time

[0057] c1~c3,ID i :Predetermined value

[0058] CNT QUEUE_ID :Queue identification code

[0059] CMD0~CMD2,CMD: command

[0060] MSI-X_INT0~MSI-X_INT2,MSI-X_INT: message signaling interrupt

[0061] S10~S12,S20~S24,S30~S33,S32A,S32B: Steps

[0062] t: time DETAILED DESCRIPTION

[0063] Figure 11 is a schematic diagram of an electronic device 10 according to an embodiment of the present invention. The electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors), which may be collectively referred to as a processor 52, and include a power supply circuit 54 and a transmission interface circuit 58, wherein the processor 52 and the transmission interface circuit 58 may be coupled to each other via a bus, and may be coupled to the power supply circuit 54 to obtain power. The processor 52 may be used to control the operation of the host device 50, and the power supply circuit 54 may be used to provide power to the processor 52, the transmission interface circuit 58, and the memory device 100, and output one or more driving voltages to the memory device 100, wherein the memory device 100 may provide storage space for the host device 50, and the one or more driving voltages may be obtained from the host device 50 as a power supply for the memory device 100. Examples of the host device 50 may include (but are not limited to): a multi-function mobile phone, a tablet computer, a wearable device, and a personal computer, such as a desktop computer and a notebook computer. Examples of the memory device 100 may include (but are not limited to): portable memory devices (e.g., memory cards conforming to SD / MMC, CF, MS or XD specifications, solid state drives (SSDs), and various types of embedded memory devices (e.g., embedded memory devices conforming to universal flash storage (UFS) specifications or embedded multi-media card (eMMC) specifications). According to the present embodiment, the memory device 100 may include a controller such as a memory controller 110, and may further include a non-volatile (NV) memory 120, wherein the controller is used to access the NV memory 120, and the NV memory 120 is used to store information. The NV memory 120 may include at least one NV memory element (e.g., one or more NV memory elements), such as a plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E , where "N E " may represent a positive integer greater than 1. For example, the NV memory 120 may be a flash memory, and the plurality of NV memory elements 122-1, 122-2, ..., and 122-N may be E They may be a plurality of flash memory chips or a plurality of flash memory dies, but the present invention is not limited thereto.

[0064] like Figure 1As shown, the memory controller 110 may include a processing circuit such as a microprocessor 112, a storage unit such as a read only memory (ROM) 112M, a control logic circuit 114, a random access memory (RAM) 116 (for example, it can be implemented by a static random access memory) and a transmission interface circuit 118, wherein the transmission interface circuit 118 may include multiple sub-circuits such as a bottom layer circuit 118B (for example, a physical layer (PHY) circuit) and a parameter controller 118P, and the parameter controller 118P can be used to control multiple parameters of the bottom layer circuit 118B. At least a portion (for example, a portion or all) of the above-listed elements can be coupled to each other via a bus. The random access memory 116 can be used to provide an internal storage space for the memory controller 110 (for example, it can temporarily store information), but the present invention is not limited thereto. In addition, the read-only memory 112M of the present embodiment is used to store the program code 112C, and the microprocessor 112 is used to execute the program code 112C to control the access of the NV memory 120. Please note that the program code 112C can also be stored in the random access memory 116 or any type of memory. In addition, the control logic circuit 114 can be used to control the NV memory 120. The control logic circuit 114 can include an error correction code (ECC) circuit (not shown). Figure 1 ), which can perform error correction code encoding and error correction code decoding to protect data, and / or perform error correction. The transmission interface circuit 118 can comply with one or more communication specifications among various communication specifications (such as Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIe) specification, Non-Volatile Memory Express (NVMe; also known as "NVM Express") specification, Embedded Multimedia Card specification and Universal Flash Storage specification), and can communicate with the host device 50 (or the transmission interface circuit 58 therein) for the memory device 100 according to the one or more communication specifications. Similarly, the transmission interface circuit 58 can comply with the one or more communication specifications, and can communicate with the host device 50 (or the transmission interface circuit 118 therein) for the memory device 100 according to the one or more communication specifications.

[0065] In the present embodiment, the host device 50 may transmit a plurality of host commands corresponding to the logical addresses to the memory controller 110 to indirectly access the NV memory 120 in the memory device 100. The memory controller 110 receives the plurality of host commands and the logical addresses, converts the plurality of host commands into memory operation commands (which may be referred to as operation commands for simplicity), and further controls the NV memory 120 with the operation commands to read or write / program the memory cells or data pages of the specific physical addresses in the NV memory 120, wherein the physical addresses may be associated with the logical addresses. For example, the memory controller 110 may generate or update at least one logical-to-physical (L2P) address mapping table to manage the relationship between the physical addresses and the logical addresses. The NV memory 120 may store a global L2P address mapping table 120AM to provide the memory controller 110 to control the memory device 100 to access the data in the NV memory 120, but the present invention is not limited thereto.

[0066] For better understanding, the global L2P address mapping table 120AM may be located in a predetermined area within the NV memory element 122-1, such as a system area, but the present invention is not limited thereto. For example, the global L2P address mapping table 120AM may be divided into a plurality of local L2P address mapping tables, and the plurality of local L2P address mapping tables may be stored in the plurality of NV memory elements 122-1, 122-2, ..., and 122-N. E In one or more NV memory elements, in particular, the NV memory elements 122-1, 122-2, ..., and 122-N may be stored in the plurality of NV memory elements 122-1, 122-2, ..., and 122-N, respectively. E When necessary, the memory controller 110 may load at least a portion (e.g., a portion or all) of the global L2P address mapping table 120AM into the random access memory 116 or other memory. For example, the memory controller 110 may load a local L2P address mapping table from the plurality of local L2P address mapping tables into the random access memory 116 as a temporary L2P address mapping table 116AM to access data in the NV memory 120 according to the local L2P address mapping table stored as the temporary L2P address mapping table 116AM, but the present invention is not limited thereto. The memory controller 110 may generate or update address mapping information in the temporary L2P address mapping table 116AM, and update the global L2P address mapping table 120AM according to the latest address mapping information in the temporary L2P address mapping table 116AM.

[0067] In addition, the at least one NV memory element (eg, one or more NV memory elements, such as the plurality of NV memory elements 122-1, 122-2, ..., and 122-N) E ) may include a plurality of blocks {BLK}, wherein the minimum unit for the memory controller 110 to perform a data erase operation on the NV memory 120 may be a block, and the minimum unit for the memory controller 110 to perform a data write operation on the NV memory 120 may be a page, but the present invention is not limited thereto. For example, the plurality of NV memory elements 122-1, 122-2, ..., and 122-N E Any NV memory element 122-n within (where “n” may represent an interval [1, N E ]) may include a plurality of blocks, and one of the plurality of blocks may include and record a specific number of pages, wherein the memory controller 110 may access a certain page in a certain block in the plurality of blocks according to the block address and the page address. In some examples, any of the above NV memory elements 122-n may include a plurality of planes, one of the plurality of planes may include a plurality of blocks, and one of the plurality of blocks may include and record a specific number of pages, wherein the memory controller 110 may access a certain page in a certain block in a certain plane in the plurality of planes according to the plane address, the block address, and the page address.

[0068] According to some embodiments, the memory controller 110 may configure any block BLK of the plurality of blocks {BLK} as a single level cell (SLC) block for storing 1 bit per memory cell, but the present invention is not limited thereto. The memory controller 110 may configure any of the above blocks BLK as an X-level cell (XLC) block for storing X bits per memory cell, where X may be a positive integer. For example, when X=1, the XLC block may represent the SLC block. In some examples, when X>1, the XLC block may represent any one of a multiple level cell (MLC) block (e.g., a double level cell (DLC) block), a triple level cell (TLC) block, a quadruple level cell (QLC) block, etc. The NV memory 120 may be implemented by three-dimensional (3D) flash memory technology to increase a predetermined upper limit X of the parameter X.MAX , to allow the memory controller 110 to configure the memory device 100 to have a larger available storage capacity, but the present invention is not limited thereto. When the memory device 100 is capable of storing a large amount of data such as user data, the key factors affecting the overall performance of the electronic device 10 may include:

[0069] (1) Factor I: During data access, in response to a plurality of commands {CMD} from the host device 50, the memory controller 110 is able to quickly access the NV memory 120 for the host device 50; and

[0070] (2) Factor II: During the data access period, the host device 50 can smoothly complete the processing of the plurality of commands {CMD}.

[0071] For example, the memory controller 110 may operate according to at least one control scheme to quickly access the NV memory 120 for the host device 50 in response to the multiple commands {CMD} during data access, and dynamically adjust the configuration of the memory device 100 to optimize the host side access control of the host device 50 for the multiple commands {CMD}. In particular, at least one configuration of at least one element (e.g., the transmission interface circuit 118) within the memory controller 110 is dynamically adjusted to minimize the total time of the host side access control of the host device 50 for the multiple commands {CMD}, so that the host device 50 can smoothly complete the processing of the multiple commands {CMD} during data access, thereby ensuring the overall performance of the electronic device 10. When necessary, the memory controller 110 may utilize at least one upper layer circuit (e.g., parameter controller 118P) within the memory controller 110 to dynamically adjust at least one parameter of the transmission interface circuit 118, such as the multiple parameters of the bottom layer circuit 118B, to perform access control in response to the latest state of the electronic device 10 (or the host device 50 and / or the memory device 100 therein), so as to accelerate the completion of the host-side access control for the multiple commands {CMD}, so as to improve the throughput (for data access) of the memory device 100, wherein the at least one element may include the transmission interface circuit 118, and the at least one configuration may include a set of configurations of the bottom layer circuit 118B within the transmission interface circuit 118, such as the configuration defined or determined by the multiple parameters of the bottom layer circuit 118B, but the present invention is not limited thereto. In some examples, the at least one upper layer circuit may include one or a combination of the microprocessor 112 and / or the parameter controller 118P.

[0072] Figure 2Ais a schematic diagram of an interrupt coalescing controller 200 according to an embodiment of the present invention, wherein Figure 1 The parameter controller 118P shown may be implemented by an interrupt aggregation controller 200, and the plurality of parameters of the bottom circuit 118B may include a plurality of aggregation parameters such as an aggregation threshold THR and an aggregation time TIME. The interrupt aggregation controller 200 may include a first arithmetic processing circuit 210, a second arithmetic processing circuit 220, a parameter generating circuit 230, an adder 240, and a third arithmetic processing circuit 250, which are respectively used to process with a first gain GAIN1 (e.g., GAIN1=c1), process with a second gain GAIN2 (e.g., GAIN2=c2), generate an aggregation time TIME (e.g., TIME=c3), perform at least one summing operation, and process with a third gain GAIN3 (e.g., GAIN3=(1 / (c1+c2))) to generate an aggregation threshold THR (respectively labeled as "c1", "c2", "c3", "Σ", and "1 / (c1+c2)" for simplicity). Under the control of the microprocessor 112, the memory controller 110 may obtain a queue depth QD from the underlying circuit 118B for input to the first arithmetic processing circuit 210. For example, the host-side parameters of the host device 50 may include the queue depth QD, and the memory controller 110 may obtain at least a portion of the host-side parameters such as the queue depth QD from the host device 50 through the underlying circuit 118B.

[0073] when Figure 2A When the circuit architecture shown performs the k-th processing, the related operations may include:

[0074] (1) The first arithmetic processing circuit 210 may apply a first gain GAIN1 (e.g., GAIN1 = c1) to a previous output (e.g., the output of the (k-1)th processing) of the third arithmetic processing circuit 250 to generate a first processing result to be input to the adder 240;

[0075] (2) The second arithmetic processing circuit 220 may apply a second gain GAIN2 (eg, GAIN2=c2) to the queue depth QD to generate a second processing result to be input to the adder 240;

[0076] (3) The adder 240 may perform a summing operation on the first processing result and the second processing result to generate a sum of the two processing results as a summing result to be input to the third arithmetic processing circuit 250;

[0077] (4) The third arithmetic processing circuit 250 may apply a third gain GAIN3 (e.g., GAIN3 = (1 / (c1 + c2))) to the summed result to generate a current output (e.g., the output of the k-th processing), and output the current output as the aggregation threshold THR; and

[0078] (5) The parameter generation circuit 230 may generate the aggregation time TIME according to the predetermined value c3 (eg, TIME=c3), and output the aggregation time TIME;

[0079] Wherein "k" may represent an integer, such as a positive integer, to indicate the number of times the memory controller 110 scans or detects the queue depth QD, but the present invention is not limited thereto. For example, based on zero-based numbering, "k" may represent a non-negative integer. For another example, "k" may represent any integer, and a series of time points {t(k)} may include time points {…, t(-1), t(0), t(1), …}, wherein the above-mentioned k-th processing, (k-1)-th processing, etc. may be replaced by processing at time points t(k), t(k-1), etc., respectively. In addition, the queue depth QD can represent the queue depth QD(i) of any queue circuit QC(i) among the multiple queue circuits {QC(i)} of the host device 50, so as to indicate the queue depth of the above-mentioned any queue circuit QC(i), and the aggregation threshold THR and the aggregation time TIME can respectively represent the aggregation threshold THR(i) and the aggregation time TIME(i) corresponding to the above-mentioned any queue circuit QC(i) (or its queue identification code (identifier, ID) QUEUE_ID(i)), so as to provide the memory controller 110 with relevant device side access control. Since the plurality of queue circuits {QC(i)} are located in the host device 50 (rather than the memory device 100), the memory controller 110 can perform dynamic configuration optimization according to the respective queue identification codes {QUEUE_ID(i)} of the plurality of queue circuits {QC(i)}. In particular, the memory controller 110 can obtain the queue depth QD(i) corresponding to the queue identification code QUEUE_ID(i) from the underlying circuit 118B, and set the aggregation threshold THR(i) and aggregation time TIME(i) corresponding to the queue identification code QUEUE_ID(i) to perform device-side access control corresponding to any of the above-mentioned queue circuits QC(i).

[0080] Figure 2B Draw Figure 2AAn example of implementation details of the circuit architecture shown, wherein the circuit architecture can be implemented by means of multiple register circuits {REG} (e.g., register circuits REG0, REG1, REG2 and REG3) and multiple arithmetic units (e.g., multipliers 212, 222 and 252 and adder 240), and any register circuit in the multiple register circuits {REG} can include at least one register. Under the control of the microprocessor 112, the memory controller 110 may pre-load a set of predetermined values ​​(1 / (c1+c2)), c1, c2, and c3 from the NV memory 120 into the register circuits REG0, REG1, REG2, and REG3, respectively, wherein a production tool may be used to control the memory controller 110 to store the set of predetermined values ​​(1 / (c1+c2)), c1, c2, and c3 in the predetermined area (e.g., the system area) in the NV memory 120 during a production stage of the memory device 100, but the present invention is not limited thereto. For example, the memory controller 110 obtains the latest values ​​of the set of predetermined values ​​(1 / (c1+c2)), c1, c2, and c3 from another source (e.g., the host device 50) to update the set of predetermined values ​​(1 / (c1+c2)), c1, c2, and c3 in the predetermined area. As another example, the set of predetermined values ​​(1 / (c1+c2)), c1, c2, and c3 may also be stored in the RAM 116 or any other type of memory.

[0081] like Figure 2B As shown, the first arithmetic processing circuit 210 can use the register circuit REG1 to output the predetermined value c1 to the multiplier 212, and use the multiplier 212 to apply the first gain GAIN1 (for example: GAIN1=c1) to the previous output of the third arithmetic processing circuit 250 to generate the first processing result; the second arithmetic processing circuit 220 can use the register circuit REG2 to output the predetermined value c2 to the multiplier 222, and use the multiplier 222 to apply the second gain GAIN2 (for example: : GAIN2=c2) is applied to the queue depth QD to generate the second processing result; the parameter generating circuit 230 can utilize the register circuit REG3 to output the predetermined value c3; and the third arithmetic processing circuit 250 can utilize the register circuit REG0 to output the predetermined value (1 / (c1+c2)) to the multiplier 252, and utilize the multiplier 252 to apply the third gain GAIN3 (for example: GAIN3=(1 / (c1+c2))) to the summed result to generate the current output.

[0082] Figure 2C Draw Figure 2AAnother example of implementation details of the circuit architecture is shown, where the circuit architecture can be implemented by a plurality of register circuits {REG} (e.g., register circuits REG1, REG2, and REG3) and a plurality of arithmetic units (e.g., multipliers 212 and 222, divider 254, and adders 240 and 256). Figure 2B In the example shown, the divider 254 and the adder 256 in this circuit architecture replace the multiplier 252 and the register circuit REG0 respectively. The third arithmetic processing circuit 250 can use the adder 256 to perform an addition operation on the predetermined values ​​c1 and c2 to generate the sum (c1+c2) of the two predetermined values ​​c1 and c2, and use the divider 254 to perform a division operation on the sum result generated by the adder 240 according to the sum (c1+c2), in particular, divide the sum result from the adder 240 by the sum (c1+c2) to generate the current output (e.g., the output of the kth processing), and output the current output as the aggregation threshold THR.

[0083] Figure 3 The right half thereof shows a dynamically optimized access control scheme according to an embodiment of the present invention, wherein Figure 3 A non-optimized access control scheme is shown in the left half for easy understanding. For example, the memory controller 110 may set TIME=0 when operating according to the non-optimized access control scheme. In this case, when receiving a command CMD, the memory controller 110 may access the NV memory 120 according to the command CMD and return a message signaling interrupt MSI-X_INT. The command CMD may represent Figure 3 The left half shows any one of the commands CMD0, CMD1 and CMD2, and the message signaling interrupt MSI-X_INT can represent Figure 3 The left half shows a corresponding message signaling interrupt among MSI-X_INT0, MSI-X_INT1 and MSI-X_INT2 (eg, a message signaling interrupt corresponding to any of the above commands).

[0084] When necessary, the memory controller 110 may operate according to the dynamically optimized access control scheme to perform the above-mentioned dynamic configuration optimization, in particular, dynamically adjust the aggregation threshold THR and the aggregation time TIME to minimize the total time of the host-side access control of the host device 50 for the multiple commands {CMD}, so that the host device 50 can smoothly complete the processing of the multiple commands {CMD} during data access, thereby ensuring the overall performance of the electronic device 10. For example, the multiple commands {CMD} may include commands {CMD0, CMD1, CMD2}. When any command CMD among the multiple commands {CMD} is received, the memory controller 110 may access the NV memory 120 according to the command CMD. Figure 3 As shown in the right half, based on the above dynamic configuration optimization, the memory controller 110 can return a message signaling interrupt MSI-X_INT corresponding to the command {CMD0, CMD1, CMD2} instead of returning any message signaling interrupt MSI-X_INT corresponding to only a single command CMD.

[0085] In addition, the message signaling interrupts MSI-X_INT, MSI-X_INT0, MSI-X_INT1 and MSI-X_INT2 can be implemented by extended message signaling interrupts (extended MSI, MSI-X), but the present invention is not limited thereto. For example, the message signaling interrupts MSI-X_INT, MSI-X_INT0, MSI-X_INT1 and MSI-X_INT2 can be implemented by standard message signaling interrupts (standard MSI) or non-extended message signaling interrupts (non-extended MSI). For another example, the message signaling interrupts MSI-X_INT, MSI-X_INT0, MSI-X_INT1 and MSI-X_INT2 can be implemented by interrupt messages to emulate legacy interrupts such as interrupts on physical interrupt pins.

[0086] Figure 4 Detailed description is a flow chart of a method for controlling access to a memory device (eg, the memory device 100 ) by means of interrupt management according to an embodiment of the present invention.

[0087] In step S10, the memory controller 110 may receive a set of commands {CMD} (e.g., commands {CMD0, CMD1, CMD2}) from the host device 50 via the transmission interface circuit 118, wherein the command number CNT_CMD of the set of commands {CMD} may be greater than one, and any command CMD in the set of commands {CMD} may indicate a request to access the memory device 100. For example, the set of commands {CMD} may include at least one read command CMD READ Such as a set of read commands {CMD READ For another example, the set of commands {CMD} may include at least one write command CMD WRITE Such as a set of write commands {CMD WRITE In some examples, the set of commands {CMD} may include at least one read command CMD READ and at least one write command CMD WRITE One or a combination of .

[0088] In step S11, in response to the set of commands {CMD}, the memory controller 110 may perform a set of access operations {OP} on the NV memory 120 for the host device 50, wherein the set of access operations {OP} may include a corresponding access operation OP performed by the memory controller 110 in response to any of the commands CMD in the set of commands {CMD}. For example, if any of the commands CMD in the set of commands {CMD} is a read command CMD READ , the memory controller 110 can read the stored data DATA from the NV memory 120 STORED As the read data DATA READ , to be sent to the host device 50. For another example, if any of the commands CMD in the set of commands {CMD} is a write command CMD WRITE , the memory controller 110 can write the data DATA from the host device 50 WRITE Write to the NV memory 120 .

[0089] In step S12, in response to the set of commands {CMD}, the memory controller 110 may transmit a single message signaling interrupt (MSI) INT (e.g., the message signaling interrupt MSI-X_INT) corresponding to the set of commands {CMD} back to the host device 50 via the transmission interface circuit 118, so as to notify the host device 50 of the completion of the device-side access control of the memory device 100 for the set of commands {CMD}, so as to allow the host device 50 to complete the host-side access control of the host device 50 for the set of commands {CMD}. For example, the single message signaling interrupt INT may be implemented in the form of one of a standard / non-extended message signaling interrupt and an extended message signaling interrupt.

[0090] like Figure 4 As shown, the memory controller 110 may execute the loop including steps S10, S11 and S12 for multiple times. For example, among all commands {CMD} (e.g., commands {CMD0, CMD1, CMD2, ...}) transmitted from the host device 50 to the memory device 100, the group of commands {CMD} may represent a first group of commands {CMD} among a plurality of groups of commands {{CMD}, ..., {CMD}}, and the plurality of groups of commands {{CMD}, ..., {CMD}} may include the first group of commands {CMD} (e.g., commands {CMD0, CMD1, CMD2}) and at least one other group of commands {CMD} (e.g., commands {CMD3, CMD4, ...}) such as a second group of commands {CMD}, etc. In addition, the group of access operations {OP} may represent a first group of access operations {OP} among multiple groups of access operations {{OP}, ..., {OP}}, and the multiple groups of access operations {{OP}, ..., {OP}} may include the first group of access operations {OP} and at least one other group of access operations {OP} such as a second group of access operations {OP}. In addition, the single message signaling interrupt INT may represent a first message signaling interrupt INT corresponding to the first group of commands {CMD} among multiple message signaling interrupts {INT}, and the multiple message signaling interrupts {INT} may include the first message signaling interrupt INT and at least one other message signaling interrupt INT such as a second message signaling interrupt INT. When this loop is executed another time, the related operations may include:

[0091] (1) In step S10, the memory controller 110 may receive another set of commands {CMD} (e.g., the second set of commands {CMD}) from the host device 50 via the transmission interface circuit 118, wherein the command number CNT_CMD of the another set of commands {CMD} may be greater than one, and any command CMD in the another set of commands {CMD} may indicate a request to access the memory device 100;

[0092] (2) In step S11, in response to the other set of commands {CMD} (e.g., the second set of commands {CMD}), the memory controller 110 may perform another set of access operations {OP} (e.g., the second set of access operations {OP}) on the NV memory 120 for the host device 50, wherein the other set of access operations {OP} may include a corresponding access operation OP performed by the memory controller 110 in response to any of the commands CMD in the other set of commands {CMD}; and

[0093] (3) In step S12, in response to the other set of commands {CMD} (e.g., the second set of commands {CMD}), the memory controller 110 may transmit a single message signaling interrupt INT (e.g., the second message signaling interrupt INT) corresponding to the other set of commands {CMD} back to the host device 50 via the transmission interface circuit 118, so as to notify the host device 50 of the completion of the device-side access control of the memory device 100 for the other set of commands {CMD}, so as to allow the host device 50 to complete the host-side access control of the host device 50 for the other set of commands {CMD}.

[0094] For a better understanding, the method can be used Figure 4 According to some embodiments, one or more steps may be performed in Figure 4The memory controller 110 may add, delete or modify the workflow shown. For example, the memory controller 110 may dynamically switch the access control mode to selectively operate according to the dynamically optimized access control scheme or the non-optimized access control scheme. In addition, the memory controller 110 may dynamically adjust the configuration of the memory device 100 to optimize the host-side access control of the host device 50 for the group of commands {CMD}, and in particular, dynamically adjust the above-mentioned at least one configuration of the above-mentioned at least one element (for example: the transmission interface circuit 118) in the memory controller 110 to minimize the total time of the host-side access control of the host device 50 for the group of commands {CMD}, so that the host device 50 can smoothly complete the processing for the group of commands {CMD} during data access, thereby ensuring the overall performance of the electronic device 10. In addition, the memory controller 110 may utilize the at least one upper layer circuit (e.g., microprocessor 112 and / or parameter controller 118P) in the memory controller 110 to dynamically adjust the at least one parameter of the transmission interface circuit 118, such as the multiple parameters of the bottom layer circuit 118B, to perform access control in response to the latest state of the electronic device 10 (or the host device 50 and / or the memory device 100 therein), so as to accelerate the completion of the host-side access control for the set of commands {CMD}, so as to improve the throughput (for data access) of the memory device 100. In particular, the at least one parameter may include the multiple aggregation parameters such as aggregation threshold THR and aggregation time TIME, and the memory controller 110 may dynamically adjust the multiple aggregation parameters according to at least one predetermined rule, so as to accelerate the completion of the host-side access control for the set of commands {CMD}, and may optimize the timing of the multiple message signaling interrupts {INT} relative to the multiple sets of commands {{CMD}, ..., {CMD}} by dynamically adjusting the multiple aggregation parameters. For the sake of brevity, similar contents in these embodiments are not repeated here.

[0095] Table 1

[0096]

[0097] Table 1 shows an example of a command double word (Dword) in a packet from the host device 50, wherein the field of bits [31:16] may be a reserved field (labeled "reserved" for simplicity), and the host device 50 may specify the recommended values ​​of the aggregation time TIME and the aggregation threshold THR using the field "aggregation time" of bits [15:08] and the field "aggregation threshold" of bits [07:00] (labeled "TIME" and "THR" for ease of understanding), but the present invention is not limited thereto. The memory controller 110 may ignore the command double word specified by the host device 50 (or the recommended values ​​of the aggregation time TIME and the aggregation threshold THR, as contained in the command double word), and in particular, may determine the aggregation time TIME and the aggregation threshold THR by itself instead of fixing the aggregation time TIME and the aggregation threshold THR to the recommended values ​​specified by the host device 50. By avoiding fixing the aggregation time TIME and the aggregation threshold THR to the recommended values ​​specified by the host device 50, the memory controller 110 can properly perform access control of the memory device 100. For example, the memory controller 110 can dynamically adjust one or more aggregation parameters of the plurality of aggregation parameters (e.g., aggregation threshold THR and aggregation time TIME) according to the at least one predetermined rule to accelerate the completion of the host-side access control for the set of commands {CMD} and optimize the timing of the plurality of message signaling interrupts {INT} relative to the plurality of sets of commands {{CMD}, ..., {CMD}}.

[0098] Some details of the dynamic adjustment for the multiple aggregation parameters can be further described as follows. When the queue depth QD is equal to a relatively small value (e.g., a value less than 4), it may be difficult to appropriately set the aggregation threshold THR. In particular, it is difficult to find an appropriate value for setting the aggregation threshold THR. For example, the number of commands {CMD} received by the memory device 100 at one time may be very small, and the processing speed of the memory device 100 can be very fast. In this case, if THR > QD, and the memory device 100 hoards these commands {CMD} within a time interval without sending an interrupt INT, then soon there will be no new commands CMD available for processing, and the state of no new commands CMD available for processing can continue until the cumulative time exceeds the aggregation time TIME (or its current setting), resulting in a reduction in overall performance. Another example, if THR < QD or the aggregation time TIME (or its current setting) is very small, the benefit of setting the aggregation threshold THR may not be significant. Additionally, in the case of a large queue depth QD, since the payload on the PCIe bus is already close to full load, enabling interrupt aggregation at this time may not help improve the overall performance. The bottleneck of the related processing should be in the memory device 100 rather than the host device 50. In particular, it should have nothing to do with the performance of the host device 50.

[0099] Figures 5 to 8 Illustrate various examples of a timing diagram regarding access control, where the horizontal axis can represent time t, and the downward arrows can respectively indicate the time points when the memory controller 110 sends the message signaling interrupt {MSI-X_INT} back to the host device 50. The length of the time interval indicated by the large brace drawn below the horizontal axis can be equal to the current setting of the aggregation time TIME (labeled "Setting of Aggregation Time" for simplicity). For ease of understanding, assume that the respective payloads of all commands {CMD} received by the memory controller 110 from the host device 50 can have the same size, such as 4 kilobytes (KB), and the time for the memory controller 110 to process these payloads can be the same for each other (labeled "4kB" for simplicity), but the present invention is not limited thereto.

[0100] As Figure 5As shown in the upper part, assuming that QD=4 and THR=2, the number of commands {CMD} received by the memory controller 110 at one time can be very small, for example, there can be only four commands {CMD}, and the memory controller 110 can process these commands {CMD} very quickly. The memory controller 110 can return a first message signaling interrupt MSI-X_INT to the host device 50 immediately after processing the first two payloads, and return a second message signaling interrupt MSI-X_INT to the host device 50 immediately after processing the second two payloads, and these message signaling interrupts {MSI-X_INT} are triggered by a trigger event corresponding to the aggregation threshold THR (for example, an event that the aggregation threshold THR is reached) (labeled "MSI-X_INT triggered by THR" for simplicity). The host device 50 may perform host-side access control for the first two commands {CMD} immediately after receiving the first message signaling interrupt MSI-X_INT, and perform host-side access control for the last two commands {CMD} immediately after receiving the second message signaling interrupt MSI-X_INT. Before the time indicated by the current setting value of the aggregation time TIME, the host device 50 and the memory device 100 may both be in an idle state.

[0101] like Figure 5 As shown in the lower part, assuming that QD=4 and THR=0, when there are only four commands {CMD}, the memory controller 110 can process these commands {CMD} very quickly. After receiving a current command CMD among the four commands {CMD}, the memory controller 110 can process the current payload corresponding to the current command CMD and immediately return a corresponding message signaling interrupt MSI-X_INT to the host device 50. The host device 50 can immediately perform host-side access control for the current command CMD after receiving the corresponding message signaling interrupt MSI-X_INT. Before the time indicated by the current setting value of the aggregation time TIME, both the host device 50 and the memory device 100 can be in an idle state.

[0102] exist Figure 5 In the examples shown, the ratio of the time that the host device 50 and the memory device 100 are idle to the time indicated by the current setting of the aggregation time TIME is quite large. Therefore, when the queue depth QD is small, the benefit that can be achieved by setting the aggregation threshold THR is not large.

[0103] like Figure 6As shown, assuming that QD=4 and THR=8, when there are only four commands {CMD}, the memory controller 110 can process these commands {CMD} very quickly. After receiving a current command CMD among the four commands {CMD}, the memory controller 110 can process the current payload corresponding to the current command CMD, but does not immediately return any message signaling interrupt MSI-X_INT to the host device 50. Before the time indicated by the current setting value of the aggregation time TIME expires, the memory controller 110 can return a message signaling interrupt MSI-X_INT to the host device 50, and this message signaling interrupt MSI-X_INT is triggered by a trigger event corresponding to the aggregation time TIME (for example, an event that the time indicated by the current setting value of the aggregation time TIME is about to expire) (labeled "MSI-X_INT triggered by TIME" for simplicity).

[0104] exist Figure 6 In the example shown, the ratio of the time that the memory device 100 is in the idle state to the time indicated by the current setting value of the aggregation time TIME is quite large, and the host device 50 has been waiting in vain before receiving the message signaling interrupt MSI-X_INT. Therefore, improperly setting the aggregation threshold THR may reduce the payload per unit time and thus cause performance degradation.

[0105] like Figure 7As shown in the upper part, assuming that QD=32 and THR=4, the memory controller 110 may receive twelve commands {CMD} and process these commands {CMD} in succession. After receiving a current command CMD among the twelve commands {CMD}, the memory controller 110 may process the current payload corresponding to the current command CMD. In addition, the memory controller 110 may return a first message signaling interrupt MSI-X_INT to the host device 50 immediately after processing the first four payloads corresponding to the first four commands {CMD}, return a second message signaling interrupt MSI-X_INT to the host device 50 immediately after processing the four subsequent payloads corresponding to the four subsequent commands {CMD}, and return a third message signaling interrupt MSI-X_INT to the host device 50 immediately after processing the last four payloads corresponding to the last four commands {CMD}. The host device 50 may perform host-side access control for the first four commands {CMD} immediately after receiving the first message signaling interrupt MSI-X_INT, perform host-side access control for the four subsequent commands {CMD} immediately after receiving the second message signaling interrupt MSI-X_INT, and perform host-side access control for the last four commands {CMD} immediately after receiving the third message signaling interrupt MSI-X_INT. Before the time indicated by the current setting value of the aggregation time TIME, the time for the memory device 100 to process these payloads almost occupies the entire period, and a large part of the operation time of all the operation times of the host device 50 can be hidden in the time for the memory device 100 to process these payloads.

[0106] like Figure 7 As shown in the lower part, assuming that QD=32 and THR=0, when there are twelve commands {CMD}, the memory controller 110 can process these commands {CMD} in succession. After receiving a current command CMD among the twelve commands {CMD}, the memory controller 110 can process the current payload corresponding to the current command CMD, and immediately return a corresponding message signaling interrupt MSI-X_INT to the host device 50. The host device 50 can immediately perform host-side access control for the current command CMD after receiving the corresponding message signaling interrupt MSI-X_INT. Before the time indicated by the current setting value of the aggregation time TIME, the time for the memory device 100 to process these payloads almost occupies a whole period of time, and a larger part of the operation time of all the operation time of the host device 50 can be hidden in the time for the memory device 100 to process these payloads.

[0107] exist Figure 7In the examples shown, the time for the memory device 100 to process the payload occupies almost the entire period of time. When the queue depth QD is large, since the number of commands in the queue can be large, setting the aggregation threshold THR to an intermediate value or a smaller value within a predetermined value range may cause the operation time of the host device 50 (e.g., the processing time of the host-side access control for a certain command CMD) to be hidden in the time for the memory device 100 to process a certain payload (e.g., the payload corresponding to another command CMD).

[0108] When the queue depth QD is not too large or too small, the memory controller 110 may dynamically adjust one or more aggregation parameters of the plurality of aggregation parameters (eg, the aggregation threshold THR and the aggregation time TIME) to improve the overall performance.

[0109] like Figure 8 As shown in the upper part, assuming that QD=8 and THR=4, the memory controller 110 may receive eight commands {CMD} and process these commands {CMD} in succession. After receiving a current command CMD among the eight commands {CMD}, the memory controller 110 may process the current payload corresponding to the current command CMD. In addition, the memory controller 110 may return a first message signaling interrupt MSI-X_INT to the host device 50 immediately after processing the first four payloads corresponding to the first four commands {CMD}, and return a second message signaling interrupt MSI-X_INT to the host device 50 immediately after processing the last four payloads corresponding to the last four commands {CMD}, and these message signaling interrupts {MSI-X_INT} are triggered by a trigger event corresponding to the aggregation threshold THR (e.g., an event that the aggregation threshold THR is reached) (labeled "MSI-X_INT triggered by THR" for simplicity). The host device 50 may perform host-side access control for the first four commands {CMD} immediately after receiving the first message signaling interrupt MSI-X_INT, and may perform host-side access control for the last four commands {CMD} immediately after receiving the second message signaling interrupt MSI-X_INT.

[0110] like Figure 8 As shown in the lower part, assuming that QD=8 and THR=0, when there are four commands {CMD}, the memory controller 110 can process these commands {CMD} in succession. After receiving a current command CMD among the four commands {CMD}, the memory controller 110 can process the current payload corresponding to the current command CMD and immediately return a corresponding message signaling interrupt MSI-X_INT to the host device 50. The host device 50 can immediately perform host-side access control for the current command CMD after receiving the corresponding message signaling interrupt MSI-X_INT.

[0111] exist Figure 8 In the examples shown, when the queue depth QD falls into a first predetermined range, the memory controller 110 can dynamically adjust the aggregation threshold THR and the aggregation time TIME to improve the overall performance, wherein the first predetermined range can represent a predetermined interval of the queue depth QD, such as the interval [8,32], which can be regarded as an interval of medium queue depth, but the present invention is not limited thereto. For example, the predetermined interval of the queue depth QD can be changed. In some examples, when starting to process an I / O command {CMD} (e.g., a read command {CMD READ} and / or write command {CMD WRITE}), the memory controller 110 (or the microprocessor 112 running the relevant program code) may periodically detect the queue depth QD of at least one queue circuit of the host device 50 (for example: the queue depth QD(i) of any of the above-mentioned queue circuits QC(i)), and in particular, detect the queue depth QD(i) corresponding to the queue identification code QUEUE_ID(i) by an interrupt service routine (ISR) controlled by a central processing unit (CPU) timer (referred to as "CPU timer") in the microprocessor 112, and set the aggregation time TIME(i) to be equal to a predetermined time length, such as a predetermined value c3, and set the initial value of the aggregation threshold THR(i) to be equal to half of the queue depth QD(i) to start dynamically adjusting the aggregation threshold THR(i).

[0112] For ease of understanding, assuming that the queue depths {QD(i)} respectively corresponding to the queue identification codes {QUEUE_ID(i)} are equal to each other, if the queue depths {QD(i)} fall within the first predetermined range, the memory controller 110 may operate according to the dynamically optimized access control scheme to dynamically adjust the aggregation threshold THR and the aggregation time TIME; otherwise, the memory controller 110 may operate according to the non-optimized access control scheme to avoid any interrupt aggregation when the queue depth {QD(i)} is too large or too small. The memory controller 110 may control any message signaling interrupt MSI-X_INT among all message signaling interrupts {MSI-X_INT} to be triggered by a trigger event corresponding to the aggregation threshold THR (e.g., an event in which the aggregation threshold THR is reached) rather than by a trigger event corresponding to the aggregation time TIME (e.g., an event in which the aggregation time TIME is reached) to avoid any performance degradation caused by the trigger event corresponding to the aggregation time TIME. For the dynamic setting of the aggregation threshold THR, taking QD=8 and THR=4 as an example, the memory controller 110 may immediately transmit a message signaling interrupt MSI-X_INT back to the host device 50 after completing the processing of four payloads corresponding to four commands {CMD} so that the host device 50 performs host-side access control for the four commands {CMD}, and then starts to process the next four payloads corresponding to the next four commands {CMD}, and the rest may be deduced in the same manner. For example, Figure 8 As shown in the upper part. When the eighth payload corresponding to the eighth command CMD is processed, before sending the second message signaling interrupt MSI-X_INT to the host device 50, it can be expected that the host device 50 will send the ninth to twelfth commands {CMD} to the memory controller 110 to achieve seamless processing connection, wherein the dynamic configuration optimization performed by the memory controller 110 according to the dynamically optimized access control scheme can make the host device 50 and the memory controller 110 share the workload evenly, instead of letting the host device 50 bear most of the time consumption.

[0113] Some implementation details of the method may be further described as follows. For example, the at least one predetermined rule may include:

[0114] (1) a first predetermined rule: when the queue depth QD is within the first predetermined range, the memory controller 110 may enable interrupt aggregation, in particular, dynamically adjust one or more aggregation parameters of the plurality of aggregation parameters (e.g., aggregation threshold THR and aggregation time TIME) to accelerate the completion of the host-side access control for the set of commands {CMD}, and optimize the timing of the plurality of message signaling interrupts {INT} relative to the plurality of sets of commands {{CMD}, ..., {CMD}}; and

[0115] (2) a second predetermined rule: when the queue depth QD is not within the first predetermined range, the memory controller 110 may disable or avoid enabling interrupt aggregation, in particular, setting (or maintaining) TIME=0;

[0116] The first predetermined rule and the second predetermined rule may be respectively referred to as a predetermined activation rule and a predetermined deactivation rule, but the present invention is not limited thereto. A first predetermined condition (e.g., the queue depth QD is within the first predetermined range) adopted by the first predetermined rule and a second predetermined condition (e.g., the queue depth QD is not within the first predetermined range) adopted by the second predetermined rule may be changed. For example:

[0117] (1) The first predetermined condition may include the queue depth QD being within the first predetermined range and further including an I / O command {CMD} from the host device 50 (e.g., a read command {CMD READ} and / or write command {CMD WRITE}) Data length L DATA within a second predetermined range; and

[0118] (2) The second predetermined rule may include "the queue depth QD is not within the first predetermined range" and "the data length L of the I / O command {CMD} from the host device 50 is less than or equal to the first predetermined range". DATA At least one of "is not within the second predetermined range" is true;

[0119] The second predetermined range may represent the data length L DATA A predetermined interval, such as the interval [4,128] (in KB), can be regarded as an interval of medium and low data length, but the present invention is not limited thereto. For example, the data length L DATA The predetermined interval may be varied.

[0120] Fig.9A According to an embodiment of the present invention, a workflow of a service I / O command routine (hereinafter referred to as "service I / O CMD routine") involved in the method is described. Fig. 9B Draw Fig.9A The service I / O CMD routine shown in FIG. 1 is a workflow of the above ISR, wherein Fig. 9B The workflow shown may correspond to the k-th processing described above, and in particular, may be used to control the memory controller 110 to perform the k-th processing without setting a Figure 2A In addition, the memory controller 110 can utilize the microprocessor 112 to run program codes such as in-system program (ISP) codes to execute Fig.9A and Fig. 9B The workflow shown in the figure is used to perform the relevant operations of the method.

[0121] like Fig.9A As shown, in step S20 , the memory controller 110 may start to execute the service I / O CMD routine.

[0122] In step S21 , the memory controller 110 may enable the ISR controlled by the CPU timer, and control the CPU timer to trigger the execution of the ISR so that the period is equal to a predetermined period T.

[0123] In step S22, the memory controller 110 may determine whether to terminate the service I / O CMD routine. If yes, proceed to step S23; if no, proceed to step S21 to keep enabling the ISR controlled by the CPU timer to continue to trigger the execution of the ISR every predetermined period T.

[0124] In step S23 , the memory controller 110 may disable the ISR controlled by the CPU timer.

[0125] In step S24 , the memory controller 110 may set the aggregation time TIME to zero.

[0126] like Fig. 9B As shown, in step S30, the memory controller 110 may start executing the ISR by being triggered by the CPU timer. Since the CPU timer triggers the execution of the ISR every predetermined period T, the period of executing the ISR is equal to the predetermined period T.

[0127] In step S31, the memory controller 110 may obtain the queue depth QD(i) corresponding to the queue identification code QUEUE_ID(i) from the bottom layer circuit 118B. For example, the number of queue identification codes {QUEUE_ID(i)} may be equal to the queue identification code number CNT QUEUE_ID , and the memory controller 110 may execute a loop CNT including steps S31, S32, and S33 QUEUE_ID times to obtain the queue depths {QD(i)} corresponding to the queue identification codes {QUEUE_ID(i)} respectively.

[0128] In step S32, the memory controller 110 may set a aggregation threshold THR(i) and an aggregation time TIME(i) corresponding to the queue identification code QUEUE_ID(i). For example, step S32 may include multiple sub-steps such as steps S32A and S32B.

[0129] In step S32A, according to the queue depth QD of the kth processing k(i) (e.g., the queue depth QD(i) just obtained in step S31) and the aggregation threshold THR processed for the (k-1)th time k-1 (i) (For example, after the CPU timer triggered the execution of the ISR last time, Fig. 9B During the workflow shown, the memory controller 110 executes the loop including steps S31, S32 and S33 for the i-th time. The memory controller 110 may set the aggregation threshold THR(i) obtained in step S32 for the k-th processing. k (i) are as follows:

[0130] THR k (i)=((c1*THR k-1 (i)+c2*(QD k (i) / 2)) / (c1+c2));

[0131] Under the control of the microprocessor 112, the memory controller 110 can pre-load the predetermined value (1 / (c1+c2)), c1, c2 and c3 from the predetermined area (e.g., the system area) in the NV memory 120 to the random access memory 116 for performing the aggregation threshold THR. k (i) is calculated, but the present invention is not limited thereto. For example, the set of predetermined values ​​(1 / (c1+c2)), c1, c2 and c3 may also be stored in any type of memory.

[0132] In step S32B, the memory controller 110 may set the aggregation time TIME(i) according to a predetermined value c3, and in particular, set TIME(i)=c3.

[0133] In step S33, the memory controller 110 may determine whether the index i is less than the queue identification code number CNT QUEUE_ID If yes, the process goes to step S31 to execute the loop including steps S31, S32 and S33 for the next time; if no, the workflow of the ISR for the k-th processing ends (labeled "end of ISR" for simplicity).

[0134] For a better understanding, the method can be used Fig.9A and Fig. 9B According to some embodiments, one or more steps may be performed in Fig.9A and Fig. 9B Add, delete or modify the workflow shown.

[0135] Fig. 10A An example of access control involved in the method is shown, and Fig. 10BAnother example of access control involved in the method is shown, wherein the access control may include host-side access control and device-side access control for at least one command CMD (e.g., the group of commands {CMD} in the multiple groups of commands {{CMD}, …, {CMD}}). The host device 50 may control (e.g., identify and / or access) the multiple queue circuits {QC(i)} based on the queue identification code {QUEUE_ID(i)}, and utilize the queue circuit QC(i) corresponding to the queue identification code QUEUE_ID(i) in the multiple queue circuits {QC(i)} to process any command CMD in the at least one command CMD. For example, the queue identification code QUEUE_ID(i) may be equal to a predetermined value ID i , and the queue circuit QC(i) may include queue identification codes QUEUE_ID(i) (eg, QUEUE_ID(i) = ID i ) includes a submission queue (SQ) SQ(i) and a completion queue (CQ) CQ(i), but the present invention is not limited thereto.

[0136] like Fig. 10A As shown, when any of the above commands CMD represents a read command CMD READ When the read command CMD READ The associated actions may include:

[0137] (1) The host device 50 can use this command CMD, such as the read command CMD READ Insert into SQ SQ(i) (marked “Insert CMD” for brevity);

[0138] (2) The host device 50 may write a first doorbell, such as an SQ taildoorbell, into the memory device 100 for signaling a new command, such as a command CMD (labeled "host writes doorbell for signaling new CMD" for simplicity);

[0139] (3) The memory device 100 may fetch a command CMD such as a read command CMD from SQ SQ(i). READ (labeled "Memory Device Get CMD" for simplicity);

[0140] (4) the memory device 100 may send read data, such as data read from the NV memory 120, to a host buffer 50B in the host device 50 (labeled “send read data to host buffer” for simplicity);

[0141] (5) The memory device 100 may push the completed command CMD (or its completion information) to CQ CQ(i);

[0142] (6) The memory device 100 may send an interrupt INT, such as a message signaling interrupt MSI-X_INT, to indicate by signaling that the command CMD from the host device 50 is completed (labeled "memory device sends interrupt to signal host CMD completion" for simplicity);

[0143] (7) The host device 50 may obtain completion information of the command CMD from CQ CQ(i) (labeled “Host Obtains Completion CMD” for simplicity); and

[0144] (8) The host device 50 may write a second doorbell, such as a CQ headdoorbell, into the memory device 100 to release a completion queue entry (CQ entry, “CQ entry” for short) (labeled “host writes doorbell to release CQ entry” for simplicity);

[0145] In the above operations, the operations performed by the host device 50 and the memory device 100 may respectively belong to the host-side access control and the device-side access control for the at least one command CMD, but the present invention is not limited thereto.

[0146] like Fig. 10B As shown, when any of the above commands CMD represents a write command CMD WRITE When writing command CMD WRITE The associated actions may include:

[0147] (1) The host device 50 may write this command CMD into the command CMD WRITE Insert into SQ SQ(i) (marked “Insert CMD” for brevity);

[0148] (2) The host device 50 may write the first doorbell, such as the above-mentioned SQ tail doorbell, into the memory device 100 for signaling a new command, such as command CMD (labeled "host writes doorbell for signaling new CMD" for simplicity);

[0149] (3) The memory device 100 may obtain a command CMD such as a write command CMD from SQ SQ(i). WRITE (labeled "Memory Device Get CMD" for simplicity);

[0150] (4) The memory device 100 may obtain write data from the host buffer 50B in the host device 50, such as data to be written to the NV memory 120 (labeled "obtain write data from the host buffer" for simplicity);

[0151] (5) The memory device 100 may push the completed command CMD (or its completion information) to CQ CQ(i);

[0152] (6) The memory device 100 may send an interrupt INT, such as a message signaling interrupt MSI-X_INT, to indicate by signaling that the command CMD from the host device 50 is completed (labeled "memory device sends interrupt to signal host CMD completion" for simplicity);

[0153] (7) The host device 50 may obtain completion information of the command CMD from CQ CQ(i) (labeled “Host Obtains Completion CMD” for simplicity); and

[0154] (8) The host device 50 may write the second doorbell, such as the CQ header doorbell, in the memory device 100 to release the CQ entry (labeled "host writes doorbell to release CQ entry" for simplicity);

[0155] In the above operations, the operations performed by the host device 50 and the memory device 100 may respectively belong to the host-side access control and the device-side access control for the at least one command CMD, but the present invention is not limited thereto.

[0156] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A method for controlling access to a memory device by means of interrupt management, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the at least one non-volatile memory element comprising a plurality of blocks, the method comprising: Receive a set of commands from a host device using the memory controller via a transmission interface circuit in the memory controller, wherein a command count of the set of commands is greater than one, and any command in the set of commands indicates a request to access the memory device; and In response to the set of commands, the memory controller is used to perform a set of access operations on the non-volatile memory for the host device, and a single message-signaled interrupt (MSI) corresponding to the set of commands is transmitted back to the host device by the transmission interface circuit to notify the host device of completion of device-side access control of the memory device for the set of commands, so as to allow the host device to complete the host-side access control of the host device for the set of commands, wherein the set of access operations includes a corresponding access operation performed by the memory controller in response to any one of the commands in the set of commands.

2. The method according to claim 1, characterized in that The single message signaling interrupt is implemented by one of a non-extended message signaling interrupt (non-extended MSI) and an extended message signaling interrupt (extended MSI, MSI-X).

3. The method according to claim 1, characterized in that The group of commands represents a first group of commands among a plurality of groups of commands, and the plurality of groups of commands include the first group of commands and a second group of commands; the group of access operations represents a first group of access operations among a plurality of groups of access operations, and the plurality of groups of access operations include the first group of access operations and a second group of access operations; the single message signaling interrupt represents a first message signaling interrupt corresponding to the first group of commands among a plurality of message signaling interrupts, and the plurality of message signaling interrupts include the first message signaling interrupt and a second message signaling interrupt; and the method further comprises: Receive the second set of commands from the host device by the memory controller through the transmission interface circuit in the memory controller, wherein the number of commands in the second set of commands is greater than one, and any command in the second set of commands indicates a request to access the memory device; as well as In response to the second set of commands, the memory controller is used to perform the second set of access operations on the non-volatile memory for the host device, and the second message signaling interrupt corresponding to the second set of commands is transmitted back to the host device through the transmission interface circuit to notify the host device of the completion of the device-side access control of the memory device for the second set of commands, so as to allow the host device to complete the host-side access control of the host device for the second set of commands, wherein the second set of access operations includes a corresponding access operation performed by the memory controller in response to any one of the second set of commands.

4. The method according to claim 1, characterized in that The set of commands includes one or a combination of a read command and a write command.

5. The method according to claim 1, characterized in that If any of the commands in the set of commands is a read command, the memory controller is used to read the stored data from the non-volatile memory as read data to be sent to the host device; as well as If any one of the commands in the set of commands is a write command, the memory controller is used to write the write data from the host device into the non-volatile memory.

6. The method according to claim 1, characterized in that The device-side access control for the set of commands includes: accessing a host buffer within the host device; and At least one completed command is pushed to at least one completion queue (CQ) in the host device.

7. The method according to claim 6, The invention is characterized in that: If any of the commands in the set of commands is a read command, accessing the host buffer in the host device includes sending read data to the host buffer, wherein the read data is read from the non-volatile memory; as well as If any of the commands in the set of commands is a write command, accessing the host buffer in the host device includes retrieving write data from the host buffer for being written to the non-volatile memory.

8. The method according to claim 1, characterized in that The host-side access control for the set of commands includes: Obtaining completion information of at least one command from at least one completion queue (CQ) in the memory device; and At least one completion queue head doorbell (CQ head doorbell) in the memory device is written to release at least one completion queue entry (CQ entry) in the at least one completion queue.

9. The method according to claim 8, characterized in that The host-side access control for the set of commands further includes: Before the memory device performs the device-side access control for the set of commands, inserting at least one host command into at least one submission queue (SQ) as at least one new command; as well as At least one submission queue tail doorbell is written into the memory device for indicating the at least one new command by signaling.

10. The method according to claim 1, characterized in that The memory controller is used to dynamically adjust at least one configuration of at least one component within the memory controller to minimize the total time of the host-side access control of the host device for the set of commands.

11. The method according to claim 10, characterized in that The at least one component includes the transmission interface circuit, and the at least one configuration includes a set of configurations of an underlying circuit in the transmission interface circuit.

12. The method according to claim 11, characterized in that The set of configurations of the underlying circuit represents configurations determined by a plurality of parameters of the underlying circuit.

13. The method according to claim 1, characterized in that The memory controller is used to dynamically adjust at least one parameter of the transmission interface circuit to accelerate the host-side access control for the group of commands.

14. The method according to claim 13, characterized in that The memory controller is used to dynamically adjust the at least one parameter to perform access control in response to the latest state of the electronic device, so as to accelerate the completion of the host-side access control for the group of commands.

15. The method according to claim 13, characterized in that The at least one parameter includes multiple parameters of a bottom layer circuit in the transmission interface circuit; and the memory controller is used to dynamically adjust the multiple parameters of the bottom layer circuit by using at least one upper layer circuit in the memory controller to accelerate the host-side access control for the group of commands.

16. The method according to claim 13, characterized in that The at least one parameter includes a plurality of aggregation parameters; and the memory controller is used to dynamically adjust the plurality of aggregation parameters according to at least one predetermined rule to accelerate the host-side access control for the group of commands.

17. The method according to claim 13, characterized in that The at least one parameter includes a plurality of aggregation parameters; the group of commands represents a first group of commands among a plurality of groups of commands, the group of access operations represents a first group of access operations among a plurality of groups of access operations, and the single message signaling interrupt represents a first message signaling interrupt corresponding to the first group of commands among a plurality of message signaling interrupts; And the memory controller is used to dynamically adjust the plurality of aggregation parameters to optimize the timing of the plurality of message signaling interrupts relative to the plurality of groups of commands.

18. A memory controller of a memory device, the memory device comprising the memory controller and a non-volatile memory, the non-volatile memory comprising at least one non-volatile memory element, the at least one non-volatile memory element comprising a plurality of blocks, the memory controller comprising: a processing circuit for controlling the memory controller according to a plurality of host commands from a host device to allow the host device to access the non-volatile memory through the memory controller, wherein the processing circuit is used to perform access control of the memory device by means of interrupt management; as well as a transmission interface circuit for communicating with the host device; in: The memory controller receives a set of commands from the host device through the transmission interface circuit in the memory controller, wherein the command count of the set of commands is greater than one, and any command in the set of commands indicates a request to access the memory device; as well as In response to the set of commands, the memory controller performs a set of access operations on the non-volatile memory for the host device, and transmits a single message-signaled interrupt (MSI) corresponding to the set of commands back to the host device through the transmission interface circuit, so as to notify the host device of the completion of device-side access control of the memory device for the set of commands, so as to allow the host device to complete the host-side access control of the host device for the set of commands, wherein the set of access operations includes a corresponding access operation performed by the memory controller in response to any one of the commands in the set of commands.

19. The memory device comprising the memory controller as claimed in claim 18, wherein the memory device comprises: The non-volatile memory is used to store information; and The memory controller is coupled to the non-volatile memory and is used to control the operation of the memory device.

20. An electronic device comprising the memory device of claim 19, and further comprising: The host device is coupled to the memory device, wherein the host device comprises: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor for providing power to the at least one processor and the memory device; The memory device provides storage space for the host device.

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