Server, method for host to access storage unit, program product and medium

Abstract

The embodiment of the invention provides a server, a method for a host to access a storage unit, a program product and a medium. The host sends an access signal to a low-pin-number protocol receiver through a low-pin-number protocol receiver bus; the access signal is used for indicating access operation; the low-pin-number protocol receiver sends an access command to the serial peripheral interface controller according to the access operation indicated by the access signal; and the serial peripheral interface controller performs access operation on the storage unit according to the access command. According to the technical scheme of the invention, access operation can be carried out on the storage unit on the substrate management controller side through a low-pin-number protocol, support of software on the substrate management controller side is not needed, and a host can still access the storage unit on the substrate management controller side under the condition that the substrate management controller is not started or breaks down.

Description

Technical Field

[0001] The present invention relates to the technical field of servers, and in particular to a method, a program product and a medium for a server and a host to access a storage unit. Background Art

[0002] As the importance of server management becomes increasingly prominent, different server manufacturers have enhanced the manageability of servers on the corresponding hardware platforms and continuously strengthened their functions. The reliable, easy-to-use management features and additional service functions of servers are becoming the core competitiveness that various server manufacturers urgently need. The birth of the intelligent platform management interface specification has solved the problem of reliable server management. The platform management interface specification defines the communication protocol between the hardware devices on the server motherboard (hardware device firmware that supports the platform management interface specification protocol) and the communication protocol interface between the system management software and the hardware devices on the server motherboard. The core of the platform management interface specification is a dedicated chip / controller called the baseboard management controller.

[0003] In the prior art, the server host can send instructions for controlling the storage unit to the electronic device controller through an email module, and the electronic device controller then operates the baseboard management controller according to these instructions to realize the reading and writing of the storage unit. However, software support on the baseboard management controller side is required. Once the baseboard management controller is not started or fails, the server host cannot send storage unit instructions; when the baseboard management controller system is not started or crashes, the host cannot access the storage unit on the baseboard management controller side. Summary of the invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a server, a method for a host to access a storage unit, a computer program product and a computer-readable storage medium that overcome the above problems or at least partially solve the above problems.

[0005] A first aspect of the present invention provides a server, comprising:

[0006] Host and baseboard management controller;

[0007] The baseboard management controller includes: a low pin count protocol receiver, a serial peripheral interface controller and a storage unit;

[0008] The low pin count protocol receiver is connected to the host and the serial peripheral interface controller through a low pin count protocol bus respectively; the serial peripheral interface controller is connected to the storage unit through a serial peripheral interface bus;

[0009] The host is used to send an access signal to the low pin count protocol receiver through the low pin count protocol receiver bus; the access signal is used to indicate an access operation;

[0010] The low pin count protocol receiver is used to send an access command to the serial peripheral interface controller according to the access operation indicated by the access signal;

[0011] The serial peripheral interface controller is used to perform an access operation on the storage unit according to the access command.

[0012] Optionally, also include:

[0013] The host is used to send a read command and a first target address to be read to a low pin count protocol receiver when the access signal indicates a read operation;

[0014] The low pin count protocol receiver is used to send the read command and the first target address to the serial peripheral interface controller;

[0015] The serial peripheral interface controller is used to send the read command and the first target address to the storage unit to read the data of the first target address in the storage unit; and send the read data to the low pin count protocol receiver;

[0016] The low pin count protocol receiver is used to send the read data to the host.

[0017] Optionally, the serial peripheral interface controller is used to send a wait cycle to the low pin count protocol receiver when sending the read command and the first target address to the storage unit;

[0018] The low pin count protocol receiver is used to send the read data to the host after the waiting period.

[0019] Optionally, the low pin count protocol receiver includes a first address register and a first data register; the serial peripheral interface controller includes a state machine, a second address register and a second data register;

[0020] The host is used for sending a write command to the low pin count protocol receiver when the access signal indicates a write operation, writing a second target address to be written into a first address register of the low pin count protocol receiver, and writing target data to be written into a first data register of the low pin count protocol receiver;

[0021] The low pin count protocol receiver is used to send the write command to the serial peripheral interface controller and activate the state machine of the serial peripheral interface controller, write the second target address in the first address register into the second address register of the serial peripheral interface controller, and write the target data in the first data register into the second data register of the serial peripheral interface controller;

[0022] The state machine of the serial peripheral interface controller is used to send a write enable command to the storage unit; after sending the write enable command to the storage unit, send the write command to the storage unit, and send the second target address in the second address register and the target data in the second data register to the storage unit, so as to write the target data into the position of the second target address in the storage unit.

[0023] Optionally, the state machine of the serial peripheral interface controller is used to set the preset first flag bit to the first identifier after activation, and to set the preset first flag bit to the second identifier after writing is completed.

[0024] Optionally, the host is used to send an erase command to the low pin count protocol receiver when the access signal indicates an erase operation, and write a third target address to be erased into a first address register of the low pin count protocol receiver;

[0025] The low pin count protocol receiver is used to send the erase command to the serial peripheral interface controller and activate the state machine of the serial peripheral interface controller to write the third target address in the first address register into the second address register of the serial peripheral interface controller;

[0026] The state machine of the serial peripheral interface controller is used to send the third target address in the second address register to the storage unit to erase the data in the third target address of the storage unit.

[0027] Optionally, also include:

[0028] The state machine of the serial peripheral interface controller is used to set the preset second flag bit to the first flag after activation, and set the preset second flag bit to the second flag after erasure is completed.

[0029] A second aspect of the present invention provides a method for a host to access a storage unit, which is applied to a server and includes:

[0030] The server comprises a host and a baseboard management controller, wherein the baseboard management controller comprises a low pin count protocol receiver, a serial peripheral interface controller and a storage unit; the method comprises:

[0031] receiving an access signal sent by the host through the low pin count protocol receiver, and sending an access command to the serial peripheral interface controller according to the access operation indicated by the access signal;

[0032] The serial peripheral interface controller performs an access operation on the storage unit according to the access command.

[0033] Optionally, also include:

[0034] The step of sending an access command to the serial peripheral interface controller according to the access operation indicated by the access signal comprises:

[0035] When the access signal indicates a read operation, receiving a read command sent by the host and a first target address to be read through the low pin count protocol receiver, and sending the read command and the first target address to the serial peripheral interface controller;

[0036] The step of performing an access operation on the storage unit according to the access command by the serial peripheral interface controller includes:

[0037] Sending the read command and the first target address to the storage unit through the serial peripheral interface controller to read the data of the first target address in the storage unit; and sending the read data to the low pin count protocol receiver;

[0038] The method further comprises:

[0039] The read data is sent to the host through the low pin count protocol receiver.

[0040] Optionally, when sending the read command and the first target address to the storage unit through the serial peripheral interface controller, a wait cycle is sent to the low pin count protocol receiver;

[0041] The read data is sent to the host after the waiting period through the low pin count protocol receiver.

[0042] Optionally, also include:

[0043] The low pin count protocol receiver includes a first address register and a first data register; the serial peripheral interface controller includes a state machine, a second address register and a second data register;

[0044] The step of sending an access command to the serial peripheral interface controller according to the access operation indicated by the access signal comprises:

[0045] When the access signal indicates a write operation, a write command sent by the host is received through the low pin count protocol receiver, a second target address to be written by the host is stored through the first address register, and target data to be written by the host is stored through the first data register; the write command is sent to the serial peripheral interface controller and a state machine of the serial peripheral interface controller is activated, the second target address in the first address register is written into the second address register of the serial peripheral interface controller, and the target data in the first data register is written into the second data register of the serial peripheral interface controller;

[0046] The step of performing an access operation on the storage unit according to the access command by the serial peripheral interface controller includes:

[0047] A write enable command is sent to the storage unit through the state machine of the serial peripheral interface controller; after sending the write enable command to the storage unit, the write command is sent to the storage unit, and the second target address in the second address register and the target data in the second data register are sent to the storage unit to write the target data into the location of the second target address in the storage unit.

[0048] Optionally, through the state machine of the serial peripheral interface controller, the preset first flag bit is set to the first identifier after activation, and the preset first flag bit is set to the second identifier after writing is completed.

[0049] Optionally, also include:

[0050] The step of sending an access command to the serial peripheral interface controller according to the access operation indicated by the access signal comprises:

[0051] When the access signal indicates an erase operation, receiving an erase command sent by the host through the low pin count protocol receiver, storing a third target address to be erased written by the host through the first address register; sending the erase command to the serial peripheral interface controller and activating a state machine of the serial peripheral interface controller, and writing the third target address in the first address register into a second address register of the serial peripheral interface controller;

[0052] The step of performing an access operation on the storage unit according to the access command by the serial peripheral interface controller includes:

[0053] The third target address in the second address register is sent to the storage unit through the state machine of the serial peripheral interface controller to erase the data in the third target address of the storage unit.

[0054] Optionally, through the state machine of the serial peripheral interface controller, the preset second flag bit is set to the first identifier after activation, and the preset second flag bit is set to the second identifier after erasure is completed.

[0055] The present invention also discloses a computer program product, including a computer program / instruction, including: when the computer program / instruction is executed by a processor, the steps of implementing any one of the above-mentioned methods for a host to access a storage unit are implemented.

[0056] The present invention also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for a host accessing a storage unit described in any one of the above are implemented.

[0057] It can be seen from the above technical solutions that the embodiments of the present invention include the following advantages:

[0058] In an embodiment of the present invention, the host of the server sends an access signal to the low pin count protocol receiver on the baseboard management controller side through the low pin count protocol receiver bus; the low pin count protocol receiver sends an access command to the serial peripheral interface controller according to the access operation indicated by the access signal; the serial peripheral interface controller performs an access operation on the storage unit according to the access command. The host can access the storage unit on the baseboard management controller side through the low pin count protocol without the support of the baseboard management controller side software. When the baseboard management controller is not started or fails, the host can still access the storage unit on the baseboard management controller side. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 It is a server step flow chart of a method for a host to access a storage unit provided by an embodiment of the present invention;

[0060] Figure 2 It is a timing diagram of a low pin count protocol read and write mode of a method for a host to access a storage unit provided by an embodiment of the present invention;

[0061] Figure 3 It is a structural block diagram of a method for a host to access a storage unit provided by an embodiment of the present invention;

[0062] Figure 4 is a structural block diagram of an electronic device provided by an embodiment of the present invention;

[0063] Figure 5 It is a structural block diagram of a computer-readable storage medium provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0064] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0065] The management of each managed device by the system management software is achieved by communicating with the baseboard management controller. The physical interface between the baseboard management controller and the system management software adopts a low-pin count communication protocol. The low-pin count protocol bus is used for the system management software to communicate with the device by connecting the port address or memory mapping address of the device.

[0066] One of the core concepts of the embodiments of the present invention is that the present invention can send an access signal to a low pin count protocol receiver through a host, and the low pin count protocol receiver sends an access command to a serial peripheral interface controller according to the access signal, and the serial peripheral interface controller performs an access operation on the storage unit according to the access command; in the present invention, the host system can access the storage unit on the baseboard management controller side through the low pin count protocol, without the need for the support of the baseboard management controller side software, thereby reducing labor expenses and providing convenience for users.

[0067] Figure 1 is a server step flow chart of a method for a host to access a storage unit provided by an embodiment of the present invention, referring to Figure 1 , a flow chart of steps of a server provided by an embodiment of the present invention, the server comprises:

[0068] Host 10 and baseboard management controller 20;

[0069] The baseboard management controller 20 includes: a low pin count protocol receiver 21, a serial peripheral interface controller 22 and a storage unit 23;

[0070] The low pin count protocol receiver 21 is connected to the host 10 and the serial peripheral interface controller 22 through a low pin count protocol bus respectively; the serial peripheral interface controller 22 is connected to the storage unit 23 through the serial peripheral interface bus;

[0071] The host 10 is used to send an access signal to the low pin count protocol receiver 21 through the low pin count protocol receiver bus; the access signal is used to indicate an access operation;

[0072] The low pin count protocol receiver 21 is used to send an access command to the serial peripheral interface controller 22 according to the access operation indicated by the access signal;

[0073] The serial peripheral interface controller 22 is used to perform an access operation on the storage unit 23 according to the access command.

[0074] In this embodiment, the host 10 sends an operation command and target data or target address to the low pin number protocol receiver 21 through the signal line in the low pin number protocol receiver bus; after receiving the operation command, the low pin number protocol receiver 21 sends the operation command and target data or target address to the serial peripheral interface controller 22 through the low pin number protocol receiver bus according to the indicated command operation; after receiving the operation command, the serial peripheral interface controller 22 sends the operation command and target data or target address to the storage unit through the data line in the serial peripheral interface controller bus to complete the access operation to the storage unit. Different commands can be sent to the serial peripheral interface controller for the low pin number protocol receiver to avoid sending the wrong operation command and improve the accuracy of managing the serial peripheral interface controller.

[0075] The host 10 and the baseboard management controller 20 are connected via a low pin count protocol bus, which includes a clock signal, a reset signal, and a signal line; the reset signal is used to indicate the start and end of the transmission signal cycle; the signal line is used to transmit address and data information, and data may be sent from the master device to the slave device, or from the slave device to the master device, depending on the transmission direction (read or write). The serial peripheral interface bus supports sending and receiving data at the same time, that is, full-duplex communication, including a data line from the master device to the slave device and a data line from the slave device to the master device.

[0076] In this embodiment, the host sends an access signal to the low pin count protocol receiver on the baseboard management controller side through the low pin count protocol receiver bus; the low pin count protocol receiver sends an access command to the serial peripheral interface controller according to the access operation indicated by the access signal; the serial peripheral interface controller performs an access operation on the storage unit according to the access command. The host can access the storage unit on the baseboard management controller side through the low pin count protocol without the support of the baseboard management controller side software. When the baseboard management controller is not started or fails, the host can still access the storage unit on the baseboard management controller side.

[0077] Figure 2 This is a low pin count protocol read and write mode timing diagram of a server of a method for accessing a storage unit provided by an embodiment of the present invention, referring to Figure 2 , showing the signal setting status of the low pin number protocol when the host accesses the storage unit in an access cycle. When the reset signal is low, it indicates the beginning of an access cycle. At this time, the signal line should be presented as the beginning, and the reset signal from low level to the next low level indicates an access cycle. Refer to Table 1 for the definition of signal lines in read and write mode. The signal line is low at the start state of the read and write mode. At the next clock signal, the signal line defines different pins and the high and low levels of the signal indicate the read and write states of different working modes.

[0078] Bits[3:2] Bits[1] definition 00 0 I / O read 00 1 I / O write 01 0 Memory Read 01 1 Memory Write 10 0 DMA Read 10 1 DMA Write 11 x reserve

[0079] Table 1

[0080] In one embodiment of the present invention, the host may perform a read operation on the storage unit;

[0081] The host 10 is used to send a read command and a first target address to be read to the low pin count protocol receiver 21 when the access signal indicates a read operation;

[0082] The low pin count protocol receiver 21 is used to send the read command and the first target address to the serial peripheral interface controller 22;

[0083] The serial peripheral interface controller 22 is used to send the read command and the first target address to the storage unit 23 to read the data of the first target address in the storage unit 23; and send the read data to the low pin count protocol receiver 21;

[0084] The low pin count protocol receiver 21 is used to send the read data to the host 10 .

[0085] In the embodiment of the present invention, when the host 10 performs a read operation on the storage unit 23, the host 10 sends the target address of the data to be read and the read command to the low pin number protocol receiver 21 through the low pin number protocol bus. After the low pin number protocol receiver 21 receives the read command and the target address, it sends the read command and the target address to the serial peripheral interface controller 22 through the low pin number protocol bus. The serial peripheral interface controller 22 sends the read command and the target address to the storage unit 23 through the serial peripheral interface bus to read the target data; after the target data is read, the storage unit 23 returns the data to the serial peripheral interface controller 22 through the serial peripheral interface bus. The serial peripheral interface controller 22 sends the data to the low pin number protocol receiver 21 through the low pin number protocol bus. After the low pin number protocol receiver 21 receives the data, it returns the data to the host 10 through the low pin number protocol bus, so that the host 10 completes the read operation on the storage unit 23. In the present invention, the read data can be sent to the baseboard management controller through the low pin number protocol receiver without the need for software support, which reduces labor expenses and provides convenience for users.

[0086] In one embodiment of the present invention, the serial peripheral interface controller 22 is used to send a wait cycle to the low pin count protocol receiver 21 when sending the read command and the first target address to the storage unit;

[0087] The low pin count protocol receiver 21 is used to send the read data to the host after the waiting period.

[0088] In this embodiment, the serial peripheral interface controller 22 sends a waiting cycle to the low pin count protocol receiver 21 when receiving the read command and the target address of the data to be read. The waiting cycle refers to reducing or optimizing the delay time of the low pin count protocol bus, which is determined according to the response speed of the slave device; the low pin count protocol receiver 21 sends the read data to the host 10 after the waiting cycle is released. The present invention can avoid confusion in the read data and ensure that all data can be read by sending the waiting cycle to the low pin count protocol receiver and sending the read data to the host after the waiting cycle is released.

[0089] In one embodiment of the present invention, the host may perform a write operation on the storage unit;

[0090] The low pin count protocol receiver 21 includes a first address register 211 and a first data register 212; the serial peripheral interface controller 22 includes a state machine 221, a second address register 222 and a second data register 223;

[0091] The host 10 is used for sending a write command to the low pin count protocol receiver 21 when the access signal indicates a write operation, writing a second target address to be written into a first address register 211 of the low pin count protocol receiver 21, and writing target data to be written into a first data register 212 of the low pin count protocol receiver 21;

[0092] The low pin count protocol receiver 21 is used to send the write command to the serial peripheral interface controller 22 and activate the state machine 221 of the serial peripheral interface controller 22, write the second target address in the first address register 211 into the second address register 222 of the serial peripheral interface controller 22, and write the target data in the first data register 212 into the second data register 223 of the serial peripheral interface controller 22;

[0093] The state machine 221 of the serial peripheral interface controller 22 is used to send a write enable command to the storage unit 23; after sending the write enable command to the storage unit 23, the write command is sent to the storage unit 23, and the second target address in the second address register 222 and the target data in the second data register 223 are sent to the storage unit 23, so as to write the target data into the position of the second target address in the storage unit 23.

[0094] In this embodiment, when the host 10 performs a write operation on the storage unit 23, a write command, data to be written, and a target address of the write data are sent to the low pin count protocol receiver 21 through the low pin count protocol bus. After receiving the command, data, and target address, the low pin count protocol receiver 21 stores the target data to be written into the data register 212 and stores the target address into the address register 211; the low pin count protocol receiver 21 sends a write command, data to be written, and a target address of the write data to the serial peripheral interface controller 22 through the low pin count protocol bus. The serial peripheral interface controller 22 stores the received target data into the data register 223 and stores the target address of the target data into the address register 222; the state machine 221 in the serial peripheral interface controller 22 simultaneously sends a write enable command to the storage unit 23. After the storage unit 23 receives the write enable command, the serial peripheral interface controller 22 sends the write command, the target data, and the target address of the target data to the storage unit 23 through the serial peripheral interface bus, thereby writing the target data into the target address of the storage unit 23. The present invention can write target data into the storage unit according to the target address sequence, thereby avoiding errors in the writing process sequence and improving the accuracy of server operations.

[0095] Among them, the internal status register judgment method in the serial peripheral interface controller includes: there are two registers representing the address port and the data port in the low pin count protocol receiver. When the low pin count protocol bus reads and writes the serial peripheral interface controller register, it is assumed that the value stored in the address port register is 0x80 and the value stored in the data port register is 0x81; the low pin count protocol bus address is compared with the port value, if the low pin count protocol bus address is 0x80, then the serial peripheral interface controller register is determined to be the address port register; if the low pin count protocol bus address is 0x81, then the serial peripheral interface controller register is determined to be the data port register. Thereby, the internal status register in the serial peripheral interface controller can achieve the effect of more accurate data transmission.

[0096] In an embodiment of the present invention, a state machine 221 of the serial peripheral interface controller 22 is further included, which is used to set the preset first flag bit to the first identification after activation, and set the preset first flag bit to the second identification after writing is completed.

[0097] In this embodiment, the serial peripheral interface controller 22 activates the state machine 221 when sending a write command, target data, and a target address of the target data to the storage unit 23. At this time, the state of the state machine is an activation state set to an activation mark. After the host 10 completes the write operation on the storage unit 23, the state of the state machine is a stop state set to a stop mark. The present invention can effectively determine the progress of the write operation process by activating the serial peripheral interface controller state machine.

[0098] The step of activating the state machine of the serial peripheral interface controller includes: the low pin count protocol receiver writes 1 to the FIFO input address completion register in the serial peripheral interface controller to activate the write state machine.

[0099] In one embodiment of the present invention, the host 10 is used to send an erase command to the low pin count protocol receiver 21 when the access signal indicates an erase operation, and write the third target address to be erased into the first address register 212 of the low pin count protocol receiver 21;

[0100] The low pin count protocol receiver 21 is used to send the erase command to the serial peripheral interface controller 22 and activate the state machine 221 of the serial peripheral interface controller 22 to write the third target address in the first address register 212 into the second address register 222 of the serial peripheral interface controller 22;

[0101] The state machine 221 of the serial peripheral interface controller 22 is used to send the third target address in the second address register 222 to the storage unit 23 to erase the data in the third target address of the storage unit 23 .

[0102] In this embodiment, when the host 10 performs an erase operation on the storage unit 23, the host 10 sends an erase command and a target address of the erased data to the low pin count protocol receiver 21 through the low pin count protocol bus, and the low pin count protocol receiver 21 stores the received target address in the address register 212; the low pin count protocol receiver 21 sends the erase command and the target address to the address register 222 of the serial peripheral interface controller 22 through the low pin count protocol bus, and activates the state machine 221 of the serial peripheral interface controller 22 at the same time. After the state machine 221 is activated, the serial peripheral interface controller 22 sends the erase command and the target address to the storage unit 23 through the serial peripheral interface bus to erase the data in the target address of the storage unit 23. The present invention activates the state machine of the serial peripheral interface controller, so that it is convenient for the user to query the execution status of the erase command, providing convenience for the user.

[0103] In an embodiment of the present invention, the state machine 221 of the serial peripheral interface controller 22 is used to set the preset second flag bit to the first flag after activation, and set the preset second flag bit to the second flag after erasure is completed.

[0104] In this embodiment, the serial peripheral interface controller 22 activates the state machine 221 when sending an erase command and a target address to the storage unit 23. At this time, the state of the state machine is an activation state set to an activation mark. After the host 10 completes the erase operation on the storage unit 23, the state of the state machine is a stop state set to a stop mark.

[0105] The step of activating the state machine of the serial peripheral interface controller includes: the low pin count protocol receiver writes 1 to the FIFO input address completion register in the serial peripheral interface controller to activate the erase state machine.

[0106] Reference Figure 3 , shows a flowchart of the steps of a method for a host to access a storage unit provided by an embodiment of the present invention, the method is applied to a server, the server includes a host and a baseboard management controller, the baseboard management controller includes a low pin count protocol receiver, a serial peripheral interface controller and a storage unit; the method includes:

[0107] Step 301, receiving an access signal sent by the host through the low pin count protocol receiver, and sending an access command to the serial peripheral interface controller according to the access operation indicated by the access signal;

[0108] Step 302: Access the storage unit according to the access command through the serial peripheral interface controller.

[0109] When the host needs to access the storage unit, the low pin count protocol receiver receives the access signal sent by the host through the low pin count protocol bus, and sends the access command to the serial peripheral interface controller through the low pin count protocol bus according to the access operation command indicated by the access signal. The serial peripheral interface controller accesses the storage unit through the serial peripheral interface bus according to the received access command.

[0110] In the embodiment of the present invention, step 301 may include:

[0111] When the access signal indicates a read operation, receiving a read command sent by the host and a first target address to be read through the low pin count protocol receiver, and sending the read command and the first target address to the serial peripheral interface controller;

[0112] The step 302 may include: sending the read command and the first target address to the storage unit through the serial peripheral interface controller to read the data of the first target address in the storage unit; and sending the read data to the low pin count protocol receiver;

[0113] The method may further comprise:

[0114] The read data is sent to the host through the low pin count protocol receiver.

[0115] When the access signal sent by the host indicates a read operation, the low pin count protocol receiver receives the read command sent by the host and the target address of the data to be read through the low pin count protocol bus, and sends the read command and the target address to the serial peripheral interface controller through the low pin count protocol bus; after the serial peripheral interface controller receives the command and the target address, it sends the read command and the target address of the data to be read to the storage unit through the serial peripheral interface bus, and receives the read data at the same time. After the data is received, the read data is sent to the low pin count protocol receiver through the low pin count protocol bus, and the low pin count protocol receiver sends the received data to the host through the low pin count protocol bus.

[0116] In an embodiment of the present invention, the low pin count protocol receiver includes a state machine, a first address register and a first data register; the serial peripheral interface controller includes a second address register and a second data register;

[0117] The step 301 may include:

[0118] When the access signal indicates a write operation, a write command sent by the host is received through the low pin count protocol receiver, a second target address to be written by the host is stored through the first address register, and target data to be written by the host is stored through the first data register; the write command is sent to the serial peripheral interface controller and a state machine of the serial peripheral interface controller is activated, the second target address in the first address register is written into the second address register of the serial peripheral interface controller, and the target data in the first data register is written into the second data register of the serial peripheral interface controller;

[0119] The step 302 may include:

[0120] A write enable command is sent to the storage unit through the state machine of the serial peripheral interface controller; after sending the write enable command to the storage unit, the write command is sent to the storage unit, and the second target address in the second address register and the target data in the second data register are sent to the storage unit to write the target data into the location of the second target address in the storage unit.

[0121] When the access signal sent by the host indicates a write operation, the host sends a write command to the low pin count protocol receiver through the low pin count protocol bus, and at the same time, the address register of the low pin count protocol receiver stores the target address of the data that the host needs to write, and the data register stores the target data that the host needs to write; then the low pin count protocol receiver sends a write command to the serial peripheral interface controller through the low pin count protocol bus and activates the state machine of the serial peripheral interface controller, and sends the target address in the address register of the low pin count protocol receiver and the target data in the data register to the address register and data register of the serial peripheral interface controller; after the serial peripheral interface controller receives the command and address, it sends a write enable command to the storage unit through the state machine of the serial peripheral interface controller. After the write enable command is sent, the serial peripheral interface controller sends a write command to the storage unit through the serial peripheral interface bus, as well as the target address and target data in the address register and data register of the serial peripheral interface controller, and the storage unit writes the target data according to the location of the target address.

[0122] In the embodiment of the present invention, step 301 may include:

[0123] When the access signal indicates an erase operation, receiving an erase command sent by the host through the low pin count protocol receiver, storing a third target address to be erased written by the host through the first address register; sending the erase command to the serial peripheral interface controller and activating a state machine of the serial peripheral interface controller, and writing the third target address in the first address register into a second address register of the serial peripheral interface controller;

[0124] The step 302 may include:

[0125] The third target address in the second address register is sent to the storage unit through the state machine of the serial peripheral interface controller to erase the data in the third target address of the storage unit.

[0126] When the access signal sent by the host indicates an erase operation, the host sends an erase command to the low pin count protocol receiver through the low pin count protocol bus, and at the same time, the address register of the low pin count protocol receiver stores the target address of the data that the host needs to erase; then the low pin count protocol receiver sends an erase command to the serial peripheral interface controller through the low pin count protocol bus and activates the state machine of the serial peripheral interface controller, and sends the target address in the address register of the low pin count protocol receiver to the address register of the serial peripheral interface controller through the low pin count protocol bus; after the serial peripheral interface controller receives the command and address, it sends a write enable command to the storage unit through the state machine of the serial peripheral interface controller. After the write enable command is sent, the serial peripheral interface controller sends an erase command to the storage unit through the serial peripheral interface bus, as well as the target address in the address register of the serial peripheral interface controller, and the storage unit erases the target data according to the location of the target address.

[0127] An embodiment of the present invention also provides a computer program product, including steps of implementing any of the above-mentioned methods for a host to access a storage unit when the computer program / instructions are executed by a processor, and can achieve the same technical effect. To avoid repetition, they are not repeated here.

[0128] like Figure 4 , showing a structural block diagram of an electronic device provided in an embodiment of the present invention, including:

[0129] It includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the various processes of the above-mentioned host access storage unit method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0130] like Figure 5 , showing that an embodiment of the present invention also provides a structural block diagram of a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for the host to access the storage unit described in any of the above items are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0131] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0132] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0133] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0134] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0135] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0136] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0137] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0138] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0139] The above describes in detail a server, a method for a host to access a storage unit, a computer program product and a computer-readable storage medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A server, characterized in that: include: Host and baseboard management controller; The baseboard management controller includes: a low pin count protocol receiver, a serial peripheral interface controller and a storage unit; The low pin count protocol receiver is connected to the host and the serial peripheral interface controller through a low pin count protocol bus respectively; the serial peripheral interface controller is connected to the storage unit through a serial peripheral interface bus; The host is used to send an access signal to the low pin count protocol receiver through the low pin count protocol receiver bus; the access signal is used to indicate an access operation; The low pin count protocol receiver is used to send an access command to the serial peripheral interface controller according to the access operation indicated by the access signal; The serial peripheral interface controller is used to perform an access operation on the storage unit according to the access command.

2. The server according to claim 1, characterized in that: The host is used to send a read command and a first target address to be read to a low pin count protocol receiver when the access signal indicates a read operation; The low pin count protocol receiver is used to send the read command and the first target address to the serial peripheral interface controller; The serial peripheral interface controller is used to send the read command and the first target address to the storage unit to read the data of the first target address in the storage unit; and sending the read data to the low pin count protocol receiver; The low pin count protocol receiver is used to send the read data to the host.

3. The server according to claim 2, characterized in that: The serial peripheral interface controller is configured to send a wait cycle to the low pin count protocol receiver when sending the read command and the first target address to the storage unit; The low pin count protocol receiver is used to send the read data to the host after the waiting period.

4. The server according to claim 1, characterized in that: The low pin count protocol receiver includes a first address register and a first data register; the serial peripheral interface controller includes a state machine, a second address register and a second data register; The host is used for sending a write command to the low pin count protocol receiver when the access signal indicates a write operation, writing a second target address to be written into a first address register of the low pin count protocol receiver, and writing target data to be written into a first data register of the low pin count protocol receiver; The low pin count protocol receiver is used to send the write command to the serial peripheral interface controller and activate the state machine of the serial peripheral interface controller, write the second target address in the first address register into the second address register of the serial peripheral interface controller, and write the target data in the first data register into the second data register of the serial peripheral interface controller; The state machine of the serial peripheral interface controller is used to send a write enable command to the storage unit; after sending the write enable command to the storage unit, send the write command to the storage unit, and send the second target address in the second address register and the target data in the second data register to the storage unit, so as to write the target data into the position of the second target address in the storage unit.

5. The server according to claim 4, characterized in that: The state machine of the serial peripheral interface controller is used to set the preset first flag bit to the first identification after activation, and to set the preset first flag bit to the second identification after writing is completed.

6. The server according to claim 4, characterized in that: The host is configured to send an erase command to the low pin count protocol receiver when the access signal indicates an erase operation, and write a third target address to be erased into a first address register of the low pin count protocol receiver; The low pin count protocol receiver is used to send the erase command to the serial peripheral interface controller and activate the state machine of the serial peripheral interface controller to write the third target address in the first address register into the second address register of the serial peripheral interface controller; The state machine of the serial peripheral interface controller is used to send the third target address in the second address register to the storage unit to erase the data in the third target address of the storage unit.

7. The server according to claim 4, characterized in that: The state machine of the serial peripheral interface controller is used to set the preset second flag bit to the first flag after activation, and set the preset second flag bit to the second flag after erasure is completed.

8. A method for a host to access a storage unit, characterized in that: Applied to the server according to any one of claims 1 to 7, the method comprises: receiving an access signal sent by the host through the low pin count protocol receiver, and sending an access command to the serial peripheral interface controller according to the access operation indicated by the access signal; The serial peripheral interface controller performs an access operation on the storage unit according to the access command.

9. The method according to claim 8, characterized in that The step of sending an access command to the serial peripheral interface controller according to the access operation indicated by the access signal comprises: When the access signal indicates a read operation, receiving a read command sent by the host and a first target address to be read through the low pin count protocol receiver, and sending the read command and the first target address to the serial peripheral interface controller; The step of performing an access operation on the storage unit according to the access command by the serial peripheral interface controller includes: Sending the read command and the first target address to the storage unit through the serial peripheral interface controller to read the data of the first target address in the storage unit; and sending the read data to the low pin count protocol receiver; The method further comprises: The read data is sent to the host through the low pin count protocol receiver.

10. The method according to claim 8, characterized in that The low pin count protocol receiver includes a first address register and a first data register; the serial peripheral interface controller includes a state machine, a second address register and a second data register; The step of sending an access command to the serial peripheral interface controller according to the access operation indicated by the access signal comprises: When the access signal indicates a write operation, a write command sent by the host is received through the low pin count protocol receiver, a second target address to be written by the host is stored through the first address register, and target data to be written by the host is stored through the first data register; the write command is sent to the serial peripheral interface controller and a state machine of the serial peripheral interface controller is activated, the second target address in the first address register is written into the second address register of the serial peripheral interface controller, and the target data in the first data register is written into the second data register of the serial peripheral interface controller; The step of performing an access operation on the storage unit according to the access command by the serial peripheral interface controller includes: A write enable command is sent to the storage unit through the state machine of the serial peripheral interface controller; after sending the write enable command to the storage unit, the write command is sent to the storage unit, and the second target address in the second address register and the target data in the second data register are sent to the storage unit to write the target data into the location of the second target address in the storage unit.

11. The method according to claim 8, characterized in that The step of sending an access command to the serial peripheral interface controller according to the access operation indicated by the access signal comprises: When the access signal indicates an erase operation, receiving an erase command sent by the host through the low pin count protocol receiver, storing a third target address to be erased written by the host through the first address register; sending the erase command to the serial peripheral interface controller and activating a state machine of the serial peripheral interface controller, and writing the third target address in the first address register into a second address register of the serial peripheral interface controller; The step of performing an access operation on the storage unit according to the access command by the serial peripheral interface controller includes: The third target address in the second address register is sent to the storage unit through the state machine of the serial peripheral interface controller to erase the data in the third target address of the storage unit.

12. A computer program product comprising a computer program / instructions, characterized in that include: When the computer program / instructions are executed by a processor, the steps of the method for a host to access a storage unit as described in any one of claims 8 to 11 are implemented.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for a host accessing a storage unit according to any one of claims 8 to 11 are implemented.

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