Ultrasonic transducer excitation system and method for generating adjustable Gaussian signal
The FPGA internal excitation system generates a Gaussian signal with adjustable parameters, which solves the problems of complex ultrasonic transducer circuit structure and difficult to control errors, and realizes a low-cost and portable Gaussian signal excitation system, which is suitable for ultrasonic non-destructive detection.
Patent Information
- Application Number
- CN202411139577.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2024-12-10
AI Technical Summary
In the prior art, the ultrasonic transducer circuit corresponding to the Gaussian signal as an ultrasonic excitation signal has a complex structure and difficult to control errors. Traditional signal generator equipment is expensive and not portable, and it is impossible to flexibly generate a Gaussian signal with adjustable parameters.
An ultrasonic transducer excitation system including digital-to-analog conversion circuit, operational amplifier circuit and FPGA internal excitation system was designed. Through the operation module, control module and communication module inside the FPGA, the signals sent by the upper computer are analyzed and the parameters are adjusted. The Gaussian signal digital sequence is used to output analog signals through digital-to-analog conversion circuits, and an excitation signal is generated in combination with an operational amplifier circuit.
A low-cost, portable parameter adjustable Gaussian signal excitation system is realized, which avoids the expensive and large size problems of traditional signal generators. It has flexibility and the frequency characteristics of Gaussian signals. The frequency error is controlled within 5%, which is suitable for ultrasonic losslessness. Test.
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Figure CN119106644A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to an ultrasonic transducer excitation system and method, and belongs to the technical field of digital signal processing. Background Art
[0002] In ultrasonic nondestructive testing, the selection of ultrasonic excitation signals is crucial. For different excitation signals, the corresponding ultrasonic transducers have different structural characteristics. In order to detect modal information with a single frequency component, Gaussian signals are often used as ultrasonic excitation signals. Compared with common square wave and sine wave excitation signals, Gaussian excitation signals have relatively concentrated frequency components and large frequency response amplitudes, and can effectively suppress small peaks next to the main frequency peak. The excitation signal can be generated by a signal generator, but the signal generator equipment is expensive and large in size, so it has poor flexibility and is not suitable for use as an ultrasonic excitation signal source in different scenarios.
[0003] Gong Jinlong and others invented an ultrasonic generating system and ultrasonic excitation signal generation method in invention patent CN105372568A. This method realizes the excitation of ultrasonic signals such as sine waves and square waves by building an analog circuit. Although the circuit design structure in this method is simple and has good stability, it can only excite simple pulse signals or sine signals, and does not have superiority in principle.
[0004] Although Gaussian signals have great advantages as ultrasonic excitation signals in principle, the corresponding ultrasonic transducer has a complex circuit structure compared to other excitation signals, and the error cannot be effectively controlled. Zhao Yonggang et al. invented a Gaussian waveform generation method and system based on FPGA in invention patent CN112346382A. The principle is designed based on DDS digital signal generator. When used, it is necessary to generate Gaussian sequences in MATLAB in advance and store them in the ROM memory inside the FPGA. This operation is relatively complicated and cumbersome, and only a single type of digital Gaussian sequence can be generated, and Gaussian signals with flexible and adjustable parameters cannot be generated. Summary of the invention
[0005] The present invention aims to solve the problem that the ultrasonic transducer corresponding to a Gaussian signal as an ultrasonic excitation signal has a complex circuit structure compared to other excitation signals and the error cannot be effectively controlled, and further proposes an ultrasonic transducer excitation system and method for generating an adjustable Gaussian signal.
[0006] The technical solution adopted by the present invention to solve the above-mentioned problem is: the system described in the present invention includes a digital-to-analog conversion circuit, a power supply circuit, an operational amplifier circuit and an FPGA internal excitation system; the FPGA internal excitation system receives a signal sent by a host computer, the signal output end of the FPGA internal excitation system is connected to the signal receiving end of the digital-to-analog conversion circuit, the signal output end of the digital-to-analog conversion circuit is connected to the signal receiving end of the operational amplifier circuit, the operational amplifier circuit emits an excitation signal, and the power supply circuit provides power for the FPGA internal excitation system, the digital-to-analog conversion circuit and the operational amplifier circuit.
[0007] Furthermore, the FPGA internal excitation system includes an operation module, a control module and a communication module; the control module parses the signal sent by the host computer and passes the parameters to the operation module, and the digital sequence of the Gaussian signal with adjustable parameters output by the operation module is transmitted to the digital-to-analog conversion circuit through the communication module.
[0008] The steps of the method of the present invention include:
[0009] Step 1, realizing a digital operation circuit of a Gaussian signal;
[0010] Step 2: Design an incentive system based on FPGA;
[0011] Step 3: Implementation of the hardware excitation circuit system.
[0012] Furthermore, the method for implementing the Gaussian signal digital operation circuit in step 1 includes:
[0013] Step 101, design the corresponding digital circuit according to the Gaussian signal time domain expression, the Gaussian signal time domain expression x(t) is:
[0014]
[0015] In formula (1), A represents the signal amplitude, N represents the frequency, and f o represents the center frequency, t represents the time;
[0016] Step 102, the phase modulator calculates the phase information under the joint action of the system clock, the external frequency control word, and the phase control word, and then the ROM memory searches according to the phase information to generate the expression of the frequency-phase controllable sinusoidal digital sequence:
[0017]
[0018] In formula (2), F represents the frequency control word, P represents the phase control word, and f o Indicates the system clock frequency of the FPGA, A nrepresents the quantization accuracy, n represents the bit width of the memory, and these parameters together determine the frequency f of the fundamental wave o and phase Therefore, another expression of the fundamental digital sequence can be obtained: for:
[0019]
[0020] In formula (3), F i Indicates that the center frequency is f i The corresponding frequency control word, P i The phase is The corresponding phase control word when k represents the digital quantity;
[0021] Step 103, after completing the design of the fundamental wave digital circuit, based on the module, design the digital operation circuit structure of the Gaussian signal according to formula (1);
[0022] By inputting different frequency control words F and phase control words P to the two fundamental wave digital circuits, it can synchronously generate two fundamental wave signals r 1 (k) and r 2 (k), their expressions are:
[0023]
[0024] According to the characteristics of formula (1), combined with the binary principle of digital signals, the complement operation circuit is used to calculate r 2 (k) Perform the complement operation to get r 2C (k), its expression is:
[0025] r 2C (k) = 2 n -r 2 (k) (5),
[0026] r 1 (k) and r after complement operation 2C (k) The two signals are synchronously input to the multiplier circuit with a bit width of 2n to achieve the multiplication of the two signals and obtain x(k), which is expressed as:
[0027]
[0028] Since the quantization accuracy of the multiplication result is 2 2n , so it is necessary to unify the quantization accuracy through division operation, because the dividend is 2 n Therefore, by shifting x(k) right by n bits through the shift register to implement the division operation, the digital sequence X(k) of the Gaussian signal can be obtained, which is expressed as:
[0029]
[0030] Substituting equations (2) and (3) into equation (7), the final expression of the Gaussian signal digital sequence is:
[0031]
[0032] where F 1 ,F 2 ,P 1 ,P 2 The relations satisfied are:
[0033]
[0034] The F input to the digital operation circuit 1 ,F 2 ,P 1 ,P 2 If equation (9) is satisfied, a Gaussian signal digital sequence with adjustable parameters as shown in equation (7) can be output.
[0035] Furthermore, the implementation of the hardware excitation circuit system in step 3 specifically includes:
[0036] The function of the FPGA minimum system circuit is to identify the instructions sent by the host computer and generate a Gaussian digital sequence. The digital-to-analog conversion circuit converts the sequence into an analog signal and transmits it to the next level circuit. The operational amplifier circuit further amplifies the analog signal to generate the excitation signal required by the system and completes the transmission of the excitation signal. The function of the power supply circuit is to provide the required voltage signal for the hardware circuit system to ensure the normal and stable operation of the system.
[0037] The beneficial effects of the present invention are as follows: the main problem solved by the present invention is to design a low-cost, parameter-adjustable Gaussian signal ultrasonic transducer excitation system based on the combination of digital circuits and analog circuits. Using a traditional signal generator as an excitation device is not only expensive, but also large in size. Compared with the traditional signal generator, the present system is portable and low-cost, and uses FPGA to design digital circuits specifically for the characteristics of Gaussian signals, and designs analog circuits that match them, which is specific. When operating, only the host computer needs to send specific instructions to it, and the instruction format is as follows Figure 4 As shown in the figure, the excitation of Gaussian signal with real-time adjustable parameters can be realized, and the excitation effect is as follows Figure 7 As shown, the figure shows the waveform of the Gaussian signal captured by the Xilinx simulation software under the transmission instruction of the host computer. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 It is a schematic diagram of a digital circuit for generating a fundamental wave;
[0039] Figure 2 It is a schematic diagram of the structure of the Gaussian signal digital operation circuit and its implementation method;
[0040] Figure 3 It is the structural diagram of the internal excitation system of FPGA;
[0041] Figure 4 It is the instruction timing diagram corresponding to different data frames;
[0042] Figure 5 (a) (b) Schematic diagram of the effect of the state detection module on the waveform when the parameters change. Figure 5 (a) is a schematic diagram of the waveform generated without the state detection module. Figure 5 (b) is a schematic diagram of the waveform generated by the state detection module;
[0043] Figure 6 It is a hardware circuit system structure diagram;
[0044] Figure 7 This is a schematic diagram of the Gaussian signal waveform captured by the software;
[0045] Figure 8 It is the frequency relative error variation curve of the Gaussian signal output by the system under different parameters;
[0046] Fig. 9 It is a schematic diagram of the output waveforms of various parts of the digital operation module;
[0047] Fig.10 It is a schematic diagram of the Gaussian signal waveform captured by the software with specified parameters. DETAILED DESCRIPTION
[0048] Specific implementation method 1: Combination Figures 1 to 10 This embodiment describes an ultrasonic transducer excitation system for generating an adjustable Gaussian signal, which includes a digital-to-analog conversion circuit, a power supply circuit, an operational amplifier circuit, and an FPGA internal excitation system; the FPGA internal excitation system receives a signal from a host computer, the signal output end of the FPGA internal excitation system is connected to the signal receiving end of the digital-to-analog conversion circuit, the signal output end of the digital-to-analog conversion circuit is connected to the signal receiving end of the operational amplifier circuit, the operational amplifier circuit emits an excitation signal, and the power supply circuit provides power to the FPGA internal excitation system, the digital-to-analog conversion circuit, and the operational amplifier circuit.
[0049] Specific implementation method 2: Combination Figures 1 to 10To illustrate this embodiment, the FPGA internal excitation system of an ultrasonic transducer excitation system for generating an adjustable Gaussian signal described in this embodiment includes a calculation module, a control module and a communication module; the control module parses the signal sent by the host computer and passes the parameters to the calculation module, and the digital sequence of the Gaussian signal with adjustable parameters output by the calculation module is transmitted to the digital-to-analog conversion circuit through the communication module.
[0050] Specific implementation method three: Combination Figures 1 to 10 To illustrate this embodiment, a method for generating an adjustable Gaussian signal described in this embodiment is implemented by the following steps:
[0051] Step 1, realizing a digital operation circuit of a Gaussian signal;
[0052] Step 2: Design an incentive system based on FPGA;
[0053] Step 3: Implementation of the hardware excitation circuit system.
[0054] In view of the metastable phenomenon and waveform disorder caused by parameter changes during signal transmission, a state detection module is designed in the FPGA internal excitation system proposed by the present invention to avoid signal disturbance caused by parameter changes. The effect produced is as follows: Figure 5 As shown, in Figure 5 In the figure, (a) shows the data waveform disorder phenomenon caused by changing parameters during signal transmission when there is no state detection module. After the new parameter setting is completed, the new waveform is sent immediately, which will cover the old waveform, destroy the stability of the signal, and cause unpredictable metastable phenomena. At this time, the transmitted waveform does not meet the requirements of the ultrasonic detection for the time domain of the excitation signal. The waveform generated by the state detection module is shown in (b). After the new parameter setting is completed, the state detection module judges the current state to ensure the complete transmission of the signal of the current cycle. After the transmission is completed, the new parameter waveform is sent, which avoids the waveform disorder phenomenon and meets the requirements of the ultrasonic detection for the time domain of the excitation signal, realizing the dynamic adjustment of parameter transformation during signal transmission.
[0055] In order to avoid the hardware circuit consuming more resources, the calculation results involved in the digital operation circuit of this system are all integers. Therefore, during the calculation process, the rounding of decimal places will introduce corresponding errors. After theoretical analysis, the relative frequency error is obtained. as follows:
[0056]
[0057] To ensure calculation accuracy and hardware compatibility, set the ROM memory bit width n to 14 and the system clock frequency f cis 125MHz; therefore, the changing trend of the Gaussian signal frequency error under different parameters is obtained from formula (10): Figure 8 As shown in the figure, it can be seen that as the frequency decreases and the center frequency increases, the relative frequency error tends to decrease; the frequency N of the Gaussian excitation signal commonly used in ultrasonic non-destructive testing is 1 to 5, and the center frequency f 0 500KHz to 20MHz, therefore, according to Fig.10 It can be concluded that in common ultrasonic nondestructive testing scenarios, the frequency error of the excitation signal of this system can be controlled within 5%.
[0058] Specific implementation method four: Combination Figures 1 to 10 To illustrate this embodiment, the method for implementing a Gaussian signal digital operation circuit in step 1 of a method for generating an adjustable Gaussian signal in this embodiment includes:
[0059] Step 101, design the corresponding digital circuit according to the Gaussian signal time domain expression, the Gaussian signal time domain expression x(t) is:
[0060]
[0061] In formula (1), A represents the signal amplitude, N represents the frequency, and f o represents the center frequency, t represents the time;
[0062] Step 102, the phase modulator calculates the phase information under the joint action of the system clock, the external frequency control word, and the phase control word, and then the ROM memory searches according to the phase information to generate the expression of the frequency-phase controllable sinusoidal digital sequence:
[0063]
[0064] In formula (2), F represents the frequency control word, P represents the phase control word, and f o Indicates the system clock frequency of the FPGA, A n represents the quantization accuracy, n represents the bit width of the memory, and these parameters together determine the frequency f of the fundamental wave o and phase Therefore, another expression of the fundamental digital sequence can be obtained: for:
[0065]
[0066] In formula (3), F i Indicates that the center frequency is f i The corresponding frequency control word, P i The phase is The corresponding phase control word when k represents the digital quantity;
[0067] Step 103, after completing the design of the fundamental wave digital circuit, based on the module, design the digital operation circuit structure of the Gaussian signal according to formula (1);
[0068] By inputting different frequency control words F and phase control words P to the two fundamental wave digital circuits, it can synchronously generate two fundamental wave signals r 1 (k) and r 2 (k), their expressions are:
[0069]
[0070] According to the characteristics of formula (1), combined with the binary principle of digital signals, the complement operation circuit is used to calculate r 2 (k) Perform the complement operation to get r 2C (k), its expression is:
[0071] r 2C (k) = 2 n -r 2 (k) (5),
[0072] r 1 (k) and r after complement operation 2C (k) The two signals are synchronously input to the multiplier circuit with a bit width of 2n to achieve the multiplication of the two signals and obtain x(k), which is expressed as:
[0073]
[0074] Since the quantization accuracy of the multiplication result is 2 2n , so it is necessary to unify the quantization accuracy through division operation, because the dividend is 2 n Therefore, by shifting x(k) right by n bits through the shift register to implement the division operation, the digital sequence X(k) of the Gaussian signal can be obtained, which is expressed as:
[0075]
[0076] Substituting equations (2) and (3) into equation (7), the final expression of the Gaussian signal digital sequence is:
[0077]
[0078] where F 1 ,F 2 ,P 1 ,P 2 The relations satisfied are:
[0079]
[0080] The F input to the digital operation circuit 1 ,F 2 ,P 1 ,P 2 If equation (9) is satisfied, a Gaussian signal digital sequence with adjustable parameters as shown in equation (7) can be output.
[0081] Specific implementation method five: Combination Figures 1 to 10 To illustrate this embodiment, the implementation of the hardware excitation circuit system in step 3 of the method for generating an adjustable Gaussian signal described in this embodiment specifically includes:
[0082] The function of the FPGA minimum system circuit is to identify the instructions sent by the host computer and generate a Gaussian digital sequence. The digital-to-analog conversion circuit converts the sequence into an analog signal and transmits it to the next level circuit. The operational amplifier circuit further amplifies the analog signal to generate the excitation signal required by the system and completes the transmission of the excitation signal. The function of the power supply circuit is to provide the required voltage signal for the hardware circuit system to ensure the normal and stable operation of the system.
[0083] Specific implementation method six: Combination Figures 1 to 10 To illustrate this embodiment, the FPGA-based excitation system of the method for generating an adjustable Gaussian signal described in this embodiment is composed of a control module, a digital operation module and a communication module. Figure 3 As shown, the system can parse the instructions sent by the host computer, pass the parameters to the operation module through the control module, and the digital sequence of Gaussian signals with adjustable parameters output by the operation module is transmitted to the DAC digital-to-analog conversion circuit through the communication module.
[0084] The control module consists of three parts: serial port module, instruction parsing module and status detection module. The host computer communicates with FPGA through the UART serial port module. The instruction parsing module parses the received data frames. The instructions corresponding to different data frames are as follows: Figure 4 The data frame is parsed into different parameters and transmitted to the status detection module.
[0085] The function of the state detection module is to transmit the instructions to the digital operation circuit in an orderly manner. Its principle is the state machine circuit. When receiving new parameters, in order to avoid timing disorder in the transmission process, it determines whether the Gaussian signal at the previous moment has been sent. If it has been sent, the F 1 , F 1 , P 1 , P 2 As the input of the next digital operation module. The effect produced by the state detection circuit is as follows Figure 5 shown.
[0086] The digital operation circuit implementation method of Gaussian signal mentioned above is implemented in the digital operation module. The internal structure of the digital operation module is as follows: Figure 2 shown.
[0087] The function of the communication module is to transmit the Gaussian digital sequence output by the digital operation module to the DAC digital-to-analog conversion circuit through a virtual interface. The timing logic of the virtual interface is determined according to the interface timing of the DAC chip in the digital-to-analog conversion circuit.
[0088] Example
[0089] First, connect the system to the host computer and send data frames on the host computer. The data frame format is as follows: Figure 4 As shown in the figure, the data frame consists of a frame header, a command byte, a parameter byte, and a frame tail. The commands include loading parameters, starting to send, and stopping to send. Set the center frequency f 0 is 100KHz, the frequency N is 5, and the repetition frequency f R The frequency is 10KHz. The first data frame 55 A501 07A1202710 05 F0 is sent to load the parameters, and then the second data frame 55 A5 02 FFFFFFFFFFFF F0 is sent to send the waveform.
[0090] When the FPGA receives the data frame and completes the parsing of the instruction, the Gaussian signal digital operation circuit inside the FPGA will perform operations based on the input parameters. The structure of the digital operation circuit is as follows: Figure 2 As shown, the software captures the output results of each part of the digital operation circuit. Fig. 9 As shown, the fundamental wave circuit generates waveforms R1_Data and R2_Data according to the input parameters. R2_Data generates waveform R2c_Data through the complement circuit, and R1_Data and R2c_Data output the final waveform X_Data, i.e., Gaussian digital sequence, through the multiplier and shift register. Analysis shows that the output results of each part meet the theoretical values of formulas (4)(5)(6)(7) respectively.
[0091] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.
Claims
1. An ultrasonic transducer excitation system for generating an adjustable Gaussian signal, characterized in that: The ultrasonic transducer excitation system for generating an adjustable Gaussian signal includes a digital-to-analog conversion circuit, a power supply circuit, an operational amplifier circuit and an FPGA internal excitation system; the FPGA internal excitation system receives a signal sent by a host computer, the signal output end of the FPGA internal excitation system is connected to the signal receiving end of the digital-to-analog conversion circuit, the signal output end of the digital-to-analog conversion circuit is connected to the signal receiving end of the operational amplifier circuit, the operational amplifier circuit emits an excitation signal, and the power supply circuit provides power to the FPGA internal excitation system, the digital-to-analog conversion circuit and the operational amplifier circuit.
2. The ultrasonic transducer excitation system for generating an adjustable Gaussian signal according to claim 1, characterized in that: The FPGA internal excitation system includes a calculation module, a control module and a communication module; the control module parses the signal sent by the host computer and transmits the parameters to the calculation module, and the digital sequence of Gaussian signals with adjustable parameters output by the calculation module is transmitted to the digital-to-analog conversion circuit through the communication module.
3. A method for generating an adjustable Gaussian signal, characterized in that: The method for generating an adjustable Gaussian signal is achieved by the following steps: Step 1, realizing a digital operation circuit of a Gaussian signal; Step 2: Design an incentive system based on FPGA; Step 3: Implementation of the hardware excitation circuit system.
4. A method for generating an adjustable Gaussian signal according to claim 3, characterized in that: The method for implementing the Gaussian signal digital operation circuit in step 1 includes: Step 101, design the corresponding digital circuit according to the Gaussian signal time domain expression, the Gaussian signal time domain expression x(t) is: In formula (1), A represents the signal amplitude, N represents the frequency, and f o represents the center frequency, t represents the time; Step 102, the phase modulator calculates the phase information under the joint action of the system clock, the external frequency control word, and the phase control word, and then the ROM memory searches according to the phase information to generate the expression of the frequency-phase controllable sinusoidal digital sequence: In formula (2), F represents the frequency control word, P represents the phase control word, and f c Indicates the system clock frequency of the FPGA, A n represents the quantization accuracy, n represents the bit width of the memory, and these parameters together determine the frequency f of the fundamental wave o and phase Therefore, another expression of the fundamental digital sequence can be obtained: for: In formula (3), F i Indicates that the center frequency is f i The corresponding frequency control word, P i The phase is The corresponding phase control word when k represents the digital quantity; Step 103, after completing the design of the fundamental wave digital circuit, based on the module, design the digital operation circuit structure of the Gaussian signal according to formula (1); By inputting different frequency control words F and phase control words P to the two fundamental wave digital circuits, two fundamental wave signals r1(k) and r2(k) are synchronously generated, and their expressions are: According to the characteristics of formula (1), combined with the binary principle of digital signals, the complement operation circuit is used to perform the complement operation on r2(k) to obtain r 2C (k), its expression is: r 2C (k)=2 n -r2(k) (5), Compare r1(k) with the complemented r 2C (k) The two signals are synchronously input to the multiplier circuit with a bit width of 2n to achieve the multiplication of the two signals and obtain x(k), which is expressed as: Since the quantization accuracy of the multiplication result is 2 2n , so it is necessary to unify the quantization accuracy through division operation, because the dividend is 2 n Therefore, by shifting x(k) right by n bits through the shift register to implement the division operation, the digital sequence X(k) of the Gaussian signal can be obtained, which is expressed as: Substituting equations (2) and (3) into equation (7), the final expression of the Gaussian signal digital sequence is: The relationships satisfied by F1, F2, P1, and P2 are: When F1, F2, P1, and P2 input to the digital operation circuit satisfy equation (9), a parameter-adjustable Gaussian signal digital sequence as shown in equation (7) can be output.
5. The method for generating an adjustable Gaussian signal according to claim 3, characterized in that: The implementation of the hardware excitation circuit system in step 3 specifically includes: The function of the FPGA minimum system circuit is to identify the instructions sent by the host computer and generate a Gaussian digital sequence. The digital-to-analog conversion circuit converts the sequence into an analog signal and transmits it to the next level circuit. The operational amplifier circuit further amplifies the analog signal to generate the excitation signal required by the system and completes the transmission of the excitation signal. The function of the power supply circuit is to provide the required voltage signal for the hardware circuit system to ensure the normal and stable operation of the system.