SOC-level memory access verification system and method and memory controller initialization method

Abstract

The invention provides an SOC-level memory access verification system and method and a memory controller initialization method. The system comprises a plurality of memory controllers and register interface configuration simulators corresponding to the memory controllers. The register interface configuration simulator is a simulator which is defined according to an interface protocol and can simulate register interface hardware behaviors; wherein each storage controller is connected with the register interface configuration simulator corresponding to the storage controller through a register interface bus; the target storage controller is used for receiving a storage controller initialization sequence issued by the register interface configuration simulator through the register interface bus so as to perform initialization; the target storage controller is any one storage controller in the plurality of storage controllers. According to the method and the device, the time of the initialization process of the whole SOC-level memory access verification can be shortened to be close to the time of initialization of a single memory controller, and the verification efficiency of the SOC-level memory access verification is improved.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a SOC-level memory access verification system and method, and a storage controller initialization method. Background Art

[0002] With the rapid development of integrated circuit technology, the scale of integrated circuits is getting larger and larger, and the cost is getting higher and higher. The cost of a single tape-out is very high. In order to fully verify the design within a limited time, simulation acceleration verification is becoming increasingly important.

[0003] In the design of processor chips, the memory storage controller is the most important module. All programs are run in the memory. Its function is to store the calculation data in the CPU and the data exchanged with external storage devices such as hard disks. Therefore, in order to ensure full verification, the CPU core memory access and peripheral memory access need to be fully verified. For example, SOC (System-on-Chip) level memory access verification will be performed.

[0004] As the scale of integrated circuits increases, the scale of SOC-level memory access verification also increases and becomes more complicated, which means that the initialization of the memory controller during simulation verification takes several hours or even a day or several days. If the initialization time of the memory controller is too long, it will seriously affect the verification efficiency of the SOC. Summary of the invention

[0005] The purpose of the embodiments of the present application is to provide a SOC-level memory access verification system and method, and a storage controller initialization method, so as to improve the verification speed of the SOC-level memory access verification.

[0006] The embodiment of the present application provides a SOC-level memory access verification system, including: multiple storage controllers, and a register interface configuration simulator corresponding to each storage controller; the register interface configuration simulator is: a simulator that can simulate the hardware behavior of the register interface defined according to the interface protocol; wherein: each of the storage controllers is connected to the register interface configuration simulator corresponding to the storage controller through a register interface bus; the target storage controller is used to: receive the storage controller initialization sequence sent by the register interface configuration simulator through the register interface bus to initialize; the target storage controller is any storage controller among the multiple storage controllers. .

[0007] In the above-mentioned SOC-level memory access verification system, since a register interface configuration simulator corresponding to each storage controller is set, and the register interface configuration simulator corresponding to each storage controller can send a storage controller initialization sequence to the storage controller, based on the above-mentioned SOC-level memory access verification system, once the SOC-level memory access verification is required, the register interface configuration simulator can be used to occupy the register interface bus, so that each register interface configuration simulator can send a storage controller initialization sequence to the storage controller connected to it, thereby realizing the initialization of each storage controller. In this way, it is only necessary to set the storage controller initialization sequence of each storage controller in advance in each register interface configuration simulator, so as to realize the independent sending of the storage controller initialization sequence to each storage controller. That is, based on the above-mentioned SOC-level memory access verification system, when performing SOC-level memory access verification, each register interface configuration simulator can send a storage controller initialization sequence to the storage controller connected to it in parallel, so that each storage controller can be initialized in parallel. In this way, the initialization time of the entire SOC-level memory access verification can be reduced to close to the initialization time of a single storage controller. The initialization time of the entire SOC-level memory access verification can be reduced to minutes, thereby reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of SOC-level memory access verification, improving the verification speed of SOC-level memory access verification, and improving the verification efficiency of SOC-level memory access verification.

[0008] Further, the storage controller initialization sequence received by the target storage controller from the register interface configuration simulator is the same as the storage controller initialization sequence in the component-level verification environment corresponding to the target storage controller.

[0009] It can be understood that in the memory access verification of the chip, there is component-level memory access verification. In the component-level memory access verification, the storage controller and memory are included, and the environment is mainly constructed with UVM (Universal Verification Methodology, a standard verification methodology for integrated circuit design) methodology. The storage controller initialization sequence is sent through the register interface driver in the form of a transaction package, and the storage controller initialization sequence is entered on the component interface. It only takes a few minutes. After the initialization configuration is completed, the memory access program sequence is sent through the data interface driver in the form of a transaction package, and the verification program sequence is directly sent on the interface. The verification speed is very fast. In the above implementation, by directly configuring the storage controller initialization sequence used by the corresponding storage controller in the component-level memory access verification in the register interface configuration simulator (i.e., the storage controller initialization sequence in the component-level verification environment), the storage controller initialization sequence in the component-level verification environment can be directly inherited, without rewriting the SOC system-level storage controller initialization sequence, thereby further reducing the complexity of the operation and improving the verification efficiency of the SOC-level memory access verification.

[0010] Furthermore, each of the register interface configuration simulators is connected to the corresponding storage controller via a bind method.

[0011] In the above implementation scheme, the register interface configuration simulator is connected to the corresponding storage controller through the bind method, which will not affect the design behavior of the chip and does not require changing the chip design, thereby improving the reliability of the scheme.

[0012] Furthermore, the register interface configuration simulator includes: a storage controller initialization sequence, a request parsing module, a read request sending module, a write sending module, and a read response receiving module; the request parsing module is used to parse each task in the storage controller initialization sequence, and send the parsed read request to the read request sending module, send the parsed write request and write data to the write sending module, and send the parsed read-after-write request to the read request sending module and the write sending module in sequence; the read request sending module is used to send a read request to the register in the storage controller requested by the read request or the read-after-write request through the register interface bus; the write sending module is used to send write data to the register in the storage controller requested by the write request or the read-after-write request through the register interface bus; the read response receiving module is used to receive read response data returned by the register in the storage controller through the register interface bus.

[0013] In the above implementation scheme, each task in the storage controller initialization sequence is parsed through the request parsing module, and the corresponding request in each parsed task is processed through the read request sending module, the write sending module, and the read response receiving module respectively. In this way, the storage controller initialization sequence can be sent and configured to the corresponding registers in the storage controller, thereby improving the reliability of the scheme.

[0014] Furthermore, the SOC-level memory access verification system also includes: a verification instruction issuing module and a memory; wherein: different storage controllers are respectively connected to different memories; the verification instruction issuing module and the register interface configuration simulator corresponding to the target storage controller are connected to the target storage controller through the same register interface bus; the target storage controller is used to: during the initialization stage, receive the storage controller initialization sequence issued by the register interface configuration simulator through the register interface bus to perform initialization; and, after the initialization is completed, receive the verification instruction issued by the verification instruction issuing module through the register interface bus to perform memory access verification.

[0015] In the above implementation, when performing SOC-level memory access verification, after the storage controller is initialized, the register interface configuration simulator corresponding to the storage controller can release the occupied register interface bus, so that the verification instruction issuing module can issue a verification instruction through the register interface bus to perform memory access verification. In this way, while completing the initialization through the register interface configuration simulator, the normal verification function can be completed to ensure the normal progress of the verification.

[0016] Furthermore, the verification instruction issuing module includes: a processor core, a verification instruction storage module, and a network module; wherein the processor core and the verification instruction storage module are connected via the network module; the network module and the register interface configuration simulator corresponding to the target storage controller are connected to the target storage controller via the same register interface bus; the processor core is used to obtain verification instructions from the verification instruction storage module and issue them to the target storage controller via the network module.

[0017] In the above implementation scheme, the processor core can implement memory access verification for each storage controller by fetching instructions (i.e., obtaining instructions) from the verification instruction storage module and issuing them through the network module, thereby ensuring the normal progress of the verification and improving the reliability of the scheme. In addition, since the initialization of each storage controller is completed by the corresponding register interface configuration simulator of each storage controller, there is no need to store the storage controller initialization sequence in the verification instruction storage module, thereby reducing the demand for the storage capacity of the verification instruction storage module and improving the feasibility of the system.

[0018] An embodiment of the present application also provides a storage controller initialization method in a SOC-level memory access verification process, which is applied to any register interface configuration simulator of a SOC-level memory access verification system; the SOC-level memory access verification system includes: multiple storage controllers, and a register interface configuration simulator corresponding to each storage controller; the register interface configuration simulator is: a simulator that can simulate the hardware behavior of the register interface defined according to an interface protocol; wherein: each of the storage controllers is connected to the register interface configuration simulator corresponding to the storage controller via a register interface bus; the method includes: sending a storage controller initialization sequence to the connected target storage controller via the register interface bus to initialize the target storage controller; the target storage controller is any storage controller among the multiple storage controllers.

[0019] Based on the above implementation scheme, the simulator can be configured through each register interface to send the storage controller initialization sequence to each connected storage controller in parallel, so that each storage controller can be initialized in parallel. In this way, the initialization time of the entire SOC-level memory access verification process can be reduced to a time close to the initialization time of a single storage controller, and the initialization time of the entire SOC-level memory access verification process can be reduced to minutes, thereby reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of the SOC-level memory access verification, improving the verification speed of the SOC-level memory access verification, and improving the verification efficiency of the SOC-level memory access verification.

[0020] Furthermore, the register interface configuration simulator includes: a storage controller initialization sequence, a request parsing module, a read request sending module, a write sending module, and a read response receiving module; the storage controller initialization sequence is sent to the connected storage controller through the register interface bus, including: parsing each task in the storage controller initialization sequence through the request parsing module to obtain a read request or a write request or a read-after-write request; sending a read request to the register in the storage controller requested by the parsed read request or the read-after-write request through the read request sending module; sending the parsed write data to the register in the storage controller requested by the parsed write request or the read-after-write request through the write sending module; and receiving the read response data returned by the register in the storage controller through the read response receiving module.

[0021] Furthermore, after receiving the read response data returned by the register in the storage controller through the read response receiving module, the method also includes: if the read response data is response data corresponding to a read-and-write request, performing a bit-by-bit write-merge operation on the read response data and the write data in the read-and-write request, and sending the write data after the bit-by-bit write-merge operation to the register requested by the read-and-write request through the write sending module.

[0022] In the above implementation, for read-after-write requests, the received read response data is bit-wise write-merged with the write data in the read-after-write request and then sent to the register. In this way, only the data related to the initialization of the storage controller in the register will be modified, while other data in the register will not be modified. This can improve the stability of the storage controller during the initialization process and reduce the risk of abnormalities.

[0023] Furthermore, after receiving the read response data returned by the register in the storage controller through the read response receiving module, the method also includes: if the read response data is response data corresponding to the read request, performing a bitwise AND operation on the read response data and a preset read data parameter; if the result of the bitwise AND operation is inconsistent with the read data parameter, re-sending the read request through the read request sending module.

[0024] In the above implementation, by performing a bitwise AND operation on the read response data and the preset read data parameters, and judging whether the result of the bitwise AND operation is consistent with the read data parameters, it is possible to quickly determine whether the data read operation is successful, thereby determining whether the read request needs to be resent, thereby improving the reliability of the storage controller initialization.

[0025] An embodiment of the present application also provides a SOC-level memory access verification method, which is applied to any storage controller of a SOC-level memory access verification system; the SOC-level memory access verification system includes: a verification instruction issuing module, a memory, multiple storage controllers, and a register interface configuration simulator corresponding to each storage controller; wherein: different storage controllers are respectively connected to different memories, and for any storage controller: the verification instruction issuing module and the register interface configuration simulator corresponding to the storage controller are connected to the storage controller through the same register interface bus; the method includes: receiving a storage controller initialization sequence issued by the connected register interface configuration simulator through the register interface bus to perform initialization; after the initialization is completed, receiving a verification instruction issued by the verification instruction issuing module through the register interface bus to perform memory access verification.

[0026] Based on the above implementation method, the initialization of each storage controller can be implemented in parallel through the simulator configured by each register interface, so that the initialization process time of the entire SOC-level memory access verification is reduced to a level close to the initialization time of a single storage controller, reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of the SOC-level memory access verification, improving the verification speed of the SOC-level memory access verification, and improving the verification efficiency of the SOC-level memory access verification.

[0027] Furthermore, the verification instruction issuing module includes: a processor core, a verification instruction storage module, and a network module; wherein the processor core, the verification instruction storage module and each storage controller are connected via the network module; the verification instruction storage module stores verification instructions; wherein: the verification instruction received via the register interface bus is a verification instruction obtained by the processor core from the verification instruction storage module and issued via the network module. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A basic structural diagram of a SOC-level memory access verification system provided in an embodiment of the present application;

[0030] Figure 2 A schematic diagram of the structure of a register interface configuration simulator provided in an embodiment of the present application;

[0031] Figure 3 A structural diagram of a specific SOC-level memory access verification system provided in an embodiment of the present application;

[0032] Figure 4 A more specific structural diagram of a SOC-level memory access verification system provided in an embodiment of the present application;

[0033] Figure 5 A flowchart of a storage controller initialization method in a SOC-level memory access verification process provided by an embodiment of the present application;

[0034] Figure 6 A flowchart of a SOC-level memory access verification method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0036] Embodiment 1:

[0037] With the rapid development of integrated circuit technology, the scale of integrated circuits is getting larger and larger, and the cost is getting higher and higher. The cost of a single tape-out is very high. In order to fully verify the design within a limited time, simulation acceleration verification is becoming increasingly important.

[0038] In processor chip design, the memory storage controller is the most important module. All programs run in the memory. Its function is to store the calculation data in the CPU and the data exchanged with external storage devices such as hard disks. Therefore, in order to ensure sufficient verification, the CPU core memory access and peripheral memory access need to be fully verified.

[0039] In the SOC pre-silicon verification, various modes and various rates of various memories need to be fully verified. There are many verification scenarios and debugging takes a long time. Before the memory runs normally, the storage controller needs to be initialized and configured first. In the memory verification scenarios of different modes and different rates, the parameter configuration of the storage controller initialization is different. In general, to complete the initialization, it is necessary to configure thousands or even tens of thousands of storage controller registers, phy (physical layer) registers and DIMM (Dual-Inline-Memory-Modules) registers, which are referred to as the initialization of the storage controller in this application. After the storage controller initialization configuration is completed, the memory can work normally. At this time, the memory access request or DMA (Direct Memory Access) memory access request can access the memory.

[0040] In order to fully perform memory access verification, component-level memory access verification and SOC-level memory access verification are usually performed. The so-called component-level memory access verification refers to the memory access verification performed on a single storage controller module, which can also be called module-level memory access verification. The verification object is a single storage controller module in the chip design; the so-called SOC-level memory access verification refers to the memory access verification performed on the entire SOC. The verification object is all storage controllers in the SOC. Specifically:

[0041] In the component-level memory access verification, including the storage controller and memory, the environment is mainly built with UVM methodology. The storage controller initialization sequence is sent through the register interface driver in the form of a transaction packet. The storage controller initialization sequence is entered on the component interface, which only takes a few minutes. After the initialization configuration is completed, the memory access program sequence is sent through the data interface driver in the form of a transaction packet. The verification program sequence is sent directly on the interface, and the verification speed is very fast.

[0042] In SOC-level memory access verification, the minimum environment also needs to integrate the processor core, storage controller, memory, and flash (flash memory). The stimulus is generally written in assembly or C language to write the storage controller initialization sequence, which is converted into a format and placed in the flash. The processor core obtains the storage controller initialization sequence from the flash and then sends it to each storage controller for storage controller initialization configuration. The SOC chip contains multiple storage controllers. For the system-level initialization configuration of multiple storage controllers, they are configured in a serial order. After the storage controller is initialized, the processor begins to access the normal memory data path. However, the methods and program implementations of SOC-level memory access verification are very different from those of component-level memory access verification, and the verification program needs to be redeveloped. The redevelopment of the verification program means that new program debugging risks may be introduced. When such risks occur, the verification speed will be slowed down.

[0043] In addition, the scale of SOC-level memory access verification has gradually increased and become more complicated, which means that the initialization of the storage controller during verification takes several hours or even a day or a few days. However, when an error occurs in the SOC-level memory access verification and needs to be reproduced, or when the problem is solved and the SOC-level memory access verification needs to be re-performed, the initialization time is too long, which will cause a large time delay in debugging. In addition, when the program or code returns to stability, each program needs to be initialized. At the same time, a general SOC chip will also contain multiple storage controllers, and multiple storage controllers need to be initialized in turn. This program running time is unacceptable for verification. Therefore, it is unacceptable for the SOC-level memory access verification process to have an excessively long storage controller initialization time, which will seriously affect the verification efficiency of the SOC and thus affect the debugging time.

[0044] In order to improve the verification speed of SOC-level memory access verification, an embodiment of the present application provides a SOC-level memory access verification system, a storage controller initialization method in the SOC-level memory access verification process applied to the system, and a SOC-level memory access verification method.

[0045] See also Figure 1 As shown, Figure 1 It is a basic structural diagram of the SOC-level memory access verification system provided in the embodiment of the present application, including multiple memory controllers and a register interface configuration simulator corresponding to each memory controller.

[0046] In the embodiment of the present application, the storage controller and the register interface configuration simulator correspond one to one.

[0047] In the embodiment of the present application, the register interface configuration simulator is a simulator that can simulate the behavior of the register interface hardware according to the interface protocol definition, wherein each storage controller is connected to the register interface configuration simulator corresponding to the storage controller via a register interface bus.

[0048] In an embodiment of the present application, the target storage controller may receive a storage controller initialization sequence sent by a register interface configuration simulator through a register interface bus to perform initialization. The target storage controller may be any storage controller among multiple storage controllers.

[0049] In this way, based on the above-mentioned SOC-level memory access verification system, once the SOC-level memory access verification is required, the register interface configuration simulator can be used to occupy the register interface bus, so that each register interface configuration simulator can send a storage controller initialization sequence to the storage controller connected to it, thereby initializing each storage controller. In this way, it is only necessary to set the storage controller initialization sequence of each storage controller in advance in each register interface configuration simulator, so as to realize the independent sending of the storage controller initialization sequence to each storage controller. That is, based on the above-mentioned SOC-level memory access verification system, when performing SOC-level memory access verification, each register interface configuration simulator can send a storage controller initialization sequence to the storage controller connected to it in parallel, so that each storage controller can be initialized in parallel. In this way, the initialization time of the entire SOC-level memory access verification can be reduced to close to the initialization time of a single storage controller. The initialization time of the entire SOC-level memory access verification can be reduced to minutes, thereby reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of SOC-level memory access verification, improving the verification speed of SOC-level memory access verification, and improving the verification efficiency of SOC-level memory access verification.

[0050] Since the initialization time of the storage controller is shortened, when an error in SOC-level memory access verification needs to be reproduced, or when the problem is solved and SOC-level memory access verification needs to be re-performed, the initialization time of the storage controller is very fast, so the debugging time of the entire chip can be shortened. In addition, when the program or code returns to stability, the initialization time of the storage controller is very fast, so the running time of the program when it returns can also be shortened.

[0051] It can be understood that in the embodiment of the present application, the register interface configuration simulator is defined according to the interface protocol adopted by the interface bus in the SOC, so that the register interface configuration simulator can use the interface bus in the SOC to implement the sending of the storage controller initialization sequence.

[0052] In a feasible implementation of an embodiment of the present application, the storage controller initialization sequence issued by the register interface configuration simulator can be the same as the storage controller initialization sequence in the component-level verification environment corresponding to the target storage controller. Among them, the target storage controller is the storage controller to which the register interface configuration simulator is connected. In this way, the storage controller initialization sequence in the component-level verification environment (that is, the storage controller initialization sequence used by the storage controller during component-level memory access verification) can be directly inherited, so there is no need to rewrite the SOC system-level storage controller initialization sequence. It is only necessary to write the verification program or verification instruction sequence after initialization, thereby further reducing the complexity of the operation and improving the verification efficiency of the SOC-level memory access verification.

[0053] In another feasible implementation of the embodiment of the present application, the storage controller initialization sequence in each register interface configuration simulator may not directly inherit the storage controller initialization sequence in the component-level verification environment, but may be rewritten by an engineer.

[0054] In a feasible implementation of the embodiment of the present application, each register interface configuration simulator is connected to the corresponding storage controller via a bind method. It can be understood that the bind method is a grammatical structure in the SystemVerilog verification language. Using this method to connect the register interface configuration simulator to the corresponding storage controller will not affect the design behavior of the chip, nor does it require changes to the chip design, which can improve the reliability of the solution.

[0055] In the examples of this application, see Figure 2 As shown, the register interface configuration simulator may include: a storage controller initialization sequence, a request parsing module, a read request sending module, a write sending module, and a read response receiving module. Among them:

[0056] The request parsing module is used to parse each task in the storage controller initialization sequence, and send the parsed read request to the read request sending module, send the parsed write request and write data to the write sending module, and send the parsed read-after-write request to the read request sending module and the write sending module in sequence;

[0057] The read request sending module is used to send a read request to the register in the storage controller requested by the read request or the read-after-write request through the register interface bus;

[0058] The write send module is used to send write data to the register in the storage controller requested by the write request or the read-after-write request through the register interface bus;

[0059] The read response receiving module is used to receive the read response data returned by the register in the storage controller through the register interface bus.

[0060] It can be understood that in the embodiment of the present application, the storage controller initialization sequence may include multiple tasks, each of which can be parsed into a specific register request. In the embodiment of the present application, the types of parsed register requests include read requests, write requests, and read-after-write requests. Among them, the write request includes the write data corresponding to the register to be written.

[0061] It can be understood that in the embodiment of the present application, the task contains the register address corresponding to the request. When the request is parsed, the register address corresponding to the request can be obtained, thereby realizing the request operation for the corresponding register address.

[0062] In the embodiment of the present application, the request parsing module, the read request sending module, the write sending module, and the read response receiving module may be circuit modules implemented in hardware or program modules obtained by simulation.

[0063] It can be understood that the above process of parsing each task in the storage controller initialization sequence through the request parsing module, and implementing the processing of the corresponding request in each parsed task through the read request sending module, the write sending module, and the read response receiving module respectively, can be understood as the storage controller receiving the storage controller initialization sequence sent by the connected register interface configuration simulator through the register interface bus for initialization.

[0064] In an embodiment of the present application, each task in the storage controller initialization sequence is parsed through a request parsing module, and the corresponding request in each parsed task is processed through a read request sending module, a write sending module, and a read response receiving module, respectively. In this way, the storage controller initialization sequence can be sent down and configured to each register in the corresponding storage controller, thereby improving the reliability of the solution.

[0065] In the embodiments of the present application, Figure 3 As shown, the SOC-level memory access verification system may also include a verification instruction issuing module and a memory.

[0066] Different storage controllers are connected to different memories;

[0067] For any storage controller: the verification instruction issuing module and the register interface configuration simulator corresponding to the storage controller are connected to the storage controller via the same register interface bus. That is, the verification instruction issuing module and the register interface configuration simulator corresponding to the target storage controller can be connected to the target storage controller via the same register interface bus.

[0068] The target storage controller is used to: during the initialization phase, receive the storage controller initialization sequence issued by the connected register interface configuration simulator through the register interface bus for initialization; and, after the initialization is completed, receive the verification instruction issued by the verification instruction issuing module through the register interface bus for memory access verification.

[0069] In an embodiment of the present application, during the initialization phase, each register interface configuration simulator will occupy the interface bus of the SOC and issue a storage controller initialization sequence to the connected storage controller. At this time, since the interface bus is occupied, the verification instruction issuing module cannot use the interface bus to issue verification instructions to the storage controller. When the storage controller is initialized, the register interface configuration simulator connected to the storage controller will release the interface bus, so that the verification instruction issuing module can use the interface bus to issue verification instructions to the storage controller. In this way, the initialization time can be shortened without affecting the normal verification test process, thereby ensuring the consistency of the verification function of the SOC-level memory access verification.

[0070] In the embodiments of the present application, the memory may be, but is not limited to, DDR (double data rate synchronous dynamic random access memory), DDR2 (second generation double data rate synchronous dynamic random access memory), DDR3 (third generation double data rate synchronous dynamic random access memory), DDR4 (fourth generation double data rate synchronous dynamic random access memory), DDR5 (fifth generation double data rate synchronous dynamic random access memory), LPDDR (Low Power Double Data Rate SDRAM, low power memory), LPDDR4 (4th generation low power memory), LPDDR5 (5th generation low power memory), and even DDR6 under development, but is not a limitation.

[0071] In the embodiments of the present application, Figure 4 As shown, the verification instruction sending module may include: a processor core, a verification instruction storage module and a network module. The processor core and the verification instruction storage module are connected through the network module; for any storage controller: the network module and the register interface configuration simulator corresponding to the storage controller are connected to the storage controller through the same register interface bus; the processor core is used to obtain the verification instruction from the verification instruction storage module and send it to the storage controller through the network module.

[0072] In the embodiments of the present application, Figure 4As shown, the verification instruction issuing module may also include: DMA (Direct Memory Access), so as to realize the DMA memory access verification by controlling DMA to access the memory connected to the memory controller to be verified. Exemplarily, the processor core may fetch instructions from the verification instruction storage module, and control DMA to access the memory connected to one or more memory controllers according to the instructions. Exemplarily, the DMA may also fetch instructions from the verification instruction storage module, and realize the DMA memory access verification according to the memory connected to the memory controller to be verified.

[0073] It can be understood that in the embodiment of the present application, the verification instruction storage module can be but not limited to flash. In the embodiment of the present application, the network module can be but not limited to NOC (network on chip). In the embodiment of the present application, the register interface bus can be an interface bus in the network module.

[0074] Based on the same inventive concept, the embodiment of the present application also provides a storage controller initialization method in the SOC level memory access verification process, which can be applied to any register interface configuration simulator of the above-mentioned SOC level memory access verification system, see Figure 5 As shown, including:

[0075] S501: Sending a storage controller initialization sequence to a connected target storage controller via the register interface bus to initialize the target storage controller.

[0076] In the embodiment of the present application, the target storage controller is any storage controller among multiple storage controllers.

[0077] In this way, the simulator can be configured through each register interface to send the storage controller initialization sequence to each connected storage controller in parallel, so that each storage controller can be initialized in parallel. In this way, the initialization time of the entire SOC-level memory access verification process can be reduced to a level close to the initialization time of a single storage controller, and the initialization time of the entire SOC-level memory access verification process can be reduced to minutes, thereby reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of the SOC-level memory access verification, improving the verification speed of the SOC-level memory access verification, and improving the verification efficiency of the SOC-level memory access verification.

[0078] In an embodiment of the present application, when the register interface configuration simulator includes a storage controller initialization sequence, a request parsing module, a read request sending module, a write sending module, and a read response receiving module, the process of sending the storage controller initialization sequence to the connected storage controller through the register interface bus may include:

[0079] Parse each task in the storage controller initialization sequence through the request parsing module to obtain a read request or a write request or a read-after-write request;

[0080] Sending a read request to a register in a storage controller requested by the parsed read request or the read-after-write request through a read request sending module;

[0081] Sending the parsed write data to the register in the storage controller requested by the parsed write request or the read-after-write request through the write sending module;

[0082] The read response data returned by the register in the storage controller is received through the read response receiving module.

[0083] It can be understood that in an embodiment of the present application, after receiving the read response data returned by the register in the storage controller through the read response receiving module, the following operations can also be performed: if the read response data is response data corresponding to a read-and-write request, the read response data and the write data in the read-and-write request are bit-by-bit write-merged, and the write data after the bit-by-bit write-merge operation is sent to the register requested by the read-and-write request through the write sending module, thereby finally completing the read-and-write request.

[0084] It can be understood that the read-after-write request may include a register field bit parameter, a field range value parameter, and write data. The register field bit parameter refers to the start bit of the register field to be modified, and the field range value parameter refers to the bit width of the field to be modified.

[0085] Exemplarily, the so-called bit-by-bit write merge operation refers to the write modification of the field bits that need to be modified in the read response data. For example, assuming that the received read response data is 32'b00010000 (the right side is the low bit, the left side is the high bit, only bits 0 to 7 are shown, bits 8 to 31 are not shown, and all are 0); assuming that the register field bit parameter parsed by the read-after-write request is bit2 (i.e., 2 bits), the field range value parameter is 3, and the write data is 3'b011 (the right side is the low bit, the left side is the high bit), then the bit-by-bit write merge operation is: modify bits 2 to 4 of the read response data to 3'b 011 (the right side is the low bit, the left side is the high bit), and the new write data obtained after the bit-by-bit write merge is 32'b00001100 (the right side is the low bit, the left side is the high bit, only bits 0 to 7 are shown, bits 8 to 31 are not shown, and all are 0).

[0086] It can be understood that in the embodiment of the present application, after receiving the read response data returned by the register in the storage controller through the read response receiving module, the following operations can be performed: if the read response data is the response data corresponding to the read request, the read response data is bitwise ANDed with the preset read data parameter; if the result of the bitwise ANDed operation is inconsistent with the read data parameter, the read request is resent through the read request sending module. If the result of the bitwise ANDed operation is consistent with the read data parameter, the next request can be processed.

[0087] It can be understood that the so-called bitwise AND operation means performing AND operations on two data in sequence according to the number of bits. For example, for data 101 and data 110, the AND operation of 1 and 1, the AND operation of 0 and 1, and the AND operation of 1 and 0 are performed in sequence, and the final bitwise AND operation result is 100.

[0088] Based on the same inventive concept, an embodiment of the present application also provides a SOC-level memory access verification method, which can be applied to any storage controller of the above-mentioned SOC-level memory access verification system, wherein: the above-mentioned SOC-level memory access verification system needs to include a verification instruction issuing module, a memory, multiple storage controllers, and a register interface configuration simulator corresponding to each storage controller; wherein: different storage controllers are respectively connected to different memories, and for any storage controller: the verification instruction issuing module and the register interface configuration simulator corresponding to the storage controller are connected to the storage controller through the same register interface bus.

[0089] See also Figure 6 As shown, the SOC level memory access verification method may include:

[0090] S601: receiving a storage controller initialization sequence sent by a connected register interface configuration simulator through a register interface bus to perform initialization.

[0091] S602: After the initialization is completed, a verification instruction issued by a verification instruction issuing module is received through a register interface bus to perform memory access verification.

[0092] It is understandable that during the initialization process, the register interface configuration simulator will occupy the register interface bus, so that the verification instruction issuing module cannot issue the verification instruction to the storage controller. After the initialization is completed, the register interface configuration simulator will release the register interface bus, so that the verification instruction issuing module can issue the verification instruction to the storage controller.

[0093] Based on the above-mentioned SOC-level memory access verification method, the initialization of each storage controller can be implemented in parallel through the simulator configuration of each register interface, so that the initialization process time of the entire SOC-level memory access verification is reduced to a level close to the initialization time of a single storage controller, reducing the initialization time of the storage controller during the SOC-level memory access verification process, thereby reducing the time of the SOC-level memory access verification, improving the verification speed of the SOC-level memory access verification, and improving the verification efficiency of the SOC-level memory access verification.

[0094] It can be understood that in the embodiment of the present application, when the verification instruction issuing module includes a processor core, a verification instruction storage module and a network module, and the processor core, the verification instruction storage module and each storage controller are connected through the network module, and the verification instruction storage module stores the verification instruction, the processor core can continuously obtain the verification instruction of each storage controller from the verification instruction storage module by fetching instructions, and issue it to the corresponding storage controller through the register interface bus in the network module. That is, at this time, the verification instruction received by each storage controller through the register interface bus is the verification instruction obtained by the processor core from the verification instruction storage module and issued through the network module.

[0095] It should be understood that, for the sake of brevity, some of the contents described in the first embodiment of the SOC-level memory access verification system will not be repeated in the above two method embodiments.

[0096] Embodiment 2:

[0097] To facilitate understanding of the solution of the embodiment of the present application, Figure 4 Taking the specific implementation structure shown as an example, the solution of this application is exemplified:

[0098] like Figure 4 As shown, each register interface configuration simulator is connected to a storage controller and shares a set of register interface buses with the network module. The register interface configuration simulator simulates the hardware behavior of the emulation register interface according to the interface protocol definition, implements the register write and register read functions, and configures the storage controller initialization sequence from the register interface.

[0099] The software consists of two parts. One part is the storage controller initialization sequence, which exists in the form of a sequence of task calls and directly inherits the storage controller initialization sequence in the component-level verification environment. The other part is the functional test part, which is developed and implemented by a C program or an assembler, stored in the verification instruction storage module, and run by the processor core in the form of instruction fetch.

[0100] In an embodiment of the present application, the register configuration simulator includes a request parsing module, a write sending module, a read request sending module, a read response receiving module, and a storage controller initialization sequence.

[0101] The request parsing module is used to parse the behavior of the task in the storage controller initialization sequence, parse the type of request in the task, the address of the request, the data contained in the request, etc., and perform different operations according to different request types, and perform different operations on the received read response data. The write sending module is used to send write requests and write data to the bus, and perform write operations on the registers of the corresponding addresses. The read request sending module is used to send read requests to the bus, and perform read operations on the registers of the corresponding addresses. The read response data receiving module is used to receive the read response data returned by the registers, and send the received read response data to the request parsing module.

[0102] The requests included in the task in the storage controller initialization sequence include three types: read request, write request, and read-after-write request. The read and write tasks contain two parameters: request address parameter and data parameter. The read-after-write request task contains four parameters: request address parameter, register field bit number parameter, field range value parameter, and write data.

[0103] The request address parameter is the register address in the storage controller to be configured; the data parameter is the write data corresponding to the write request, or the read data parameter corresponding to the read request.

[0104] The register field bit number parameter refers to the starting bit of the register field to be modified. For example, assuming that the current register is a 32-bit register, the bit starts from bit 0 and the value range is 0 to 31, then the register field bit number parameter is a value from 0 to 31; the field range value parameter refers to the bit width of the field to be modified, and the minimum value is 1.

[0105] The request parsing module is used to parse the request behavior of the task. After the parsing is completed, it enters different processing modules for processing according to the corresponding request type. The working steps of the request parsing module are as follows:

[0106] Step 1: Call the storage controller initialization sequence and parse line by line. If the parsing request type is a read-after-write request, execute step 5, otherwise execute step 2;

[0107] Step 2: If the parsed request is a read request, go to step 4; otherwise, go to step 3;

[0108] Step 3: Send the write request and write data to the write send module;

[0109] Step 4: Send a read request to the read request sending module and wait for a read response; after receiving the read response data, perform a bitwise AND operation with the read data parameter and compare them. If they are not equal, continue to step 4;

[0110] Step 5: Send a read request to the read request sending module; after receiving the read response data, perform a bit-by-bit write merge operation with the write data; execute step 3.

[0111] In the above operation, the read response data comes from the read response receiving module.

[0112] The verification process is as follows:

[0113] Step 1: Connect the register configuration simulator to the storage controller in bind mode;

[0114] Step 2: The simulator is compiled and run, the initial value of the memory controller initialization completion mark signal is configured to 0, the SOC is powered on and reset, and the processor core reset is not released (at this time, other circuits of the SOC except the processor core are restored to the initial state, and the register interface works normally). After the memory controller is powered on and reset, the register configuration simulator starts working, performs the memory controller initialization configuration, and occupies the register interface bus.

[0115] Step 3: After the storage controller initialization configuration is completed, the initialization completion mark signal of the storage controller is configured to 1, the processor core is reset and released, and the register configuration simulator releases the register interface bus.

[0116] Step 4: The processor core starts to fetch instructions from the verification instruction storage module and performs memory access testing.

[0117] In the existing SOC-level memory access verification, the initialization of the storage controller is configured through the processor core, and the configuration time takes several hours or even more than a day, which is unacceptable for debugging or regression verification. After using the above solution, for the same test stimulus, the initialization time can be reduced to the same time as the storage controller initialization in the component-level memory access verification, which can be completed within a few minutes, greatly improving the efficiency of the SOC-level memory access verification.

[0118] The scheme of the present application uses a register interface configuration simulator to perform initialization configuration on the register interface. The register interface configuration simulator is directly bound to the register interface. The chip design does not require any changes. During operation, after the hardware initialization is completed, the bus is released and the software program starts working. For the program, the program behaviors of the two are completely consistent, but the verification efficiency can be improved. In addition, the scheme of the present application does not need to develop an initialization program at the soc level (i.e., a storage controller initialization sequence), and directly reuses the storage controller initialization sequence at the component level, reducing the time for writing and debugging the initialization program at the soc level.

[0119] It can be understood that for the sake of convenience, the drawings of the present application only show the case of two storage controllers, but in actual applications, the number of storage controllers can be more.

[0120] In the embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. The embodiments described above are merely illustrative. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be an indirect coupling or communication connection through some communication interface, device or unit, which can be electrical, mechanical or other forms.

[0121] Furthermore, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0122] In this document, relational terms such as first and second, etc. are used merely to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0123] As used herein, a plurality refers to two or more than two.

[0124] The above description is only an embodiment of the present application and is not intended to limit the protection scope of the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A SOC level memory access verification system, characterized in that: include: A plurality of storage controllers and a register interface configuration simulator corresponding to each storage controller; The register interface configuration simulator is a simulator that can simulate the register interface hardware behavior defined according to the interface protocol; wherein: each of the storage controllers is connected to the register interface configuration simulator corresponding to the storage controller via a register interface bus; The target storage controller is used to: receive the storage controller initialization sequence sent by the register interface configuration simulator through the register interface bus to perform initialization; The target storage controller is any storage controller among the multiple storage controllers.

2. The SOC level memory access verification system according to claim 1, characterized in that: The storage controller initialization sequence received by the target storage controller from the register interface configuration simulator is the same as the storage controller initialization sequence in the component-level verification environment corresponding to the target storage controller.

3. The SOC level memory access verification system according to claim 1, characterized in that: Each of the register interface configuration simulators is connected to the corresponding storage controller via a bind method.

4. The SOC level memory access verification system according to claim 1, characterized in that: The register interface configuration simulator includes: a storage controller initialization sequence, a request parsing module, a read request sending module, a write sending module, and a read response receiving module; The request parsing module is used to parse each task in the storage controller initialization sequence, and send the parsed read request to the read request sending module, send the parsed write request and write data to the write sending module, and send the parsed read-after-write request to the read request sending module and the write sending module in sequence; The read request sending module is used to send a read request to the register in the storage controller requested by the read request or the read-after-write request through the register interface bus; The write sending module is used to send write data to the register in the storage controller requested by the write request or the read-after-write request through the register interface bus; The read response receiving module is used to receive read response data returned by the register in the storage controller through the register interface bus.

5. The SOC level memory access verification system according to any one of claims 1 to 4, characterized in that: The SOC-level memory access verification system further includes: a verification instruction issuing module and a memory; wherein: Different storage controllers are respectively connected to different memories; The verification instruction issuing module and the register interface configuration simulator corresponding to the target storage controller are connected to the target storage controller via the same register interface bus; The target storage controller is used to: during the initialization phase, receive the storage controller initialization sequence issued by the register interface configuration simulator through the register interface bus to perform initialization; and, after the initialization is completed, receive the verification instruction issued by the verification instruction issuing module through the register interface bus to perform memory access verification.

6. The SOC level memory access verification system as claimed in claim 5, characterized in that: The verification instruction issuing module includes: a processor core, a verification instruction storage module, and a network module; wherein the processor core and the verification instruction storage module are connected via the network module; The network module and the register interface configuration simulator corresponding to the target storage controller are connected to the target storage controller via the same register interface bus; The processor core is used for obtaining the verification instruction from the verification instruction storage module and sending it to the target storage controller through the network module.

7. A method for initializing a storage controller in a SOC-level memory access verification process, characterized in that: The invention is applied to any register interface configuration simulator of a SOC-level memory access verification system; the SOC-level memory access verification system comprises: a plurality of memory controllers, and a register interface configuration simulator corresponding to each memory controller; the register interface configuration simulator is a simulator that can simulate the hardware behavior of the register interface defined according to the interface protocol; wherein: each of the memory controllers is connected to the register interface configuration simulator corresponding to the memory controller via a register interface bus; the method comprises: A storage controller initialization sequence is sent to the connected target storage controller via the register interface bus to initialize the target storage controller; the target storage controller is any storage controller among the multiple storage controllers.

8. The SOC level memory access verification method according to claim 7, characterized in that: The register interface configuration simulator includes: a storage controller initialization sequence, a request parsing module, a read request sending module, a write sending module, and a read response receiving module; Sending a storage controller initialization sequence to the connected storage controller via the register interface bus includes: Parsing each task in the storage controller initialization sequence through the request parsing module to obtain a read request or a write request or a read-after-write request; Sending a read request to the register in the storage controller requested by the parsed read request or read-after-write request through the read request sending module; Sending the parsed write data to the register in the storage controller requested by the parsed write request or the read-after-write request through the write sending module; The read response data returned by the register in the storage controller is received through the read response receiving module.

9. The SOC level memory access verification method according to claim 8, characterized in that: After receiving the read response data returned by the register in the storage controller through the read response receiving module, the method further includes: If the read response data is response data corresponding to a read-and-write request, a bit-by-bit write-merge operation is performed on the read response data and the write data in the read-and-write request, and the write data after the bit-by-bit write-merge operation is sent to the register requested by the read-and-write request through the write sending module.

10. The SOC level memory access verification method according to claim 8, characterized in that: After receiving the read response data returned by the register in the storage controller through the read response receiving module, the method further includes: If the read response data is response data corresponding to the read request, performing a bitwise AND operation on the read response data and a preset read data parameter; If the result of the bitwise AND operation is inconsistent with the read data parameter, the read request is resent through the read request sending module.

11. A SOC level memory access verification method, characterized in that: Applicable to any storage controller of SOC-level memory access verification system; The SOC-level memory access verification system includes: a verification instruction issuing module, a memory, multiple storage controllers, and a register interface configuration simulator corresponding to each storage controller; wherein: different storage controllers are respectively connected to different memories, and for any storage controller: the verification instruction issuing module and the register interface configuration simulator corresponding to the storage controller are connected to the storage controller through the same register interface bus; the method includes: Receiving a storage controller initialization sequence sent by a connected register interface configuration simulator through the register interface bus to perform initialization; After the initialization is completed, the verification instruction issued by the verification instruction issuing module is received through the register interface bus to perform memory access verification.

12. The SOC level memory access verification method according to claim 8, characterized in that: The verification instruction issuing module includes: a processor core, a verification instruction storage module, and a network module; wherein the processor core, the verification instruction storage module, and each storage controller are connected via the network module; the verification instruction storage module stores the verification instruction; wherein: The verification instruction received through the register interface bus is a verification instruction obtained by the processor core from the verification instruction storage module and issued through the network module.

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