Method and device for determining cutting points of quantum circuit

Abstract

The invention discloses a quantum circuit cutting point determination method and device, and the method comprises the steps: obtaining a to-be-cut quantum circuit, generating a graph corresponding to the quantum circuit, and enabling the vertex of the graph to represent a quantum logic gate in the quantum circuit, the edge of the graph represents a quantum bit segment connected with a corresponding quantum logic gate in the quantum circuit; obtaining a Laplacian matrix corresponding to the graph; according to the Laplacian matrix, determining a to-be-clustered sample corresponding to the quantum circuit; and performing spectral clustering on the to-be-clustered samples to obtain cutting points of the quantum circuit. According to the embodiment of the invention, the quantum circuit to be cut is processed, the processing result is subjected to spectral clustering, and the cutting point is accurately and quickly determined based on the characteristics of spectral clustering.

Description

Technical Field

[0001] The present application belongs to the technical field of quantum circuit splitting, and in particular to a method and device for determining a quantum circuit cutting point. Background Art

[0002] At present, although NISQ (Noisy Intermediate Scale Quantum) computers with hundreds of qubits have been designed, they are still too noisy to run large-bit quantum circuits directly. At the same time, for future mature large-scale fault-tolerant quantum computers, the large-scale integration of qubits is affected by inherent problems such as control systems, bit arrangement, and crosstalk between bits, and cannot be easily upgraded like classical integrated circuit chips. Quantum circuit splitting technology provides a feasible solution to the above problems. It splits the circuit into multiple subcircuits with small bit numbers and low depths. Each subcircuit runs separately on a NISQ computer. Finally, the output information of these subcircuits is recombined to obtain the target information, so as to achieve the purpose of simulating large-scale quantum circuits using small-scale quantum computers.

[0003] The key to splitting quantum circuits lies in the determination of the cutting point. The way of determining the cutting point determines the accuracy and efficiency of the quantum circuit splitting and is an important factor affecting the development of large-scale quantum circuits. Therefore, how to accurately and quickly determine the cutting point is a problem that needs to be solved urgently. Summary of the invention

[0004] The purpose of the present application is to provide a method and device for determining a quantum circuit cutting point, by processing a quantum circuit to be cut, performing spectral clustering on the processing results, and based on the characteristics of spectral clustering, accurately and quickly determining the cutting point.

[0005] An embodiment of the present application provides a method for determining a quantum circuit cutting point, the method comprising:

[0006] Obtaining a quantum circuit to be cut, and generating a graph corresponding to the quantum circuit, wherein the vertices of the graph represent quantum logic gates in the quantum circuit, and the edges of the graph represent quantum bit segments in the quantum circuit that connect corresponding quantum logic gates;

[0007] Obtaining the Laplace matrix corresponding to the graph;

[0008] Determining, according to the Laplace matrix, samples to be clustered corresponding to the quantum circuit;

[0009] Perform spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit.

[0010] Optionally, generating a graph corresponding to the quantum circuit includes:

[0011] Numbering the quantum logic gates according to the execution sequence of the quantum logic gates in the quantum circuit;

[0012] Based on the numbers of the quantum logic gates and the relationship between the quantum logic gates, a graph corresponding to the quantum circuit is generated, wherein the relationship is determined by the quantum bits acted on by the corresponding quantum logic gates.

[0013] Optionally, obtaining the Laplace matrix corresponding to the graph includes:

[0014] Using the graph, generating an adjacency matrix corresponding to the graph, wherein the adjacency matrix is ​​composed of weights of edges in the graph;

[0015] Based on the adjacency matrix, a Laplacian matrix corresponding to the graph is obtained.

[0016] Optionally, obtaining a Laplacian matrix corresponding to the graph based on the adjacency matrix includes:

[0017] Determining the weights to be processed in the adjacency matrix based on a target transmission direction, wherein the target transmission direction includes a transmission direction of the quantum state in the quantum circuit;

[0018] Adjusting the weights to be processed to obtain an adjacency matrix after the weights are adjusted;

[0019] The obtained adjacency matrix after weight adjustment is used to generate a Laplacian matrix corresponding to the graph.

[0020] Optionally, determining the weights to be processed in the adjacency matrix based on the obtained target transmission direction includes:

[0021] Using the obtained target transmission direction, potential cut edges are determined from the graph, and weights corresponding to the edges are used as weights to be processed in the adjacency matrix.

[0022] Optionally, performing spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit includes:

[0023] Determining a target number according to the jump points determined by the samples to be clustered, wherein the target number is the number of clusters of spectral clustering;

[0024] Performing spectral clustering on the samples to be clustered to obtain a clustering result consisting of a target number of clusters;

[0025] Based on the clustering result, a cutting point of the quantum circuit is determined.

[0026] Another embodiment of the present application provides a device for determining a quantum circuit cutting point, the device comprising:

[0027] A generation module, used to obtain a quantum circuit to be cut, and generate a graph corresponding to the quantum circuit, wherein the vertices of the graph represent quantum logic gates in the quantum circuit, and the edges of the graph represent quantum bit segments in the quantum circuit that connect corresponding quantum logic gates;

[0028] A first obtaining module, used to obtain the Laplace matrix corresponding to the graph;

[0029] A determination module, used to determine the samples to be clustered corresponding to the quantum circuit according to the Laplace matrix;

[0030] The second obtaining module is used to perform spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit.

[0031] Another embodiment of the present application provides a quantum super-cooperative operating system, which implements the determination of quantum circuit cutting points according to any of the methods described above.

[0032] Yet another embodiment of the present application provides a storage medium, wherein the storage medium stores a computer program, wherein the computer program is configured to implement any of the above methods when executed.

[0033] Yet another embodiment of the present application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to implement any of the above methods.

[0034] Compared with the prior art, the present invention first obtains the quantum circuit to be cut and generates a graph corresponding to the quantum circuit; then obtains the Laplace matrix corresponding to the graph; then determines the samples to be clustered corresponding to the quantum circuit according to the Laplace matrix; finally, performs spectral clustering on the samples to be clustered to obtain the cutting point of the quantum circuit. By processing the quantum circuit to be cut and performing spectral clustering on the processing results, the cutting point can be accurately and quickly determined based on the characteristics of spectral clustering. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 This is a network block diagram of a system for determining a quantum circuit cutting point provided by an embodiment of the present application;

[0036] Figure 2 A schematic diagram of a flow chart of a method for determining a quantum circuit cutting point provided in an embodiment of the present application;

[0037] Figure 3 A schematic diagram of the structure of a quantum circuit provided in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of a quantum circuit numbered according to execution sequence provided in an embodiment of the present application;

[0039] Figure 5 A schematic diagram of a diagram corresponding to a quantum circuit provided in an embodiment of the present application;

[0040] Figure 6 A schematic diagram of a target transmission direction provided in an embodiment of the present application;

[0041] Figure 7 A schematic diagram of a diagram corresponding to another quantum circuit provided in an embodiment of the present application;

[0042] Figure 8 A schematic diagram of a quantum circuit with a cutting point provided in an embodiment of the present application;

[0043] Fig. 9 A schematic diagram of the structure of a device for determining a quantum circuit cutting point provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0045] Figure 1 1 is a network block diagram of a system for determining a quantum circuit cutting point provided by an embodiment of the present application. The system for determining a quantum circuit cutting point may include a network 110, a server 120, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0046] The network 110 is a medium for providing communication links between various devices and computers connected together in the system for determining the cutting point of the quantum circuit, including but not limited to the Internet, corporate intranet, local area network, mobile communication network and their combination. The connection method can be wired, wireless communication links or optical fiber cables.

[0047] The server 120 and the client 140 are conventional data processing systems that may contain data and applications or software tools that perform conventional computing processes. The client 140 may be a personal computer or a network computer, so the data may also be provided by the server 120. The wireless device 130 may be a smart phone, a tablet, a laptop, a smart wearable device, etc. The storage unit 150 may include a database 151, which may be configured to store data such as quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0048] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application 162 (application 173). The application 162 (application 173) may be used to implement a quantum algorithm compiled according to the method for determining a quantum circuit cutting point provided in an embodiment of the present application.

[0049] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0050] It should be noted that a true quantum computer is a hybrid structure, which includes at least Figure 1 There are two major parts in it: the classical processing system 160, which is responsible for performing classical calculations and control; and the quantum processing system 170, which is responsible for running quantum programs and thus realizing quantum calculations.

[0051] The classical processing system 160 and the quantum processing system 170 may be integrated into one device or distributed in two different devices. For example, the first device including the classical processing system 160 runs a classical computer operating system, on which quantum application development tools and services are provided, as well as storage and network services required for quantum applications. Users develop quantum applications through the quantum application development tools and services thereon, and send quantum programs to the second device including the quantum processing system 170 through the network services thereon. The second device runs a quantum computer operating system, parses the code of the quantum program through the quantum computer operating system, and compiles it into instructions that can be recognized and executed by the quantum computer measurement and control system. The quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0052] In the classic processing system 160 based on silicon chips, the unit of the classic processor 161 is a CMOS tube. This computing unit is not limited by time and coherence, that is, this computing unit is not limited by the length of use and is available at any time. In addition, in silicon chips, the number of such computing units is also sufficient. Currently, the number of computing units in a classic processor is tens of thousands. The number of computing units is sufficient and the computing logic that can be selected by the CMOS tube is fixed, such as AND logic. When calculating with the help of CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the computing effect.

[0053] Unlike this logic unit in the classical processing system 160, the basic computing unit of the quantum processor 171 in the quantum processing system 170 is a quantum bit, and the input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the use time and is not available at any time. Making full use of the quantum bit within the available use time of the quantum bit is a key problem in quantum computing. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of a quantum computer. Each quantum bit realizes the computing function through the logical function configured on demand. In view of the limited number of quantum bits, the logical functions in the field of quantum computing are diverse, such as: Hadamard gate (Hadamard gate, H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. In quantum computing, it is necessary to use limited quantum bits combined with a variety of logical functions to achieve the computing effect.

[0054] A quantum program as a whole corresponds to a total quantum circuit, and the total number of quantum bits in the quantum circuit is the same as the total number of quantum bits in the quantum program. A quantum circuit can contain quantum bits and dozens, hundreds, or even thousands of quantum logic gates. The operation of a quantum circuit is the process in which all quantum logic gates evolve quantum states according to a certain execution sequence. It should be noted that the execution sequence is the time order in which quantum logic gates are executed.

[0055] Based on these differences, the design of the logical function acting on quantum bits (including the design of whether the quantum bits are used or not and the design of the efficiency of the use of each quantum bit) is the key to improving the computing performance of quantum computers, and requires special design. The above-mentioned design for quantum bits is a technical problem that ordinary computing devices do not need to consider or face. Based on this, in order to determine the cutting point of the quantum circuit in quantum computing and improve the accuracy and efficiency of quantum circuit splitting, this application proposes a method for determining the cutting point of the quantum circuit, which aims to improve the accuracy and efficiency of quantum circuit splitting by processing the quantum circuit to be cut and performing spectral clustering on the processing results to determine the cutting point.

[0056] See also Figure 2 , Figure 2 A schematic flow chart of a method for determining a quantum circuit cutting point provided in an embodiment of the present application may include the following steps:

[0057] S201: Obtain a quantum circuit to be cut, and generate a graph corresponding to the quantum circuit to be cut, wherein the vertices of the graph represent quantum logic gates in the quantum circuit, and the edges of the graph represent quantum bit segments in the quantum circuit that connect corresponding quantum logic gates.

[0058] The quantum circuit to be cut can be obtained through quantum application development tools and services provided by the classical processing system, or can be sent by other devices. The quantum circuit to be cut is processed so that the quantum circuit is converted into a corresponding graph, which can be a graph for spectral clustering, specifically, an undirected graph or a directed acyclic graph. If two quantum logic gates are in adjacent execution sequences in the quantum circuit to be cut and there are quantum bits that act together, there is an edge between the two vertices.

[0059] A quantum circuit includes a quantum bit, a timeline, and a quantum logic gate. A timeline corresponds to a quantum bit. A timeline is divided into multiple segments due to the action of a quantum logic gate. These segments are called quantum bit segments. A quantum bit segment includes a timeline corresponding to a quantum bit that is acted upon by two quantum logic gates, a timeline between a quantum bit input and a quantum logic gate, and a timeline between a quantum logic gate and a quantum bit output. For example, Figure 3 As shown, one quantum bit corresponds to multiple quantum bit segments, q0 corresponds to quantum bit segment A and quantum bit segment B, q1 corresponds to quantum bit segment C, quantum bit segment D and quantum bit segment E, and q2 corresponds to quantum bit segment F and quantum bit segment G.

[0060] In actual splitting, we may only care about the quantum bit segment that is connected to the two-bit quantum logic gate at both ends. This quantum bit segment corresponds to the edge in the graph, that is, the edge in the graph corresponds to the timeline corresponding to the quantum bit that is acted upon by the two quantum logic gates. Figure 3 For example, only quantum bit segment D has a corresponding edge in the graph. If there are other quantum logic gates acting after quantum logic gate U2, the edges in the generated graph may include one or more of quantum bit segments B, E, and G, which is determined by the quantum bit acted by quantum logic gate U2. The cutting point of the quantum circuit is located on the quantum bit segment. When a quantum bit segment has a cutting point, the quantum bit segment is cut into two quantum bit segments.

[0061] S202: Obtain the Laplacian matrix corresponding to the graph.

[0062] The graph is converted into a corresponding matrix. The rows and columns of the matrix represent the vertices of the graph. The elements in the matrix are determined by the edges of the graph. The Laplacian matrix can be obtained by further processing the matrix.

[0063] S203: Determine the samples to be clustered corresponding to the quantum circuit according to the Laplace matrix.

[0064] The eigenvector of the Laplace matrix can be calculated using standard linear algebra methods. For example, the Lanczos algorithm (an algorithm that transforms a symmetric matrix into a symmetric tridiagonal matrix through an orthogonal similarity transformation, named after the Hungarian mathematician Lanczos) can be used to quickly solve the problem, and the eigenvector finally obtained can be used as a sample to be clustered. It should be noted that the Laplace matrix can be a standardized Laplace matrix.

[0065] S204: Perform spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit.

[0066] Spectral clustering is performed on the clustering samples to obtain clustering results, and the cutting points of the quantum circuit can be obtained based on the clustering results.

[0067] It can be seen that the present application first obtains the quantum circuit to be cut and generates a graph corresponding to the quantum circuit; then obtains the Laplace matrix corresponding to the graph; then determines the samples to be clustered corresponding to the quantum circuit according to the Laplace matrix; finally, performs spectral clustering on the samples to be clustered to obtain the cutting point of the quantum circuit. By processing the quantum circuit to be cut and performing spectral clustering on the processing results, the cutting point can be accurately and quickly determined based on the characteristics of spectral clustering.

[0068] In some possible implementations of the present application, generating a graph corresponding to the quantum circuit includes:

[0069] Numbering the quantum logic gates according to the execution sequence of the quantum logic gates in the quantum circuit;

[0070] Based on the numbers of the quantum logic gates and the relationship between the quantum logic gates, a graph corresponding to the quantum circuit is generated, wherein the relationship is determined by the quantum bits acted on by the corresponding quantum logic gates.

[0071] The execution sequence of quantum logic gates in a quantum circuit can be predetermined or divided according to preset rules. The quantum logic gates in one execution sequence are numbered first, and then the quantum logic gates in the next execution sequence are numbered. For the same execution sequence, the quantum logic gates can be numbered starting from the quantum logic gates that act on the lower-order quantum bits, or of course, they can be numbered starting from the quantum logic gates that act on the higher-order quantum bits, as long as they are numbered according to certain rules. For example, the quantum circuit numbered according to the execution sequence can be as follows: Figure 4 As shown, the quantum circuit is a random Clifford circuit. At this time, there are only quantum bits and two-bit U gates in the quantum circuit. The dotted lines in the figure represent the divided execution sequence.

[0072] The relationship between quantum logic gates can be the order of execution of quantum logic gates. When quantum logic gates with adjacent execution sequences have quantum bits that work together, it means that the execution of these two quantum logic gates is dependent on each other. The execution of the previous quantum logic gate is required before the execution of the next quantum logic gate. In this case, there is an edge between the vertices corresponding to these two quantum logic gates in the graph. According to this rule, the generated Figure 3 The diagram corresponding to the quantum circuit shown can be expressed as Figure 5 As shown, the dotted line indicates that the corresponding quantum logic gate acts on the highest-order quantum bit or the lowest-order quantum bit.

[0073] In some possible implementations of the present application, obtaining the Laplacian matrix corresponding to the graph includes:

[0074] Using the graph, generating an adjacency matrix corresponding to the graph, wherein the adjacency matrix is ​​composed of weights of edges in the graph;

[0075] Based on the adjacency matrix, a Laplacian matrix corresponding to the graph is obtained.

[0076] The adjacency matrix, also known as the weight matrix, is an n×n symmetric matrix consisting of the weights between vertices. The weights between vertices are the weights of the edges connecting the vertices, and the weights of the edges are determined according to preset rules. Figure 4 The corresponding adjacency matrix W can be expressed as an upper triangular matrix as shown below:

[0077]

[0078] The Laplace matrix is ​​constructed based on the adjacency matrix and the degree matrix. The degree matrix is ​​a diagonal matrix, and the diagonal elements of the degree matrix can be Among them, w ij is the element in the i-th row and j-th column of the adjacency matrix. Of course, the diagonal elements of the adjacency matrix can also be directly used as elements in the degree matrix. The relationship between the Laplacian matrix, the adjacency matrix and the degree matrix can be: L = DW, where L is the Laplacian matrix and D is the degree matrix.

[0079] In some possible implementations of the present application, obtaining the Laplacian matrix corresponding to the graph based on the adjacency matrix includes:

[0080] Determining the weights to be processed in the adjacency matrix based on a target transmission direction, wherein the target transmission direction includes a transmission direction of the quantum state in the quantum circuit;

[0081] Adjusting the weights to be processed to obtain an adjacency matrix after the weights are adjusted;

[0082] The obtained adjacency matrix after weight adjustment is used to generate a Laplacian matrix corresponding to the graph.

[0083] The target transmission direction can be determined according to the transmission direction of the quantum information flow. For the quantum circuit to be cut in the present application, there can be only one target transmission direction. In this case, the quantum circuit can be the original quantum circuit or a quantum circuit that needs to be further cut after cutting the original quantum circuit. When there are multiple transmission directions for the quantum circuit to be cut, the quantum circuit to be cut can be segmented to determine the target transmission direction of each segmented quantum circuit.

[0084] When the target transmission direction is determined, the edges whose weights are to be reduced or increased can be determined from the graph, and then the weights to be processed in the adjacency matrix, that is, the elements to be processed in the adjacency matrix, can be determined. The weights to be processed are adjusted according to preset rules to obtain the adjacency matrix after the weights are adjusted. Each weight to be processed can be reduced by the same proportion or by the same value. Of course, for different weights to be processed, the same adjustment rules can be set, or different adjustment rules can be set. Based on the above example, each weight to be processed is reduced by the same proportion, and the adjacency matrix W′ after the weight adjustment can be obtained as shown below:

[0085]

[0086] In this application, by selectively changing the weights of the quantum bit segments (edges) connected to any U gate in the quantum circuit, the accuracy and efficiency of quantum circuit splitting can be improved. At the same time, it helps to balance the number of quantum bits and two-bit quantum logic gates split in the quantum circuit, improve the splitting effect, and promote the application of quantum circuit splitting technology.

[0087] In some possible implementations of the present application, determining the weights to be processed in the adjacency matrix based on the target transmission direction includes:

[0088] Using the target transmission direction, potential cut edges are determined from the graph, and weights corresponding to the edges are used as weights to be processed in the adjacency matrix.

[0089] For example, a target transmission direction can be Figure 6 As shown in the figure, the direction of the arrow is the target transmission direction, A, B, C, and D are 4 quantum bit segments respectively, then the corresponding Figure 5 Can become like Figure 7 As shown, the edge pointing to the same direction as the target transmission is the potential cutting edge, that is, Figure 7The edges with arrows are all potential cutting edges, and the edges corresponding to the dotted lines are also considered as potential cutting edges. Non-potential cutting edges are edges that are opposite to the target transmission direction. Increasing the weight of non-potential cutting edges is equivalent to reducing the weight of potential cutting edges. By reducing the weight of potential cutting edges or increasing the weight of non-potential cutting edges, the emergence of nested circuit splitting can be effectively avoided, and the number of split sub-circuits can be determined more conveniently.

[0090] In some possible implementations of the present application, performing spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit includes:

[0091] Determining a target number according to the jump points determined by the samples to be clustered, wherein the target number is the number of clusters of spectral clustering;

[0092] Performing spectral clustering on the samples to be clustered to obtain a clustering result consisting of a target number of clusters;

[0093] Based on the clustering result, a cutting point of the quantum circuit is determined.

[0094] Since the degree of connection between the two-bit quantum logic gates of different types of quantum circuits is different, the number of cutting points is also different. However, quantum circuit splitting is to simulate and combine quantum channels with classical channels. Too many cutting points have a great impact on the efficiency of quantum circuit execution. Therefore, before splitting the quantum circuit, it is necessary to determine the number of sub-circuits that the quantum circuit can be split into and the difficulty of splitting, that is, the number of cutting points. The number of sub-circuits can be determined by the samples to be clustered. Specifically, the first jump of the samples to be clustered arranged from small to large is determined, and the number of samples to be clustered before the jump is determined as the target number, that is, the number of sub-circuits obtained by splitting. The larger the jump, the easier it is to split the quantum circuit. Therefore, adjusting the weight of the adjacency matrix can help find a clearer k value.

[0095] The k value determines the number of clusters. The clustering result includes k clusters. The cut point can be determined by processing the k clusters. Figure 3 The clustering results corresponding to the quantum circuit shown are (1,2,4,6) and (3,5,7,8), so the two cutting points can be as follows Figure 8 As shown, × in the figure indicates the cutting point.

[0096] See also Fig. 9 , Fig. 9 A schematic diagram of a device for determining a quantum circuit cutting point provided in an embodiment of the present application, and Figure 2 Corresponding to the process shown, the device includes:

[0097] A generation module 901 is used to obtain a quantum circuit to be cut, and generate a graph corresponding to the quantum circuit, wherein the vertices of the graph represent quantum logic gates in the quantum circuit, and the edges of the graph represent quantum bit segments in the quantum circuit that connect corresponding quantum logic gates;

[0098] A first obtaining module 902 is used to obtain the Laplace matrix corresponding to the graph;

[0099] A determination module 903 is used to determine the samples to be clustered corresponding to the quantum circuit according to the Laplace matrix;

[0100] The second obtaining module 904 is used to perform spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit.

[0101] In some possible implementations of the present application, the generating module 901 may be specifically used for:

[0102] Numbering the quantum logic gates according to the execution sequence of the quantum logic gates in the quantum circuit;

[0103] Based on the numbers of the quantum logic gates and the relationship between the quantum logic gates, a graph corresponding to the quantum circuit is generated, wherein the relationship is determined by the quantum bits acted on by the corresponding quantum logic gates.

[0104] In some possible implementations of the present application, the first obtaining module 902 may include:

[0105] A generating unit, configured to generate an adjacency matrix corresponding to the graph using the graph, wherein the adjacency matrix is ​​composed of weights of edges in the graph;

[0106] An obtaining unit is used to obtain a Laplace matrix corresponding to the graph based on the adjacency matrix.

[0107] In some possible implementations of the present application, the obtaining unit may be specifically used to:

[0108] Determining the weights to be processed in the adjacency matrix based on a target transmission direction, wherein the target transmission direction includes a transmission direction of the quantum state in the quantum circuit;

[0109] Adjusting the weights to be processed to obtain an adjacency matrix after the weights are adjusted;

[0110] The obtained adjacency matrix after weight adjustment is used to generate a Laplacian matrix corresponding to the graph.

[0111] In some possible implementations of the present application, the obtaining unit may also be specifically used to:

[0112] Using the target transmission direction, potential cut edges are determined from the graph, and weights corresponding to the edges are used as weights to be processed in the adjacency matrix.

[0113] In some possible implementations of the present application, the second obtaining module 904 may be specifically used to:

[0114] Determining a target number according to the jump points determined by the samples to be clustered, wherein the target number is the number of clusters of spectral clustering;

[0115] Performing spectral clustering on the samples to be clustered to obtain a clustering result consisting of a target number of clusters;

[0116] Based on the clustering result, a cutting point of the quantum circuit is determined.

[0117] It can be seen that the present application first obtains the quantum circuit to be cut and generates a graph corresponding to the quantum circuit; then obtains the Laplace matrix corresponding to the graph; then determines the samples to be clustered corresponding to the quantum circuit according to the Laplace matrix; finally, performs spectral clustering on the samples to be clustered to obtain the cutting point of the quantum circuit. By processing the quantum circuit to be cut and performing spectral clustering on the processing results, the cutting point can be accurately and quickly determined based on the characteristics of spectral clustering.

[0118] An embodiment of the present application also provides a quantum-super cooperative operating system, which runs on a quantum computer including a quantum processor and / or a supercomputer including a classical processor, and is used to determine the cutting point of a quantum circuit according to the method described in the embodiment of the method side of the present application.

[0119] An embodiment of the present application further provides a storage medium, in which a computer program is stored, wherein the computer program is configured to implement the steps of any of the above method embodiments when executed.

[0120] Specifically, in this embodiment, the above storage medium may be configured to store a computer program for implementing the following steps:

[0121] S201: obtaining a quantum circuit to be cut, and generating a graph corresponding to the quantum circuit, wherein the vertices of the graph represent quantum logic gates in the quantum circuit, and the edges of the graph represent quantum bit segments in the quantum circuit that connect corresponding quantum logic gates;

[0122] S202: Obtaining the Laplacian matrix corresponding to the graph;

[0123] S203: Determine, according to the Laplace matrix, samples to be clustered corresponding to the quantum circuit;

[0124] S204: Perform spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit.

[0125] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to implement the steps in any one of the above method embodiments.

[0126] Specifically, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0127] Specifically, in this embodiment, the processor may be configured to implement the following steps through a computer program:

[0128] S201: obtaining a quantum circuit to be cut, and generating a graph corresponding to the quantum circuit, wherein the vertices of the graph represent quantum logic gates in the quantum circuit, and the edges of the graph represent quantum bit segments in the quantum circuit that connect corresponding quantum logic gates;

[0129] S202: Obtaining the Laplacian matrix corresponding to the graph;

[0130] S203: Determine, according to the Laplace matrix, samples to be clustered corresponding to the quantum circuit;

[0131] S204: Perform spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit.

[0132] The embodiments of this specification also provide a computer program product comprising instructions, which, when executed by a computer, enables the computer to perform the determination of the quantum circuit cut point in any of the above embodiments.

[0133] It can be understood that in the various implementations of this specification, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of this specification.

[0134] It can be understood that the various embodiments described in this specification can be implemented individually or in combination, and the embodiments of this specification are not limited to this.

[0135] Unless otherwise specified, all technical and scientific terms used in the embodiments of this specification have the same meaning as those generally understood by those skilled in the art of the technical field of this specification. The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit the scope of this specification. The term "and / or" used in this specification includes any and all combinations of one or more related listed items. The singular forms of "a", "above", and "the" used in the embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0136] It can be understood that the processor of the embodiment of this specification can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method implementation can be completed by the hardware integrated logic circuit or software instructions in the processor. The above processor can be a general processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiment of this specification can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of this specification can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor are combined and executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0137] It is understood that the memory in the embodiments of this specification may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasablePROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0138] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this specification.

[0139] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0140] In the several embodiments provided in this specification, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0141] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0142] In addition, each functional unit in each embodiment of the present specification may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0143] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this specification, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of this specification. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0144] The above is only a specific implementation of this specification, but the protection scope of this application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in this specification, which should be included in the protection scope of this specification. Therefore, the protection scope of this application should be based on the protection scope of the claims.

Claims

1. A method for determining a quantum circuit cutting point, characterized in that: The method comprises: Obtaining a quantum circuit to be cut, and generating a graph corresponding to the quantum circuit, wherein the vertices of the graph represent quantum logic gates in the quantum circuit, and the edges of the graph represent quantum bit segments in the quantum circuit that connect corresponding quantum logic gates; Obtaining the Laplace matrix corresponding to the graph; Determining, according to the Laplace matrix, samples to be clustered corresponding to the quantum circuit; Perform spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit.

2. The method according to claim 1, characterized in that Generating a graph corresponding to the quantum circuit includes: Numbering the quantum logic gates according to the execution sequence of the quantum logic gates in the quantum circuit; Based on the numbers of the quantum logic gates and the relationship between the quantum logic gates, a graph corresponding to the quantum circuit is generated, wherein the relationship is determined by the quantum bits acted on by the corresponding quantum logic gates.

3. The method according to claim 1 or 2, characterized in that: The obtaining of the Laplace matrix corresponding to the graph comprises: Using the graph, generating an adjacency matrix corresponding to the graph, wherein the adjacency matrix is ​​composed of weights of edges in the graph; Based on the adjacency matrix, a Laplacian matrix corresponding to the graph is obtained.

4. The method according to claim 3, characterized in that The step of obtaining a Laplace matrix corresponding to the graph based on the adjacency matrix includes: Determining the weights to be processed in the adjacency matrix based on a target transmission direction, wherein the target transmission direction includes a transmission direction of the quantum state in the quantum circuit; Adjusting the weights to be processed to obtain an adjacency matrix after the weights are adjusted; The obtained adjacency matrix after weight adjustment is used to generate a Laplacian matrix corresponding to the graph.

5. The method according to claim 4, characterized in that The step of determining the weights to be processed in the adjacency matrix based on the target transmission direction includes: Using the target transmission direction, potential cut edges are determined from the graph, and weights corresponding to the edges are used as weights to be processed in the adjacency matrix.

6. The method according to claim 1, characterized in that The performing spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit includes: Determining a target number according to the jump points determined by the samples to be clustered, wherein the target number is the number of clusters of spectral clustering; Performing spectral clustering on the samples to be clustered to obtain a clustering result consisting of a target number of clusters; Based on the clustering result, a cutting point of the quantum circuit is determined.

7. A device for determining a quantum circuit cutting point, characterized in that: The device comprises: A generation module, used to obtain a quantum circuit to be cut, and generate a graph corresponding to the quantum circuit, wherein the vertices of the graph represent quantum logic gates in the quantum circuit, and the edges of the graph represent quantum bit segments in the quantum circuit that connect corresponding quantum logic gates; A first obtaining module, used to obtain the Laplace matrix corresponding to the graph; A determination module, used to determine the samples to be clustered corresponding to the quantum circuit according to the Laplace matrix; The second obtaining module is used to perform spectral clustering on the samples to be clustered to obtain the cutting points of the quantum circuit.

8. A quantitative super-cooperative operating system, characterized in that: The quantum super cooperative operation system realizes the determination of the quantum circuit cutting point according to the method described in any one of claims 1 to 6.

9. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to implement the method according to any one of claims 1 to 6 when executed.

10. An electronic device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to implement the method according to any one of claims 1 to 6.

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