Image resolution expansion method, system, medium and equipment based on FPGA (Field Programmable Gate Array)

Abstract

The invention provides an image resolution expansion method and system based on an FPGA, a medium and equipment, and relates to the technical field of image processing. The parallel processing capability of the FPGA is maximized by adopting a memory access strategy and a data pipeline, and the resource utilization rate is improved. And a linear interpolation algorithm is adopted, so that the calculation complexity is low, the method is easy to implement on the FPGA, and the resource utilization of the FPGA is effectively optimized. And flexible data read-write control is realized through the design of the field counter and the double memories. Whether interpolation calculation is carried out or not is determined by judging whether two continuous rows of image data are the same or not, and the calculation amount can be remarkably reduced when an image containing a large number of repeated rows is processed. Compared with the prior art, computing resources can be reduced, so that expansion of the image resolution is completed in the FPGA.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular to an image resolution expansion method, system, medium and device based on FPGA. Background Art

[0002] Infrared imaging technology is widely used in military, security, industrial detection and other fields. At present, 640*512 infrared detectors have become one of the mainstream choices for infrared imaging systems due to their good performance and relatively moderate cost. In practical applications, the output of 640*512 infrared detectors is usually converted to PAL video format (720*576) to be compatible with existing video processing and display systems. However, with the rapid development of display technology and the continuous improvement of users' requirements for image quality, this resolution output has been difficult to meet the needs of many application scenarios.

[0003] In the related art, most of the image expansion methods for infrared images are implemented based on general-purpose processors or GPUs. These methods often consume a lot of computing resources and are difficult to implement in the FPGA inside the detector. Summary of the invention

[0004] The present application provides an image resolution expansion method, system, medium and device based on FPGA, which can reduce computing resources and thus complete the expansion of image resolution in FPGA.

[0005] In a first aspect, the present application provides an image resolution expansion method based on FPGA, the method comprising: Get the image to be expanded; Using the average value of adjacent pixels in each row of the image to be expanded as a pixel horizontal interpolation value, and inserting it between the corresponding adjacent pixels to obtain target image data; Writing the target image data into a memory, and reading two consecutive lines of the target image data from the memory respectively; Using the target image data corresponding to two consecutive rows as even-numbered row image data; Calculating the average value of pixels corresponding to two consecutive rows of the target image data to obtain odd-numbered rows of image data; The even-numbered lines of image data and the odd-numbered lines of image data are integrated to obtain a target image, wherein the resolution of the target image is greater than the resolution of the image to be expanded.

[0006] By adopting the above technical solutions, the memory access strategy and data pipeline are used to maximize the parallel processing capability of FPGA and improve resource utilization. The linear interpolation algorithm has low computational complexity and is easy to implement on FPGA, which effectively optimizes FPGA resource utilization. Flexible data read and write control is achieved through field counter and dual memory design. By judging whether two consecutive lines of image data are the same, it is determined whether to perform interpolation calculations, which can significantly reduce the amount of calculation when processing images containing a large number of repeated lines. Compared with related technologies, it can reduce computing resources, thereby completing the expansion of image resolution in FPGA.

[0007] Optionally, the memory includes a first memory and a second memory, the two consecutive lines of target image data include a first line of image data and a second line of image data, and the writing of the target image data into the memory and the reading of the two consecutive lines of target image data from the memory respectively include: Writing the target image data into the first memory at the first even-numbered line of the field counter, and reading the first-line image data of two consecutive lines of the target image data within two consecutive lines after the first even-numbered line; The first line of image data in the target image data is written into the second memory in the second even line of the field counter, and the second line of image data in two consecutive lines of the target image data is read, and the second even line is the line number of the field counter that is spaced one line after the first even line.

[0008] By adopting the above technical solution, the mechanism of alternating operation of the first memory and the second memory is adopted, combined with the precise control of the field counter, pipeline processing of data is realized. The target image data is written into the first memory in the first even-numbered row of the field counter, and the first-row image data is read in the following two rows. This design ensures the timing stability of data writing and reading. Then, the first-row image data is written into the second memory in the second even-numbered row, and the second-row image data is read from the first memory at the same time. This interleaved operation makes full use of the parallel processing capability of the FPGA.

[0009] Optionally, obtaining the image to be expanded includes: Acquire an initial image and a first clock frequency of the initial image, and determine a second clock frequency required for the image to be expanded, wherein the first clock frequency is less than the second clock frequency; The initial image is written into a FIFO register at the first clock frequency, and the initial image in the FIFO register is read at the second clock frequency to obtain the image to be expanded.

[0010] By adopting the above technical solution, the initial image and its corresponding first clock frequency are first obtained, and the higher second clock frequency required for the image to be expanded is determined. This design takes into account the difference in data volume and processing speed between the original image and the expanded image. By writing the initial image into the FIFO register at a lower first clock frequency, perfect synchronization with the original image source (such as a 640*512 infrared detector) is ensured, avoiding data loss or duplication. Subsequently, the system reads data from the FIFO register at a higher second clock frequency. This operation not only realizes a smooth conversion of the clock domain, but also provides sufficient time margin for subsequent resolution expansion processing. The use of the FIFO register effectively alleviates the speed mismatch problem between the two clock domains and ensures the continuity and stability of data transmission. This method can achieve seamless conversion from low resolution to high resolution while keeping the original frame rate unchanged, and control the image transmission delay to a minimum.

[0011] Optionally, acquiring an initial image and a first clock frequency of the initial image and determining a second clock frequency required for the image to be expanded includes: Acquire a maximum value of a first row counter of an initial image and a first clock frequency of the initial image, and acquire a maximum value of a second row counter required for the image to be expanded; Substituting the maximum value of the first row counter, the first clock frequency, and the maximum value of the second row counter into a relational expression, to obtain a second clock frequency required for the image to be expanded; The relationship is: Wherein, org_h_cnt_total represents the maximum value of the first row counter, clk_1 represents the first clock frequency, exp_h_cnt_total represents the maximum value of the second row counter, and clk_h represents the second clock frequency.

[0012] By adopting the above technical solution, the computing resource requirements are effectively reduced by accurately calculating and adapting the clock frequency of images with different resolutions, so that the expansion of image resolution can be efficiently completed in FPGA. It is possible to achieve dynamic adjustment of image resolution while minimizing additional computing resources, and provide a flexible solution for application scenarios with different resolution requirements. Optionally, the method of obtaining the maximum value of the first row counter of the initial image and obtaining the maximum value of the second row counter required for the image to be expanded includes: Acquire a first number of pixels corresponding to each row in the resolution of the initial image and a first field blanking of the initial image; Calculate the sum of the first number of pixels and the first field blanking to obtain the maximum value of the first row counter of the initial image; obtain the second number of pixels corresponding to each row in the resolution of the image to be expanded, and the second field blanking of the image to be expanded; calculate the sum of the second number of pixels and the second field blanking to obtain the maximum value of the second row counter of the image to be expanded.

[0013] By adopting the above technical solution, the field blanking changes that may occur during the image expansion process are taken into account, providing the system with more accurate timing control. By calculating the maximum value of the line counter of the initial image and the image to be expanded respectively, this method can not only accurately adapt to the image processing requirements of different resolutions, but also provide an accurate basis for the clock management and resource allocation inside the FPGA.

[0014] Optionally, the integrating the even-numbered lines of image data and the odd-numbered lines of image data to obtain a target image includes: The even-numbered line image data and the odd-numbered line image data are outputted in the order of the line numbers of the field counter to obtain a target image.

[0015] By adopting the above technical solution, the characteristics of the field counter are fully utilized to ensure that each line of the expanded image can be output and organized in the correct order. By arranging the even-numbered line image data and the odd-numbered line image data alternately, this method not only doubles the resolution in the vertical direction, but also ensures the continuity and integrity of the expanded image. The application of the field counter enables the system to accurately control the output timing of each line of data, effectively avoiding the problem of data misalignment or duplication. This output strategy based on the field counter also simplifies the complexity of data management, reduces additional buffering and sorting operations, and thus optimizes the use of FPGA resources.

[0016] Optionally, before calculating the average value of pixels corresponding to two consecutive rows of the target image data to obtain the odd-numbered rows of image data, the method further includes: Determining whether two consecutive rows of the target image data are the same; If the target image data of two consecutive rows are the same, the target image data are directly used as the odd-numbered row image data.

[0017] By adopting the above technical solution, by avoiding repeated calculations of the same data, this method not only saves the computing resources of the FPGA, but also improves the efficiency of the entire image processing process. At the same time, this method also ensures the consistency of image quality, because for completely identical continuous lines, direct copying can better maintain the characteristics of the original image than calculating the average value. In addition, this optimization strategy also indirectly improves the real-time performance of the system, especially when processing images containing a large number of repeated lines, the processing time can be significantly reduced.

[0018] In a second aspect, the present application provides an image resolution expansion system based on FPGA, the system comprising: An image acquisition module, used for acquiring the image to be expanded; A horizontal expansion module, used to use the average value of adjacent pixels in each row of the image to be expanded as a pixel horizontal interpolation, and insert it between the corresponding adjacent pixels to obtain target image data; A data staggered reading module, used for writing the target image data into a memory, and reading two consecutive lines of the target image data from the memory respectively; A first data determination module, configured to use the target image data corresponding to two consecutive rows as even-numbered row image data; A second data determination module is used to calculate the average value of pixels corresponding to two consecutive rows of the target image data to obtain odd-numbered row image data; The target image integration module is used to integrate the even-numbered line image data and the odd-numbered line image data to obtain a target image, wherein the resolution of the target image is greater than the resolution of the image to be expanded.

[0019] In a third aspect, the present application provides a computer storage medium, wherein the computer storage medium stores a plurality of instructions, wherein the instructions are suitable for being loaded by a processor and executing any one of the above methods.

[0020] In a fourth aspect, the present application provides an electronic device, comprising a processor, a memory and a transceiver, wherein the memory is used to store instructions, the transceiver is used to communicate with other devices, and the processor is used to execute the instructions stored in the memory so that the electronic device performs any one of the methods described above.

[0021] In summary, the beneficial effects brought about by the technical solution of this application include: By adopting the above technical solutions, the memory access strategy and data pipeline are used to maximize the parallel processing capability of FPGA and improve resource utilization. The linear interpolation algorithm has low computational complexity and is easy to implement on FPGA, which effectively optimizes FPGA resource utilization. Flexible data read and write control is achieved through field counter and dual memory design. By judging whether two consecutive lines of image data are the same, it is determined whether to perform interpolation calculations, which can significantly reduce the amount of calculation when processing images containing a large number of repeated lines. Compared with related technologies, it can reduce computing resources, thereby completing the expansion of image resolution in FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a flowchart of an image resolution expansion method based on FPGA according to an embodiment of the present application; Figure 2It is a schematic diagram of a vertical expansion structure provided by an embodiment of the present application; Figure 3 It is a structural schematic diagram of an image resolution expansion system based on FPGA in an embodiment of the present application; Figure 4 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0023] Description of reference numerals: 400, electronic device; 401, processor; 402, communication bus; 403, user interface; 404, network interface; 405, memory. DETAILED DESCRIPTION

[0024] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0025] In the description of the embodiments of the present application, words such as "illustrative", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "illustrative", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "illustrative", "for example" or "for example" is intended to present related concepts in a specific way.

[0026] In the description of the embodiments of the present application, the meaning of the term "multiple" refers to two or more. For example, multiple systems refer to two or more systems, and multiple screen terminals refer to two or more screen terminals. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0027] See also Figure 1 , is a flowchart of an FPGA-based image resolution expansion method provided in an embodiment of the present application. The method can be implemented by a computer program, can be implemented by a single-chip microcomputer, or can be run on an FPGA-based image resolution expansion system based on the von Neumann system. The computer program can be integrated into an application or run as an independent tool application. The specific steps of the FPGA-based image resolution expansion method are described in detail below.

[0028] S101: Acquire an image to be expanded.

[0029] The image to be expanded refers to the original image that needs to be processed for resolution enhancement. In the embodiment of the present application, it can be understood as image data obtained by reading the FIFO register and not yet interpolated. The image to be expanded is an intermediate state of image data, which has been converted from the initial image but has not yet been subjected to actual resolution expansion processing. According to the method of the present application, the image to be expanded is obtained by writing the initial image into the FIFO register at a first clock frequency and then reading it at a higher second clock frequency.

[0030] In this embodiment, in order to achieve efficient image processing and resolution expansion, this embodiment adopts a dual clock domain design. First, the data of the original image is written into the FIFO register at a lower clock frequency. This frequency matches the resolution and frame rate of the original image, ensuring the stable input of the data. Subsequently, the image data to be expanded is read out from the FIFO register at a higher clock frequency clk_h. In this way, the read and write rate balance of the FIFO can be ensured, that is, the time for the original resolution image to transmit 1 line of data to the FIFO register is exactly equal to the time for the extended resolution image to transmit 2 lines of data. Specifically, when the original resolution image has transmitted 512 lines of data, the extended resolution image can transmit 1024 lines. This method not only ensures that the FIFO register will not be filled, but also controls the image transmission delay to a range of no more than 1 line.

[0031] Based on the above embodiment, as an optional implementation manner, the specific step of acquiring the image with extension also includes S201-S202.

[0032] S201: Acquire an initial image and a first clock frequency of the initial image, determine a second clock frequency required for the image to be expanded, and the first clock frequency is less than the second clock frequency.

[0033] Wherein the first clock frequency refers to the reference clock frequency used for raw image data transmission and processing. In the embodiment of the present application, it can be understood as clk_1, which is used to control the rate at which the raw image data acquired by the 640*512 infrared detector is written into the FIFO register. This clock frequency matches the resolution and frame rate of the original image, ensuring the stable input of data. Specifically, the first clock frequency clk_1 determines the data transmission speed of the original resolution image (640*512), including the transmission rhythm of 512 lines per frame and 640 pixels per line. By using this lower clock frequency, it can be ensured that the raw image data can be accurately captured and stored according to the output rate of the detector, providing a stable and reliable data source for subsequent resolution expansion processing.

[0034] The second clock frequency refers to a high-speed clock frequency for processing and outputting extended resolution image data. In the embodiment of the present application, it can be understood as clk_h, which is used to control the rate of reading the image data to be extended from the FIFO register and the subsequent resolution extension processing. This clock frequency is higher than the first clock frequency clk_l to adapt to the processing requirements of higher resolution images after expansion. Specifically, the second clock frequency clk_h determines the data processing and transmission speed of the extended resolution image (1280*1024), including 1024 lines per frame and 1280 pixels per line. By using this higher clock frequency, it can be ensured that there is enough processing time to execute resolution extension algorithms such as linear interpolation, while ensuring that the extended image data can be generated and transmitted in time according to the requirements of the target output device. The setting of the second clock frequency is the key to achieving high-efficiency resolution expansion. It and the first clock frequency together constitute a dual clock domain design, which ensures the balance of the FIFO read and write rates, so that the entire image processing process can be pipelined, thereby achieving low-latency and high-efficiency image resolution expansion.

[0035] When implementing the image resolution expansion method of the present invention, it is first necessary to obtain the initial image and its corresponding first clock frequency, and determine the second clock frequency required for the image to be expanded. The core of this step is to process the conversion from the original resolution (640*512) to the expanded resolution (1280*1024) to ensure that the average rates of the read and write ends of the FIFO are equal.

[0036] First, the initial image with a resolution of 640*512 is obtained through the image input interface, and the clock signal associated with it is read to obtain the first clock frequency clk_l of the initial image. This clk_l is a clock frequency that matches the original resolution and is sufficient to support data transmission of 512 lines per frame and 640 pixels per line.

[0037] Next, the second clock frequency clk_h required for the image to be expanded (1280*1024 resolution) needs to be determined. Since the expanded image needs to process more pixel data while maintaining the same frame rate, clk_h must be greater than clk_l.

[0038] In order to realize the clock domain conversion from clk_l to clk_h, the present invention adopts FIFO (first in first out) register. The initial image data is written into FIFO at the frequency of clk_l, and then read out from FIFO at the higher frequency of clk_h. This method can effectively solve the data transmission problem between different clock domains and ensure the correctness and synchronization of data during the frequency conversion process.

[0039] Based on the above embodiment, as an optional implementation, a maximum value of a first row counter of an initial image and a first clock frequency of the initial image are obtained, and a maximum value of a second row counter required for the image to be extended is obtained; Substituting the maximum value of the first row counter, the first clock frequency and the maximum value of the second row counter into the relationship, the second clock frequency required for the image to be expanded is obtained; The relationship is: Wherein, org_h_cnt_total represents the maximum value of the first row counter, clk_l represents the first clock frequency, exp_h_cnt_total represents the maximum value of the second row counter, and clk_h represents the second clock frequency.

[0040] The maximum value of the first row counter refers to the total value of each row in the original image (i.e., the image with a resolution of 640*512). It includes not only the number of visible pixels, but also the count of the horizontal blanking period. Specifically, the maximum value of the first row counter is equal to the number of valid pixels per row plus the number of pixels in the horizontal blanking period. For example, if the horizontal blanking period takes up 160 pixel times, then the maximum value of the first row counter is 800 (640+160). This value reflects the total number of clock cycles that the FPGA needs to process from the beginning of one row to the beginning of the next row.

[0041] The second row counter maximum value refers to the total value of each row in the expanded image (i.e., the image with a resolution of 1280*1024). Similar to the first row counter maximum value, it includes not only the number of visible pixels, but also the count of the horizontal blanking period. Specifically, the second row counter maximum value is equal to the number of valid pixels in each row after expansion plus the number of pixels in the corresponding horizontal blanking period.

[0042] In the embodiment of the present application, it can be understood that the maximum value of the second row counter is a value greater than or equal to 1280. For example, if the extended horizontal blanking period occupies 320 pixel times, then the maximum value of the second row counter is 1600 (1280+320). This value reflects the total number of clock cycles that the FPGA needs to process from the start of one row to the start of the next row at the extended resolution.

[0043] In the specific implementation, we first need to obtain the maximum value of the first row counter (org_h_cnt_total) and the first clock frequency (clk_l) of the initial image. org_h_cnt_total reflects the total number of pixels per row in the 640*512 resolution image, including valid pixels and horizontal blanking period. clk_l is the clock frequency required to process this resolution image. These two parameters can usually be directly obtained from the image source or system configuration.

[0044] Next, we need to determine the maximum value of the second row counter (exp_h_cnt_total) required for the image to be expanded (1280*1024 resolution). exp_h_cnt_total represents the total number of pixels per row of the expanded image, including valid pixels and the corresponding horizontal blanking period. This value can be pre-calculated or set according to the target resolution and system requirements.

[0045] After obtaining these parameters, substitute them into the relationship. The principle of the relationship is that the time required to process a line of the original image and the extended image should be consistent while keeping the frame rate unchanged. The time required to process a line of the original image is org_h_cnt_total / clk_l, while the time required to process a line of the extended image is (2×exp_h_cnt_total) / clk_h because the horizontal expansion is doubled. The 2x coefficient in the equation reflects the doubling of the horizontal resolution.

[0046] In an optional implementation manner, the maximum value of the first row counter and the maximum value of the second row counter may be obtained by using the following steps.

[0047] Acquire a first number of pixels corresponding to each row in the resolution of the initial image and a first field blanking of the initial image; Calculate the sum of the first pixel number and the first field blanking to obtain the maximum value of the first line counter of the initial image; Acquire a second number of pixels corresponding to each row in the resolution of the image to be expanded, and a second field blanking of the image to be expanded; The sum of the second pixel number and the second field blanking is calculated to obtain the maximum value of the second row counter of the image to be expanded.

[0048] Among them, the first field blanking refers to the time period outside the effective display area in the vertical direction of the original image (640*512 resolution). Specifically, it includes the sum of the three parts of the vertical front shoulder, the vertical synchronization pulse and the vertical back shoulder. During this period of time, there is no effective image data transmission, but it is used for vertical retracement and synchronization of the display device. In the embodiment of the present application, it can be understood that the first field blanking is a value expressed in the number of lines, which represents the number of additional lines in addition to the 512 effective display lines in a complete image frame. For example, if the total vertical period is 525 lines, then the first field blanking is 13 lines (525-512). These 13 lines are used for vertical synchronization and retracement.

[0049] Among them, the second field blanking refers to the time period outside the effective display area in the vertical direction of the expanded image (1280*1024 resolution). Similar to the first field blanking, it also includes the sum of the three parts of the vertical front shoulder, the vertical synchronization pulse and the vertical back shoulder. During this period of time, there is no effective image data transmission, but it is used for vertical retrace and synchronization of high-resolution display devices. In the embodiment of the present application, it can be understood that the second field blanking is a value expressed in the number of lines, indicating the number of additional lines in addition to the 1024 effective display lines in the expanded complete image frame. For example, if the total vertical period after expansion is 1066 lines, then the second field blanking is 42 lines (1066-1024). These 42 lines are used for vertical synchronization and retrace of high-resolution display.

[0050] In the specific implementation, we first need to obtain the parameters of the initial image. For the initial image with a resolution of 640*512, the number of the first pixels corresponding to each line is 640, which represents the number of pixels actually displayed in each line. At the same time, we also need to obtain the first field blanking of the initial image, which includes the sum of the horizontal front porch, horizontal synchronization pulse and horizontal back porch. Assuming that the first field blanking is 160 pixels, we can calculate the maximum value of the first line counter of the initial image: 640+160=800. This value represents the total clock cycle required to process a line of data of the initial image.

[0051] Next, we need to obtain the parameters of the image to be expanded. For the image to be expanded with a resolution of 1280*1024, the number of second pixels corresponding to each row is 1280. We also need to obtain the second field blanking of the image to be expanded. Assuming that the second field blanking is 320 pixels (usually high-resolution images have a longer blanking period to adapt to more complex timing requirements), we can calculate the maximum value of the second row counter of the image to be expanded: 1280+320=1600. This value represents the total clock cycle required to process a row of data of the image to be expanded.

[0052] S202: writing the initial image into the FIFO register at a first clock frequency, and reading the initial image in the FIFO register at a second clock frequency to obtain the image to be expanded.

[0053] In the specific implementation, first configure a FIFO register of appropriate size in the FPGA, whose depth needs to be sufficient to accommodate at least one or more lines of image data, while taking into account the possible speed difference between the two clock domains. Then, the initial image data is written to the FIFO register at the first clock frequency. This process is synchronous, and one pixel data is written per clock cycle. The write operation needs to be precisely controlled to ensure that the correct pixel data is written during each valid display cycle, and the write is suspended during the blanking period. Next, read the data from the FIFO register at the second clock frequency, which is the core of the expansion operation. Since the second clock frequency is usually higher than the first clock frequency, data can be read multiple times within the duration of each original pixel, thereby achieving horizontal expansion. During the reading process, data repetition and interpolation need to be implemented. For example, for 2x horizontal expansion, each pixel can be simply read twice, or interpolation calculations can be performed between adjacent pixels to generate new pixel values. This process requires precise control to ensure that the generated image to be expanded maintains the correct timing and pixel ratio.

[0054] S102: taking the average value of adjacent pixels in each row of the image to be expanded as a pixel horizontal interpolation value, and inserting it between corresponding adjacent pixels to obtain target image data.

[0055] The target image data refers to the image data to be presented on a high-resolution display device after the horizontal resolution expansion process. In the embodiment of the present application, it can be understood as the image data expanded from the original 640*512 resolution to the 1280*512 resolution. Specifically, the target image data includes the color and brightness information of each pixel after the expansion. This information is obtained by linear interpolation of the original image data.

[0056] In the embodiment of the present invention, the average value of adjacent pixels in each row of the image to be expanded is used as the pixel horizontal interpolation and inserted between the corresponding adjacent pixels to obtain the target image data, which is a key step to achieve high-quality image horizontal resolution expansion. The selection of this method is based on the linear interpolation principle in image processing, and aims to increase the horizontal resolution by calculating and inserting new pixel values ​​while maintaining the original image information, thereby achieving expansion from 640*512 resolution to 12805*12 resolution.

[0057] In the specific implementation, each row of the image to be expanded needs to be processed first. For each pair of adjacent pixels in each row, such as P(n) and P(n+1), calculate their average value [P(n)+P(n+1)] / 2, and insert this average value as the new interpolation pixel P'(2n+1) between the original pixels. The original pixel remains unchanged, that is, P'(2n)=P(n). This process starts from the first pixel of each row and continues to the second to last pixel. For the last pixel of each row, since there are no subsequent pixels for calculating the average value, it is directly copied once, that is, P'(1279)=P(639). This processing method ensures that each row after expansion has 1280 pixels, doubling the resolution in the horizontal direction.

[0058] In the actual hardware implementation, this process is closely integrated with clock control and FIFO reading. A raw pixel is read from the FIFO every other clock cycle, and the interpolation calculation is performed using the idle clock cycles. This timing arrangement not only ensures the continuity of data reading, but also provides enough time window for interpolation calculation, so that the entire expansion process can be carried out in real time without additional buffering or delay.

[0059] S103: writing the target image data into the memory, and reading two consecutive lines of target image data from the memory respectively.

[0060] In the specific implementation, the target image data with a resolution of 1280*512 obtained by horizontal interpolation is first written into the memory in row order. The memory is usually selected as a RAM with sufficient capacity and read / write speed to ensure that it can accommodate the image data after the entire frame is expanded and support fast read and write operations. During the writing process, the target image data of 1280 pixels per row is stored continuously to form a complete image data block.

[0061] After writing is completed, the system starts to read data from the memory for output. The key here is to read two consecutive lines of target image data at the same time. Specifically, the system reads the data of the nth line and the n+1th line at the same time. The design of this reading method takes into account the needs of many aspects. First, it provides the necessary data basis for possible vertical interpolation operations. Although the current target image data maintains the original 512 lines in the vertical direction, by reading two consecutive lines of data at the same time, the system reserves operating space for possible future vertical resolution expansion. Secondly, this reading method can realize pipeline processing of data and improve the overall efficiency of the system.

[0062] Based on the above embodiment, as an optional implementation, step S103 of vertical expansion specifically includes S401-S402.

[0063] S301: writing target image data into a first memory at a first even-numbered line of a field counter, and reading a first line of image data in two consecutive lines of target image data after the first even-numbered line.

[0064] The field counter refers to a counter device for tracking and counting vertical synchronization pulses in a video signal. In the embodiment of the present application, it can be understood as a digital counter for recording and controlling the number of vertical lines of an image. The field counter is mainly used to track which line of the image is currently being processed or displayed. It starts counting from 0, and increments by 1 after each line of image data is processed until the total number of lines of the image (512 in this case) is reached, and then reset to 0 to start counting the next frame of the image.

[0065] Among them, the first memory refers to a storage device for temporarily storing and buffering image data. In the embodiment of the present application, it can be understood as a high-speed random access memory (RAM) for storing target image data after horizontal resolution expansion processing. In the embodiment of the present application, the first memory can be understood as a dual-port RAM or a storage device with similar functions. The reason for selecting a dual-port RAM is that it can support data writing and reading operations at the same time. The dual-port feature allows the system to read stored data for display or further processing while writing new target image data, thereby realizing parallel operation of data processing and output.

[0066] The first even-numbered row of the field counter (i.e., exp_v_cnt=2n, where n=0) writes the target image data obtained after the horizontal resolution expansion process into the first memory (RAM1). Then, in the two consecutive rows after the first even-numbered row (i.e., exp_v_cnt=2n+1 and exp_v_cnt=2n+2), the system starts to read the first row of image data in the two consecutive rows of target image data stored in RAM1. The data writing operation is arranged to be performed in the even-numbered rows, which reserves a sufficient time window for the subsequent reading operation, ensuring that when reading the data, the data of the previous row has been completely written and stabilized, thereby avoiding potential data conflicts and reading errors.

[0067] In specific implementation, when the field counter reaches the first even value (exp_v_cnt=2n, n=0), the system activates the write control signal to write the target image data of 1280 pixels to address 0 to address 1279 of RAM1 in sequence. This process is continuous, ensuring that a complete row of image data is stored. Subsequently, during the two rows when the field counter values ​​are 2n+1 and 2n+2, the system activates the read control signal to read the data of the 1280 pixels again, starting from address 0 of RAM1, i.e., the image data of the first row. It is worth noting that the read operation is deliberately arranged to be performed within two rows after the write operation. The purpose of this is to ensure that the data read is already stable, rather than data that may still be in the writing process.

[0068] That is, the even-numbered image data is written into the first memory in the even-numbered row (2n) of the field counter, and the first image data is read from the first memory in the two consecutive rows (2n+1 and 2n+2) after the even-numbered row. For example, the image data of RAM1 is read starting from the (2n+1)th row of the field counter, and the data is read all the way to the (2n+1024)th row of the field counter, and a total of 1024 rows are read. The data of every two rows are completely consistent. For example, the field counter rows (2n+1) and (2n+2) read the first row of the image data; the field counter rows (2n+3) and (2n+4) read the second row of the image data... The field counter rows (2n+1023) and (2n+1024) read the 512th row (the last row) of the image data.

[0069] S302: Write the first line of image data in the target image data into the second memory at the second even line of the field counter, and read the second line of image data in two consecutive lines of target image data after the second even line, where the second even line is the line number of the field counter that is one line apart after the first even line.

[0070] Specifically, the first line of the target image data is written into the second memory (RAM2) at the second even line of the field counter (i.e., exp_v_cnt=2n+2, where n=0). Then, within two consecutive lines after the second even line (i.e., exp_v_cnt=2n+3 and exp_v_cnt=2n+4), the system starts to read the second line of the target image data stored in the first memory (RAM1). It should be noted here that the second even line is the field counter line number after the first even line by one line.

[0071] The first line of image data is written to RAM2 to create a data buffer so that two different lines of image data can be accessed simultaneously in subsequent processing. Secondly, the second line of image data is read within two lines after the second even-numbered line. This approach ensures the timing correctness of the data and reserves sufficient time for possible data processing operations.

[0072] In specific implementation, when the field counter reaches the second even value (exp_v_cnt=2n+2, n=0), the system activates the write control signal of RAM2, and writes the first line of image data (1280 pixels) previously read from RAM1 to address 0 to address 1279 of RAM2 in sequence. This process is continuous, ensuring that the complete first line of image data is stored in RAM2. Subsequently, during the two lines with field counter values ​​of 2n+3 and 2n+4, the system activates the read control signal of RAM1, and reads 1280 pixels of data, i.e., the image data of the second line, starting from the corresponding address of RAM1. The read operation here is deliberately arranged to be performed within two lines after the write operation, in order to ensure that the data read is already stable and avoid potential data conflicts.

[0073] By storing the first line of data in RAM2 and reading the second line of data from RAM1 at the same time, the system can access two different lines of image data at the same time. This facilitates subsequent complex image processing operations, especially operations that require the participation of multiple lines of data (such as interpolation or filtering in the vertical direction). Secondly, this method greatly improves the flexibility of data processing. For example, when performing vertical resolution expansion, the system can simultaneously access the first line of data stored in RAM2 and the second line of data being read from RAM1, perform real-time interpolation calculations, and generate new line data.

[0074] In addition, this interleaving of writing and reading forms an efficient data pipeline. When the second line of data begins to be read from RAM1, the first line of data has been written to RAM2 and is available. This pipeline operation ensures that the entire system can continue to operate efficiently, minimizing waiting or idle time. This is essential for achieving real-time image processing and display, especially when processing high-resolution images or video streams, which can significantly improve the overall performance of the system.

[0075] See also Figure 2 , is a schematic diagram of a vertically expanded structure provided in an embodiment of the present application, in which RAM1 is a first memory, RAM2 is a second memory, and A, B, and C respectively represent different rows of a field counter.

[0076] Figure 2Specifically, it can be divided into the following stages: Data writing stage: When exp_v_cnt (field counter) is 0, the system starts to write the first line of image data to RAM1. This process continues until exp_v_cnt = 1. The first data reading stage: When exp_v_cnt = 1 and exp_v_cnt = 2, the system reads the first line of data from RAM1. This process spans two counter cycles, which may be to ensure the stability of the data or to reserve time for subsequent processing. Data transfer stage: When exp_v_cnt = 2, the system writes the first line of data previously read from RAM1 to RAM2. This process creates a data buffer that allows the system to access two different data rows at the same time. The second data reading stage: When exp_v_cnt = 3 and exp_v_cnt = 4, the system reads the second line of data from RAM1. Similarly, this process also spans two counter cycles. Cyclic process: The figure shows that when exp_v_cnt = 4, the system starts to write new data (i.e., the third line) to RAM1, which shows that the whole process is cyclic. Data flow: The arrows in the figure clearly show the flow of data between RAM1 and RAM2. Data is first written to RAM1, then read and written to RAM2, and new data is written to RAM1 at the same time, forming a continuous data flow.

[0077] In the above way, the original pixel data can be continuously read from FIFO, and then the horizontal resolution of the image is expanded and stored in RAM1, and then RAM1 is read and stored in RAM2, and then RAM2 is read and the vertical resolution is expanded. This pipeline operation continues until the transmission of a frame of image is completed. The image is expanded from the input 640*512 resolution to the output 1280*1024 resolution.

[0078] S104: Using the corresponding target image data in two consecutive rows as even-numbered row image data.

[0079] Specifically, after the system processes the data in the first memory (RAM1) and the second memory (RAM2), we define the corresponding target image data in two consecutive rows as even-numbered row image data. Here, "two consecutive rows" refers to two adjacent rows in the original 640*512 resolution image, and "corresponding target image data" refers to the data at the 1280*1024 resolution after the horizontal resolution expansion process.

[0080] In the specific implementation, the system first reads two consecutive lines of target image data from RAM1 and RAM2. Assuming that the current processing is the nth line and the n+1th line (n is an even number), the system will read these two lines of data into the processing unit respectively. Then, the processing unit marks these two lines of data as the even-numbered line image data of the nth line and the n+2th line. This means that in the output 1280*1024 resolution image, these two lines of data will correspond to the nth line and the n+2th line respectively.

[0081] S105: Calculate the average value of pixels corresponding to two consecutive rows of target image data to obtain odd-numbered rows of image data.

[0082] In specific implementation, first, by calculating the average value of two adjacent rows of pixels, we can smoothly increase the vertical resolution while maintaining the overall structure of the image. This interpolation method can effectively reduce the aliasing of the image in the vertical direction, making the expanded image more natural and coherent. Secondly, average value calculation is an interpolation method with low computational complexity, which can ensure the real-time processing capability of the system while ensuring image quality, which is particularly important for scenes that require efficient processing.

[0083] In specific implementation, the system first accesses two consecutive rows of target image data stored in RAM1 and RAM2. Assuming that the current processing is the nth row and the n+1th row (n is an even number), these two rows have been defined as even-numbered row image data in the previous step, corresponding to the nth row and the n+2th row of the output image, respectively. The system will read these two rows of data pixel by pixel and perform the following processing: For each horizontal position x, the calculation formula is: odd-numbered row pixel value (x) = (nth row pixel value (x) + n+1th row pixel value (x)) / 2. This calculation process will be performed on all 1280 horizontal pixels to generate the n+1th row data between the nth row and the n+2th row, that is, the odd-numbered row image data.

[0084] As an optional implementation manner, it is determined whether two consecutive rows of target image data are the same; if the two consecutive rows of target image data are the same, the target image data are directly used as odd-numbered row image data.

[0085] First, determine whether two consecutive lines of target image data are the same. If they are the same, directly use the target image data as the odd-numbered line image data. In specific implementation, when the system processes two consecutive lines of target image data read from RAM1 and RAM2, it first performs a data comparison. Assuming that the current processing is the nth line and the n+1th line (n is an even number), the system will compare these two lines of data pixel by pixel. For images containing a large number of repeated lines (such as some computer-generated images or natural images with large uniform areas), this method can greatly reduce the amount of calculation and speed up the processing.

[0086] S106: Integrate the image data of the even-numbered lines and the image data of the odd-numbered lines to obtain a target image, wherein the resolution of the target image is greater than the resolution of the image to be expanded.

[0087] In the specific implementation, the system will create a new 1280*1024 pixel image buffer to store the final target image. Then, the system will read the processed even and odd rows of image data from RAM1 and RAM2 in sequence. For each pair of consecutive rows (assuming it is the nth row and the n+1th row, n starts from 0), the system will copy the even row data (nth row) directly to the nth row of the target image buffer, and copy the corresponding odd row data (n+1th row) to the n+1th row of the target image buffer. This process will be repeated 512 times until all 1024 rows of data are filled into the target image buffer.

[0088] As an optional implementation, the image data of even-numbered lines and the image data of odd-numbered lines are output according to the line number arrangement order of the field counter to obtain the target image.

[0089] In specific implementation, the system will operate according to the following process: First, initialize a field counter, which starts counting from 0, corresponding to the first line of the image. Then, the system will decide whether to output even-numbered line data or odd-numbered line data based on the value of the field counter. If the value of the field counter is an even number, the system will read and output the corresponding even-numbered line image data from RAM1; if the value of the field counter is an odd number, the system will read and output the corresponding odd-numbered line image data from RAM2. For each line of data output, the field counter increases by 1. This process will continue until all 1024 lines of data are output, forming the final target image with a resolution of 1280*1024.

[0090] The following is an embodiment of the system of the present application, which can be used to execute the embodiment of the method of the present application. For details not disclosed in the embodiment of the system of the present application, please refer to the embodiment of the method of the application.

[0091] See also Figure 3 , which shows a schematic diagram of the structure of an FPGA-based image resolution expansion system provided by an exemplary embodiment of the present application. The system can be implemented as all or part of the system through software, hardware, or a combination of both. The FPGA-based image resolution expansion system includes: An image acquisition module, used for acquiring the image to be expanded; A horizontal expansion module is used to use the average value of adjacent pixels in each row of the image to be expanded as a pixel horizontal interpolation value and insert it between corresponding adjacent pixels to obtain target image data; A data staggered reading module is used to write the target image data into the memory, and read two consecutive lines of target image data from the memory respectively; A first data determination module, used for taking corresponding target image data in two consecutive rows as even-numbered row image data; The second data determination module is used to calculate the average value of pixels corresponding to two consecutive lines of target image data to obtain odd-numbered lines of image data; The target image integration module is used to integrate the image data of the even-numbered lines and the image data of the odd-numbered lines to obtain a target image, wherein the resolution of the target image is greater than the resolution of the image to be expanded.

[0092] Based on the above embodiment, as an optional embodiment, the image acquisition module is also used to acquire the initial image and the first clock frequency of the initial image, determine the second clock frequency required for the image to be expanded, and the first clock frequency is less than the second clock frequency; write the initial image into the FIFO register at the first clock frequency, and read the initial image in the FIFO register at the second clock frequency to obtain the image to be expanded.

[0093] Based on the above embodiment, as an optional embodiment, the image acquisition module is further used to obtain the maximum value of the first row counter of the initial image and the first clock frequency of the initial image, and obtain the maximum value of the second row counter required for the image to be expanded; the maximum value of the first row counter, the first clock frequency and the maximum value of the second row counter are substituted into the relationship to obtain the second clock frequency required for the image to be expanded; the relationship is: Wherein, org_h_cnt_total represents the maximum value of the first row counter, clk_l represents the first clock frequency, exp_h_cnt_total represents the maximum value of the second row counter, and clk_h represents the second clock frequency.

[0094] Based on the above embodiment, as an optional embodiment, the image acquisition module is also used to acquire the first number of pixels corresponding to each row in the resolution of the initial image, and the first field blanking of the initial image; calculate the sum of the first number of pixels and the first field blanking to obtain the maximum value of the first row counter of the initial image; acquire the second number of pixels corresponding to each row in the resolution of the image to be expanded, and the second field blanking of the image to be expanded; calculate the sum of the second number of pixels and the second field blanking to obtain the maximum value of the second row counter of the image to be expanded.

[0095] On the basis of the above embodiment, as an optional embodiment, the data difference reading module is also used to write the target image data into the first memory in the first even row of the field counter, and read the first row of image data in two consecutive rows of target image data after the first even row; write the first row of image data in the target image data into the second memory in the second even row of the field counter, and read the second row of image data in two consecutive rows of target image data after the second even row, and the second even row is the row number of the field counter with one row interval after the first even row.

[0096] Based on the above embodiment, as an optional embodiment, the first data determination module is further used to output the even-numbered line image data and the odd-numbered line image data according to the line number arrangement order of the field counter to obtain the target image.

[0097] Based on the above embodiment, as an optional embodiment, the target image integration module is further used to determine whether two consecutive rows of target image data are the same; if two consecutive rows of target image data are the same, the target image data is directly used as odd-numbered row image data.

[0098] The present application also provides a computer storage medium that can store multiple instructions, which are suitable for being loaded and executed by a processor as described above. Figure 1-Figure 2 The FPGA-based image resolution expansion method of the embodiment shown in the figure can be found in the specific implementation process. Figure 1-Figure 2 The specific description of the illustrated embodiment will not be repeated here.

[0099] See also Figure 4 , is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Figure 4 As shown, the electronic device 400 may include: at least one processor 401 , at least one network interface 404 , a user interface 403 , a memory 405 , and at least one communication bus 402 .

[0100] The communication bus 402 is used to realize the connection and communication between these components.

[0101] The user interface 403 may include a standard wired interface or a wireless interface.

[0102] The network interface 404 may optionally include a standard wired interface or a wireless interface (such as a WI-FI interface).

[0103] Among them, the processor 401 may include one or more processing cores. The processor 401 uses various interfaces and lines to connect various parts in the entire server, and executes various functions of the server and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 405, and calling data stored in the memory 405. Optionally, the processor 401 can be implemented in at least one hardware form of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), and programmable logic array (Programmable Logic Array, PLA). The processor 401 can integrate one or more combinations of a central processing unit (Central Processing Unit, CPU), a graphics processing unit (Graphics Processing Unit, GPU) and a modem. Among them, the CPU mainly processes the operating system, user interface and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; the modem is used to process wireless communications. It can be understood that the above-mentioned modem may not be integrated into the processor 401, and it can be implemented by a single chip.

[0104] Among them, the memory 405 may include a random access memory (Random Access Memory, RAM) and may also include a read-only memory (Read-Only Memory). Optionally, the memory 405 includes a non-transitory computer-readable storage medium. The memory 405 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 405 may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area may store data involved in the above-mentioned various method embodiments, etc. The memory 405 may optionally be at least one storage device located away from the aforementioned processor 401. As Figure 4 As shown, the memory 405 as a computer storage medium may include an operating system, a network communication module, a user interface module, and an application program of an image resolution expansion method based on FPGA.

[0105] exist Figure 4In the electronic device 400 shown, the user interface 403 is mainly used to provide an input interface for the user and obtain data input by the user; and the processor 401 can be used to call an application program stored in the memory 405 for an image resolution expansion method based on FPGA. When executed by one or more processors, the electronic device executes one or more methods in the above-mentioned embodiments.

[0106] An electronic device readable storage medium stores instructions, which, when executed by one or more processors, enable the electronic device to execute one or more methods in the above embodiments.

[0107] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required for the present application.

[0108] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0109] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0110] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0111] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0112] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the various embodiments of the present application. The aforementioned memory includes: various media that can store program codes, such as USB flash drives, mobile hard drives, magnetic disks or optical disks.

[0113] The above are only exemplary embodiments of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification and the truth of practice, it will be easy for those skilled in the art to think of other embodiments of the present disclosure. This application is intended to cover any variation, use or adaptive change of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field that are not recorded in the present disclosure.

Claims

1. An image resolution expansion method based on FPGA, characterized in that: The method comprises: Get the image to be expanded; Using the average value of adjacent pixels in each row of the image to be expanded as a pixel horizontal interpolation value, and inserting it between the corresponding adjacent pixels to obtain target image data; Writing the target image data into a memory, and reading two consecutive lines of the target image data from the memory respectively; Using the target image data corresponding to two consecutive rows as even-numbered row image data; Calculating the average value of pixels corresponding to two consecutive rows of the target image data to obtain odd-numbered rows of image data; The even-numbered lines of image data and the odd-numbered lines of image data are integrated to obtain a target image, wherein the resolution of the target image is greater than the resolution of the image to be expanded.

2. The method according to claim 1, characterized in that: The memory includes a first memory and a second memory, the two consecutive lines of target image data include a first line of image data and a second line of image data, and the writing of the target image data into the memory and the reading of the two consecutive lines of target image data from the memory respectively include: Writing the target image data into the first memory at the first even-numbered line of the field counter, and reading the first-line image data of two consecutive lines of the target image data within two consecutive lines after the first even-numbered line; The first line of image data in the target image data is written into the second memory in the second even line of the field counter, and the second line of image data in two consecutive lines of the target image data is read, and the second even line is the line number of the field counter that is spaced one line after the first even line.

3. The method according to claim 1, characterized in that The step of obtaining the image to be expanded includes: Acquire an initial image and a first clock frequency of the initial image, and determine a second clock frequency required for the image to be expanded, wherein the first clock frequency is less than the second clock frequency; The initial image is written into a FIFO register at the first clock frequency, and the initial image in the FIFO register is read at the second clock frequency to obtain the image to be expanded.

4. The method according to claim 3, characterized in that The acquiring the initial image and the first clock frequency of the initial image, and determining the second clock frequency required for the image to be expanded, comprises: Acquire a maximum value of a first row counter of an initial image and a first clock frequency of the initial image, and acquire a maximum value of a second row counter required for the image to be expanded; Substituting the maximum value of the first row counter, the first clock frequency, and the maximum value of the second row counter into a relational expression, to obtain a second clock frequency required for the image to be expanded; The relationship is: Wherein, org_h_cnt_total represents the maximum value of the first row counter, clk_1 represents the first clock frequency, exp_h_cnt_total represents the maximum value of the second row counter, and clk_h represents the second clock frequency.

5. The method according to claim 4, characterized in that The step of obtaining the maximum value of the first row counter of the initial image and obtaining the maximum value of the second row counter required for the image to be expanded includes: Acquire a first number of pixels corresponding to each row in the resolution of the initial image and a first field blanking of the initial image; Calculating the sum of the first number of pixels and the first field blanking to obtain a maximum value of a first row counter of the initial image; Acquire the second number of pixels corresponding to each row in the resolution of the image to be expanded and the second field blanking of the image to be expanded; calculate the sum of the second number of pixels and the second field blanking to obtain the maximum value of the second row counter of the image to be expanded.

6. The method according to claim 1, characterized in that The step of integrating the even-numbered line image data and the odd-numbered line image data to obtain a target image includes: The even-numbered line image data and the odd-numbered line image data are outputted in the order of the line numbers of the field counter to obtain a target image.

7. The method according to claim 1, characterized in that Before calculating the average value of pixels corresponding to two consecutive rows of the target image data to obtain the odd-numbered row image data, the method further includes: Determining whether two consecutive rows of the target image data are the same; If the target image data of two consecutive rows are the same, the target image data are directly used as the odd-numbered row image data.

8. An image resolution expansion system based on FPGA, characterized in that: The system comprises: An image acquisition module, used for acquiring the image to be expanded; A horizontal expansion module, used to use the average value of adjacent pixels in each row of the image to be expanded as a pixel horizontal interpolation, and insert it between the corresponding adjacent pixels to obtain target image data; A data staggered reading module, used for writing the target image data into a memory, and reading two consecutive lines of the target image data from the memory respectively; A first data determination module, configured to use the target image data corresponding to two consecutive rows as even-numbered row image data; A second data determination module is used to calculate the average value of pixels corresponding to two consecutive rows of the target image data to obtain odd-numbered row image data; The target image integration module is used to integrate the even-numbered line image data and the odd-numbered line image data to obtain a target image, wherein the resolution of the target image is greater than the resolution of the image to be expanded.

9. A computer storage medium, characterized in that The computer storage medium stores a plurality of instructions, and the instructions are suitable for being loaded by a processor and executing the method according to any one of claims 1 to 7.

10. An electronic device, characterized in that: The electronic device comprises a processor, a memory and a transceiver, wherein the memory is used to store instructions, the transceiver is used to communicate with other devices, and the processor is used to execute the instructions stored in the memory so that the electronic device executes the method according to any one of claims 1 to 7.

Images