Memory module, electronic equipment and data migration method

Abstract

The invention discloses a memory module, electronic equipment and a data migration method, which are used for realizing a low-cost memory expansion scheme of a server system. The cold and hot migration scheme is realized through the combination of the processing module in the memory module and the module external component, the working pressure of the processing module can be saved, and compared with the scheme that an integrated unit in the memory module is re-developed to independently realize cold and hot migration, the method has a simpler research and development process, the required labor cost and research and development cost are lower, and the implementation is more convenient. And a low-cost memory expansion scheme of the server system can be realized. Besides, the power supply pin of the golden finger connector in the memory module is redefined as the pin with the width larger than that of the original power supply pin, the through-current capacity of the power supply pin can be improved, the power supply power of the power supply pin can be improved, the improved power supply power can support more storage media to be arranged in the memory module, and the memory of the server system is further expanded.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on June 9, 2023, with application number 202310685185.3 and application name "Memory Module and Electronic Device", all contents of which are incorporated by reference in this application. Technical Field

[0003] The present application relates to the field of memory technology, and in particular to a memory module, an electronic device, and a data migration method. Background Art

[0004] Traditional server systems usually package memory together with the central processing unit (CPU) in the server motherboard. However, due to the size of the rack, the amount of memory that can be packaged together with the processor is extremely limited. For example, see Figure 1 Currently, most mainstream servers are installed in 19-inch racks, which limit the width of the server motherboard to about 430mm. Under this size limit, if the current mainstream 8-channel memory control design is adopted, in the mode where each memory channel corresponds to 2 dual inline memory modules (DIMM per channel, DPC), the server motherboard can only support a maximum of 32 dual inline memory modules (DIMM), such as 32 double data rate synchronous dynamic random access memory (DDR SRAM), Figure 1 It is abbreviated as DDR in Chinese. Although there are CPUs that can use up to 12 channels of memory control design, the system can only support 1DPC mode in implementation. If a 2-way configuration is implemented, it can only support the placement of a maximum of 24 DIMMs. For various reasons, it is difficult to improve the system's memory performance and capacity on traditional server systems.

[0005] In order to solve the problem of limited memory performance and capacity in traditional server systems, the industry has proposed a new server system. Figure 2In addition to packaging DDR on the server motherboard, the new server system also sets up some memory modules outside the server motherboard, wherein each memory module is packaged with an application specific integrated circuit (ASIC) and DDR, and the CPU connects the ASIC in each memory module through a serial bus to access the DDR in each memory module. Although the new server system can expand more DDR outside the server motherboard, the DDR in the memory module will have a longer access delay than the DDR on the server motherboard. For example, accessing the DDR on the server motherboard usually only takes a few nanoseconds (ns), but accessing the DDR in the memory module takes dozens of ns. Although there are some solutions that can use the ASIC in the memory module to migrate the frequently accessed data in the memory module to the server motherboard to reduce the access delay of the frequently accessed data, this solution requires the redevelopment of the ASIC in the memory module, which requires high manpower and research and development costs, which is not conducive to realizing the low-cost design concept of the server system.

[0006] Therefore, low-cost memory expansion solutions in server systems need further research. Summary of the invention

[0007] The present application provides a memory module, an electronic device and a data migration method for realizing a low-cost memory expansion solution for a server system.

[0008] In the first aspect, the present application provides a memory module, including a processing module and a gold finger connector connected to the processing module; the gold finger connector is used to plug with a component outside the memory module to realize the communication connection between the device in the memory module and the component outside the memory module; the processing module is used to receive a read and write request from the component outside the memory module through the gold finger connector, access at least one storage medium in the memory module according to the read and write request, and transmit the access frequency information of each storage address corresponding to at least one storage medium in the memory module to the component outside the memory module through the gold finger connector. Among them, the access frequency information of each storage address is used for the component outside the memory module to migrate the data stored in the storage address whose access frequency is greater than the heat threshold to the storage medium connected to the processor.

[0009] Through the above memory module, when realizing the hot and cold migration function, the processing module in the memory module can be used to transmit the access frequency information of the storage medium in the memory module to the components outside the module, so as to complete the hot and cold migration together with the components outside the module. In this way, the memory module can only add the information transmission function to the function of accessing the storage medium. Compared with the solution of redeveloping the ASIC in the memory module to realize the memory migration function independently, the development difficulty is lower, and less additional development cost and labor cost can be introduced, thereby realizing low-cost memory expansion of the server.

[0010] In a possible design, the processing module may include a first integrated unit and a second integrated unit, the first integrated unit is connected to at least one storage medium in the memory module, and the gold finger connector connects the first integrated unit and the second integrated unit. The first integrated unit is used to receive a read / write request from a component outside the memory module through the gold finger connector, and access at least one storage medium in the memory module according to the read / write request; the second integrated unit is used to send access frequency information of each storage address corresponding to at least one storage medium in the memory module to the component outside the memory module through the gold finger connector.

[0011] In the above design, the first integrated unit can be understood as an ASIC in the existing memory module. By adding a second integrated unit to the memory module, the hot and cold migration solution of the server can be realized by developing the second integrated unit without redeveloping the first integrated unit. The operation of developing the second integrated unit has a simpler research and development process than redeveloping the first integrated unit. For example, there is no need to modify the layout and routing of the original devices in the first integrated unit, nor is there any need to consider how to layout the positions of each device to avoid the interference of the hot and cold migration function with the original function of the first integrated unit. The required manpower cost and research and development cost are relatively low. It can be seen that the memory module can not only realize the hot and cold migration solution and improve the memory performance of the server, but also introduce as little additional cost as possible, which helps to realize the low-cost memory expansion of the server, and does not increase the working pressure of the first integrated unit in the memory module.

[0012] In one possible implementation of the above design, one or more reserved pins of the gold finger connector are defined as out-of-band communication pins, and the second integrated unit is connected to the out-of-band communication pins through an out-of-band communication bus. In this way, when the memory module is plugged into the component outside the memory module through the gold finger connector, the out-of-band communication bus can realize the connection between the second integrated unit and the gold finger connector, and then realize the connection between the second integrated unit and the component outside the memory module. Through this connection, the second integrated unit can send the access frequency information of each storage address of at least one storage medium in the memory module to the component outside the memory module.

[0013] In a further possible implementation, the out-of-band communication pin transmits the access frequency information through a differential signal. In this case, the B68 pin and the B69 pin of the gold finger connector can be defined as two sending pins, and the A68 pin and the A69 pin of the gold finger connector can be defined as two receiving pins; the second integrated unit is used to send the access frequency information of each storage address of at least one storage medium in the memory module to the gold finger connector through the B68 pin and the B69 pin, so as to forward it to the component outside the memory module through the gold finger connector, and receive the return information of the gold finger connector through the A68 pin and the A69 pin, and the return information can be sent to the gold finger connector by the component outside the memory module. In this way, the differential signal can be transmitted between the second integrated unit and the component outside the memory module through two sending pins and two receiving pins.

[0014] In a possible implementation of the above design, the memory module may also include a control address line, the first integrated unit is connected to at least one storage medium in the memory module through the control address line, the first integrated unit is specifically used to: access at least one storage medium in the memory module by adjusting the control address (CA) signal on the control address line, and the second integrated unit is specifically used to: determine the access frequency information of the storage address corresponding to at least one storage medium in the memory module within a preset time period according to the change of the CA signal on the control address line. Through this design, since the read and write operations of the storage address are triggered by the CA signal, the second integrated unit can detect the access status of each storage address in real time by monitoring the change of the CA signal, thereby helping to improve the accuracy of the statistical access frequency information.

[0015] In a possible design, the processing module may include only one integrated unit, which is connected between at least one storage medium in the memory module and the gold finger connector. In this way, the hot and cold migration solution can be realized by simply modifying the original first integrated unit in the memory module and combining the modified first integrated unit with the external module components. The structure of the processing module is relatively simple, and communication between multiple integrated units is not required, which helps to reduce communication loss.

[0016] It is understandable that the processing module may also include three or more integrated units, each of which shares part of the functions of the processing module, and three or more integrated units jointly implement all the functions of the processing module. There are many possible implementation methods, which are not listed here one by one.

[0017] In one possible design, there is a first positive pin in the area where the B1 pin to the B6 pin of the gold finger connector is located, and there is a first ground pin in the area where the A1 pin to the A6 pin of the gold finger connector is located. The widths of the first positive pin and the first ground pin are both greater than a preset width, and the preset width is the original pin width defined by the standard.

[0018] In the above design, by redefining the power pin of the gold finger connector so that the pin width of the redefined power pin is larger than the pin width of the original power pin defined by the standard, the area of ​​the conductive spring corresponding to the power pin can be increased, thereby increasing the current carrying capacity of the power pin and improving the power supply power of the power pin. The increased power supply power can support the layout of more storage media in the memory module, further expanding the storage capacity of the memory module.

[0019] In a possible implementation of the above design, considering that the original power pins are 6 groups, the number of the redefined power pins can be any value less than 6. Assuming that the preset width is K, then:

[0020] In some possible implementations, the redefined power pins are 1 group. In this case, the width of the first positive pin and the first ground pin can be configured to be 11K. For example, if the original pin width is 0.3mm, the first positive pin and the first ground pin can be configured to be 3.3mm. In this way, by only arranging one group of power pins in the area where the original B1 pin to the original B6 pin of the gold finger connector are located, the pin width of the group of power pins can be maximized, thereby maximizing the current carrying capacity of the power pins and achieving maximum power supply capacity.

[0021] In some other possible implementations, the redefined power pins are divided into two groups. In this case, the width of each first positive pin and each first ground pin can be configured as 5K, or there can be a first positive pin and a first ground pin with a width configured as 7K, and another first positive pin and another first ground pin with a width configured as 3K. For example, if the original pin width is 0.3mm, then the two first positive pins and the two first ground pins can be configured as 1.5mm, or one first positive pin and one first ground pin can be configured as 2.1mm, and another first positive pin and another first ground pin can be configured as 0.9mm. In this way, by arranging two groups of power pins in the area where the original B1 pin to the original B6 pin of the gold finger connector are located, the pin width of the power pin can be increased, the power supply capacity of the power pin can be improved, and it can be plugged and unplugged better than the gold finger connector with only one group of power pins. Moreover, by configuring the widths of the two groups of power pins to be larger than the width of the original power pins, the power supply capacity of each group of power pins can be larger than the power supply capacity of the original power pins. In this way, even if only one group of power pins is used for power supply, a better power supply effect can be achieved.

[0022] In some other possible implementations, the redefined power pins are 3 groups. In this case, the width of each first positive pin and each first ground pin can be configured as 3K. For example, if the original pin width is 0.3mm, the 3 first positive pins and the 3 first ground pins can be configured as 0.9mm. In this way, by arranging three groups of power pins in the area where the original B1 pin to the original B6 pin of the gold finger connector are located, it is possible to increase the pin width of the power pin and improve the power supply capacity of the power pin, and it is also possible to have less friction than the gold finger connector with only one or two groups of power pins, making it easier to achieve flexible plugging and unplugging of the gold finger connector. Moreover, by configuring the three groups of power pins to have the same width, the three groups of power pins can also have the same power supply capacity, which helps to achieve balanced power supply to different power pins on the gold finger connector.

[0023] It should be noted that the redefined power pins can be larger than 3 groups, such as 4 or 5 groups. However, in the 4 or 5 groups, one or more groups of power pins will have the same width as the original power pins, which will have limited improvement on power supply capacity, but will make plugging and unplugging more convenient. Therefore, in some possible designs, if the plug-in requirements are high, 4 or 5 groups of power pins can be configured to meet the needs of flexible plug-in, and in the scenarios with high power supply requirements, 1, 2 or 3 groups of power pins can be configured to meet high power supply requirements.

[0024] In a possible implementation of the above design, the first positive electrode pin and the first ground pin can be implemented by copper gold plating, so that the power pin has the advantages of beautiful appearance, good corrosion resistance, wear resistance and easy maintenance.

[0025] In a second aspect, the present application provides an electronic device, which may be any device with a hot and cold migration function, such as a server, or a computer device with a display screen and a server. The electronic device may include a memory module as in the above-mentioned first aspect or any one of the designs of the first aspect.

[0026] In a possible design, the electronic device may also include an electronic device mainboard and a media management board, the electronic device mainboard includes a processor and at least one first storage medium, the memory module includes at least one second storage medium, the number of memory modules is N, and N is a positive integer; any memory module is used to send the access frequency information of each second storage address corresponding to at least one second storage medium in the memory module within a preset time period to the media management board; the media management board is used to send the access frequency information of each second storage address corresponding to each second storage medium in N memory modules within a preset time period to the processor; the processor is used to migrate the data stored in the target second storage address with an access frequency greater than a heat threshold to the first storage medium, and migrate the data stored in the target first storage address with an access frequency less than a cold threshold to the second storage medium according to the access frequency information of each first storage address corresponding to at least one first storage medium within the preset time period and the access frequency information of each second storage address corresponding to each second storage medium in N memory modules within the preset time period.

[0027] In the above scheme, since the processor's access delay to the first storage medium on the electronic device's mainboard is smaller than the access delay to the second storage medium on the memory module, by migrating the hot data in the memory module to the electronic device's mainboard, the processor can access the hotter data more quickly, thereby improving data access performance. By migrating the cold data in the electronic device's mainboard to the memory module, the occupation of the electronic device's mainboard by the cold data can be released, thereby increasing the storage capacity of the hot data.

[0028] In one possible design, the processing module includes a first integrated unit and a second integrated unit. The first integrated unit in any memory module is used to access at least one second storage medium in the memory module; the second integrated unit in any memory module is used to send access frequency information of each second storage address corresponding to at least one second storage medium in the memory module within a preset time period to the media management board.

[0029] Compared with the hot-cold migration scheme in the new server system, the above design adds an additional second integrated unit to the existing memory module, and the second integrated unit can be used to migrate the frequently accessed data in the second storage medium of the memory module to the first storage medium of the electronic device motherboard, without the need to redevelop the first integrated unit in the memory module. The operation of developing the second integrated unit has a simpler R&D process than redeveloping the first integrated unit, and the required manpower and R&D costs are lower. It can be seen that this solution can not only improve the memory performance of the server, but also introduce as little additional cost as possible, which helps to realize a low-cost memory expansion solution for the server system.

[0030] In one possible design, the media management board may include a third integrated unit and a fourth integrated unit, the third integrated unit being connected to the fourth integrated unit and the second integrated unit in each memory module, respectively, and the fourth integrated unit being also connected to the processor; the third integrated unit being used to receive access frequency information of each second storage address in the memory module within a preset time period sent by the second integrated unit in each memory module, and to aggregate the access frequency information of each second storage address in N memory modules within the preset time period and send it to the fourth integrated unit; the fourth integrated unit being used to send the aggregated access frequency information of each second storage address in the N memory modules within the preset time period to the processor.

[0031] In the above design, the third integrated unit can be understood as an integrated unit in the existing media management board. By adding a fourth integrated unit to the media management board, the fourth integrated unit can be used to send the access frequency corresponding to each memory module to the processor without forwarding by the third integrated unit, thereby minimizing the impact on the original communication process of the third integrated unit. In other words, this design can implement the cold and hot migration solution on the original device architecture of the server as much as possible, reduce the redevelopment of the original device, and minimize the impact on the function of the original device.

[0032] In a further possible design, the fourth integrated unit and the processor can be connected via a universal serial bus (USB) or a peripheral component interconnect express (PCIe) bus so as to achieve the effect of reducing costs and improving communication quality while realizing the communication connection between the fourth integrated unit and the processor.

[0033] It can be understood that in another possible design, the media management board may also include only one integrated unit, which is respectively connected to the processing module in each memory module and the processor in the electronic device mainboard, and is used to receive the access frequency information of each second storage address in the memory module within a preset time period sent by the processing module in each memory module, and summarize the access frequency information of each second storage address in N memory modules within the preset time period and send it to the processor in the electronic device mainboard. Under this design, the structure of the media management board is relatively simple, and communication between multiple integrated units is not required, which helps to reduce communication losses. Alternatively, in another possible design, the media management board may also include three or more integrated units, each of which shares part of the functions of the media management board, and three or more integrated units jointly realize all the functions of the media management board. There are many possible implementation methods, which are not listed here one by one.

[0034] In a third aspect, the present application provides a data migration method, which can be executed by the memory module in the above-mentioned first aspect or any one of the designs of the first aspect, or can be executed by the electronic device in the above-mentioned second aspect or any one of the designs of the second aspect, the method comprising: obtaining a hot-cold migration instruction, the hot-cold migration instruction carrying at least one of the address information of the cold data in the first storage address associated with the processor or the second storage address associated with the memory module; sending the hot data in the second storage address to the processor in the electronic device according to the address information of the second storage address carried in the hot-cold migration instruction; storing the cold data in the first storage address carried in the hot-cold migration instruction to the second storage address.

[0035] Here, "associated" can be understood as "logically connected" or "functionally accessible". For example, the first storage address associated with the processor refers to a storage address that can be directly accessed by the processor in the electronic device mainboard. For example, it can be a storage address located in the electronic device mainboard. The storage address is directly connected to the processor in the electronic device mainboard, and its internal data can be directly accessed by the processor in the electronic device mainboard. Similarly, the second storage address associated with the memory module refers to a storage address that can be directly accessed by the processing module in the memory module. For example, it can be a storage address located in the memory module. The storage address is directly connected to the processing module in the memory module, and its internal data can be directly accessed by the processing module in the memory module.

[0036] In a possible design, before obtaining the hot-cold migration instruction, it can also include: accessing one or more second storage addresses associated with the memory module, and sending the access frequency information of each second storage address associated with the memory module to the media management board in the electronic device.

[0037] In a fourth aspect, the present application provides a cold-hot data migration device, which may be a processing device in a memory module, such as a processing module, and the device includes: an acquisition module, used to acquire a cold-hot migration instruction, the cold-hot migration instruction carrying at least one of the address information of the cold data in the first storage address associated with the processor or the second storage address associated with the memory module; a transceiver module, used to send the hot data in the second storage address to the processor in the electronic device according to the address information of the second storage address carried in the cold-hot migration instruction; a storage module, used to store the cold data in the first storage address carried in the cold-hot migration instruction to the second storage address.

[0038] In a fifth aspect, the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a hot-cold data migration device, the method in the third aspect or any one of the third aspects is implemented.

[0039] In a sixth aspect, the present application provides a computer program product, which, when executed on a data migration device, implements the third aspect or any one of the methods described in the third aspect.

[0040] The various designs in the above-mentioned first aspect are also applicable to the above-mentioned second to sixth aspects. For the corresponding beneficial effects, please refer to the technical effects that can be achieved by the corresponding designs in the above-mentioned first aspect, and no further details will be given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram showing an exemplary layout of a server motherboard in a rack;

[0042] Figure 2 A schematic diagram of a system architecture of a new type of server is shown as an example;

[0043] Figure 3 A schematic diagram of an application scenario of a server provided by the present application is exemplified;

[0044] Figure 4 A schematic diagram of a system architecture of a server provided by the present application is exemplified;

[0045] Figure 5a A schematic diagram showing a specific architecture of a server provided by the present application is exemplified;

[0046] Figure 5b A schematic diagram showing an exemplary architecture of another server provided by the present application;

[0047] Figure 6a The product structure diagram of a memory module provided by the present application is exemplified;

[0048] Figure 6b The product structure diagram of another memory module provided by the present application is exemplified;

[0049] Figure 7 A schematic diagram showing a structural comparison of a gold finger connector provided by the present application before and after redefinition is exemplified;

[0050] Figure 8 A schematic diagram showing possible situations of a power pin before and after redefinition provided by the present application is exemplified;

[0051] Fig. 9 A schematic diagram of the interaction process of a cold-hot migration solution provided by the present application is exemplified;

[0052] Fig.10 An internal circuit diagram of a memory module provided by the present application is exemplarily shown;

[0053] Fig.11 An internal circuit diagram of another memory module provided by the present application is exemplarily shown;

[0054] Fig.12 A schematic diagram of the structure of a data migration device provided by the present application is exemplified. DETAILED DESCRIPTION

[0055] The present application will be described in detail below with reference to the accompanying drawings.

[0056] Below, some terms in this application are explained. It should be noted that these explanations are for the convenience of understanding by those skilled in the art and do not constitute a limitation on the scope of protection claimed in this application.

[0057] 1. Storage medium and storage address.

[0058] Storage media are usually made of semiconductor materials and are used to temporarily store computing data and exchange data with external storage devices such as hard disks. Storage media include various types of memory, such as dynamic random access memory (DRAM) and double data rate synchronous dynamic random access memory (DDR SRAM). DDR SRAM is also often referred to as DDR.

[0059] The storage address is an identifier of the storage location. The data stored in the storage medium can be found by indexing the storage address. In some scenarios, the storage medium is composed of multiple storage units, and each storage unit can have its own storage address. For example, taking hexadecimal as an example, assuming that a complete storage medium is composed of 17 storage units, and the physical addresses of these storage units are 0x0000 to 0x0010, then 0x0000 represents the storage address of the first storage unit of the storage medium, 0x0001 represents the storage address of the second storage unit of the storage medium, and so on, 0x0010 represents the storage address of the 17th storage unit of the storage medium. Of course, with the development of storage technology, the storage address of the storage unit in the future may also be expressed in the form of a virtual address, and the physical address corresponding to the virtual address can be found by querying the preset address mapping table.

[0060] 2. Memory controller.

[0061] The memory controller manages the exchange of data from the storage medium to the processing unit. It can be a separate chip or integrated into the storage medium or processing unit. Figure 2In a new server system, a server motherboard and a memory module may respectively have memory controllers. The memory controller on the server motherboard may be integrated into a central processing unit (CPU), and the memory controller on the memory module may be integrated into an application specific integrated circuit (ASIC).

[0062] 3. Gold finger connector (connecting finger).

[0063] Gold finger connectors are also called board edge connectors. They are usually used to connect storage media to slots and graphics cards to graphics card slots to transmit all signals between the two connected devices. Gold finger connectors are usually composed of many golden conductive springs. Because their surface is gold-plated and the conductive springs are arranged like fingers, they are commonly called "gold finger connectors".

[0064] The foregoing text introduces some of the terms involved in this application. The following text introduces possible application scenarios of this application.

[0065] In a possible implementation, the memory module can be integrated into the server, for example, it can be placed in a memory slot inside the server case and plugged into the server motherboard. Figure 3 , exemplarily shows a possible application scenario of the present application. In this application scenario, a rack server is used as the server and the rack server is placed in a reserved position in the middle of the rack. It is understandable that the rack server can also be placed in other positions of the rack, such as outside any direction or multiple directions of the four directions of top, bottom, left and right, so as to reduce the number of racks.

[0066] It should be understood that the above application scenarios are only examples, and the memory module provided in this application can also be applied to other possible scenarios, not limited to the scenarios exemplified above. For example, the memory module can also be integrated into any type of server such as a tower server, a blade server, a high-density server or a cabinet server. For another example, the memory module can also be integrated into a non-server, such as a terminal device, as an additional expanded memory to improve the storage capacity of the terminal device. For another example, the memory module can also be integrated into a vehicle as a medium for storing vehicle-specific information or other non-critical information to expand the storage space of the vehicle. They are not listed one by one here. It should be noted that the application scenarios described in this application are to more clearly illustrate the technical solution of the present application, and do not constitute a limitation on the technical solution provided in this application.

[0067] In recent years, with the continuous development of semiconductor technology, the processing power and number of cores of processors have basically increased by 2 to 3 times every two years, but the development of memory technology is relatively slow, basically increasing by 2 to 3 times every three years. After years of asynchronous development, although the total memory capacity of servers has been improved, the memory capacity of each core in its internal processor is actually gradually decreasing, especially the memory bandwidth, which has decreased more significantly. This has caused the latency of processor access to memory to increase by 30% instead of decreasing.

[0068] In order to cope with the unbalanced development of processors and memory, the industry has proposed Figure 2 The new server system shown. However, as described in the background technology, this new server system requires the redevelopment of the ASIC in the memory module, so that in addition to accessing the DDR of the memory module where it is located, the ASIC also needs to migrate the frequently accessed data in the DDR of the memory module where it is located to the DDR of the server mainboard. This requires manual modification of the device arrangement in the original ASIC of the memory module. Not only new devices need to be added to realize new functions, but also the anti-interference of signal transmission between devices when the two functions are realized must be considered. Although the memory access performance of the server is improved, it brings huge labor costs and R&D costs, and also brings greater work pressure to the ASIC in the memory module.

[0069] In view of the above problems, the present application proposes a memory module. The memory module can be used without modifying the ASIC in the existing memory module, or only with minor modifications to the ASIC in the existing memory module, and can be used together with external components of the module to implement a hot and cold migration solution, so as to minimize the introduction of additional costs in the process of memory expansion and reduce the working pressure of the memory module.

[0070] Based on the above content, the solution proposed in this application is described in detail below in conjunction with the accompanying drawings.

[0071] It should be noted that the "first storage medium" hereinafter refers to the storage medium in the electronic device mainboard (such as the server mainboard), the first storage medium is connected to the processor in the electronic device mainboard, and its internal data can be directly accessed by the processor in the electronic device mainboard. "Second storage medium" refers to the storage medium in the memory module, the second storage medium is connected to the processing module in the memory module, and its internal data can be directly accessed by the processing module in the memory module. Therefore, the "first storage medium" hereinafter can also be replaced by the storage medium in the electronic device mainboard, the storage medium associated with the processor, the storage medium connected to the processor, or other similar names, and the "second storage medium" can also be replaced by the storage medium in the memory module, the storage medium associated with the memory module, the storage medium connected to the processing module in the memory module, or other similar names, and this application does not make specific restrictions on this. In addition, the implementation form of the first storage medium or the second storage medium can be internal memory or external memory, which is not specifically limited.

[0072] See also Figure 4 , which is a schematic diagram of a system architecture of a server provided by the present application. The system architecture includes a server motherboard 410, a media management board 420 and N memory modules, such as memory module 431, memory module 432, ..., memory module 43N, where N is a positive integer. From the perspective of the memory module, the server motherboard 410 and the media management board 420 can be considered as the external components of the memory module. The structure and connection relationship of each device in the server system are first introduced below.

[0073] The server motherboard 410, also known as a mainboard, system board or motherboard, is installed in a chassis and is a core component of the server. The server motherboard 410 may include a processor 411 and at least one first storage medium. Figure 4In the example, eight first storage media are included and the first storage medium is DDR, and the eight first storage media are named DDR01, DDR02, ..., DDR08. Among them, the processor 411, for example, can be a CPU, and in some scenarios, it can also be a graphics processing unit (GPU) or a neural processing unit (NPU). The processor 411 can be connected to DDR01~DDR08 respectively, and specifically, it can be connected to DDR01~DDR08 through a memory controller integrated in the processor 411. For example, when the 2DPC mode is adopted, one memory controller can be connected to two DDRs, so four memory controllers need to be integrated in the processor 411. For another example, when the 1DPC mode is adopted, one memory controller can be connected to one DDR, so eight memory controllers need to be integrated in the processor 411. Since DDR01-DDR08 are relatively close to the processor 411 and can be directly accessed by the processor 411 , in some scenarios, DDR01-DDR08 are also referred to as proximal memory or one level (L1) memory of the processor 411 .

[0074] The media management board 420 is an integrated board used to manage storage media such as hard disks and memory modules in the server, and can be used to manage the temperature, occupancy, and status of indicator lights of these storage media. The media management board 420 may include a third integrated unit 421 and a fourth integrated unit 422. The third integrated unit 421 may be, for example, Figure 2 The original complex programmable logic device (CPLD) in the new server system shown in the figure Figure 2 The fourth integrated unit 422, for example, may be an ASIC, or other units or modules with processing capabilities, which are used to implement the original management operations on the storage medium. Figure 2The additional devices added to the new server system shown. In addition, on the basis of adding the fourth integrated unit 422 in the media management board 420, a local bus (Local Bus) and an external bus (External Bus) can be added. The local bus is used to connect the fourth integrated unit 422 and the third integrated unit 421, and the external bus is used to connect the fourth integrated unit 422 and the processor 411 in the server motherboard 410. The type of the external bus can be, for example, a universal serial bus (USB) or a peripheral component interconnect express (PCIe) bus, or it can also be other types of full-duplex communication buses, such as a universal asynchronous receiver / transmitter (UART) bus, an inter-integrated circuit (IC) bus, or a processor 411 in the server motherboard 410. 2 C) bus or serial peripheral interface (SPI) bus, etc., without specific limitation.

[0075] It is understandable that the media management board 420 may also include only one integrated unit, or include three or more integrated units. When only one integrated unit is included, the integrated unit is used to perform all the work of the third integrated unit 421 and the fourth integrated unit 422 in this application. When three or more integrated units are included, each of the integrated units is used to share part of the work of the media management board 420, and the three or more integrated units jointly complete all the work of the media management board 420. The following only takes the example of the media management board 420 including two integrated units for introduction, and other solutions can be implemented with reference to this, and this application will not repeat it in detail.

[0076] The memory module is a module placed outside the server motherboard 410 for expanding memory (or memory and external memory). The memory module may include a processing module, at least one second storage medium, and a gold finger connector. In the case where the server includes multiple memory modules, the number of second storage media in different memory modules may be the same or different. For example, in Figure 4In the example, memory module 431 includes 4 second storage media, memory module 432 includes 3 second storage media, and memory module 43N includes 5 second storage media. The number of second storage media included in each memory module may be different. However, this is only an optional implementation. In an actual product, at least two memory modules may include the same number of second storage media, or all memory modules may include the same number of second storage media. There is no specific limitation.

[0077] Taking the memory module 431 as an example, the memory module 431 includes a processing module 4311, a gold finger connector 4312 and four second storage media, which are named DDR11, DDR12, DDR13 and DDR14 respectively. The processing module 4311 may include one or more integrated units. For example, taking only one integrated unit as an example, refer to Figure 5a , the integrated unit can be connected between the gold finger connector 4312 and at least one second storage medium DDR11-DDR14. The integrated unit can be understood as an ASIC in an existing memory module, or it can also be any other circuit or chip that can realize the processing function, such as an FPGA. For another example, taking two integrated units as an example, please refer to Figure 5b The processing module 4311 may include a first integrated unit 43111 and a second integrated unit 43112. The first integrated unit 43111 may be, for example, an ASIC, such as Figure 2 The original ASIC in the memory module of the new server system shown, or other units or modules with processing capabilities. The first integrated unit 43111 can be connected to DDR11~DDR14 respectively, for example, it can be connected to DDR11~DDR14 through the memory controller integrated in the first integrated unit 43111. The first integrated unit 43111 can also be connected to the processor 411 in the server motherboard 410, for example, through the serial bus X4 of 4 memory channels, the serial bus X8 of 8 memory channels or the serial bus X16 of 16 memory channels and the gold finger connector 4312 to connect to the processor 411. Since the second storage medium is far away from the processor 411, the processor 411 needs to access it indirectly through communication with the first integrated unit 43111. Therefore, in some scenarios, the second storage medium is also called the remote memory or the second level (two level, L2) memory of the processor 411. In addition, the second integrated unit 43112, for example, can be a field programmable gate array (FPGA), or other units or modules with processing capabilities, which belongs to the Figure 2The new server system shown in the figure has additional devices in the memory module 431. In addition, based on the addition of the second integrated unit 43112 in the memory module 431, a local bus and an out-of-band communication bus can be additionally added. The local bus is used to connect the second integrated unit 43112 and the first integrated unit 43111, and the out-of-band communication bus is used to connect the second integrated unit 43112 and the third integrated unit 421 in the media management board 420. The out-of-band communication bus can be any type of full-duplex communication bus, such as a high-speed interconnect bus (such as a Hisport bus), or a UART bus, I 2 C bus or SPI bus, etc., and there is no specific limitation.

[0078] In some scenarios, each memory module may include a printed circuit board (PCB) in addition to a processing module, a gold finger connector, and a second storage medium. For example:

[0079] For an example, see Figure 6a , which shows a product structure diagram of a memory module provided by the present application, and the structure takes the processing module including only one integrated unit as an example. The integrated unit can be illustratively the ASIC shown in the figure, or it can also be any other circuit or chip that can realize the processing function, such as FPGA, without specific limitation. Taking the integrated unit as ASIC as an example, the ASIC can be placed in the middle area of ​​the PCB, and at least one second storage medium can be evenly distributed on both sides of the ASIC. For example, when the second storage medium is DDR and the memory module contains 4 DDRs, the 4 DDRs can be evenly distributed in the upper area and the lower area of ​​the ASIC, such as 2 DDRs placed in the upper area of ​​the ASIC, and 2 DDRs placed in the lower area of ​​the ASIC;

[0080] For another example, see Figure 6b , which shows a product structure diagram of another memory module provided by the present application, in which the processing module includes two integrated units, one of which is an ASIC and the other is an FPGA. Figure 6b As shown, the ASIC and FPGA can be placed side by side in the middle area of ​​the PCB, and at least one second storage medium is evenly distributed on both sides of the ASIC and FPGA. For example, when the second storage medium is DDR and the memory module includes 4 DDRs, the 4 DDRs can be evenly distributed in the upper area and the lower area of ​​the ASIC and FPGA, such as 2 DDRs are placed in the upper area of ​​the ASIC and FPGA, and 2 DDRs are placed in the lower area of ​​the ASIC and FPGA.

[0081] Furthermore, the gold finger connector can be arranged at any edge of the PCB, such as the edge of any one or more of the four directions of top, bottom, left, and right. Figure 6a and Figure 6b Taking the layout of the gold finger connector on the right edge of the PCB as an example, three small rectangular areas can be protruded side by side on the right edge of the PCB, and a portion of conductive springs are attached to the right edge of each small rectangular area. By defining the position and function of these conductive springs, the defined conductive springs can be plugged with the server motherboard 410 and the media management board 420 to achieve communication connection between the memory module and the server motherboard 410 and the media management board 420. For example, Figure 4 The processing module in the memory module shown is respectively connected to the communication of the processor 411 in the server mainboard 410 and the third integrated unit 421 in the media management board 420, or to realize Figure 5a The integrated unit in the memory module shown is respectively connected to the communication of the processor 411 in the server mainboard 410 and the third integrated unit 421 in the media management board 420, or, as shown in FIG. Figure 5b The connection between the first integrated unit in the memory module and the processor 411 in the server mainboard 410, and the connection between the second integrated unit in the memory module and the third integrated unit 421 in the media management board 420 are shown. In addition, the power supply function of the external power supply to each device in the memory module and some other functions can also be realized. By setting a gold finger connector on the memory module, the memory module can be connected or disconnected with the server mainboard and the media management board through flexible plugging and unplugging of the memory module.

[0082] It can be understood that the structures of memory modules 432 to 43N are similar to those of memory module 431. For example, see Figure 4 , the memory module 432 may include a processing module 4321, a gold finger connector 4322 and three second storage media, respectively named DDR21, DDR22 and DDR23; ...; the memory module 43N may include a processing module 43N1, a gold finger connector 43N2 and five second storage media, respectively named DDR N1, DDR N2, DDR N3, DDR N4 and DDR N5. Take the example that each memory module's processing module includes two integrated units, please combine Figure 4 and Figure 5b , the processing module 4321 in the memory module 432 may include a first integrated unit 43211 and a second integrated unit 43212, ..., the processing module 43N1 in the memory module 43N may include a first integrated unit 43N11 and a second integrated unit 43N12.

[0083] in addition, Figure 5a and Figure 5b The components and their positions shown are only one possible way to divide the server system. This division is only a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. For example, in another example, the processing module in each memory module may also include three or more integrated units, each integrated unit shares part of the functions of the processing module, and three or more integrated units jointly realize all the functions of the processing module. For example, in another example, the media management board 420 may also include only one integrated unit, which completes all the functions of the media management board 420, or the media management board 420 may also include three or more integrated units, each integrated unit shares part of the functions of the media management board 420, and three or more integrated units jointly realize all the functions of the media management board 420.

[0084] Furthermore, the processing modules in different memory modules may include the same or different numbers of integrated units, for example, the processing module in memory module 431 includes one integrated unit, while the processing module in memory module 432 includes two integrated units, or the processing module in memory module 431 includes two integrated units, while the processing module in memory module 432 includes one integrated unit, or the processing module in memory module 431 includes one integrated unit, while the processing module in memory module 432 includes three integrated units, and so on, which are not listed one by one here.

[0085] Furthermore, Figure 4 , Figure 5a or Figure 5b The key components in the server mainboard 410, the media management board 420 or the memory module are only exemplarily introduced. The server mainboard 410, the media management board 420 or the memory module may also include more or fewer components than those shown in the figure. For example, in some scenarios, the server mainboard 410 may also include a power supply, an input / output (IO) bus, and a hard disk drive. In other scenarios, in addition to the server mainboard 410, the media management board 420 and the memory module, the server may also include a disk, a hard disk or a chassis housing. There are many possible situations, which will not be listed here one by one.

[0086] as well as, Figure 4 , Figure 5a or Figure 5bThe possible architecture of the electronic device is only introduced by taking the server as an example. When the electronic device is other devices, the server motherboard can also be replaced with other motherboards at the same time. In other words, the server motherboard can be understood as the electronic device motherboard. When the electronic device is a server, the electronic device motherboard can be specifically a server motherboard. When the electronic device is a mobile phone, the electronic device motherboard can be specifically a mobile phone motherboard. When the electronic device is a computer, the electronic device motherboard can be specifically a computer motherboard. Etc., this application will not list them one by one.

[0087] The above content introduces the server and Figure 2 The differences in system architecture between the existing new servers shown are as follows. In addition to the differences in system architecture, the present application also redefines some pins of the gold finger connector in the server memory module.

[0088] The following takes the definition of the gold finger connector in accordance with the enterprise and data center solid state drive standard (enterprise & data center SSD form factor, EDSFF) as an example to explain in detail the differences in the structure and pin definition of the gold finger connector before and after the redefinition. It is worth noting that EDSFF is only an example and does not constitute a limitation on the technical solution to be protected by this application. In the specific implementation, custom standards or other standard specifications that can realize the functions of the gold finger connector to be protected by this application can also be adopted.

[0089] See also Figure 7 , which shows a schematic diagram of the structure comparison of a gold finger connector before and after redefinition provided by the present application, wherein: Figure 7 (A) shows a top view of the gold finger connector before redefinition. Figure 7 (B) shows a right view of a portion of the gold finger connector before redefinition. Figure 7 (C) shows a top view of the redefined gold finger connector. Figure 7 The middle (D) shows a right view of a part of the area of ​​the redefined gold finger connector. By comparison, it can be seen that the differences between the redefined gold finger connector and the redefined gold finger connector mainly include the following two points.

[0090] As a possible embodiment, the present application provides a gold finger connector with less than 6 power pins.

[0091] See also Figure 7 Middle (A) and Figure 7In (B), there are 6 groups of power pins in the gold finger connector before redefinition, each group of power pins includes a positive pin (VCC) and a ground pin (GND). According to the EDSFF specification, the positions and input signals of these 6 groups of power pins are shown in Table 1.1 below. Assuming that the standard defines the width of each power pin as 0.3mm (i.e., the preset width K), the parameter information of these 6 groups of power pins is shown in Table 1.2 below:

[0092] Table 1.1

[0093] Pinout Signal Signal Pinout B1 12V GND A1 B2 12V GND A2 B3 12V GND A3 B4 12V GND A4 B5 12V GND A5 B6 12V GND A6

[0094] Table 1.2

[0095] parameter Value unit Rated voltage of each power pin 29 V Rated current of each power pin 1.1 A Rated temperature -40°～85° C Pin width 0.3 mm Pin spacing 0.6 mm

[0096] Combined with Table 1.1, Table 1.2, Figure 7 Middle (A) and Figure 7 In (B), in the gold finger connector before redefinition, pins B1 to B6 are defined as 6 positive pins, and pins A1 to A6 are defined as 6 ground pins corresponding to the 6 positive pins. The rated voltage of each group of power pins is 29V, the rated current is 1.1A, and the rated temperature is -40° to -85°. Although the rated voltage is 29V, the gold finger connector in the memory module usually uses a working voltage of 12V, that is, each group of power pins can receive a 12V working voltage and supply it to the memory module. Therefore, according to the parameter design of the power pin, since there are a total of 6 groups of power pins in the gold finger connector before redefinition, the rated current of each group of power pins is 1.1A, and the working voltage of each group of power pins is 12V, therefore, the maximum power supply power that the gold finger connector before redefinition can provide is: 1.1A×6×12V=79.8W.

[0097] Different from the gold finger connector before redefinition, the gold finger connector after redefinition can include less than six groups of power pins, and these power pins include at least one group of first power pins, and the pin widths of the first positive pin and the first ground pin of the first power pin are larger than the pin widths of the positive pin and the ground pin of the original power pin, that is, larger than 0.3mm. For example, see Figure 7 Middle (C) and Figure 7In (D), in one example, the redefined gold finger connector may only include one group of large power pins (i.e., the first power pin), the positive pin (i.e., the first positive pin) in the group of large power pins occupies the entire area where the original pins B1 to B6 are located, and the ground pin (i.e., the first ground pin) occupies the entire area where the original pins A1 to A6 are located. The positions and input signals of the group of power pins may be shown in Table 2.1 below, and the parameter information of the group of power pins may be shown in Table 2.2 below:

[0098] Table 2.1

[0099] Pinout Signal Signal Pinout B1 12V GND A1

[0100] Table 2.2

[0101] parameter Value unit Rated voltage of power supply pins 29 V Rated current of power supply pin 30 A Rated temperature -40°～85° C Pin width 3.3 mm

[0102] Combined with Table 2.1, Table 2.2, Figure 7 Middle (C) and Figure 7 In (D), in the gold finger connector with only one set of power pins after redefinition, any pin from pins B1 to B6 can be defined as a positive pin, and any pin from pins A1 to A6 can be defined as a ground pin. For example, in Table 2.1, pin B1 is defined as a positive pin and pin A1 is defined as a ground pin. In the case where the width of each original pin is 0.3mm and the pin spacing is 0.6mm, the width of each pin after redefinition can be increased to 3.3mm. In this way, although the operating voltage remains at 12V, due to the increase in the width of the pin to 3.3mm, compared with the original 6 pins with a width of 0.3mm, the area of ​​the conductive spring corresponding to the power pin after redefinition is nearly doubled. After testing, the current carrying capacity of the conductive spring of this area can be increased to more than 30A. Therefore, the maximum power supply power that the gold finger connector can provide after redefinition can reach: 30A×12V=360W, which is more than 4 times higher than the 79.W before redefinition.

[0103] Since the power supply of the power pin is increased, the increased power supply can support the configuration of more second storage media in the memory module. For example, the power consumption of each DDR is about 10-15W at present, and the power consumption of other devices and circuits in the memory module is about 20W. If the gold finger connector before redefinition is used, the power supply of its power pin can only reach 79.8W at most. In addition to the 20W supplied to other devices and circuits in the memory module, the remaining 59.8W can only be supplied to 4-6 DDRs at most. In other words, each memory module can only be packaged with 4-6 DDRs at most. If the gold finger connector after redefinition is used, the power supply of its power pin can reach 360W. In addition to the 20W supplied to other devices and circuits in the memory module, the remaining 340W can also supply 22-34 DDRs. Therefore, each memory module can be packaged with 22-34 DDRs, which greatly expands the storage capacity of the server.

[0104] It should be noted that as the number of DDR increases, the power of the memory controller will also increase, resulting in an increase in the power of other devices and circuits in the memory module. Therefore, the number of DDRs that can actually be expanded in the memory module is less than the 22 to 34 mentioned above. Through experimental verification, it was found that even considering the increased power of the memory controller, the redefined gold finger connector can still support the expansion of more than 10 DDRs, which is sufficient for current use.

[0105] In addition, the above Figure 7 The example of a group of power pins in the redefined gold finger connector is only used for introduction. However, in actual products, the redefined gold finger connector can contain any number of power pins from 1 to 5. For example, please refer to Figure 8 , which shows several possible schematic diagrams of power pins before and after redefinition provided by the present application.

[0106] Figure 8 (A) shows the power pin structure before redefinition, in which the pin width of each pin is 0.3mm, and the pin spacing between the center points of two adjacent pins is 0.6mm. Therefore, the area where the original pins B1 to B6 or the original pins A1 to A6 are located occupies a total width of 3.6mm. The power pin structure before redefinition defines six groups of power pins within the 3.6mm width range where the original pins B1 to B6 or the original pins A1 to A6 are located, and the distance between the edges of two adjacent pins is 0.3mm.

[0107] Figure 8(B), (C), (D), (E) and (F) show five redefined power pin structures. These five redefined power pin structures redefine one, two, three, four and five groups of power pins within the 3.6 mm width range of the original pins B1 to B6 or the original pins A1 to A6, respectively. Figure 8 Compared with the power pin structure before redefinition shown in (A), any power pin structure after redefinition has at least one power pin with a pin width greater than 0.3 mm, and as the number of power pins in the layout increases, the pin width of the power pin will generally become smaller. In order to facilitate understanding of this solution, each power pin structure after redefinition is described in detail below.

[0108] For a possible redefinition, see Figure 8 (B) shows a structure in which only one group of power pins exists after redefinition. This structure defines pin A1 as a ground pin and pin B1 as a positive pin. The ground pin A1 occupies the area between the left edge of the original pin A1 and the right edge of the original pin A6, and the positive pin B1 occupies the area between the left edge of the original pin B1 and the right edge of the original pin B6. In addition to maintaining a 0.3mm space between the pin and the left edge of the gold finger connector, the remaining 3.3mm can be used to configure the conductive spring of the pin, that is, the width of the conductive spring corresponding to the redefined ground pin A1 or positive pin B1 can be increased to 3.3mm.

[0109] For another possible redefinition, see Figure 8 Middle (C1) and Figure 8 In (C2), two structures with two groups of power pins after redefinition are shown. This structure defines pins A3 and A5 as two ground pins, and pins B3 and B5 as two positive pins. In addition to maintaining a 0.3mm space between the pins and the left edge of the gold finger connector and a 0.3mm space between the edges of adjacent pins, the remaining 3mm can be used to configure the conductive springs of the two ground pins or the two positive pins. For example, in Figure 8 In the structure shown in (C1), the conductive springs of each ground pin and each positive pin may have the same width. For example, the ground pin A3 occupies the area between the illustrated left edge of the original pin A1 and the illustrated right edge of the original pin A3, the ground pin A5 occupies the area between the illustrated left edge of the original pin A4 and the illustrated right edge of the original pin A6, the positive pin B3 occupies the area between the illustrated left edge of the original pin B1 and the illustrated right edge of the original pin B3, and the positive pin B5 occupies the area between the illustrated left edge of the original pin B4 and the illustrated right edge of the original pin B6. In this way, the width of the conductive spring corresponding to any positive pin or any ground pin can be increased to 1.5 mm. For another example, in Figure 8 In the structure shown in (C2), each ground pin or each positive pin may have a different width, for example, the ground pin A3 occupies the area between the illustrated left edge of the original pin A1 and the illustrated right edge of the original pin A4, the ground pin A5 occupies the area between the illustrated left edge of the original pin A5 and the illustrated right edge of the original pin A6, the positive pin B3 occupies the area between the illustrated left edge of the original pin B1 and the illustrated right edge of the original pin B4, and the positive pin B5 occupies the area between the illustrated left edge of the original pin B5 and the illustrated right edge of the original pin B6. In this way, the width of the conductive spring corresponding to the ground pin A3 and the positive pin B3 can be increased to 2.1 mm, while the width of the conductive spring corresponding to the ground pin A5 and the positive pin B5 can be increased to 0.9 mm.

[0110] For another possible redefinition, see Figure 8 Middle (D1) and Figure 8 In (D2), it shows a structure with three groups of power pins after two redefinitions. This structure defines pins A2, A4 and A5 as three ground pins, and defines pins B2, B4 and B5 as three positive pins. In addition to maintaining a 0.3mm space between the pins and the left edge of the gold finger connector and a total of 0.6mm space between the edges of two adjacent groups of pins, the remaining 2.7mm can be used to configure the three ground pins or the three positive pins. Conductive springs. For example, in Figure 8 In the structure shown in (D1), the conductive springs of each grounding pin and each positive pin may have the same width, for example, the grounding pin A2 occupies the area between the illustrated left edge of the original pin A1 and the illustrated right edge of the original pin A2, the grounding pin A4 occupies the area between the illustrated left edge of the original pin A3 and the illustrated right edge of the original pin A4, the grounding pin A5 occupies the area between the illustrated left edge of the original pin A5 and the illustrated right edge of the original pin A6, the positive pin B2 occupies the area between the illustrated left edge of the original pin B1 and the illustrated right edge of the original pin B2, the positive pin B4 occupies the area between the illustrated left edge of the original pin B3 and the illustrated right edge of the original pin B4, and the positive pin B5 occupies the area between the illustrated left edge of the original pin B5 and the illustrated right edge of the original pin B6. In this way, the width of the conductive spring corresponding to any positive pin or any grounding pin may be increased to 0.9 mm. For another example, in Figure 8In the structure shown in (D2), each ground pin or each positive pin may have a different width, for example, the ground pin A2 occupies the area between the illustrated left edge of the original pin A1 and the illustrated right edge of the original pin A2, the ground pin A4 occupies the area between the illustrated left edge of the original pin A3 and the illustrated right edge of the original pin A5, the ground pin A5 occupies the area of ​​the original pin A6, the positive pin B2 occupies the area between the illustrated left edge of the original pin B1 and the illustrated right edge of the original pin B2, the positive pin B4 occupies the area between the illustrated left edge of the original pin B3 and the illustrated right edge of the original pin B5, and the positive pin B5 occupies the area of ​​the original pin B6. In this way, the width of the conductive spring corresponding to the ground pin A2 and the positive pin B2 can be increased to 0.9 mm, the width of the conductive spring corresponding to the ground pin A4 and the positive pin B4 can be increased to 1.5 mm, and the width of the conductive spring corresponding to the ground pin A5 and the positive pin B5 remains at 0.3 mm.

[0111] For another possible redefinition, see Figure 8 In (E), it shows a structure with four groups of power pins after redefinition, in which pins A2, A4, A5 and A6 are defined as ground pins, and pins B2, B4, B5 and B6 are defined as positive pins, and ground pin A2 occupies the area between the left edge of the original pin A1 and the right edge of the original pin A3, ground pin A4 occupies the area of ​​the original pin A4, ground pin A5 occupies the area of ​​the original pin A5, ground pin A6 occupies the area of ​​the original pin A6, and positive pin B2 It occupies the area between the left edge of the original pin B1 in the diagram and the right edge of the original pin B3 in the diagram, the positive pin B4 occupies the area of ​​the original pin B4, the positive pin B5 occupies the area of ​​the original pin B5, and the positive pin B6 occupies the area of ​​the original pin B6. In this way, the width of the conductive spring corresponding to the ground pin A2 and the positive pin B2 can be increased to 1.5mm, and the width of the conductive spring corresponding to the ground pin A4, the ground pin A5, the ground pin A6, the positive pin B4, the positive pin B5 and the positive pin B6 remains at 0.3mm.

[0112] For another possible redefinition, see Figure 8In (F), it shows a structure with five groups of power pins after redefinition, which defines pins A2, A3, A4, A5 and A6 as ground pins, defines pins B2, B3, B4, B5 and B6 as positive pins, and the ground pin A2 occupies the area of ​​the original pin A1, the ground pin A3 occupies the area of ​​the original pin A2, the ground pin A4 occupies the area between the left edge of the original pin A3 and the right edge of the original pin A4, the ground pin A5 occupies the area of ​​the original pin A5, the ground pin A6 occupies the area of ​​the original pin A6, and the positive pin B2 occupies the area of ​​the original pin A1. The positive pin B3 occupies the area of ​​the original pin B2, the positive pin B4 occupies the area between the left edge of the original pin B3 in the diagram and the right edge of the original pin B4 in the diagram, the positive pin B5 occupies the area of ​​the original pin B5, and the positive pin B6 occupies the area of ​​the original pin B6. In this way, the width of the conductive spring corresponding to the ground pin A4 and the positive pin B4 can be increased to 0.9mm, and the width of the conductive spring corresponding to the ground pin A2, the ground pin A3, the ground pin A5, the ground pin A6, the positive pin B2, the positive pin B3, the positive pin B5 and the positive pin B6 remains at 0.3mm.

[0113] It should be noted that the above Figure 8 Several examples of pinouts are given for illustration only. This example uses the example of selecting the same numbered pins for the positive pin and the ground pin. However, in actual products, the ground pin can be defined by selecting any 1 to 5 pins from pins A1 to A6, and the positive pin can be defined by selecting any 1 to 5 corresponding pins from pins B1 to B6. The numbers of the selected ground pins and positive pins can be the same or different. For example, in another example, pins A2 and A5 can be selected as two ground pins, and pins B2 and B4 can be selected as two positive pins. This is just a difference in the pin numbers. It is sufficient to define the positions of the corresponding ground pins and positive pins at the same position on the front and back of the PCB.

[0114] In addition, the widths of the positive pins and the ground pins shown above are only an example to ensure that the power pin can cover the area where the original pins B1 to B6 and the original pins A1 to A6 are located to the greatest extent. However, in actual scenarios, all the defined positive pins may only cover part of the area where the original pins B1 to B6 are located, and all the defined ground pins may only cover part of the area where the original pins A1 to A6 are located. Figure 8Taking (C1) as an example, in another example, the pin width of the ground pin A3 and the positive pin B3 can be configured to be 1mm, and the pin width of the ground pin A5 and the positive pin B5 can be configured to be 1.5mm. Although such a configuration cannot completely cover the entire area where the original pins B1~B6 and the original pins A1~A6 are located, it can also increase the power supply capacity by increasing the width of the conductive spring.

[0115] Furthermore, although any number of power pins in groups 1 to 5 of power pins can be redefined, the fewer the number of power pins, the more difficult it may be to plug and unplug the gold finger connector. Therefore, in order to achieve a balance between flexible plugging and unplugging and large power supply, two to three large power pins can be redefined in the area where the original power pins are located, thereby ensuring that the power supply capacity is improved while maintaining the flexibility of the gold finger connector plugging and unplugging.

[0116] It should be understood that the above content is only introduced by taking the pin width of 0.3mm defined by the EDSFF standard as an example. This is only for the convenience of explaining the solution, and does not limit the pin width to this value. With the evolution of the EDSFF standard, the pin width may also be changed to other values, or when applied in other fields, the standards followed may also stipulate that the pin width is other values, or due to process manufacturing errors, the pin width cannot be strictly limited to 0.3mm, but fluctuates around 0.3mm. However, as long as the power pin with greater power supply power is realized according to the solution of merging pins given in this application, it is within the protection scope of this application.

[0117] In addition, the above only uses the memory expansion scenario as an example to introduce how to obtain greater power supply capacity by redefining the power pins to achieve large-scale memory expansion. This solution can also be applied to any other scenarios that require high-power modules, such as accelerator cards or GPU cards. By redefining the power pins of the gold finger connector involved in the accelerator card or GPU card, a greater power supply is provided for the accelerator card and GPU card, thereby supporting the configuration of more accelerator cards or GPU cards. This application does not limit the scenarios to which the solution of redefining the power pins of the gold finger connector is applicable.

[0118] And, since the power pins of the gold finger connector have been redefined, the power connector plugged into the gold finger connector also needs to be adjusted accordingly. For example, when the gold finger connector is redefined as two groups of power pins (input pins), the power connector can also be redefined as two groups of power supply pins (output pins). Alternatively, even if the power connector is not redefined, but still uses the original design of 6 groups of power supply pins, according to the redefinition scheme given in this application, after the two are plugged in, the original 6 groups of power supply pins in the power connector can still contact each power pin in the redefined gold finger connector, so that the redefined gold finger connector can still be compatible with the original power connector. Alternatively, even if the gold finger connector is not redefined, but the power supply pins of the power connector are redefined in this way, the gold finger connector can also be compatible with the redefined power connector. It can be seen that this power pin redefinition scheme can make the gold finger connector adapt to the original power connector or the redefined power connector, and its compatibility and adaptability are good.

[0119] As another possible embodiment, the present application also provides a gold finger connector with a newly added out-of-band communication pin. Compared with the gold finger connector before redefinition, the gold finger connector can realize the communication between the processing module in the memory module and the media management board outside the memory module through the newly added out-of-band communication pin. Figure 5b Taking the shown architecture as an example, the newly added out-of-band communication pins can be used to realize communication between the second integrated unit in the memory module and the third integrated unit 421 in the media management board 420 outside the memory module, so as to provide hardware support for the second integrated unit in the memory module to transmit access frequency information to the third integrated unit 421 outside the memory module, and realize a hot and cold migration solution based on the second integrated unit.

[0120] For more information, please see Figure 7 Middle (A) and Figure 7In (C), compared with the gold finger connector before redefinition, the gold finger connector after redefinition has a new set of out-of-band communication pins, which can be connected to the second integrated unit in the memory module through the aforementioned out-of-band communication bus. In this way, when the memory module is plugged into the media management board 420 through the gold finger connector, the out-of-band communication bus can realize the connection between the second integrated unit and the gold finger connector, and then realize the connection between the second integrated unit and the third integrated unit 421 on the media management board 420. In this way, the second integrated unit can send the access frequency information of each second storage address in the memory module to the third integrated unit 421 through the out-of-band communication bus and the out-of-band communication pins on the gold finger connector. Among them, the out-of-band communication pins can be defined by selecting the reserved pins in the gold finger connector, such as pin B68, pin B69, pin A68, pin A69, pin A70 and pin S2 in the EDSFF specification.

[0121] In some scenarios, the out-of-band communication pin may transmit access frequency information by means of differential signals. In this case, according to the EDSFF specification, the location and input signal of the out-of-band communication pin may be configured as shown in Table 3 below:

[0122] Table 3

[0123] Pinout Signal Signal Pinout B68 Hisport_TXn Hisport_RXn A68 B69 Hisport_TXp Hisport_RXp A69

[0124] Combined with Table 3 and Figure 7 In (C), in the redefined gold finger connector, the reserved pins B68 and B69 can be defined as two sending pins of differential signals, the reserved pins A68 and A69 can be defined as two receiving pins of differential signals, and the conductive springs corresponding to these four pins can be pasted at the free position on the right edge of the PCB to realize the corresponding out-of-band communication function. In this way, the second integrated unit can send the access frequency information of each second storage address in the memory module to the third integrated unit 421 through the defined B68 pin and the defined B69 pin, and can receive the return information of the third integrated unit 421 through the defined A68 pin and the A69 pin, such as the response information of successful reception.

[0125] In some examples, the pin width of each sending pin or each receiving pin and the pin spacing between adjacent sending pins or adjacent receiving pins can remain the same as the configuration of the gold finger connector before redefinition, for example, the pin width of each sending pin and each receiving pin is configured to be 0.3mm, and the pin spacing between two adjacent sending pins or two adjacent receiving pins is configured to be 0.6mm. However, this is only an optional implementation. In another optional implementation, there may be one or more sending pins, or one or more receiving pins, or one or more groups of adjacent sending pins, or one or more groups of adjacent receiving pins. The pin spacing remains different from the configuration of the gold finger connector before redefinition, and there is no specific limitation.

[0126] It should be understood that the positions of the various transmitting pins, receiving pins and conductive springs shown in the above content are only examples. In other scenarios, other reserved pins can be selected as transmitting pins or receiving pins, or conductive springs can be packaged at other locations on the PCB, without specific limitation.

[0127] Based on the above two differences, the following takes the redefinition of two groups of power pins as an example, and introduces the definition of each pin in the redefined gold finger connector based on Table 4. It should be noted that this example takes the gold finger connector following the EDSFF standard as an example, but it should be understood that the same design concept can also be applied to any existing or future information security standard that may evolve, such as the common criteria of information technical security evaluation methodology (CEM), technical specification standard OCP or other similar standards, and this application does not make specific limitations on this.

[0128] Table 4

[0129]

[0130]

[0131]

[0132] Referring to Table 4, compared with the gold finger connector before redefinition, the pin definitions of pins B7 to B67, pin B70, pin A7 to A67, and pin A70 in the gold finger connector after redefinition remain unchanged, while pins B1 and B5 are defined as two positive pins, pins A2 and A4 are defined as two ground pins, and the original reserved pins B67 and B68 are defined as two transmission pins of differential signals, and the original reserved pins A67 and A68 are defined as two receiving pins of differential signals. In addition, although pins B2 to B4, pin B6, pin A1, pin A3, pin A5, and pin A6 are no longer defined, the areas where these pins are located have been occupied by the large power pins after redefinition, so these pins no longer exist.

[0133] In the present application, by redefining the pins in the gold finger connector using the above two differences, not only can the power supply capacity of the gold finger connector be improved, which is convenient for supporting the setting of more second storage media in the memory module, but also the redefined gold finger connector can be adapted to the updated memory module. More specifically, it can adapt to the receiving and sending capabilities of the newly added second integrated unit in the memory module, providing support for the implementation of the following hot and cold data migration solutions.

[0134] It should be noted that the above content only exemplifies a possible redefinition method. The specific selection of which pins to use as power pins or out-of-band communication pins can be set by technical personnel in this field according to needs or habits, and this application does not make any specific limitations on this.

[0135] Also, in the present application, the conductive spring can be made of any material with conductive function, such as gold-plated copper, beryllium copper, manganese steel, phosphor bronze, brass, iron or stainless steel. The shape of the conductive spring can be designed according to actual product requirements, for example, it can be set as follows Figure 7 The rectangle shown can also be set to a bent shape. In addition to realizing the conductive function, the bent conductive spring can also make the two connected devices closer and less likely to dislocate through the mutual contact with the opposite connector through the bent end, thereby maintaining the reliability of the connection.

[0136] In addition, with the development of mechanical manufacturing technology, conductive contacts may develop more materials and forms. Any solution that merges the original power pins to obtain a larger power pin, or that adds an out-of-band communication pin to achieve hot and cold migration based on the second integrated unit, is within the scope of protection of this application, and this application does not limit this.

[0137] The above content introduces the specific differences between the gold finger connector in the memory module provided by the present application and the gold finger connector in the existing memory module. In addition, the present application also provides a solution for hot and cold migration of server data. The specific implementation of the hot and cold migration solution is introduced below.

[0138] To facilitate the introduction of the solution, the storage addresses corresponding to the first storage medium are referred to as first storage addresses, and the storage addresses corresponding to the second storage medium are referred to as second storage addresses, but it should be understood that this does not constitute a limitation on the present application.

[0139] For example, Figure 5b For example, see the server architecture shown in Fig. 9 , which shows a schematic diagram of the interaction process of a cold and hot data migration solution provided by this application. Fig. 9 As shown in the figure, the cold and hot data migration process includes the following steps:

[0140] Step 901: A first integrated unit accesses one or more second storage addresses in a memory module.

[0141] Exemplarily, for each memory module, the first integrated unit in the memory module can connect all the storage units contained in each first storage medium in the memory module through the control address line. When the processor 411 needs to read and write data in a certain memory module, it can send a read and write request to the first integrated unit in the memory module. The first integrated unit determines the storage unit that needs to be accessed this time according to the read and write request, and then opens the storage unit that needs to be accessed by adjusting the high and low levels of the control address line, and then stores data in the storage unit, or reads data from the storage unit. Among them, the storage unit that needs to be accessed may be one, multiple, or all, and there is no specific limitation.

[0142] Step 902: The second integrated unit sends access frequency information of each second storage address in the memory module to the third integrated unit.

[0143] Exemplarily, the second integrated unit in any memory module can monitor the various control address lines set in the memory module in a periodic manner. During the cycle period of each cycle, if there is a level jump on a certain control address line, the second integrated unit can determine the storage unit being accessed this time based on the jump situation, and determine the second storage address to which the storage unit being accessed this time belongs, and then update the access frequency of the second storage address. Afterwards, at the end of the cycle period of each cycle, the second integrated unit can send the access frequency of each second storage address in the memory module to the third integrated unit. Specifically, it can be sent to the third integrated unit via the additional out-of-band communication bus in the aforementioned memory module and the newly added out-of-band communication pin on the gold finger connector.

[0144] Wherein, the access frequency of each second storage address in the memory module can be exemplarily counted in the second access frequency table, and the second access frequency table can be stored locally in the second integrated unit, or stored outside the second integrated unit, such as in the first integrated unit or the second storage medium. The second access frequency table can include each second storage address in the memory module and the corresponding access frequency, and can be refreshed according to a preset cycle duration, such as refreshing once every 2 seconds. Wherein, each second storage address can contain only the address of one storage unit, or can contain the addresses of multiple storage units. For example, when the second storage address is divided according to the space of one storage unit, the memory module contains as many second storage addresses as the number of storage units, and when the second storage address is divided according to the space of not one storage unit, the memory module contains less second storage addresses than the number of storage units, and the number of storage units corresponding to different second storage addresses can be the same or different, and there is no specific limitation.

[0145] For example, in a specific example, please refer to Table 5.1, which shows a second access frequency table obtained after dividing the second storage address in the memory module 431 according to the space of non-one storage unit:

[0146] Table 5.1

[0147]

[0148] In the diagram of Table 5.1, there are 17 storage units in total in the memory module 431, among which: the 1st to 6th storage units are divided into the first second storage address, i.e., 0x0000~0x0005, and the second storage address has been accessed 10 times so far; the 7th storage unit is divided into the second second storage address, i.e., 0x0006, and the second storage address has been accessed 5 times so far; the 8th to 14th storage units are divided into the third second storage address, i.e., 0x0007~0x000D, and the second storage address has not been accessed so far; the 15th to 17th storage units are divided into the fourth second storage address, i.e., 0x000E~0x0010, and the second storage address has been accessed 15 times so far.

[0149] Assuming that at a certain moment in the current cycle, the second integrated unit 43112 determines that the storage unit being accessed this time is the 7th to 10th storage unit according to the level jump of the control address line in the memory module 431, the second integrated unit 43112 can update the second access frequency table as shown in the following Table 5.2:

[0150] Table 5.2

[0151]

[0152] Referring to Table 5.1 and Table 5.2 together, since the 7th storage unit is accessed, the access count of the corresponding second storage address 0x0006 is increased by 1 and updated to 6. Since the 8th to 10th storage units are accessed, the access count of the corresponding second storage addresses 0x0007 to 0x000D is also increased by 1 and updated to 1.

[0153] It should be clarified that the above content is only introduced by taking the table as an example to carry the access frequency of each second storage medium unit. The present application is not limited to the use of tables for carrying. For example, in other examples, access frequency bar charts, access frequency line charts, stacks or queues and other methods can also be used to carry, without specific limitation.

[0154] Step 903: The third integrated unit obtains access frequency information of each second storage address in each memory module through statistics.

[0155] Exemplarily, the second integrated unit in each memory module can send the second access frequency table of the memory module to the third integrated unit 421 in the same cycle. After receiving the second access frequency table of each memory module, the third integrated unit 421 obtains a large second access frequency table. In this way, the large second access frequency table can include the access frequency of all second storage addresses in each memory module in the same period, and because it has the same time standard, its comparability is better.

[0156] Step 904: The third integrated unit sends the access frequency information of each second storage address in each memory module to the fourth integrated unit.

[0157] Exemplarily, the third integrated unit 421 may send the large second access frequency table to the fourth integrated unit 422 via a local bus between the third integrated unit 421 and the fourth integrated unit 422 .

[0158] Step 905: The fourth integrated unit sends the access frequency information of each second storage address in each memory module to the processor.

[0159] Exemplarily, the media management board 420 and the server mainboard 410 may be connected via an external bus, and after receiving the large second access frequency table from the third integrated unit 421, the fourth integrated unit 422 may send the second access frequency table to the processor 411 via the external bus. The external bus may be, for example, USB or PCIe.

[0160] Step 906: The processor determines a target first storage address where cold data exists and a target second storage address where hot data exists based on the access frequency information of each first storage address and the access frequency information of each second storage address.

[0161] Exemplarily, the processor 411 may also monitor the access frequency of each first storage address directly connected to it in the same cycle as the second integrated unit. For example, a first access frequency table may be provided in the processor 411, and the first access frequency table includes the access frequency of each first storage address on the server motherboard 410 in the current cycle. When the processor 411 receives the second access frequency table from the fourth integrated unit 422, it can interpret the access frequency of all second storage addresses in all memory modules, and then determine the second storage addresses with higher access frequency (for example, the access frequency is greater than the heat threshold) according to the access frequency of all second storage addresses, and determine these second storage addresses as the target second storage addresses where hot data exists. And, the processor can also determine the first storage addresses with lower access frequency (for example, the access frequency is less than the cold threshold) according to the access frequency of all first storage addresses, and determine these first storage addresses as the target first storage addresses where cold data exists. Wherein, the heat threshold is greater than the cold threshold, for example, in some scenarios, the heat threshold can be set to 10, and the cold threshold can be set to 2.

[0162] Step 907: The processor sends a cold-hot migration indication to the first integrated unit, where the cold-hot migration indication includes address information of cold data in the target first storage address and / or the target second storage address.

[0163] Here, the address information of the target second storage address may be, for example, a physical address of the target second storage address.

[0164] Exemplarily, after determining the target first storage address where cold data exists, the processor 411 may first read the cold data stored in the target first storage address through the memory controller integrated in the processor 411, and then combine the data volume of the read cold data and the memory module where the target second storage address where hot data exists, use the address information of the read cold data and / or the target second storage address where hot data exists to generate one or more cold-hot migration instructions, and then send them to the first integrated unit in one or more memory modules. Among them, any cold-hot migration instruction may include only cold data, or only address information of the target second storage address where hot data exists, or both cold data and address information of the target second storage address where hot data exists.

[0165] For example, when the target second storage address where hot data exists does not exist, but the target first storage address where cold data exists exists, the processor 411 can generate one or more cold-hot migration instructions based on the cold data in the target first storage address. For example, if the amount of cold data is small, the processor 411 can directly generate a cold-hot migration instruction based on all the cold data, and send it to the first integrated unit in the memory module with the smallest occupancy, so as to migrate the cold data on the server motherboard 410 to the available memory module as soon as possible, freeing up the occupied space of the server motherboard 410. Conversely, if the amount of cold data is large, the processor 411 can generate multiple cold-hot migration instructions by splitting the cold data, and send them to the first integrated unit in multiple memory modules with smaller occupancy, so as to achieve the balance of memory module occupancy while migrating the cold data on the server motherboard 410 to the available memory modules.

[0166] For example, when the target first storage address for cold data does not exist, but the target second storage address for hot data exists, the processor 411 can carry the physical address of the target second storage address contained in each memory module in the corresponding cold-hot migration indication according to the memory module to which the target second storage address belongs, and send it to the memory module, so that each memory module can return its local hot data to the processor 411 in a targeted manner.

[0167] For another example, when the target first storage address with cold data exists and the target second storage address with hot data also exists, the processor 411 can select several memory modules with small current occupancy according to the occupancy of each memory module, and use these memory modules and the memory modules with hot data as candidate memory modules. Then, for the candidate memory modules without the target second storage address among these candidate memory modules, the processor can generate the corresponding cold-hot migration instruction according to only part of the cold data, and send it to the first integrated unit in the candidate memory module, so as to use the large amount of available space in the candidate memory module to evenly store the cold data on the server motherboard 410. For the candidate memory modules with the target second storage address among these candidate memory modules, the processor can generate the corresponding cold-hot migration instruction according to the target second storage address or the target second storage address and part of the cold data, and send it to the first integrated unit in the candidate memory module, so as to instruct the candidate memory module to return the contained hot data, and also use the available space in the candidate memory module to store the cold data on the server motherboard 410. Of course, carrying the second storage address and the cold data together in a hot-cold migration indication and sending it to the first integrated unit is only an optional implementation. In other implementations, different hot-cold migration indications can also be generated according to the second storage address and the cold data and sent to the same first integrated unit. This application does not make any specific limitations on this.

[0168] Step 908: The first integrated unit sends the hot data in the target second storage address to the processor according to the address information of the target second storage address carried in the cold-hot migration indication.

[0169] Exemplarily, the first integrated unit can read the hot data in the target second storage address through a locally integrated memory controller, and then send the hot data to the processor 411 through a serial bus. The serial bus supports memory semantics, and the transmission of memory data and its control signals can be achieved through a protocol of a serial bus that supports memory semantics.

[0170] Further exemplary, the hot / cold migration indication carries the physical address of the target second storage address, and the first integrated unit directly accesses the physical address to obtain the hot data stored in the target second storage address. The physical address of the target second storage address can be continuous or discontinuous, and is not specifically limited.

[0171] Step 909: The first integrated unit stores the cold data in the target first storage address carried in the cold-hot migration instruction in the second storage address of the memory module.

[0172] Here, the first integrated unit can store the cold data in the target first storage address in the target second storage address, or in other idle second storage addresses, or partially in the target second storage address and partially in other idle second storage addresses, without specific limitation.

[0173] Step 910: The processor stores the hot data in the target second storage address in the first storage address of the server mainboard.

[0174] Further exemplarily, after receiving the thermal data in the target second storage address sent by any first integrated unit, the processor 411 may store the thermal data in the target first storage address, or in other free first storage addresses, or may store the thermal data partially in the target first storage address and partially in other free first storage addresses, without specific limitation.

[0175] In the above-mentioned hot-cold migration scheme, since the processor's access delay to the first storage medium on the server mainboard is smaller than the access delay to the second storage medium on the memory module, by migrating the hot data in the memory module to the server mainboard, the processor can access the hotter data more quickly, thereby improving the data access performance. By migrating the cold data in the server mainboard to the memory module, the cold data can be freed from occupying the server mainboard, thereby increasing the storage capacity of the hot data. Whether it is to increase the access speed of the hot data or to increase the storage capacity of the hot data, the memory performance of the server can be improved.

[0176] It is understandable that the above is only Figure 5b The server architecture shown in the figure is used as an example to introduce the cold and hot data migration method. Figure 5a In the architecture shown, the processing module in the memory module includes only one integrated unit, which can be connected between the gold finger connector of the memory module and at least one second storage medium of the memory module, and can be used to implement the above Fig. 9 The entire functions of the first integrated unit and the second integrated unit in the method embodiment shown include the above Fig. 9Steps 901, 902, 907, 908 and 909 in the embodiment. For example, the integrated unit may receive a read / write request from the media management board 420 through the gold finger connector in the memory module, and may access at least one second storage medium in the memory module according to the read / write request, and then send the access frequency information of each second storage address corresponding to at least one second storage medium in the memory module within a preset period of time to the media management board 420 through the gold finger connector, so that the media management board 420 sends the access frequency information to the processor 411 in the server mainboard 410, and the processor 411 determines the target first storage address where the cold data exists and the target second storage address where the hot data exists. The integrated unit can also receive hot and cold migration instructions from the processor 411 through the gold finger connector in the memory module where it is located. The hot and cold migration instructions carry the address information of the cold data in the first storage address associated with the processor (i.e., the target first storage address) and / or the second storage address associated with the memory module (i.e., the target second storage address). According to the hot and cold migration instructions, the integrated unit can send the hot data in the target second storage address to the processor 411 through the gold finger connector, and can store the cold data in the target first storage address in the second storage address of the memory module 431, so as to realize the migration operation of hot and cold data.

[0177] Alternatively, in another example, the processing module in any memory module may be divided into three or more integrated units, each integrated unit shares part of the functions of the processing module, and three or more integrated units jointly implement all the functions of the processing module.

[0178] Similarly, in another example, when the server uses Figure 5a In the architecture shown in the figure, the media management board 421 includes only one integrated unit, which can be connected between the gold finger connector of any memory module and the processor 411 of the server motherboard 410 to implement the above Fig. 9 The entire functions of the third integrated unit 421 and the fourth integrated unit 422 in the method embodiment shown include the above Fig. 9 For example, the integrated unit may receive access frequency information of each second storage address in the memory module sent by the processing module in any memory module through the gold finger connector, and may count the access frequency information of each second storage address in each memory module, and then send the statistical information to the processor 411 to assist the processor 411 and the memory module to implement the above-mentioned hot-cold migration solution.

[0179] Alternatively, in another example, the media management board 420 may further include three or more integrated units, each of which shares part of the functions of the media management board 420 , and the three or more integrated units jointly implement all the functions of the media management board 420 .

[0180] It should be noted that the concepts, explanations, and detailed descriptions of the hot-cold migration solution and other steps involved in this section can be found above. Fig. 9 The description of these contents in the illustrated method embodiment will not be repeated here.

[0181] It can be understood that the above schemes will combine the processing module in the memory module and the media management board outside the memory module to realize the migration operation of hot and cold data. The processing module in the memory module can only be used to send the access frequency information of the storage medium in the memory module to the components outside the module, and the specific memory migration operation is performed on the side of the components outside the module. Therefore, if the processing module only includes one integrated unit, even if the integrated unit is obtained by improving the ASIC in the existing memory module, the integrated unit can only add the information sending function on the basis of the original memory access function of the ASIC. Compared with the existing new server system that needs to redevelop the ASIC to realize the memory migration function as a whole, the development difficulty is lower, and on the basis of realizing the hot and cold migration scheme, less additional development cost and labor cost can be introduced, thereby realizing low-cost memory expansion of the server. If the processing module includes at least two integrated units, one of the integrated units (such as the first integrated unit) can remain as the original ASIC, and by adding one or two new integrated units (such as the second integrated unit) to the memory module, the one or two new integrated units can be used in conjunction with the external components of the module to migrate the frequently accessed data in the second storage medium of the memory module to the first storage medium of the server mainboard, without the need to redevelop the original integrated unit in the memory module. The operation of developing one or two new integrated units has a simpler research and development process than redeveloping the original integrated unit. For example, there is no need to consider how to layout the devices corresponding to different functions on one unit, nor is there any need to consider how to route to enhance the anti-interference between devices with different functions, and the required manpower cost and research and development cost are low. It can be seen that no matter how many integrated units are included in the processing module, the server system proposed in this application is used to implement the hot and cold migration solution, which can not only improve the memory performance of the server, but also introduce as little additional cost as possible, and can also not increase the working pressure of the original integrated unit in the memory module, which is helpful to realize the design concept of cost reduction in the process of expanding the server memory.

[0182] The above content introduces the specific implementation of the hot and cold migration solution from the perspective of node interaction of the entire server system. The following content introduces the work performed by each device in the memory module when implementing the hot and cold migration solution, as well as some other functions, from the perspective of the internal implementation of the memory module.

[0183] by Figure 5b For example, see the system architecture shown in Fig.10 , which shows a schematic diagram of the internal circuit of a memory module provided by the present application, and the memory module 431 is taken as an example. Fig.10 As shown, in addition to the first integrated unit 43111, the second integrated unit 43112, at least one second storage medium (such as DDR11 to DDR14) and the gold finger connector 4312, the memory module 431 may also include a power module (power, PWR) 4314, at least one indicator light (such as a read-write status indicator light 43151 and a memory module indicator light 43152), at least one temperature sensor (temperature transducer, TMP) (such as TMP 43161 and TMP 43162) and a flash memory (flash memory, FLASH) 4317, as well as various data lines, control address lines and other communication lines that implement the connection relationship shown in the figure. In addition, a PCB may also be included, and the various devices in the memory module 431 are arranged at corresponding positions on the PCB, and two interconnected devices can be connected through the internal wiring on the PCB.

[0184] It should be pointed out that only the single-board layout relationship of the memory module 431 is shown here, and a multi-board layout can also be configured in some scenarios. For example, the memory module 431 includes multiple PCBs that overlap each other, and the various devices in the memory module 431 are separately arranged on multiple PCBs. The devices arranged on one PCB are connected through intra-board routing, and the devices arranged on different PCBs are connected through inter-board routing. Among them, the overlap of multiple PCBs can be complete overlap, partial overlap, or partial overlap of some PCBs and complete overlap of some PCBs. In this way, by performing overlapping layouts in space, the occupied area of ​​the memory module can be reduced, and the miniaturized design of the memory module can be achieved.

[0185] as well as, Fig.10The device composition of the memory module shown is only an example, and the memory module may also include more or fewer components than shown. For example, in some embodiments, the memory module 431 may also include other integrated units in addition to the first integrated unit 43111 and the second integrated unit 43112, and the other integrated units are used to share the work of the first integrated unit 43111 or the second integrated unit 43112. For example, in other embodiments, the DDRC may not be integrated in the first integrated unit 43111, for example, it may also be used as a separate device, or integrated in the second integrated unit 43112, or integrated in other non-integrated units. For example, in some other embodiments, the memory module 431 may not include PWR4314, but may be directly powered by an external power supply to save the occupied volume of the memory module 431. For example, in some other embodiments, the memory module 431 may also include more or less than two indicator lights, or more or less than two TMPs. There are many possible implementation methods, and this application will not list them one by one.

[0186] Below Fig.10 Taking the device composition shown in the figure as an example, each device in the memory module is introduced in detail.

[0187] The first integrated unit 43111 includes a high-speed serial protocol (compute express link, CXL) interface and at least one DDR controller (DDR controller, DDRC). Among them, CXL can be connected to the serial pin a1 in the gold finger connector 4312 through a serial bus. The serial bus can be, for example, an X16 bus with 16 serial transmission channels shown in the figure, or an X4 bus or an X8 bus, etc., without limitation. In addition, the number of DDRC depends on the memory mode and the number of DDRs in the memory module 431. For example, when the 2DPC mode is adopted, one DDRC can be connected to 2 DDRs. Since the memory module 431 contains 4 DDRs, the first integrated unit 43111 may include two DDRCs, such as DDRC0 and DDRC1. DDRC0 is connected to DDR11 and DDR12 through a data line, and DDR1 is connected to DDR13 and DDR14 through a data line. Among them, the data line can be used to transmit data signals, such as DQ signals. In the scenario of reading data, DDRC can determine when to receive the read data based on the DQ signal sent by the connected DDR. In the scenario of writing data, DDR can determine when to trigger the reception of data based on the DQ signal sent by the connected DDRC. For example, in some scenarios, reading and writing data depends on the DQ signal and the data selection signal DQS. The DQS signal is transmitted on the DQS signal line. Each chip has a DQS data line (not shown in the figure) to transmit the DQS signal for reading and writing reference. The DQS signal can be received by DDRC and DDR in real time. In the scenario of reading data, after receiving the DQ signal of DDR, DDRC can compare the DQ signal and the DQS signal. When the edge of the DQ signal is aligned with the edge of the DQS signal (for example, the rising edge of the DQ signal is aligned with the rising edge of the DQS signal), it starts to read the data stored in the storage unit. On the contrary, in the scenario of writing data, after receiving the DQ signal of DDRC, DDR can compare the DQ signal and the DQS signal, and when the center of the DQ signal is aligned with the center of the DQS signal (for example, the pulse center of the DQ signal is aligned with the pulse center of the DQS signal), it starts to write data to the storage unit. In addition, DDRC0 can also connect each storage unit in DDR11 and DDR12 through the control address line, and DDR1 can also connect each storage unit in DDR13 and DDR14 through the control address line. Among them, the control address line is used to transmit the control address signal (CA) signal.The control address lines generally include row control address lines and column control address lines. For example, assuming that there are M rows and N columns of storage cells, the control address lines may include M row control address lines and N column control address lines. When it is necessary to read and write data in a certain storage cell, DDR can first send a valid level on the row control address line of the row where the storage cell is located to drive the row where the storage cell is located to open, and then send a valid level on the column control address line of the column where the storage cell is located to drive the storage cell to open. At this time, DDR can read and write data in the opened storage cell. In this process, the CA signal on the row control address line of the row where the storage cell to be read and written is located and the CA signal on the column control address line of the column where the storage cell to be read and written is present as a valid level, and the CA signal on the other control address lines except the row and the column is present as an invalid level. In some embodiments, the valid level can be a "1" level, and the invalid level is a "0" level, or, in other embodiments, the valid level is a "0" level and the invalid level is a "1" level.

[0188] It should be noted that, in addition to CXL, the first integrated unit 43111 may also include other interfaces, such as a clock interface b2 and a status interface b3. Among them, the clock interface b2 can be connected to the clock pin a2 on the gold finger connector 4312 through the reference clock signal line Ref_clk, and is used to receive the reference clock signal transmitted through the clock pin a2 of the gold finger connector 4312. The reference clock signal may be, for example, sent by the processor 411, and the first integrated unit 43111 may provide a reference clock for each device in the memory module 431 according to the received reference clock signal. The status interface b3 may be connected to the management pin a3 on the gold finger connector 4312 through the out-of-band management bus SMBUS, and is used to receive a status request message transmitted through the management pin a3 of the gold finger connector 4312. The status request message may be, for example, sent by the processor 411, and is used to obtain relevant status information of the memory module 431, such as temperature. In this case, the first integrated unit 43111 can obtain the temperatures collected by TMP 43161 and TMP 43162 located at different positions of the memory module 431 according to the status request message, and can return the temperature or processed temperature to the processor 411 through the SMBUS and the management pin a3 on the gold finger connector 4312.

[0189] In addition, the first integrated unit 43111 can also be connected to the read / write status indicator light 43151 through a line. When reading and writing data in DDR11 to DDR14, the first integrated unit 43111 can send a lighting indication to the read / write status indicator light 43151, and after the reading and writing are completed, it can send a light-off indication to the read / write status indicator light 43151, so as to timely notify the outside personnel whether the memory module 431 is reading and writing by controlling whether the read / write status indicator light 43151 is lit.

[0190] In addition, the codes or instructions for implementing the above functions by the first integrated unit 43111 can be stored in FLASH 4317. The first integrated unit 43111 is connected to FLASH 4317 via a serial peripheral interface (SPI), and when needed, the required codes or instructions can be obtained from FLASH 4317 via SPI to execute the above functions.

[0191] The second integrated unit 43112 can be connected to all the control address lines in the memory module 431, and is used to monitor the CA signals on these control address lines in real time. When a level jump of the CA signal on a certain control address line is detected, the jump is analyzed to determine the storage unit accessed by the first integrated unit 43111 this time, and then determine the second storage address to which the storage unit belongs. In some scenarios, the second integrated unit 43112 can also store a second access frequency table, which includes multiple second storage addresses and corresponding access frequencies, wherein the multiple second storage addresses are obtained by dividing DDR11 to DDR14. For example, assuming that DDR11 to DDR14 has a total of 128GB, 33,554,432 second storage addresses can be obtained by dividing one second storage address per 4KB. The second integrated unit 43112 can update the second access frequency table in a periodic manner. In each cycle, after the second integrated unit 43112 determines that a second storage address is accessed, it can add 1 to the access frequency of the second storage address in the second access frequency table until the end of the current cycle, and obtain the second access frequency table corresponding to the current cycle. The second integrated unit 43112 can also be connected to the out-of-band communication pin a4 on the gold finger connector 4312 through an out-of-band communication bus. The out-of-band communication bus can be, for example, the Hisport bus shown in the figure. Correspondingly, the out-of-band communication pin a4 on the gold finger connector 4312 corresponds to the Hisport pin, and the Hisport pin can also be connected to the third integrated unit 421 on the media management board 420. After each cycle ends, the second integrated unit 43112 can send the second access frequency table of the current cycle to the third integrated unit 421 through the Hisport bus and the Hisport pin on the gold finger connector 4312. After that, the second integrated unit 43112 can refresh the second access frequency table, such as clearing the access frequency of all second storage addresses in the second access frequency table, and starting the update operation of the second access frequency table of the next cycle.

[0192] In addition to the serial pin a1, clock pin a2, management pin a3 and Hisport pin a4 mentioned above, the gold finger connector 4312 may also include a power pin a5, which is connected to the PWR4314 in the memory module 431, and is used to receive the 12V power signal transmitted by the processor 411 and provide it to the PWR4314. The PWR4314 divides the 12V power signal to obtain multiple sub-power signals such as 1.3V and 1.2V, and then provides the multiple sub-power signals to the first integrated unit 43111, the second integrated unit 43112 and DDR11 to DDR14 respectively. The gold finger connector 4312 may also include a status control pin a6, which is connected to the memory module indicator light 43152. When a failure occurs in the memory module 431, the memory module indicator light 43152 may receive the light indication information sent by the processor 411 through the status control pin a6 of the gold finger connector 4312, and light up the memory module indicator light 43152 according to the light indication information, so as to promptly prompt external personnel of the failure status of the memory module 431.

[0193] With reference to the above introduction to each device in the memory module 431, when implementing the hot-cold migration solution, the processor 411 can send a read / write request to the CXL of the first integrated unit 43111 through the serial pin a1 of the gold finger connector 4312. The first integrated unit 43111 determines the storage unit to be accessed this time according to the read / write request, and sends a read / write instruction to the DDRC connected to the DDR where the storage unit is located. The DDRC sends a CA signal to the control address line corresponding to the storage unit according to the read / write instruction, and after opening the storage unit, reads and writes the data stored in the storage unit. After the second integrated unit 43112 monitors the change of the CA signal, it determines the storage unit to be accessed according to the changed CA signal, and updates the access frequency of the second storage address to which the storage unit belongs in the second access frequency table of the current cycle, and continues to monitor the CA signal until the end of the current cycle, and sends the final second access frequency table to the third integrated unit 421 through the Hisport bus and the Hisport pin a4 of the gold finger connector 4312. Subsequently, the third integrated unit 421 counts the access frequency tables of each memory module and communicates with the fourth integrated unit 422, and sends the second access frequency tables of all memory modules to the processor 411. The processor 411 performs statistical analysis on the second access frequency tables of each memory module and the access frequencies of each first storage address on the server motherboard 410 to determine the hot data in each memory module and the cold data in the server motherboard 410. The processor 411 communicates with the first integrated unit in each memory module to implement the exchange operation between the hot data in each memory module and the cold data in the server motherboard 410. For the specific implementation of the subsequent operations, please refer to the above. Fig. 9 The contents in will not be repeated here one by one.

[0194] Similarly, when the server system uses Figure 5a When the architecture is shown, see Fig.11 , shows a schematic diagram of the internal circuit of another memory module provided by the present application, and the figure still takes the memory module 431 as an example. In the memory module 431, in addition to the clock interface b2 and the status interface b3, the integrated unit may also include a Hisport interface b4. The Hisport pin a4 of the gold finger connector 4312 is connected to the Hisport interface b4 of the integrated unit through the Hisport bus. The integrated unit can send the access frequency information of the current cycle to the gold finger connector 4312 through the Hisport interface b4, and then transmit it to the media management board 420 through the gold finger connector 4312. About Fig.11 For the functions and connection relationships of the various interfaces and devices in Fig.10 The descriptions of each interface and device in the description will not be repeated here one by one.

[0195] It is understandable that the above is only introduced by taking the redefinition scheme of the application of the gold finger connector or the application of the hot and cold migration scheme in the server field as an example. In actual scenarios, the redefinition scheme of the gold finger connector can be applied to any device that is connected using a gold finger connector and has power pins on the gold finger connector. By merging the original number of power pins into a smaller number of power pins, a greater power supply capacity can be achieved, thereby broadening the specifications of the device where the gold finger connector is located. The hot and cold migration scheme can be applied to any solution with two storage media. By migrating hot data from a storage medium with a large access delay to a storage medium with a small access delay, and migrating cold data from a storage medium with a small access delay to a storage medium with a large access delay, the effect of quickly accessing hot data and improving the storage capacity of the storage medium where the hot data is located can be achieved, thereby improving the storage performance of storage devices with two storage media.

[0196] According to the structure and functional principles of the memory module introduced above, the present application can also provide a data migration method, which can be executed by the aforementioned memory module or electronic device (such as a server), and the method includes: obtaining a hot-cold migration instruction, the hot-cold migration instruction carries the address information of the cold data in the first storage address associated with the processor and / or the second storage address associated with the memory module; according to the address information of the second storage address carried in the hot-cold migration instruction, sending the hot data in the second storage address to the processor in the electronic device; storing the cold data in the first storage address carried in the hot-cold migration instruction to the second storage address.

[0197] Here, "associated" can be understood as "logically connected" or "functionally accessible". For example, the first storage address associated with the processor refers to a storage address that can be directly accessed by the processor in the electronic device mainboard. For example, it can be a storage address located in the electronic device mainboard. The storage address is directly connected to the processor in the electronic device mainboard, and its internal data can be directly accessed by the processor in the electronic device mainboard. Similarly, the second storage address associated with the memory module refers to a storage address that can be directly accessed by the processing module in the memory module. For example, it can be a storage address located in the memory module. The storage address is directly connected to the processing module in the memory module, and its internal data can be directly accessed by the processing module in the memory module.

[0198] Optionally, before obtaining the hot-cold migration instruction, the method may further include: accessing one or more second storage addresses in the memory module, and sending access frequency information of each second storage address in the memory module to a media management board in the electronic device.

[0199] It should be noted that the specific implementation process of this method can refer to the above Fig. 9The relevant introduction contents will not be repeated here one by one.

[0200] According to the aforementioned method, the present application can also provide a data migration device, see Fig.12 , showing a possible structural diagram of the data migration device. The data migration device 1200 may be a chip or a circuit. The data migration device 1200 may correspond to the memory module in the above method, such as a processing module in the memory module, or a first integrated unit and a second integrated unit. The data migration device 1200 may implement the above Fig. 9 The steps of the method corresponding to the first integrated unit and the second integrated unit in the embodiment shown. Fig.12 As shown, the data migration device 1200 may include an acquisition module 1210 , a transceiver module 1220 and a storage module 1230 .

[0201] In the present application, the acquisition module 1210 can acquire a hot-cold migration instruction, which carries the address information of the cold data in the first storage address associated with the processor and / or the second storage address associated with the memory module; the transceiver module 1220 can send the hot data in the second storage address to the processor in the electronic device according to the address information of the second storage address carried in the hot-cold migration instruction; the storage module 1230 can store the cold data in the first storage address carried in the hot-cold migration instruction to the second storage address.

[0202] For the concepts, explanations, detailed descriptions and other steps involved in the data migration device 1200 and related to the technical solution provided in this application, please refer to the description of these contents in the aforementioned method or other embodiments, which will not be repeated here.

[0203] It can be understood that the functions of each module in the above-mentioned data migration device 1200 can be implemented by referring to the corresponding method embodiment, and will not be repeated here.

[0204] It should be understood that the above division of units of the data migration device 1200 is merely a division of logical functions, and in actual implementation, all or part of them may be integrated into one physical entity, or they may be physically separated, and there is no specific limitation.

[0205] In addition, based on the foregoing content, the present application also provides an electronic device, which may be, for example, the foregoing server, or include the foregoing server. For example, in some embodiments, the electronic device may be a computer device with a display screen and a server. The computer device may also include peripherals such as a hard disk, a speaker, a microphone, a mouse or a keyboard, or may also include internal devices such as a drive or an input / output interface.

[0206] The present application also provides a chip, which may include any one or more of the above-mentioned processing module or media management board, or may include any one or more of the above-mentioned first integrated unit, second integrated unit, third integrated unit, and fourth integrated unit, or may also include a processor, or may also include an interface, any one or more devices are used to read instructions through the interface to execute such as Fig. 9 The corresponding method in the embodiment shown.

[0207] The present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed, the following is achieved: Fig. 9 A method performed by any device in the illustrated embodiments.

[0208] The present application also provides a computer program product, which, when executed, implements the following Fig. 9 A method performed by any device in the illustrated embodiments.

[0209] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory module, characterized in that: It includes a processing module and a gold finger connector connected to the processing module; The gold finger connector is used to be plugged into a component outside the memory module to achieve a communication connection between the device in the memory module and the component outside the memory module; The processing module is used to receive a read / write request from the component outside the memory module through the gold finger connector, access at least one storage medium in the memory module according to the read / write request, and transmit access frequency information of each storage address corresponding to at least one storage medium in the memory module within a preset time period to the component outside the memory module through the gold finger connector; wherein the access frequency information of each storage address is used by the component outside the memory module to migrate data stored in storage addresses whose access frequency is greater than a heat threshold to a storage medium connected to a processor.

2. The memory module according to claim 1, wherein: The processing module includes a first integrated unit and a second integrated unit, the first integrated unit is connected to at least one storage medium in the memory module, and the gold finger connector connects the first integrated unit and the second integrated unit; The first integrated unit is used to receive a read / write request from a component outside the memory module through the gold finger connector, and access at least one storage medium in the memory module according to the read / write request; The second integrated unit is used to send access frequency information of each storage address corresponding to at least one storage medium in the memory module within a preset time period to the component outside the memory module through the gold finger connector.

3. The memory module according to claim 2, wherein: One or more reserved pins of the gold finger connector are defined as out-of-band communication pins, and the second integrated unit is connected to the out-of-band communication pins via an out-of-band communication bus; The second integrated unit is used to send the access frequency information of each storage address to the gold finger connector through the out-of-band communication bus and the out-of-band communication pin.

4. The memory module according to claim 3, wherein: The out-of-band communication pin transmits the access frequency information through a differential signal, the B68 pin and the B69 pin of the gold finger connector are defined as two sending pins, and the A68 pin and the A69 pin of the gold finger connector are defined as two receiving pins; The second integrated unit is used to send the access frequency information of each storage address to the gold finger connector through the B68 pin and the B69 pin, and receive the return information of the gold finger connector through the A68 pin and the A69 pin.

5. The memory module according to any one of claims 2 to 4, characterized in that: The memory module further includes a control address line, and the first integrated unit is connected to at least one storage medium in the memory module via the control address line; The first integrated unit is specifically used to: access at least one storage medium in the memory module by adjusting the control address CA signal on the control address line; The second integrated unit is specifically used to determine the access frequency information of the storage address corresponding to at least one storage medium in the memory module within the preset time period according to the change of the CA signal on the control address line.

6. The memory module according to claim 1, wherein: The processing module includes an integrated unit connected between at least one storage medium in the memory module and the gold finger connector.

7. The memory module according to any one of claims 2 to 6, wherein: There is a first positive pin in the area where the B1 pin to the B6 pin of the gold finger connector are located, and there is a first ground pin in the area where the A1 pin to the A6 pin of the gold finger connector are located. The widths of the first positive pin and the first ground pin are both greater than a preset width, and the preset width is the original pin width defined by the standard.

8. The memory module according to claim 7, wherein: The preset width is K, and the widths of the first positive pin and the first ground pin are both 11K.

9. The memory module according to claim 7, wherein: The first positive pins include 2 and the first ground pins include 2. If the preset width is K, the width of each of the first positive pins and each of the first ground pins is 5K, or there is a first positive pin and a first ground pin whose width is 7K, and another first positive pin and another first ground pin whose width is 3K.

10. The memory module according to claim 7, wherein: The first positive electrode pins include three, and the first grounding pins include three. If the preset width is K, the width of each of the first positive electrode pins and each of the first grounding pins is 3K.

11. The memory module according to any one of claims 7 to 10, wherein: The first positive pin and the first ground pin are implemented by gold plating on copper.

12. An electronic device, characterized in that: Comprising the memory module as claimed in any one of claims 1 to 11.

13. The electronic device according to claim 12, characterized in that: It also includes an electronic device mainboard and a media management board, the electronic device mainboard includes a processor and at least one first storage medium, the memory module includes at least one second storage medium, the number of the memory modules is N, and N is a positive integer; Any of the memory modules is used to send access frequency information of each second storage address corresponding to at least one second storage medium in the memory module to the media management board within a preset time period; The media management board is used to send access frequency information of each second storage address corresponding to each second storage medium in the N memory modules within the preset time period to the processor; The processor is used to migrate data stored in a target second storage address with an access frequency greater than a heat threshold to the first storage medium, and migrate data stored in a target first storage address with an access frequency less than a coldness threshold to the second storage medium, based on access frequency information of each first storage address corresponding to the at least one first storage medium within the preset time period and access frequency information of each second storage address corresponding to each second storage medium in the N memory modules within the preset time period.

14. The electronic device according to claim 13, characterized in that: The processing module in any of the memory modules comprises a first integrated unit and a second integrated unit; A first integrated unit in any of the memory modules, used to access at least one second storage medium in the memory module; The second integrated unit in any of the memory modules is used to send access frequency information of each second storage address corresponding to at least one second storage medium in the memory module within a preset time period to the media management board.

15. The electronic device according to claim 13 or 14, characterized in that: The media management board includes a third integrated unit and a fourth integrated unit, the third integrated unit is respectively connected to the fourth integrated unit and the second integrated unit in each of the memory modules, and the fourth integrated unit is also connected to the processor; The third integrated unit is used to receive the access frequency information of each second storage address in the memory module within the preset time period sent by the second integrated unit in each of the memory modules, and summarize the access frequency information of each second storage address in the N memory modules within the preset time period and send it to the fourth integrated unit; The fourth integrated unit is used to send the aggregated access frequency information of each second storage address in the N memory modules within the preset time period to the processor.

16. A data migration method, characterized in that: The method is performed by the memory module according to any one of claims 1 to 11, or the method is performed by the electronic device according to any one of claims 12 to 15, and the method comprises: Obtaining a hot-cold migration instruction, wherein the hot-cold migration instruction carries at least one of cold data in a first storage address associated with a processor or address information of a second storage address associated with the memory module; Sending the hot data in the second storage address to the processor in the electronic device according to the address information of the second storage address carried in the cold-hot migration instruction; The cold data in the first storage address carried in the cold-hot migration indication is stored in the second storage address.

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