Actuator in memory

Abstract

The invention provides an in-memory arithmetic unit. The in-memory arithmetic unit comprises a plurality of operation blocks, a first reference weight block and an output result generator, the operation block has a plurality of weight values, respectively receives a plurality of input signals and generates a plurality of operation results. Each operation block generates each operation result according to the corresponding input signal and the corresponding weight value. The first reference weight block provides a first reference resistance value according to a plurality of reference weight values, and generates a first reference signal according to the first reference resistance value and a read voltage. The output result generator generates a plurality of output operation results according to the first reference signal and the operation results.

Description

Technical Field

[0001] The present invention relates to an in-memory operator, and more particularly to an in-memory operator capable of adjusting a data acquisition time point. Background Art

[0002] With the advancement of electronic technology, the development of artificial intelligence is becoming more and more mature. As a result, a large amount of data computing needs are generated. Based on this, the in-memory operator was introduced.

[0003] In the prior art, a fixed data acquisition time point is often set for a computing unit in a memory to perform a data acquisition operation for the computing result. However, in a neural network, the sizes of various computing layers are different. The delay time for generating computing results based on computing layers of different sizes is different. Therefore, setting a fixed data acquisition time point to perform a data acquisition operation for the computing result may often cause errors in data acquisition or reduce the rate of data acquisition. Summary of the invention

[0004] The invention provides an in-memory operator, which can effectively provide a data acquisition time point for an operation result.

[0005] The in-memory operator of the present invention includes a plurality of operation blocks, a first reference weight block and an output result generator. The operation blocks receive a plurality of input signals respectively and generate a plurality of operation results. Each operation block has a plurality of weight values. Each operation block generates each operation result according to the corresponding input signals and the corresponding weight values. The first reference weight block provides a first reference resistance value according to a plurality of reference weight values, and generates a first reference signal according to the first reference resistance value and the read voltage. The output result generator couples the operation block and the first reference weight block, and generates a plurality of output operation results according to the first reference signal and the operation result.

[0006] Based on the above, the reference weight block of the present invention provides a first reference resistance value according to a preset reference weight value, and generates a reference signal as a data acquisition time basis according to the first reference resistance value. In this way, corresponding to operation blocks of different sizes, the in-memory operator of the present invention can set a better data acquisition time point, thereby improving the working efficiency of the in-memory operator. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of an arithmetic unit in a memory according to an embodiment of the present invention;

[0008] Figure 2 is a schematic diagram of an implementation of a reference weight block in an in-memory operator according to an embodiment of the present invention;

[0009] Figure 3A is a schematic diagram of a unit circuit of an embodiment of the present invention;

[0010] Figure 3B is a relationship diagram between the size of the operator in the memory and the delay time of the corresponding operation result generated in an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of an arithmetic unit in a memory according to another embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of an arithmetic unit in a memory according to another embodiment of the present invention;

[0013] Figure 6 is a schematic diagram of an arithmetic unit in a memory according to another embodiment of the present invention;

[0014] Figure 7 FIG. 4 is a schematic diagram of an implementation of a reference weight block according to an embodiment of the present invention.

[0015] Description of Reference Numerals

[0016] 100, 300, 400, 500, 600: In-memory arithmetic unit

[0017] 110, 410, 510, 610: Output generator

[0018] 121~12N, 421~42N, 521~52N, 621~62N: Operation blocks

[0019] 130, 200, 430, 530, 631, 632, 700: Reference weight blocks

[0020] 211~21A, 711~71A: Unit circuit series

[0021] 411~41N、511~51N Data Capture Device

[0022] C1~CN, CR: capacitor

[0023] CU11~CUAM, CUX: unit circuit

[0024] DO1~DON: Output operation result

[0025] Dt1: delay time

[0026] GTI, GTI1, GTI2: Capture time information

[0027] IN1~INN, IN11~INAM: input signal

[0028] IR1~IRA: Current

[0029] MC: Flash Memory Cell

[0030] MUX: Multiplexer R1, R2: Resistance value

[0031] Rs: unit resistance value

[0032] SA1~SAN, SAR, SAR1, SAR2: Sense amplifier

[0033] V1~VN:Calculation result

[0034] VL: Sensing reference signal

[0035] VR: Read voltage

[0036] Vref, Vref1, Vref2: reference signal

[0037] VSS: reference ground

[0038] WL: Word Line DETAILED DESCRIPTION

[0039] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of an in-memory operator according to an embodiment of the present invention. The in-memory operator 100 includes an output result generator 110, a plurality of operation blocks 121-12N, and a reference weight block 130. Each operation block 121-12N has a plurality of weight values. The operation blocks 121-12N receive a plurality of input signals IN1-INN respectively. Each operation block 121-12N performs operations according to the weight values ​​it has and the input signals IN1-INN it receives, and generates operation results V1-VN corresponding to each operation block 121-12N. In this embodiment, each operation block 121-12N can perform multiplication and addition operations according to the weight values ​​it has and the input signals IN1-INN it receives, and transmits the generated operation results V1-VN to the output result generator 110. In addition, the operation blocks 121-12N can be set in the same memory 120, and the memory 120 can be any form of non-volatile memory.

[0040] To further illustrate, each operation block 121~12N may include multiple unit circuits, which may be multiple memory cells. By performing programming operations on each memory cell, a weight value can be written into the memory cell. Each memory cell can provide a resistance value according to the weight value it has and according to the received input signal IN1~INN. Multiple memory cells in each operation block 121~12N can be integrated to provide an equivalent resistance value. The operation blocks 121~12N also receive a read voltage VR, and generate a current based on the read voltage VR and the provided equivalent resistance value. The operation blocks 121~12N cause the generated current to charge the capacitors C1~CN respectively, and thereby generate operation results V1~VN. Among them, the capacitors C1~CN are respectively coupled between the operation blocks 121~12N and the reference ground terminal VSS.

[0041] The reference weight block 130 is coupled to the output result generator 110. The reference weight block 130 provides a reference resistance value according to a plurality of reference weight values. The reference weight block 130 receives the read voltage VR, and generates a current according to the provided reference resistance value and the read voltage VR, and allows the generated current to charge the capacitor CR, thereby generating a reference signal Vref.

[0042] In detail, the reference weight block 130 may have the same circuit architecture as each of the operation blocks 121 to 12N. The reference weight block 130 may also have a unit circuit for a storage unit, each of which has a preset reference weight value and provides a unit resistance value according to the reference weight value. For example, the multiple storage units in the reference weight block 130 can be divided into multiple first storage units and multiple second storage units. The first storage unit may have the same first reference weight value and provide the same first unit resistance value. The multiple second storage units in the reference weight block 130 may have the same second reference weight value and provide the same second unit resistance value, and the first reference weight value is different from the second reference weight value, and the first unit resistance value is different from the second unit resistance value, for example, the first unit resistance value can be a high resistance value, and the second unit resistance value can be a low resistance value. By integrating the above-mentioned first storage unit and the second storage unit, the reference weight block 130 can generate a reference resistance value according to the above-mentioned multiple first unit resistance values ​​and second unit resistance values.

[0043] Incidentally, the number of the first storage unit and the second storage unit may be the same or different. For example, the number of the first storage unit may be 1 / 2, 1 / 4 or 1 / 8 of all the storage units in the reference weight block 130, without any limitation.

[0044] On the other hand, the output result generator 110 can generate a plurality of output operation results DO1-DON corresponding to the operation blocks 121-12N respectively according to the reference signal Vref and the operation results V1-VN. The output result generator 110 can generate the operation results V1-VN by comparing each of the operation results V1-VN with the reference signal Vref.

[0045] In detail, the reference signal Vref can be used to indicate the time point of capturing the operation results V1 -VN. The output result generator 110 captures the operation results V1 -VN according to the capture time information indicated by the reference signal Vref, and generates output operation results DO1 -DON respectively.

[0046] Please refer to Figure 2 , Figure 2 Schematic diagram of an implementation of a reference weight block in an arithmetic unit in a memory according to an embodiment of the present invention. The reference weight block 200 includes a plurality of unit circuit strings 211-21A. The unit circuit strings 211-21A are connected in parallel between a read voltage VR and one end of a capacitor C1, and the other end of the capacitor C1 is coupled to a reference ground terminal VSS.

[0047] The unit circuit string 211 has a plurality of unit circuits CU11~CU1M connected in series with each other; the unit circuit string 212 has a plurality of unit circuits CU21~CU2M connected in series with each other; ...; the unit circuit string 21A has a plurality of unit circuits CUA1~CUAM connected in series with each other. Each unit circuit CU11~CUAM has a reference weight value and can provide a unit resistance value according to the reference weight value. In this embodiment, the unit circuits CU11~CUAM can respectively receive input signals IN11~INAM. In this way, based on the read voltage VR, each unit circuit string 211~21A can respectively provide currents IR1~IRA to the capacitor C1 for charging, and thereby generate a reference signal Vref.

[0048] It is worth mentioning that each of the unit circuits CU11-CUAM can be a flash memory cell, such as Figure 3A Schematic diagram of a unit circuit of an embodiment of the present invention. Figure 3A The unit circuit CUX in can be Figure 2Any one of the unit circuits CU11~CUAM. Among them, the unit circuit CUX is a flash memory cell MC, and can receive an input signal through the word line WL. When setting the reference weight value of the unit circuit CUX, a programming action can be performed on the flash memory cell MC, and the threshold voltage of the flash memory cell MC can be adjusted. According to the reference weight value, the flash memory cell MC can provide a unit resistance value Rs. In this embodiment, the number of unit circuits in the reference weight block is the same as the number of weight values ​​in each of the operation blocks 121~12N.

[0049] Please refer again Figure 2 The unit circuit strings 211 ˜ 21A may have a plurality of resistance values ​​respectively, and may generate a plurality of currents IR1 ˜IRA respectively according to the read voltage VR.

[0050] Please refer to the following Figure 3B , Figure 3B : is a relationship diagram between the size of the arithmetic unit in the memory and the delay time of the corresponding arithmetic result generated in the embodiment of the present invention. Figure 3B The vertical axis is the delay time, and the horizontal axis is the size of the operation result of the operation block. By performing simulations based on different sizes of the operation results, the corresponding relationship between the delay time of the effective operation result corresponding to the different sizes of the operation results can be obtained. Based on the above corresponding relationship, a distribution area 310 with a linear trend can be obtained.

[0051] In this embodiment, when the size of the operation result of the operation block in the in-memory operator is M1 (between 400 and 500), the expected delay time Dt1 can be calculated through the distribution area 310. According to the delay time Dt1, the reference resistance value provided by the reference weight block can be set, and the reference weight value can be set according to the calculated reference resistance value.

[0052] In this way, according to the reference weight value, the reference signal generated by the reference weight block can be used as a basis for extracting the calculation result at an effective time.

[0053] Please refer to Figure 4 , Figure 4 Schematic diagram of an in-memory operator according to another embodiment of the present invention. The in-memory operator 400 includes an output result generator 410, a plurality of operation blocks 421-42N, and a reference weight block 430. The operation blocks 421-42N are respectively coupled to capacitors C1-CN, and the reference weight block 430 is coupled to capacitor CR. The operation blocks 421-42N respectively generate operation results V1-VN, and the reference weight block 430 is used to generate a reference signal Vref.

[0054] The reference weight block 430 includes sensing amplifiers SA1-SAN, SAR, and data capturers 411-41N. The sensing amplifiers SA1-SAN receive the operation results V1-VN respectively. The sensing amplifiers SA1-SAN also receive a sensing reference signal VL together, and sense the operation results V1-VN respectively according to the sensing reference signal VL to generate a plurality of sensing results SR1-SRN respectively. The sensing amplifier SAR receives the reference signal Vref and the sensing reference signal VL, and senses the reference signal Vref according to the sensing reference signal VL to generate the capture time information GTI.

[0055] The data capturers 411-41N are respectively coupled to the sensing amplifiers SA1-SAN and the sensing amplifier SAR. The data capturers 411-41N respectively receive the sensing results SR1-SRN and receive the capturing time information GTI together. The data capturers 411-41N capture the sensing results SR1-SRN according to the capturing time information GTI to generate output results DO1-DON respectively. The data capturers 411-41N can perform the data capturing operation of the sensing results SR1-SRN at an appropriate time point according to the capturing time information GTI.

[0056] Incidentally, the sensing amplifiers SA1-SAN, SAR in this embodiment can be implemented by using sensing amplifier circuits known to those skilled in the art without any particular limitation. The data capturers 411-41N are circuit elements that can perform data capture operations based on the capture time information GTI as a trigger point, such as D-type flip-flops.

[0057] It is worth noting that, in the reference weight block 430, the more unit circuits providing high resistance values, the longer the time delay of the provided acquisition time information GTI can be. Therefore, by adjusting the number of unit circuits providing high resistance values ​​in the reference weight block 430, the acquisition time information GTI can be changed.

[0058] Please refer to Figure 5 , Figure 5 Schematic diagram of an in-memory operator according to another embodiment of the present invention. The in-memory operator 500 includes an output result generator 510, a plurality of operation blocks 521-52N, and a reference weight block 530. The operation blocks 521-52N are respectively coupled to capacitors C1-CN, and the reference weight block 530 is coupled to capacitor CR. The operation blocks 521-52N respectively generate operation results V1-VN, and the reference weight block 530 is used to generate a reference signal Vref.

[0059] and Figure 4In different embodiments, the reference weight block 530 includes sense amplifiers SA1-SAN and data capturers 511-51N. The sense amplifiers SA1-SAN receive the operation results V1-VN respectively and receive the reference signal Vref together. The sense amplifiers SA1-SAN sense the operation results V1-VN respectively according to the reference signal Vref to generate a plurality of sense results SR1-SRN respectively.

[0060] The data capturers 511-51N are respectively coupled to the sense amplifiers SA1-SAN. The data capturers 511-51N respectively receive the sensing results SR1-SRN and receive the capture time information GTI together. In this embodiment, the capture time information GTI is a preset signal and can be input from the outside. The data capturers 511-51N capture the sensing results SR1-SRN according to the capture time information GTI to generate output results DO1-DON respectively.

[0061] Please refer to Figure 6 , Figure 6 Schematic diagram of an in-memory operator according to another embodiment of the present invention. The in-memory operator 600 includes an output result generator 610, a plurality of operation blocks 621-62N, and reference weight blocks 631 and 632. The operation blocks 621-62N are respectively coupled to capacitors C1-CN, and the reference weight blocks 631 and 632 are respectively coupled to capacitors CR1 and CR2. The operation blocks 621-62N generate operation results V1-VN, respectively, and the reference weight blocks 631 and 632 are respectively used to generate reference signals Vref1 and Vref2.

[0062] The output result generator 610 includes sensing amplifiers SA1-SAN, SAR1, SAR2, data capturers 611-61N and a multiplexer MUX. The sensing amplifiers SA1-SAN receive the operation results V1-VN respectively. The sensing amplifiers SA1-SAN also receive a sensing reference signal VL together, and sense the operation results V1-VN respectively according to the sensing reference signal VL to generate a plurality of sensing results SR1-SRN respectively. The sensing amplifiers SAR1 and SAR2 receive reference signals Vref1 and Vref2 respectively, and also receive the sensing reference signal VL together. The sensing amplifiers SAR1 and SAR2 sense the reference signals Vref1 and Vref2 according to the sensing reference signal VL to generate the capture time information GTI1 and GTI2 respectively.

[0063] The multiplexer MUX is coupled between the sensing amplifiers SAR1, SAR2 and the data capturers 611-61N. The multiplexer MUX can select one of the capture time information GTI1, GTI2 according to the selection signal to generate the capture time information GTI, and output the capture time information GTI to the data capturers 611-61N. The data capturers 611-61N are also coupled to the sensing amplifiers SA1-SAN respectively. The data capturers 611-61N receive the sensing results SR1-SRN respectively, and receive the capture time information GTI together. The data capturers 611-61N capture the sensing results SR1-SRN according to the capture time information GTI to generate the output results DO1-DON respectively.

[0064] In this embodiment, the reference signals Vref1 and Vref2 provided by the reference weight blocks 631 and 632 may correspond to different time delays. Therefore, the sense amplifiers SAR1 and SAR2 generate the acquisition time information GTI1 and GTI2, respectively, corresponding to different data acquisition times. Thus, in this embodiment, by sequentially selecting the acquisition time information GTI1 or GTI2 to generate the acquisition time information GTI, the data capturers 611 to 61N may perform multi-stage data acquisition operations at different data acquisition time points.

[0065] It is worth mentioning that in other embodiments of the present invention, the number of reference weight blocks may be greater than two. Designers may adjust the number of reference weight blocks according to actual needs without fixed restrictions.

[0066] Please refer to Figure 7 , Figure 7 Schematic diagram of an implementation of a reference weight block according to an embodiment of the present invention. Reference weight block 700 includes a plurality of unit circuit strings 711 to 71A. Unit circuit string 711 includes a plurality of unit circuits CU11 to CU1M connected in series with each other; unit circuit string 712 includes a plurality of unit circuits CU21 to CU2M connected in series with each other; ...; unit circuit string 71A includes a plurality of unit circuits CUA1 to CUAM connected in series with each other.

[0067] In this embodiment, each unit circuit CU11-CUAM can provide a unit resistance value according to the reference weight value it has. Among the unit circuits CU11-CUAM, part of the first unit circuit provides a relatively high high resistance value R1, and the other part of the second unit circuit provides a relatively low low resistance value R2. By adjusting the proportion of the first unit circuit in all the unit circuits CU11-CUAM, the reference signal Vref provided by the reference weight block 700 can be adjusted. The above proportion can be any value between 1 and 0.

[0068] When multiple reference weight blocks are set in the memory operator, the ratio of the unit circuits providing relatively high resistance value R1 in the reference weight blocks may be different. For example, if the number of reference weight blocks is 4, the above ratios may be 1 / 4, 2 / 4, 3 / 4 and 4 / 4 respectively.

[0069] Incidentally, the unit circuits CU11 ˜CUAM all receive the same input signal IN. The input signal IN may have a fixed and relatively low voltage value.

[0070] In summary, the in-memory operator of the present invention provides a reference signal according to a plurality of reference weight values ​​by setting a reference weight block, and sets the data acquisition time point of the operation result according to the reference signal. In this way, the in-memory operator of the present invention can set a better data acquisition time point corresponding to operation blocks of different sizes, thereby improving the working efficiency of the in-memory operator.

Claims

1. An in-memory operator, comprising: A plurality of operation blocks respectively receive a plurality of input signals and generate a plurality of operation results, each of the operation blocks has a plurality of weight values, and each of the operation blocks generates each of the operation results according to the corresponding input signals and the corresponding weight values; a first reference weight block, providing a first reference resistance value according to a plurality of reference weight values, and generating a first reference signal according to the first reference resistance value and a read voltage; as well as An output result generator is coupled to the operation blocks and the first reference weight block, and generates a plurality of output operation results according to the first reference signal and the operation results.

2. The in-memory operator according to claim 1, wherein the first reference weight block comprises: A plurality of unit circuit strings are connected in parallel with each other, each of the unit circuit strings has a plurality of unit circuits connected in series, and the unit circuits respectively provide a plurality of unit resistance values ​​according to the reference weight values. 3 . The in-memory operator according to claim 2 , wherein the number of the unit circuits is the same as the number of the weight values ​​of each of the operation blocks.

4. The in-memory operator according to claim 2, wherein a plurality of first unit circuits of the unit circuits provide a same first unit resistance value, a plurality of second unit circuits of the unit circuits provide a same second unit resistance value, and the first unit resistance value is different from the second unit resistance value. 5 . The in-memory operator according to claim 4 , wherein the number of the first unit circuits is the same as or different from the number of the second unit circuits.

6. The in-memory operator according to claim 1, wherein the output result generator comprises: A plurality of first sensing amplifiers are respectively coupled to the operation blocks, and respectively sense the operation results according to a sensing reference signal to generate a plurality of sensing results; a second sensing amplifier, coupled to the first reference weight block, sensing the first reference signal according to the sensing reference signal to generate a capture time information; as well as A plurality of data capturers are coupled to the first sensing amplifiers and the second sensing amplifier, and capture the sensing results according to the capture time information to respectively generate a plurality of output results.

7. The in-memory operator according to claim 1, wherein the output result generator comprises: A plurality of first sensing amplifiers are respectively coupled to the operation blocks, and respectively sense the operation results according to the first reference signal to generate a plurality of sensing results; as well as A plurality of data capturers are coupled to the first sensing amplifiers and capture the sensing results according to a preset capture time information to respectively generate a plurality of output results.

8. The in-memory operator according to claim 1, further comprising: At least one second reference weight block provides at least one second reference resistance value according to at least one second reference weight value, and generates at least one second reference signal according to the at least one second reference resistance value and the read voltage.

9. The in-memory operator according to claim 8, wherein the output generator comprises: A plurality of first sensing amplifiers are respectively coupled to the operation blocks, and respectively sense the operation results according to a sensing reference signal to generate a plurality of sensing results; A plurality of second sensing amplifiers are respectively coupled to the first reference weight block and the at least one second reference weight block, and sense the first reference signal and the at least one second reference signal according to the sensing reference signal to respectively generate a plurality of acquisition time information; a multiplexer coupled to the second sensing amplifiers and selecting one of the captured time information for output; as well as A plurality of data capturers are coupled to the first sensing amplifiers and the multiplexer, and capture the sensing results according to the output of the multiplexer to respectively generate a plurality of output results.

10. The in-memory operator according to claim 2, wherein the first reference weight block further comprises: A capacitor has a first end coupled to the unit circuit strings, a second end of the capacitor coupled to a reference ground end, wherein the first end of the capacitor provides the first reference signal. 11 . The in-memory operator according to claim 10 , wherein each of the operation blocks provides a current signal to the capacitor for charging according to the corresponding input signals and the corresponding weight values, and generates each of the operation results. 12 . The in-memory operator as claimed in claim 1 , wherein the reference weight value is determined according to the number of the operation blocks and the weight values.

13. The in-memory operator according to claim 1, wherein each of the operation blocks comprises: A plurality of unit circuit strings are connected in parallel with each other, each of the unit circuit strings has a plurality of unit circuits connected in series, each of the unit circuits has a respective weight value, and provides a resistance value according to each weight value.

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