Memory and signal processing method

Abstract

The invention provides a memory and a signal processing method, the memory comprises a control circuit, the control circuit comprises N logic transmission chains, each logic transmission chain comprises a plurality of logic devices, a first input end of each logic device receives one first signal, and a second input end of each logic device receives one second signal; the second input ends of the non-first logic devices are connected with the output end of the previous logic device, and the last logic device outputs a second signal.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a memory and a signal processing method. Background Art

[0002] In memory, it is often necessary to encode multiple signals and transmit the encoded signals to subsequent working modules. Taking dynamic random access memory (DRAM) as an example, it includes multiple storage blocks (Bank), and the storage rows (or word lines) in each storage block are divided into multiple storage groups (Blocks) for management. Each storage group determines whether it is activated based on the received address signal (main address signal or redundant address signal), and generates an activation indication signal indicating whether it is activated. The activation indication signals of all storage groups need to be encoded and transmitted to the subsequent column redundancy module, hammer refresh module, etc., so that the subsequent modules know which storage group is activated. However, the signal encoding and transmission process occupies too much circuit area, which is not conducive to the improvement of memory performance. Summary of the invention

[0003] The present disclosure provides a memory and a signal processing method.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a memory, wherein the memory comprises a control circuit, and the control circuit is used to encode M first signals into N second signals, and transmit the N second signals, M>N; the control circuit comprises N logic transmission chains, each of which receives a portion of the first signals and outputs one second signal; wherein each of the logic transmission chains comprises a plurality of logic devices, a first input end of each of the logic devices receives one of the first signals, a second input end of the logic device at the first position receives a preset level signal, second input ends of the logic devices other than the first position are connected to the output end of the previous logic device, and an output end of the logic device at the last position outputs the second signal.

[0006] In some embodiments, the memory includes multiple storage blocks, each storage block corresponds to one control circuit; the storage blocks are divided into M storage groups, and the control circuit also includes M address decoders; the i-th address decoder is configured to receive a main address signal and a redundant address signal, decode the main address signal and the redundant address signal, generate and output the i-th first signal; wherein the i-th first signal indicates whether the i-th storage group is selected to perform an activation operation; i≤M.

[0007] In some embodiments, the i-th address decoder is configured to decode the main address signal to generate the i-th first signal when the redundant address signal does not carry valid information; or, when the redundant address signal carries valid information, mask the main address signal and decode the redundant address signal to generate the i-th first signal.

[0008] In some embodiments, the control circuit further includes: a hammering refresh module connected to the N logic transmission chains, configured to receive the N second signals, decode the N second signals to know the activated memory banks; a column redundancy module connected to the N logic transmission chains, configured to receive the N second signals, decode the N second signals to know the activated memory banks.

[0009] In some embodiments, 2N - 1 < M ≤ 2N; the M first signals are divided into a first-level signal group_1 and a first-level signal group_2, and each of the first-level signal groups is further divided into a second-level signal group_1 and a second-level signal group_2... until each (N - 1)-level signal group is divided into an N-level signal group_1 and an N-level signal group_2; the first logic transmission chain is configured to receive the first signals in the first-level signal group_1, perform a logic operation on the received first signals, and output the first second signal; the second logic transmission chain is configured to receive the first signals in all the second-level signal group_1, perform a logic operation on the received first signals, and output the first second signal;... the N-th logic transmission chain is configured to receive the first signals in all the N-level signal group_1, perform a logic operation on the received first signals, and output the N-th second signal.

[0010] In some embodiments, the type of the logic device is one of the following: AND gate, OR gate, NAND gate, NOR gate, XNOR gate, XOR gate; when all the logic devices are OR gates, the preset level signal is a low-level signal;

[0011] When all the logic devices are AND gates, the preset level signal is a high-level signal.

[0012] In some embodiments, when M = 2N, each logic transmission chain includes M / 2 logic devices.

[0013] In some embodiments, when M=64 and N=6, each of the logical transmission chains includes 32 OR gates; the number of the first-level signal group_1 is 1, and the first-level signal group_1 includes the first signals numbered 63 to 32; the number of the second-level signal group_1 is 2, and the second-level signal group_1 includes the first signals numbered {63 to 48}U{31 to 16}; the number of the third-level signal group_1 is 4, and the third-level signal group_1 includes the first signals numbered {55 to 48}U{39 to 32}U{23 to 16}U{7 to 0}; the number of the fourth-level signal group_1 is 8, and the fourth-level signal group_1 includes the first signals numbered {63 to 60}U{55 to 52}U{47 to 44}}U{39-36}U{31-28}U{23-20}U{15-12}U{7-4}; the number of five-level signal groups_1 is 16, and the five-level signal group_1 includes the first signals numbered {63-62}U{59-58}U{55-54}U{51-50}U{47-46}U{43-42}U{39-38}U{35-34}U{31-30}U{27-26}U{23-22}U{19-18}U{15-14}U{11-10}U{7-6}U{3-2}; the number of six-level signal groups_1 is 32, and the six-level signal group_1 includes the first signals numbered as odd numbers.

[0014] In some embodiments, the control circuit further includes M sensitive amplifier control modules and M word line control modules, the M sensitive amplifier control modules correspond one-to-one to the M address decoders, and the M word line control modules correspond one-to-one to the M address decoders; the sensitive amplifier control module is connected to the corresponding address decoder and configured to receive the corresponding first signal; when the first signal indicates that the corresponding storage group is selected to perform an activation operation, an amplifier control timing signal is generated and output according to a preset timing rule; the word line control module is connected to the corresponding address decoder and configured to receive the corresponding first signal; when the first signal indicates that the corresponding storage group is selected to perform an activation operation, a word line control timing signal is generated and output according to a preset timing rule; wherein the amplifier control timing signal is used to control the sensitive amplifier in the memory, and the word line control timing signal is used to activate the selected storage group.

[0015] In a second aspect, an embodiment of the present disclosure provides a signal processing method, which is applied to a storage block in a memory, and each of the storage blocks is divided into M storage groups, and the method includes:

[0016] Receive a main address signal and a redundant address signal, decode the main address signal and the redundant address signal, and generate M first signals; wherein the i-th first signal indicates whether the i-th storage group is selected to perform an activation operation; use N logic transmission chains to encode the M first signals into N second signals, and transmit the N second signals; wherein the logic transmission chain includes a plurality of logic devices, the first input end of each of the logic devices receives one of the first signals, the second input end of the logic device at the first position receives a preset level signal, the second input ends of the logic devices other than the first position are connected to the output end of the previous logic device, and the input end of the logic device at the last position outputs the second signal.

[0017] In some embodiments, decoding the primary address signal and the redundant address signal to generate M first signals includes:

[0018] When the redundant address signal does not carry valid information, the main address signal is decoded to generate M first signals; or, when the redundant address signal carries valid information, the main address signal is shielded and the redundant address signal is decoded to generate M first signals.

[0019] In some embodiments, the method further includes: sending N second signals to a hammer refresh module and a column redundancy module, so that the hammer refresh module and the column redundancy module are informed of the activated storage group.

[0020] In some embodiments, 2 N-1 <M≤2 N The method of encoding the M first signals into N second signals by using N logical transmission chains comprises:

[0021] Divide the M first signals into a first-level signal group_1 and a first-level signal group_2, divide each of the first-level signal groups into a second-level signal group_1 and a second-level signal group_2...until each (N-1)-level signal group is divided into an N-level signal group_1 and an N-level signal group_2; use the first logic transmission chain to perform logic operations and transmission processing on the first signal in the first-level signal group_1, and output the first second signal; use the second logic transmission chain to perform logic operations and transmission processing on all the first signals in the second-level signal group_1, and output the second second signal... Use the Nth logic transmission chain to perform logic operations and transmission processing on all the first signals in the N-level signal group_1, and output the Nth second signal.

[0022] In some embodiments, the type of the logic device is one of the following: AND gate, OR gate, NAND gate, NOR gate, XNOR gate, XOR gate; when all logic devices are OR gates, the preset level signal is a low level signal; when all logic devices are AND gates, the preset level signal is a high level signal.

[0023] In some embodiments, after generating the M first signals, the method further includes:

[0024] Based on the M first signals, an amplifier control timing signal and a word line control timing signal are generated according to a preset timing rule; wherein the amplifier control timing signal is used to control the sensitive amplifier in the memory, and the word line control timing signal is used to activate the selected storage group.

[0025] The embodiments of the present disclosure provide a memory and a signal processing method, which can simultaneously realize signal encoding and transmission by using a logical transmission chain, save circuit area, and improve memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram of the structure of a storage block provided in an embodiment of the present disclosure;

[0028] Figure 3 A schematic diagram of a specific structure of a control circuit provided in an embodiment of the present disclosure;

[0029] Figure 4 A specific structural diagram of another control circuit provided in an embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of a specific structure of a logical transmission chain provided by an embodiment of the present disclosure;

[0031] Figure 6 A schematic diagram of a partial structure of a memory provided by an embodiment of the present disclosure;

[0032] Figure 7 A flowchart of a signal processing method provided by an embodiment of the present disclosure;

[0033] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

[0035] The following are explanations of professional terms involved in the embodiments of the present disclosure and the corresponding relationships of some terms:

[0036] Synchronous Dynamic Random Access Memory (SDRAM);

[0037] Double Data Rate SDRAM (DDR);

[0038] Low Power DDR (LPDDR).

[0039] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0040] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the structure of a memory 10 provided by an embodiment of the present disclosure. Figure 1 As shown, the memory 10 includes a control circuit 20, and the control circuit 20 is used to encode M first signals into N second signals and transmit the N second signals, M>N; the control circuit 20 includes N logical transmission chains 21 (in Figure 1 , each logic transmission chain 21 receives a portion of the first signal and outputs a second signal; wherein each logic transmission chain 21 includes a plurality of logic devices 30 ( Figure 1Only one logic device is taken as an example to illustrate the numbering), the first input terminal of each logic device 30 receives one of the first signals, the second input terminal of the logic device 30 located in the first position receives the preset level signal, the second input terminals of the non-first logic devices 30 are connected to the output terminals of the previous logic device 30, and the output terminal of the last logic device 30 outputs the second signal.

[0041] It should be noted that the memory 10 may be various types of dynamic memory 10, such as DRAM, SDRAM, DDR, LPDDR, etc. The first signal may be a signal of various types, meanings, and functions. In other words, any application scenario involving encoding and transmission in the memory 10 may adopt this embodiment.

[0042] In the embodiment of the present disclosure, for each logic transmission chain 21, different first signals enter different logic devices 30, and the subsequent logic device 30 operates on the operation result of the previous logic device 30 and the received first signal, so that the operation result of the logic device 30 carries the information of the first signal and is transmitted backward in sequence, and finally generates a second signal, so that each logic transmission chain 21 has both transmission and operation functions.

[0043] In this way, the encoding and transmission processes of the first signal are combined, and there is no need to set up independent encoding and transmission modules, thus saving circuit area and reducing chip costs.

[0044] For better understanding, the embodiments of the present disclosure are further described below by taking an address decoding scenario as an example.

[0045] It should be understood that the memory 10 also includes multiple storage blocks Bank, and the working principle of each storage block Bank is similar. The following only takes one storage block Bank as an example for explanation.

[0046] like Figure 2 As shown, each storage block Bank is divided into M storage groups Block. During the operation of the memory 10, each storage group Block determines whether it needs to perform an activation operation based on the received address signal, thereby generating an activation indication signal, that is, the M storage groups Block generate a total of M activation indication signals BLK[M-1,0]. In order to save transmission channels, the M activation indication signals BLK[M-1,0] can be encoded into N selection address signals RHRRA[N-1,0], so that the N selection address signals RHRRA[N-1,0] are transmitted backward to inform the relevant working modules which storage group Block is activated. In other words, for this scenario, the first signal specifically refers to the activation indication signal BLK[M-1,0], and the second signal specifically refers to the selection address signal RHRRA[N-1,0].

[0047] Based on this, each storage block Bank is provided with a corresponding control circuit 20, see Figure 3 Each control circuit 20 also includes M address decoders 22 (in Figure 3 In the example, the address decoder 22 may be respectively referred to as address decoder 0, address decoder 1, ..., address decoder M-1), each address decoder 22 corresponds to one storage group, for example, address decoder 0 corresponds to storage group 0, address decoder 1 corresponds to storage group 1, ...

[0048] Furthermore, the i-th address decoder 22 is configured to receive the main address signal and the redundant address signal, decode the main address signal and the redundant address signal, generate and output the i-th first signal BLK[i-1]; wherein the i-th first signal BLK[i-1] indicates whether the i-th storage group Block is selected to perform an activation operation; i≤M.

[0049] It should be noted that in addition to the normally planned storage rows (or word lines), some redundant storage rows are additionally set in the memory. When a storage row is invalid or damaged, the address of the storage row is mapped to a redundant storage row, so that the invalid or damaged storage row is replaced with the redundant storage row. Therefore, the address decoder 22 will receive the main address signal and the redundant address signal at the same time. If the redundant address signal is invalid, it means that the storage row corresponding to the main address signal has not been replaced redundantly. At this time, it will be addressed according to the main address signal for subsequent operations; if the redundant address signal is valid, it means that the storage row corresponding to the main address signal has been replaced redundantly. At this time, it will be addressed according to the redundant address signal for subsequent operations. In short, each storage block Bank divides the internal storage rows into multiple storage groups Block; generally, once the design is completed, the address specifically set by the user will be activated on the specific storage group Block. In the case of redundant addresses, the address specifically set by the user may be transferred to another storage group Block containing redundant addresses. Therefore, the address decoder 22 needs to decode according to the main address signal and the redundant address signal. After determining which storage group Block to activate, it needs to pass the activation information to other functional units (such as column redundancy module, hammer refresh module...) so that subsequent functional units can operate.

[0050] That is to say, each storage group Block corresponds to an address decoder 22 (or called Row block Decoder), and the i-th address decoder 22 generates the i-th first signal BLK(i-1) according to the received main address signal and redundant address signal. At this time, the first signal BLK(i-1) indicates whether the i-th storage group Block is selected to perform the activation operation. In this way, for the same storage block Bank, M first signals BLK[M-1,0] are output through M address decoders 22.

[0051] That is to say, the i-th address decoder 22 is configured to decode the main address signal to generate the i-th first signal BLK[i-1] when the redundant address signal does not carry valid information; or, to shield the main address signal and decode the redundant address signal to generate the i-th first signal BLK[i-1] when the redundant address signal carries valid information.

[0052] It should be noted that the address decoder 22 can decode the address (indicating the operation object of this time) sent by the memory controller and provide corresponding timing signals, so as to activate the sub wordline driver (SWD), sub wordline control (SWC), sensitive amplifier (SA) and other modules of a certain area, and finally activate the corresponding storage group Block.

[0053] Furthermore, if Figure 4 As shown, the control circuit 20 also includes M sense amplifier control modules 23 (SenseAmplifier Control) and M word-liner control modules 24 (Word-liner Control), the M sense amplifier control modules 23 correspond to the M address decoders 22 one by one, and the M word-liner control modules 24 correspond to the M address decoders 22 one by one; the sense amplifier control module 23 is connected to the corresponding address decoder 22 and configured to receive the corresponding first signal; when the first signal indicates that the corresponding storage group is selected to perform the activation operation, the amplifier control timing signal is generated and output according to the preset timing rule; the word-liner control module 24 is connected to the corresponding address decoder 22 and configured to receive the corresponding first signal, and when the first signal indicates that the corresponding storage group is selected to perform the activation operation, the word-liner control timing signal is generated and output according to the preset timing rule; wherein, the amplifier control timing signal is used to control the sense amplifier in the memory 10, and the word-liner control timing signal is used to activate the selected storage group Block.

[0054] Specifically, during the activation of the storage group, the corresponding word line needs to be turned on, and the storage unit controlled by the word line shares charge with the respective bit line, and then the corresponding sensitive amplifier amplifies and writes back the signal on the bit line. Therefore, the i-th first signal BLK[i-1] needs to be transmitted to the i-th sensitive amplifier control module 23 and the word line control module 24. If the i-th first signal BLK[i-1] indicates that the corresponding storage group is activated, then the i-th sensitive amplifier control module 23 outputs an amplifier control timing signal of a preset waveform, thereby controlling the corresponding sensitive amplifier to work; at the same time, the i-th word line control timing module 24 outputs a word line control timing signal of a preset waveform, and the amplifier control timing signal of the preset waveform and the word line control timing signal of the preset waveform jointly realize the activation of the specified storage group; if the i-th first signal BLK[i-1] indicates that the corresponding storage group is not activated, the i-th sensitive amplifier control module 23 outputs an invalid amplifier control timing signal, and the i-th word line control timing module 24 outputs an invalid word line control timing signal.

[0055] In particular, for M first signals, since only one storage group is selected for operation each time, at most one first signal is in a valid state (indicating that the corresponding storage group is selected), and the other first signals are in an invalid state. Based on this, the M first signals can be further encoded into N second signals, and the second signal only needs to indicate which first signal is in a valid state or all first signals are invalid, thereby saving signal transmission channels.

[0056] In some embodiments, 2 N-1 <M≤2 N The M first signals are divided into a primary signal group_1 and a primary signal group_2;

[0057] Each primary signal group (primary signal group_1 and primary signal group_2 both belong to the primary signal group) is divided into secondary signal group_1 and secondary signal group_2, that is, there are 2 secondary signal groups_1 and 2 secondary signal groups_2;

[0058] Each secondary signal group (secondary signal group_1 and secondary signal group_2 both belong to the secondary signal group) is divided into tertiary signal group_1 and tertiary signal group_2, that is, there are 4 tertiary signal groups_1 and 4 tertiary signal groups_2;

[0059] Each three-level signal group (three-level signal group_1 and three-level signal group_2 both belong to the three-level signal group) is divided into four-level signal group_1 and four-level signal group_2, that is, four-level signal group_1 has 8 and four-level signal group_2 has 8;

[0060] Each four-level signal group (four-level signal group_1 and four-level signal group_2 both belong to the four-level signal group) is divided into five-level signal group_1 and five-level signal group_2, that is, there are 16 five-level signal group_1 and 16 five-level signal group_2;

[0061] ...until each (N-1)-level signal group is divided into N-level signal group_1 and N-level signal group_2; the first logic transmission chain 21 is configured to receive the first signal in the first-level signal group_1, perform a logic operation on the received first signal, and output the first second signal; the second logic transmission chain 21 is configured to receive the first signal in all the second-level signal groups_1, perform a logic operation on the received first signal, and output the first second signal; ...the Nth logic transmission chain 21 is configured to receive the first signal in all the N-level signal groups_1, perform a logic operation on the received first signal, and output the Nth second signal.

[0062] It should be noted that all logic devices 30 are of the same type. Exemplarily, each logic device 30 may include one or more of the following devices: AND gate, NAND gate, NOT gate, NOR gate, OR gate, XOR gate, XNOR gate, depending on the encoding rule of the first signal. Exemplarily, if the valid state of the first signal is a high level (1), then all logic devices 30 may use an OR gate or a NOR gate; if the valid state of the first signal is a low level (0), then all logic devices 30 may use an AND gate or a NAND gate.

[0063] Furthermore, when all logic devices 30 are OR gates, the preset level signal is a low level signal; when all logic devices 30 are AND gates, the preset level signal is a high level signal.

[0064] In some embodiments, when M=2 N In this case, each logic transmission chain 21 includes M / 2 logic devices 30.

[0065] See also Figure 5 , taking the effective state of the first signal as a high level as an example, assuming that M=64, N=6; at this time, the first signal [M-1:0] is specifically represented by BLK0~BLK63, and the second signal [N-1:0] is specifically represented by RHRRA

[10] ~

[15] .

[0066] At this time, each logical transmission chain 21 includes 32 OR gates; the number of the first-level signal group_1 is 1, and the first-level signal group_1 includes the first signals numbered 63 to 32 (i.e., BLK63 to BLK32, which will be used as an example later); the number of the second-level signal group_1 is 2, and the second-level signal group_1 includes the first signals numbered {63 to 48}U{31 to 16}; the number of the third-level signal group_1 is 4, and the third-level signal group_1 includes the first signals numbered {55 to 48}U{39 to 32}U{23 to 16}U{7 to 0}; the number of the fourth-level signal group_1 is 8, and the fourth-level signal group_1 includes the first signals numbered {63 to 60}U{55 to 52}U{47 to 44}U {39~36}U{31~28}U{23~20}U{15-12}U{7~4}; the number of five-level signal groups_1 is 16, and the five-level signal group_1 includes the first signals numbered {63~62}U{59~58}U{55~54}U{51~50}U{47~46}U{43~42}U{39~38}U{35~34}U{31~30}U{27~26}U{23~22}U{19~18}U{15-14}U{11~10}U{7~6}U{3~2}; the number of six-level signal groups_1 is 32, and the six-level signal group_1 includes the first signals numbered with odd numbers.

[0067] In this way, assuming that RHRRA[15:10]=111111, it means that the activated storage block is located in the first-level signal group_1, and in one of the second-level signal groups_1, and in one of the third-level signal groups_1... and in one of the sixth-level signal groups_1, so the activated storage block = first-level signal group_1∩second-level signal group_1∩third-level signal group_1∩fourth-level signal group_1∩fifth-level signal group_1∩sixth-level signal group_1, that is, the storage group numbered 55 is activated.

[0068] In particular, such as Figure 5As shown, the BLK8 signal is not actually connected to any logical transmission chain, that is, there may be a first signal that is not connected to the logical transmission chain. In other words, in theory, when RHRRA[15:10]=000000, it can only be determined that BLK0~7 and BLK9~63 are all 0, that is, the storage group blocks 0~7 and 9~63 are not activated, but it is not known whether the 8th storage group block is activated. In the embodiment of the present disclosure, when RHRRA[15:10]=000000, it can be considered that the 8th storage group block is activated, and this is allowed for the following reasons: (1) The subsequent related modules will actually perform specific operations in combination with other information, such as determining the storage group block that is finally activated; (2) Even if the 8th storage group block is not activated, and the above mechanism determines that the 8th storage group block is activated, this will only bring some redundant operations, such as the row hammer module recording redundant activation addresses, which will not cause harm to the memory.

[0069] In another example, the number of primary signal groups 1 is 1, and the primary signal group 1 includes first signals numbered 31 to 0; the number of secondary signal groups 1 is 2, and the secondary signal group 1 includes first signals numbered {47 to 32}U{31 to 16}; the number of tertiary signal groups 1 is 4, and the tertiary signal group 1 includes first signals numbered {55 to 48}U{47 to 49}U{23 to 16}U{15 to 8}; the number of quadruple signal groups 1 is 8, and the quadruple signal group 1 includes first signals numbered {59 to 56}U{55 to 52}U{43 to 40}U{39 to 36}U{27 to 24}U {23~20}U{11-8}U{7~4}; the number of five-level signal groups_1 is 16, and the five-level signal group_1 includes the first signals numbered {63~62}U{59~58}U{55~54}U{51~50}U{47~46}U{43~42}U{39~38}U{35~34}U{31~30}U{27~26}U{23~22}U{19~18}U{15-14}U{11~10}U{7~6}U{3~2}; the number of six-level signal groups_1 is 32, and the six-level signal group_1 includes the first signals numbered with odd numbers.

[0070] In this way, assuming that RHRRA[15:10]=111111, it means that the activated storage block is located in the first-level signal group_1, and in one of the second-level signal groups_1, and in one of the third-level signal groups_1... and in one of the sixth-level signal groups_1, so the activated storage block = first-level signal group_1∩second-level signal group_1∩third-level signal group_1∩fourth-level signal group_1∩fifth-level signal group_1∩sixth-level signal group_1, that is, the storage group numbered 23 is activated.

[0071] In another example, taking the effective state of the first signal as a low level and the preset level signal as a high level signal as an example, assuming that M=64, N=6, each logic transmission chain 21 includes 32 AND gates; the number of the first-level signal group_1 is 1, and the first-level signal group_1 includes the first signals numbered 63 to 32; the second-level signal group_1 includes the first signals numbered {47 to 32}U{31 to 16}; the third-level signal group_1 includes the first signals numbered {63 to 56}U{39 to 32}U{31 to 24}U{7 to 0}; the fourth-level signal group_1 includes the first signals numbered {59 to 56}U{55 to 52} U{43~40}U{39~36}U{27~24}U{23~20}U{11-8}U{7~4}; the five-level signal group_1 includes the first signals numbered {61~60}U{59~58}U{53~52}U{51~50}U{45~44}U{43~42}U{37~36}U{35~34}U{29~28}U{27~26}U{22~20}U{19~18}U{13~12}U{11~10}U{5~4}U{3~2}; the six-level signal group_1 includes the first signals numbered as odd numbers.

[0072] In this way, assuming that RHRRA[15:10]=000000, it means that the activated storage block is located in the first-level signal group_1, and in one of the second-level signal groups_1, and in one of the third-level signal groups_1... and in one of the sixth-level signal groups_1, so the activated storage block = first-level signal group_1∩second-level signal group_1∩third-level signal group_1∩fourth-level signal group_1∩fifth-level signal group_1∩sixth-level signal group_1, that is, the storage group numbered 37 is activated.

[0073] It should be noted that a certain buffer unit may be provided in each logic transmission chain 21 , and the buffer unit may be composed of an even number of inverters.

[0074] In some embodiments, Figure 6 As shown, the control circuit 20 also includes:

[0075] A hammer refresh module 25 is connected to the N logic transmission chains 21 and is configured to receive the N second signals and decode the N second signals to obtain the activated storage group;

[0076] The column redundancy module 26 is connected to the N logic transmission chains 21 and is configured to receive the N second signals and decode the N second signals to obtain the activated storage group.

[0077] It should be noted that, for the memory 10, if a certain storage row is frequently activated in a short period of time, it may cause data errors in its physically adjacent rows, which is called row hammering. The hammer refresh module 26 is designed to deal with this problem. The hammer refresh module 25 can record the activation information of the storage row (which must include the activation information of the storage group). When it is detected that the number of activations of a certain storage row in a unit time exceeds a preset threshold, the adjacent rows of the storage row will be refreshed to avoid data errors.

[0078] It should also be noted that the column redundancy module 26 is used to manage the redundant columns (or redundant bit lines) in the memory 10. For specific operations, not all redundant columns need to work, which will increase power consumption. Therefore, the column redundancy module 26 also receives N second signals to control the corresponding redundant columns to work according to the activated storage group to reduce power consumption.

[0079] In summary, the embodiments of the present disclosure provide a memory that can simultaneously implement signal encoding and transmission using a logical transmission chain, thereby saving circuit area and improving memory performance.

[0080] In another embodiment of the present disclosure, see Figure 7 , which shows a signal processing method provided by an embodiment of the present disclosure, which is applied to the aforementioned memory 10. Specifically, the memory 10 includes a plurality of memory blocks Bank, and each memory block Bank is divided into M memory groups. The method includes:

[0081] S401: receiving a main address signal and a redundant address signal, decoding the main address signal and the redundant address signal, and generating M first signals.

[0082] It should be noted that the i-th first signal indicates whether the i-th storage group is selected to perform the activation operation.

[0083] S402: Encode M first signals into N second signals by using N logical transmission chains, and transmit the N second signals.

[0084] Please note that, see Figure 1 to Figure 6 The logic transmission chain includes multiple logic devices, the first input end of each logic device receives one of the first signals, the second input end of the logic device in the first position receives a preset level signal, the second input ends of the non-first logic devices are connected to the output end of the previous logic device, and the input end of the logic device in the last position outputs the second signal.

[0085] In some embodiments, decoding the primary address signal and the redundant address signal to generate M first signals includes:

[0086] When the redundant address signal does not carry valid information, the main address signal is decoded to generate M first signals; or, when the redundant address signal carries valid information, the main address signal is shielded and the redundant address signal is decoded to generate M first signals.

[0087] In some embodiments, the method further comprises:

[0088] N second signals are sent to the hammer refresh module and the column redundancy module, so that the hammer refresh module and the column redundancy module know the activated storage group.

[0089] In some embodiments, 2 N-1 <M≤2 N The method of encoding the M first signals into N second signals by using N logical transmission chains comprises:

[0090] Divide M first signals into a first-level signal group_1 and a first-level signal group_2, divide each first-level signal group into a second-level signal group_1 and a second-level signal group_2... until each (N-1)-level signal group is divided into an N-level signal group_1 and an N-level signal group_2; use the first logic transmission chain to perform logic operations and transmission processing on the first signal in the first-level signal group_1, and output the first second signal; use the second logic transmission chain to perform logic operations and transmission processing on the first signals in all the second-level signal groups_1, and output the second second signal... Use the Nth logic transmission chain to perform logic operations and transmission processing on the first signals in all the N-level signal groups_1, and output the Nth second signal.

[0091] In some embodiments, the type of logic device is one of the following: AND gate, OR gate, NAND gate, NOR gate, XNOR gate, XOR gate; when all logic devices are OR gates, the preset level signal is a low level signal; when all logic devices are AND gates, the preset level signal is a high level signal.

[0092] In some embodiments, after generating the M first signals, the method further includes:

[0093] Based on the M first signals, an amplifier control timing signal and a word line control timing signal are generated according to a preset timing rule; wherein the amplifier control timing signal is used to control a sensitive amplifier in the memory, and the word line control timing signal is used to activate a selected storage group.

[0094] In another embodiment of the present disclosure, see Figure 8 , which shows an electronic device 50 provided by an embodiment of the present disclosure, and the electronic device 50 at least includes the aforementioned memory 10.

[0095] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, It is characterized in that The memory includes a control circuit, and the control circuit is used to encode M first signals into N second signals and transmit the N second signals, M>N; The control circuit includes N logic transmission chains, each of which receives a portion of the first signal and outputs a second signal; wherein each of the logic transmission chains includes multiple logic devices, a first input end of each of the logic devices receives one of the first signals, a second input end of the logic device at the first position receives a preset level signal, second input ends of the logic devices other than the first position are connected to the output end of the previous logic device, and an output end of the logic device at the last position outputs the second signal.

2. The memory according to claim 1, It is characterized in that The memory includes a plurality of storage blocks, and each storage block is correspondingly provided with one control circuit; The storage block is divided into M storage groups, and the control circuit further includes M address decoders; The i-th address decoder is configured to receive a main address signal and a redundant address signal, decode the main address signal and the redundant address signal, generate and output the i-th first signal; wherein the i-th first signal indicates whether the i-th storage group is selected to perform an activation operation; i≤M.

3. The memory according to claim 2, It is characterized in that The i-th address decoder is configured to decode the main address signal to generate the i-th first signal when the redundant address signal does not carry valid information; or, when the redundant address signal carries valid information, shield the main address signal and decode the redundant address signal to generate the i-th first signal.

4. The memory according to claim 2, It is characterized in that The control circuit further comprises: A hammer refresh module, connected to the N logic transmission chains, configured to receive the N second signals and decode the N second signals to obtain the activated storage group; The column redundancy module is connected to the N logic transmission chains and is configured to receive the N second signals and decode the N second signals to obtain the activated storage group.

5. The memory according to any one of claims 1 to 4, It is characterized in that 2 N-1 <M≤2 N The M first signals are divided into a primary signal group _1 and a primary signal group _2, and each of the primary signal groups is divided into a secondary signal group _1 and a secondary signal group _2 ... until each (N-1) level signal group is divided into an N level signal group _1 and an N level signal group _2; The first logic transmission chain is configured to receive the first signal in the first-level signal group_1, perform a logic operation on the received first signal, and output the first second signal; The second logic transmission chain is configured to receive all the first signals in the secondary signal group_1, perform logic operations on the received first signals, and output the first second signal; …… The Nth logic transmission chain is configured to receive the first signals in all the N-level signal groups_1, perform logic operations on the received first signals, and output the Nth second signal.

6. The memory according to claim 5, It is characterized in that The type of the logic device is one of the following: AND gate, OR gate, NAND gate, NOR gate, XNOR gate, XOR gate; When all logic devices are OR gates, the preset level signal is a low level signal; In the case where all logic devices are AND gates, the preset level signal is a high level signal.

7. The memory according to claim 5, It is characterized in that At M = 2 N In this case, each of the logical transmission chains includes M / 2 logic devices.

8. The memory according to claim 5, It is characterized in that When M=64 and N=6, each of the logic transmission chains includes 32 OR gates; The number of the first-level signal group_1 is 1, and the first-level signal group_1 includes the first signals numbered 63 to 32; The number of secondary signal groups_1 is 2, and the secondary signal group_1 includes the first signals numbered {63-48}U{31-16}; The number of three-level signal groups_1 is 4, and the three-level signal group_1 includes the first signals numbered {55-48}U{39-32}U{23-16}U{7-0}; The number of four-level signal groups_1 is 8, and the four-level signal group_1 includes the first signals numbered {63-60}U{55-52}U{47-44}U{39-36}U{31-28}U{23-20}U{15-12}U{7-4}; The number of five-level signal groups_1 is 16, and the five-level signal group_1 includes the first signals numbered {63-62}U{59-58}U{55-54}U{51-50}U{47-46}U{43-42}U{39-38}U{35-34}U{31-30}U{27-26}U{23-22}U{19-18}U{15-14}U{11-10}U{7-6}U{3-2}; The number of six-level signal groups_1 is 32, and the six-level signal group_1 includes the first signals that are odd-numbered.

9. The memory according to claim 2, It is characterized in that The control circuit further includes M sensitive amplifier control modules and M word line control modules, the M sensitive amplifier control modules correspond one-to-one to the M address decoders, and the M word line control modules correspond one-to-one to the M address decoders; The sensitive amplification control module is connected to the corresponding address decoder and configured to receive the corresponding first signal; when the first signal indicates that the corresponding storage group is selected to perform an activation operation, generate and output an amplifier control timing signal according to a preset timing rule; The word line control module is connected to the corresponding address decoder and configured to receive the corresponding first signal; when the first signal indicates that the corresponding storage group is selected to perform an activation operation, generate and output a word line control timing signal according to a preset timing rule; The amplifier control timing signal is used to control the sense amplifier in the memory, and the word line control timing signal is used to activate the selected storage group.

10. A signal processing method, It is characterized in that Applied to a storage block in a memory, wherein each storage block is divided into M storage groups, the method comprising: receiving a main address signal and a redundant address signal, decoding the main address signal and the redundant address signal, and generating M first signals; wherein the i-th first signal indicates whether the i-th storage group is selected to perform an activation operation; Encoding the M first signals into N second signals by using N logical transmission chains, and transmitting the N second signals; Wherein, the logic transmission chain includes multiple logic devices, the first input end of each of the logic devices receives one of the first signals, the second input end of the logic device at the first position receives a preset level signal, the second input ends of the logic devices other than the first position are connected to the output end of the previous logic device, and the input end of the logic device at the last position outputs the second signal.

11. The method according to claim 10, It is characterized in that The decoding of the main address signal and the redundant address signal to generate M first signals includes: When the redundant address signal does not carry valid information, the main address signal is decoded to generate M first signals; or, when the redundant address signal carries valid information, the main address signal is shielded and the redundant address signal is decoded to generate M first signals.

12. The method according to claim 10, It is characterized in that The method further comprises: N of the second signals are sent to a hammer refresh module and a column redundancy module, so that the hammer refresh module and the column redundancy module are informed of the activated storage group.

13. The method according to claim 10, It is characterized in that 2 N-1 <M≤2 N The method of encoding the M first signals into N second signals by using N logical transmission chains comprises: Divide the M first signals into a primary signal group_1 and a primary signal group_2, and divide each of the primary signal groups into a secondary signal group_1 and a secondary signal group_2, ... until each (N-1)-level signal group is divided into an N-level signal group_1 and an N-level signal group_2; The first logic transmission chain is used to perform logic operations and transmission processing on the first signal in the first-level signal group_1, and the first second signal is output; the second logic transmission chain is used to perform logic operations and transmission processing on the first signals in all the second-level signal groups_1, and the second second signal is output… The Nth logic transmission chain is used to perform logic operations and transmission processing on the first signals in all the N-level signal groups_1, and the Nth second signal is output.

14. The method according to claim 10, It is characterized in that The type of the logic device is one of the following: AND gate, OR gate, NAND gate, NOR gate, XNOR gate, XOR gate; When all logic devices are OR gates, the preset level signal is a low level signal; In the case where all logic devices are AND gates, the preset level signal is a high level signal.

15. The method according to any one of claims 10 to 14, It is characterized in that After generating the M first signals, the method further includes: Based on the M first signals, generating an amplifier control timing signal and a word line control timing signal according to a preset timing rule; The amplifier control timing signal is used to control the sense amplifier in the memory, and the word line control timing signal is used to activate the selected storage group.

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