Manufacturing method of semiconductor device and semiconductor device

Abstract

The invention discloses a manufacturing method of a semiconductor device and the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method of the semiconductor device comprises the steps: providing a semiconductor substrate, forming an epitaxial layer at one side of the semiconductor substrate, and forming a trench region at one side, away from the semiconductor substrate, of the epitaxial layer; sequentially growing a gate oxide layer and a gate polycrystalline silicon layer in the trench region, and performing body injection of source elements into the epitaxial layer on two sides of the gate polycrystalline silicon to form a source region; processing the grid polycrystalline silicon layer by adopting an etching process to form a grid region; filling gate metal in the gate region so as to fill the gate region with the gate metal; forming a dielectric layer on the surfaces of the gate metal and the source region, and etching to form a contact hole; and depositing source metal on the surfaces of the dielectric layer and the contact hole to form the semiconductor device. According to the semiconductor device, the process complexity and the manufacturing cost can be reduced, and meanwhile, the gate resistance is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] With the widespread application of electronic devices, the manufacturing process of semiconductors is also developing rapidly. The size of semiconductor devices, especially MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), is constantly shrinking, the operating frequency is constantly increasing, and the requirements for the performance of electronic devices are getting higher and higher. Gate resistance (Gate Resistance, Rg) has become one of the important factors affecting MOSFET performance. The existence of gate resistance will increase switching losses, limit switching speed, and may cause signal delays, thereby affecting the performance of the entire circuit. Therefore, in order to reduce the switching loss of the device and increase the switching frequency of the device, it is particularly important to study how to reduce the gate resistance.

[0003] At present, in the related technology, the gate resistance can be reduced by improving the manufacturing process, for example, by using better semiconductor materials or optimizing the doping process. However, this solution requires a lot of manpower and material resources, resulting in high costs and high process complexity. Summary of the invention

[0004] The purpose of the present application is to provide a method for manufacturing a semiconductor device and a semiconductor device, which can increase the effective conductive area of ​​the gate, reduce the process complexity and manufacturing cost, and reduce the gate resistance.

[0005] To achieve the above objectives, this application provides the following solutions: In a first aspect, the present application provides a method for manufacturing a semiconductor device, comprising: Providing a semiconductor substrate, forming an epitaxial layer on one side of the semiconductor substrate, and forming a trench region on a side of the epitaxial layer away from the semiconductor substrate; A gate oxide layer and a gate polysilicon layer are sequentially grown inside the trench region, and source elements are body-implanted into the epitaxial layers on both sides of the gate polysilicon layer to form a source region; Processing the gate polysilicon layer by an etching process to form a gate region; Filling gate metal in the gate region to fill the gate region with the gate metal; Forming a dielectric layer on the surface of the gate metal and the source region, and etching to form a contact hole; A source metal is deposited on the surfaces of the dielectric layer and the contact hole to form the semiconductor device.

[0006] Optionally, the gate polysilicon layer is processed by an etching process to form a gate region, including: coating a photoresist on the gate polysilicon layer; The photoresist is sequentially exposed, developed and etched through a first mask, and residual photoresist is removed to form the gate region.

[0007] Optionally, a gate oxide layer and a gate polysilicon layer are sequentially grown inside the trench region, and source elements are body-implanted into the epitaxial layers on both sides of the gate polysilicon to form a source region, including: At a first preset temperature, reacting the epitaxial layer inside the trench region with oxygen to form a gate oxide layer; At the first preset temperature, depositing a gate element on the gate oxide layer to form a gate polysilicon layer; At a second preset temperature, the epitaxial layers on both sides of the gate polysilicon layer are body-implanted and diffused to form an implantation region, and source elements are deposited in the implantation region to form the source region; the second preset temperature is lower than the first preset temperature.

[0008] Optionally, forming a dielectric layer on the surface of the gate metal and the source region, and etching to form a contact hole specifically includes: Depositing a dielectric compound on the surface of the gate metal and the source region to form the dielectric layer; coating a photoresist on the dielectric layer; The photoresist is sequentially exposed, developed and etched through a second mask, and residual photoresist is removed to form the contact hole.

[0009] Optionally, the thickness of the dielectric layer is 0.5um-1.2um.

[0010] Optionally, the groove depth of the groove area is 0.3um-0.5um.

[0011] Optionally, the gate element is boron, the source element is arsenic or phosphorus, the gate metal material is tungsten or aluminum, and the source metal material is aluminum.

[0012] In a second aspect, the present application provides a semiconductor device, comprising: Semiconductor substrate; An epitaxial layer, the epitaxial layer is located on one side of the semiconductor substrate, and a trench region is provided on a side of the epitaxial layer away from the semiconductor substrate; A gate region, the gate region is located in the trench region, the gate region includes a gate oxide layer and a gate polysilicon layer connected to the gate oxide layer, and the gate region is filled with a gate metal; A source region, the source region is located in the epitaxial layer on both sides of the gate polysilicon layer and is filled with source elements; A dielectric layer is provided on a side of the gate metal and the source region away from the semiconductor substrate, the contact hole is provided on the dielectric layer, and source metal is provided on the surfaces of the dielectric layer and the contact hole.

[0013] According to the specific embodiments provided in this application, this application discloses the following technical effects: The present application provides a method for manufacturing a semiconductor device and a semiconductor device, wherein a semiconductor substrate is provided, an epitaxial layer is formed on one side of the semiconductor substrate, and a trench region is formed on the epitaxial layer on a side away from the semiconductor substrate; a gate oxide layer and a gate polysilicon layer are sequentially grown inside the trench region, and a source element is body-implanted into the epitaxial layer on both sides of the gate polysilicon layer to form a source region; the gate polysilicon layer is processed by an etching process to form a gate region; a gate metal is filled in the gate region to fill the gate region with the gate metal; a dielectric layer is formed on the surface of the gate metal and the source region, and a contact hole is etched to form a semiconductor device. A source metal is deposited on the surface of the dielectric layer and the contact hole to form a semiconductor device. Compared with the prior art, the technical solution of the present application is provided with a trench region on the epitaxial layer, and after a gate oxide layer and a gate polysilicon layer are grown in the trench region, etching is performed to form a gate region, thereby increasing the effective conductive area of ​​the gate; and a gate metal is filled in the gate region. Since the metal has a lower resistivity, current is more likely to pass through, increasing the conductive path, so that current can be conducted through the gate metal, thereby reducing the resistance of the gate polysilicon layer, and after the source region is formed, a dielectric layer is formed on the surface of the gate metal and the source, which can isolate the gate metal from the semiconductor substrate, and then after etching the contact hole and depositing the source metal, a semiconductor device with reduced gate resistance can be formed while reducing process complexity and manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0015] Figure 1 A schematic diagram of a process for manufacturing a semiconductor device in an embodiment of the present application; Figure 2 A schematic diagram of a structure for forming a trench region on an epitaxial layer provided in one embodiment of the present application; Figure 3A schematic diagram of a structure for forming a gate oxide layer in a trench region according to an embodiment of the present application; Figure 4 A schematic diagram of a structure for forming a gate polysilicon layer on a gate oxide layer according to an embodiment of the present application; Figure 5 A schematic structural diagram of a method for forming a gate oxide layer, a gate polysilicon layer and a source region provided in one embodiment of the present application; Figure 6 A schematic diagram of a structure for performing body implantation on the epitaxial layers on both sides of the gate polysilicon layer provided in an embodiment of the present application; Figure 7 A schematic diagram of a structure in which a source electrode element is deposited in an implantation region to form a source electrode region provided in an embodiment of the present application; Figure 8 A schematic diagram of a structure formed after etching a gate polysilicon layer according to an embodiment of the present application; Fig. 9 A schematic diagram of a structure in which a gate metal is filled in a gate region according to an embodiment of the present application; Fig.10 A schematic diagram of a structure for forming a dielectric layer provided in one embodiment of the present application; Fig.11 A schematic diagram of a structure in which a contact hole is formed after etching a dielectric layer according to an embodiment of the present application; Fig.12 A schematic diagram of the structure of a semiconductor device provided in one embodiment of the present application.

[0016] Description of reference numerals: Semiconductor substrate-10, trench region-11, epitaxial layer-12, gate region-20, gate oxide layer-21, gate polysilicon layer-22, gate metal-23, source metal-31, dielectric layer-40, contact hole-41. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0018] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0019] As mentioned in the background technology, in the related art, the gate resistance is reduced by improving the manufacturing process, for example, by using better semiconductor materials or optimizing the doping process. However, this solution requires a lot of manpower and material resources, resulting in high costs and high process complexity.

[0020] Based on the above defects, the present application provides a method for manufacturing a semiconductor device. Compared with the prior art, the technical solution of the present application is provided with a trench region on the epitaxial layer, and after the gate oxide layer and the gate polysilicon layer are grown in the trench region, the gate region is formed by etching, thereby increasing the effective conductive area of ​​the gate; and the gate metal is filled in the gate region, and since the metal has a lower resistivity, the current is easier to pass through, and the conductive path is increased, so that the current can be conducted through the gate metal, thereby reducing the resistance of the gate polysilicon layer, and after the source region is formed, a dielectric layer is formed on the surface of the gate metal and the source, which can isolate the gate metal from the semiconductor substrate, and then the source metal is deposited after etching the contact hole, which can reduce the process complexity and manufacturing cost while forming a semiconductor device with reduced gate resistance.

[0021] In an exemplary embodiment, Figure 1 As shown, a method for manufacturing a semiconductor device is provided, which includes the following steps S201 to S206 in the embodiment of the present application. Among them: Step S201 , providing a semiconductor substrate, forming an epitaxial layer on one side of the semiconductor substrate, and forming a trench region on a side of the epitaxial layer away from the semiconductor substrate.

[0022] Please note that, see Figure 2 As shown, Figure 2 A schematic diagram of the structure of a semiconductor substrate, an epitaxial layer and a trench region provided for an embodiment of the present application. The semiconductor substrate 10 may be a silicon substrate, a germanium substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a gallium nitride (GaN) substrate or a silicon-on-insulator substrate, etc. The shape of the trench region 11 may be a long strip of trenches, or a wavy trench, etc. The number of trench regions 11 may be one, two or more. The shape of the semiconductor substrate 10 may be a rectangular parallelepiped, a cylindrical shape, or a prism shape. In this embodiment, no limitation is imposed on the number and shape of the trenches. The epitaxial layer 12 is grown on the semiconductor substrate 10.

[0023] Specifically, after the epitaxial layer 12 is obtained, the trench region 11 can be formed by etching the epitaxial layer 12 in a dry or wet manner. Among them, wet etching uses a chemical solution to dissolve the epitaxial layer 12 material, and the chemical solution can be, for example, an acidic solution or an alkaline solution. Dry etching uses plasma or other gaseous chemicals for etching, and has high selectivity and good directionality.

[0024] As an optional implementation, in the process of etching the groove area 11 on the epitaxial layer 12 by dry method, reactive ion etching, deep reactive ion etching, and electron cyclotron resonance can be used. Specifically, a patterned mask can be formed on the upper surface of the epitaxial layer 12. The patterned mask can be the shape of the desired groove. The pattern can be customized according to actual needs, for example, it can be a long strip. Then, the epitaxial layer 12 is placed in the etching chamber, and a suitable etching gas is introduced. A radio frequency (RF) power supply is applied to generate plasma. The active particles in the plasma will bombard the surface of the epitaxial layer 12 and remove the part not covered by the mask. The etching depth of the groove can be 0.3um-0.5um. After the etching is completed, the epitaxial layer 12 can be cleaned and the photoresist mask can be removed, so as to form a groove area on the epitaxial layer 12. At this time, the groove depth of the formed groove area is 0.3um-0.5um.

[0025] As another optional implementation, a layer of photoresist may be first coated on the epitaxial layer 12, and then the desired pattern may be transferred to the photoresist by photolithography to form a mask, and the desired pattern may be the pattern of the groove area. The epitaxial layer 12 with the mask is immersed in an etching solution, and the etching solution dissolves the portion not protected by the mask, thereby forming a groove area 11 on the epitaxial layer 12. After the etching is completed, the epitaxial layer 12 needs to be cleaned to remove the residual etching solution, and the photoresist is removed using a solvent.

[0026] Step S202 , a gate oxide layer and a gate polysilicon layer are sequentially grown inside the trench region, and source elements are body-implanted into the epitaxial layer to form a source region.

[0027] Please note that, see Figure 3 As shown, the gate oxide layer 21 is located between the epitaxial layer 12 and the gate polysilicon layer 22 inside the trench region 11. The gate oxide layer 21 is a very thin silicon dioxide (SiO2) layer, which acts as an insulating medium to prevent current from flowing directly from the gate to the semiconductor substrate, which ensures that the gate voltage can effectively control the charge state of the channel region without being short-circuited. The gate oxide layer 21 is an insulating layer, so the electric field between the gate and the semiconductor can be established through this layer to form a capacitor. The characteristics of this capacitor determine many important properties of the semiconductor device, such as the threshold voltage (Vth). The gate oxide layer is also used to isolate the gate region from the source region. The gate polysilicon layer 22 can also include: amorphous silicon, amorphous germanium, amorphous carbon, SiGe, Si:C and combinations thereof.

[0028] For details, please refer to Figure 3As shown, after the trench region 11 is formed on the epitaxial layer 12, a gate oxide layer 21 with a thickness of 165A-1000A can be obtained at a preset temperature, and then Figure 4 As shown, a gate polysilicon layer 22 is deposited on the gate oxide layer 21, and the thickness of the gate polysilicon layer 22 can be customized according to actual needs. After the gate oxide layer 21 and the gate polysilicon layer 22 are grown, the epitaxial layer can be body-implanted with source elements to form a source region.

[0029] As an achievable method, in the process of sequentially growing the gate oxide layer 21 and the gate polysilicon layer 22 inside the trench region 11 and forming the source region, see Figure 5 As shown, the following method steps may be included: Step S301 , at a first preset temperature, reacting the epitaxial layer in the trench region with oxygen to form a gate oxide layer.

[0030] Step S302 , depositing a gate element on the gate oxide layer at a first preset temperature to form a gate polysilicon layer.

[0031] Step S303, at a second preset temperature, body implantation and diffusion treatment are performed on the epitaxial layer on both sides of the gate polysilicon layer to form an implantation region, and source elements are deposited in the implantation region to form a source region; the second preset temperature is lower than the first preset temperature.

[0032] It is understandable that the first preset temperature and the second preset temperature can be customized according to actual needs, for example, the first preset temperature can be 950°C-1050°C, and the second preset temperature can be 900°C-950°C. The source element can be arsenic (As) or phosphorus (P). The gate element can be boron.

[0033] Specifically, after forming the trench region 11 on the epitaxial layer 12, the epitaxial layer 12 can be reacted with oxygen at a growth temperature of 950°C-1050°C to form a gate oxide layer 21, which can be SiO2, and then the gate element boron is deposited on the gate oxide layer 21, with a dosage of 7e12-1e13, an injection energy of 80k3v-140kev, and a high-temperature diffusion temperature of a first preset temperature of 950C-1150C, thereby forming a gate polysilicon layer 22. See Figure 6 As shown, after the gate polysilicon layer 22 is formed, the epitaxial layers on both sides of the gate polysilicon layer 22 may be implanted with a body to form an implantation region, and see Figure 7As shown, after the injection region is formed, the source element arsenic As can be injected into the injection region of the epitaxial layer, and the corresponding dose can be 3e15-8e15, the injection energy is 40kev-60kev, and the high-temperature diffusion temperature is the second preset temperature 900℃-950C℃, thereby forming a source region.

[0034] The gate polysilicon layer 22 can control the conductivity of the region below by applying voltage, and has the ability to store charge. Taking the semiconductor device as MOSFET as an example, if the semiconductor substrate is P-type silicon, the source element corresponding to the source region usually uses N-type dopants, such as phosphorus (P) or arsenic (As). On the contrary, if the substrate is N-type silicon, the source element corresponding to the source region may use P-type dopants, such as boron (B).

[0035] In this embodiment, by sequentially growing a gate oxide layer 21 and a gate polysilicon layer 22 in the trench region 11, a gate region can be formed in the trench region 11 to increase the conductive area of ​​the gate, and depositing source elements on the epitaxial layer 12 on both sides of the gate polysilicon layer 22 can accurately form a source region, thereby reducing process complexity.

[0036] Step S203 , processing the gate polysilicon layer by an etching process to form a gate region.

[0037] Specifically, see Figure 8 As shown, in the process of forming the gate region, photoresist may be coated on the gate polysilicon layer 22, and the photoresist is sequentially exposed, developed and etched through a first mask, and residual photoresist is removed to form the gate region. The first mask may be set according to the size of the trench region.

[0038] It is understandable that the above etching process mainly uses chemical or physical methods to selectively etch or strip the surface of the gate oxide layer 22 or the thin film covering the surface of the substrate. Through the etching process, the oxide film outside the photoresist coverage is removed, and the oxide film under the photoresist protection layer is retained. Then, by removing the photoresist, the top view of the retained oxide film is obtained, which is the mask pattern.

[0039] It should be noted that after the gate polysilicon layer 22 is deposited in the groove area 11, the photolithography technology can be used to define the position that needs to be reserved as the gate on the gate polysilicon layer 22. First, a layer of photoresist is evenly coated on the gate polysilicon layer 22, and then the photoresist is exposed using a first mask and a light source (such as ultraviolet light) to cause chemical changes in certain areas of the photoresist. The exposed portion is then removed using a developer, that is, the gate polysilicon layer 22 not covered by the photoresist is removed. The etching depth is 0.3um-0.5um, thereby forming the desired gate area structure. After the etching is completed, the remaining photoresist needs to be removed, usually using oxygen plasma or other chemical methods to form the gate area.

[0040] Optionally, in the process of removing the gate polysilicon layer not covered by the photoresist, wet etching or dry etching can be used. Wet etching is the use of a chemical solution (such as a mixture of hydrofluoric acid HF and other chemicals) to dissolve the gate polysilicon layer not protected by the photoresist. Dry etching is done by plasma etching or reactive ion etching (RIE), in which plasma is used to selectively etch away the gate polysilicon layer not masked by the photoresist. This method can provide higher directionality and better resolution.

[0041] In this embodiment, the gate polysilicon layer 22 is processed by an etching process to form a gate region, which can provide a setting channel for the subsequent conductive path, thereby increasing the number of effective paths for current flow.

[0042] Step S204, filling the gate region with gate metal to completely fill the gate region with gate metal.

[0043] The gate metal is made of tungsten or aluminum. The gate metal controls the conductivity of the channel region by applying voltage, thereby controlling the current between the source and the drain.

[0044] Specifically, see Fig. 9 As shown, after the gate region is obtained, the gate metal 23 can be filled in the gate region 20, and is deposited on the gate polysilicon layer 22 corresponding to the gate region by using physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) technology, so that the gate metal 23 fills the entire gate region 20. The height of the gate region 20 after being filled with the gate metal 23 can be consistent with the height of the epitaxial layer 12 outside the trench region 11.

[0045] It is understandable that the gate resistance will affect the speed performance and power consumption of the device. In this embodiment, by etching a groove in the gate resistance gate and filling it with metal, the conductive path can be increased, and specifically the number of effective paths for current flow can be increased, which means that the current no longer depends solely on the gate polysilicon layer above, but can be conducted through the gate metal layer below, thereby reducing the gate resistance.

[0046] Step S205, forming a dielectric layer on the surface of the gate metal and the source region, and etching to form contact holes.

[0047] Please note that, see Fig.10 and Fig.11 As shown, the dielectric layer 40 can be generally made of insulating materials, such as silicon dioxide (SiO2), silicon nitride (Si3N4), high dielectric constant materials (High-k materials), etc. The contact holes 41 are openings formed in the dielectric layer 40, which allow the metal layer or the conductive layer to directly contact the source region below, thereby forming an electrical contact. The shape of the contact hole can be a long strip or any other shape, and this embodiment does not impose any limitation on the shape of the contact hole.

[0048] After the gate metal 23 is deposited on the gate polysilicon layer 22, a dielectric layer 40 may be deposited on the surface of the gate metal 23 and the source region, and the dielectric layer 40 is etched to form a contact hole 41. The dielectric layer 40 has a thickness of 0.5um-1.2um.

[0049] In the process of forming the dielectric layer 40 on the surface of the gate metal 23 and the source region and etching to form the contact hole 41, a dielectric compound may be first deposited on the surface of the gate metal 23 and the source region to form the dielectric layer 40, and then a photoresist may be coated on the dielectric layer 40, and the photoresist may be sequentially exposed, developed and etched through a second mask, and residual photoresist may be removed to form the contact hole 41. The second mask may be customized according to actual needs.

[0050] Specifically, in the process of depositing the dielectric layer 40, chemical vapor deposition (CVD), atomic layer deposition (ALD) and other technologies can usually be used to deposit the dielectric layer 40 on the surface of the source metal and the surface of the source region. After the dielectric layer is formed, the photolithography technology can be used to define the location where the contact hole needs to be formed on the dielectric layer according to the second mask, which usually includes steps such as coating photoresist, exposure, and development. Then, the dielectric layer outside the covered area is removed by etching technology to form the required contact hole 41. Common etching methods include dry etching (such as plasma etching or reactive ion etching RIE) and wet etching. After etching is completed, the contact hole 41 needs to be inspected to ensure that the aperture, depth and shape meet the design requirements.

[0051] In this embodiment, a dielectric layer 40 is formed on the surface of the gate metal 23 and the source region, thereby isolating the gate and the channel, so that the voltage on the gate can control the conductivity of the channel without directly contacting the channel, and can protect the underlying semiconductor substrate from the influence of the external environment, prevent chemical pollution or mechanical damage, for example, during the packaging process, the dielectric layer 40 can prevent moisture or pollutants from entering the device. By etching the dielectric layer 40 to form a contact hole 41, electrical contact with the source region can be formed.

[0052] Step S206 , depositing source metal on the surface of the dielectric layer and the contact hole to form a semiconductor device.

[0053] Please note that, see Fig.12 As shown, the source metal 31 refers to the metal layer in contact with the source region in the semiconductor device. The main function of the source metal is to provide a low-resistance ohmic contact so that current can enter the source region between the semiconductor devices from the external circuit. Optionally, the material of the source metal can be aluminum, copper, tungsten, nickel, cobalt, etc.

[0054] After etching the dielectric layer 40 to form the contact hole 41, the source metal 31 may be injected into the surface of the dielectric layer 40 and the contact hole 41. For example, the source metal may be deposited onto the surface of the dielectric layer 40 and the contact hole 41 by using physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques to obtain a source electrode, thereby forming a semiconductor device.

[0055] Optionally, after forming the gate polysilicon layer 22 and the dielectric layer, the gate polysilicon layer 22 and the dielectric layer 40 may be etched simultaneously, thereby forming a corresponding gate region after the gate polysilicon layer 22 is etched, and forming a contact hole 41 after the dielectric layer 40 is etched.

[0056] Among them, the material of the gate metal can be tungsten or aluminum, and its corresponding resistivity is <0.003mohm.cm, while the resistivity of the gate polysilicon layer is >3mohm.cm. Since the gate metal has better conductivity than the gate polysilicon layer, for example, the gate metal material (such as aluminum, copper, tungsten, etc.) has a lower resistivity and can effectively transmit current through the gate metal. In contrast, the resistivity of the gate polysilicon is higher, especially at a finer line width, the resistance will become higher.

[0057] In this embodiment, a trench region 11 is provided on the semiconductor substrate 10 to construct a gate region 20, thereby increasing an effective conductive path, and filling the gate region with a gate metal 23, thereby enabling effective current transmission. Since the gate metal 23 has a relatively low resistivity, the gate resistance can be greatly reduced, for example, the resistance of the gate polysilicon can be reduced by at least 90%.

[0058] It can be understood that the above resistivity is an inherent property of a material, which describes the resistance of a material per unit length or unit volume. Resistivity (ρ) is a physical quantity that measures the conductivity of a material, which reflects the material's resistance to current. The size of the resistor (R) is not only related to the resistivity, but also to the length (L) and cross-sectional area (S) of the conductor. Specifically, when the length and cross-sectional area of ​​the resistor remain unchanged, the size of the resistor is proportional to the resistivity, that is, the larger the resistivity, the greater the resistance; conversely, the smaller the resistivity, the smaller the resistance.

[0059] The present application provides a method for manufacturing a semiconductor device, which comprises providing a semiconductor substrate, forming an epitaxial layer on one side of the semiconductor substrate, and forming a trench region on the epitaxial layer on a side away from the semiconductor substrate; sequentially growing a gate oxide layer and a gate polysilicon layer inside the trench region, and body-implanting source elements into the epitaxial layers on both sides of the gate polysilicon layer to form a source region; processing the gate polysilicon layer by an etching process to form a gate region; filling the gate region with gate metal to fill the gate region with the gate metal; forming a dielectric layer on the surface of the gate metal and the source region, and etching to form a contact hole; and depositing a source metal on the surface of the dielectric layer and the contact hole to form a semiconductor device. Compared with the prior art, the technical solution of the present application, since a trench region is provided on the epitaxial layer, can form a gate region by etching after growing a gate oxide layer and a gate polysilicon layer in the trench region, thereby increasing the effective conductive area of ​​the gate; and fill the gate region with gate metal, since the metal has a lower resistivity, it is easier for current to pass through, increasing the conductive path, so that the current can be conducted through the gate metal, thereby reducing the resistance of the gate polysilicon layer, and after forming the source region, a dielectric layer is formed on the surface of the gate metal and the source, isolating the gate metal from the semiconductor substrate, and after etching the contact hole and depositing the source metal, it is possible to form a semiconductor device with reduced gate resistance while reducing process complexity and manufacturing cost.

[0060] On the other hand, in another exemplary embodiment of the present application, a semiconductor device is also provided. Figure 8As shown, the semiconductor device includes: a semiconductor substrate 10, an epitaxial layer 12, a gate region 20, a source region and a dielectric layer 40. The epitaxial layer 12 is located on one side of the semiconductor substrate 10, and a trench region 11 is provided on the side of the epitaxial layer 12 facing away from the semiconductor substrate 10; the gate region 20 is located in the trench region 11, and the gate region 20 includes a gate oxide layer 21 and a gate polysilicon layer 22, and the gate region 20 is filled with a gate metal 23. The source region is located in the epitaxial layer 12 on both sides of the gate polysilicon layer 22 and is filled with source elements. The dielectric layer 40 is provided on the surface of the gate metal and the source region, and a contact hole 41 is opened on the dielectric layer, and the surface of the dielectric layer 40 and the contact hole 41 is provided with a source metal 31.

[0061] It should be noted that the trench region 11 is a region for manufacturing a gate, which may include one, two or more trenches, and the trench depth of the trench region 11 is 0.3um-0.5um. The gate region is located in the trench region 11, including a gate oxide layer 21 and a gate polysilicon layer 22. The gate oxide layer 21 may be silicon dioxide, and its thickness may be 165A-1000A. The gate polysilicon layer 22 may include polysilicon. The gate polysilicon layer 22 may be located above the gate oxide layer 21.

[0062] In this embodiment, since the depth of the trench region 11 is set to 0.3 um-0.5 um, the effective conductive area of ​​the gate can be increased while ensuring a certain thickness of the semiconductor substrate 10, thereby reducing the gate resistance.

[0063] The gate oxide layer 21 may be in the shape of a long strip with a certain thickness, and the gate polysilicon layer 22 may be in the shape of a groove, which may be formed by an etching process.

[0064] It is understood that the gate oxide layer 21 is located between the epitaxial layer 12 and the gate polysilicon layer 22. The gate oxide layer 21 is used to isolate the gate from the channel region to prevent the current from flowing directly, and can withstand high electric field strength without being broken down. The gate polysilicon layer 22 is a polycrystalline silicon, which is formed by depositing amorphous silicon and then annealing it to transform it into a polysilicon structure. The polysilicon can be doped to reduce its resistance, which helps to increase the operating speed of the semiconductor device.

[0065] The gate region 20 is filled with a gate metal 23. The thickness of the gate metal 23 can be consistent with the groove depth of the groove of the gate region 20. The groove of the gate region 20 can be filled. The gate metal 23 can provide a reliable electrical connection so that the subsequent interconnection layer can be connected to the gate through the contact hole, and can improve the conductivity of the gate, thereby reducing the gate resistance, which helps to improve the switching speed and overall circuit performance of the semiconductor device. At the same time, filling the gate metal 23 in the gate region can provide mechanical support, help stabilize the gate structure, and avoid deformation or damage caused by stress in subsequent processing steps. By filling the gate metal 23, the uniformity and stability of the gate on the entire chip can also be ensured.

[0066] The source region may be located on both sides of the gate polysilicon layer 22. First, an injection region is formed on both sides of the gate polysilicon layer 22 by body injection, and then source elements are deposited in the injection region to form the source region. The deposited source elements may be formed by ion implantation and diffusion, and the depth is generally determined by the implantation energy and the type of doping. The source region is filled with source elements. When the semiconductor device is an N-type MOSFET, the source elements may include phosphorus or arsenic. Each atom of this element has one more valence electron than silicon, forming free electrons, thereby reducing the resistance of the region. When the semiconductor device is a P-type MOSFET, the source element may use trivalent elements (such as boron). Each atom of these elements has one less valence electron than silicon, forming holes, which also reduces the resistance. The doping concentration of the source element may be high to ensure that the region has good conductivity.

[0067] Optionally, the semiconductor device may further include a drain region (not shown in the figure), which may be located in a region of the doped region other than the source region. The source region and the drain region are usually adjacent to the gate region in the horizontal direction, but are separated in the vertical direction by a gate oxide layer or a dielectric layer. This structure enables the gate region to effectively control the current flow between the source region and the drain region.

[0068] The heights of the source region and the gate region generally refer to their diffusion depths on the semiconductor substrate, while the height of the gate region depends on the design of the gate material and its structure.

[0069] The dielectric layer 40 can be arranged on the surface of the gate metal 23 and the source region, and contact holes can be formed on the dielectric layer 40 by etching. The number of contact holes 41 can be one, two or more, and the apertures of the contact holes 41 can be the same or different. Then, the source metal 31 is arranged on the surface of the dielectric layer 40 and the contact holes 41. The gate element is boron, the source element is arsenic or phosphorus, the material of the gate metal 23 is tungsten or aluminum, and the material of the source metal 31 is aluminum.

[0070] In this embodiment, the source metal 31 is mainly used to provide good electrical contact for the source region, and is used to introduce external drive current into the source region, so that the semiconductor device can work normally. The low resistance characteristic of the source metal helps to reduce the loss during signal transmission. The source metal 31 usually has good conductivity, which can significantly reduce the contact resistance of the source region, thereby improving the conduction performance of the entire semiconductor device. It also has a certain mechanical support function, which contributes to the stability of the semiconductor device structure.

[0071] Optionally, the semiconductor device may be applicable to a MOSFET / IGBT with a planar gate, or to a MOSFET / IGBT with a polysilicon gate.

[0072] The semiconductor device in the embodiment of the present application includes a semiconductor substrate, an epitaxial layer, a gate region, a source region and a dielectric layer, wherein the epitaxial layer is located on one side of the semiconductor substrate, and a trench region is provided on the side of the epitaxial layer away from the semiconductor substrate; the gate region is located in the trench region, and the gate region includes a gate oxide layer and a gate polysilicon layer, and the gate region is filled with a gate metal. The source region is located in the epitaxial layer on both sides of the gate polysilicon layer and is filled with source elements. The dielectric layer is provided on the side of the gate metal and the source region away from the semiconductor substrate, the contact hole is provided on the dielectric layer, and the surface of the dielectric layer and the contact hole is provided with a source metal. The technical solution of the present application, since a trench region is provided on the epitaxial layer, can form a gate region after growing a gate oxide layer and a gate polysilicon layer in the trench region, thereby increasing the effective conductive area of ​​the gate; and fill the gate region with gate metal. Since the metal has a lower resistivity, current is more likely to pass through, increasing the conductive path, so that the current can be conducted through the gate metal, thereby reducing the resistance of the gate polysilicon layer, and after the source region is formed, a dielectric layer is formed on the surface of the gate metal and the source to isolate the gate metal from the semiconductor substrate, and after etching the contact hole and depositing the source metal, a semiconductor device with reduced gate resistance can be formed while reducing process complexity and manufacturing cost.

[0073] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A method for manufacturing a semiconductor device, It is characterized in that The method for manufacturing the semiconductor device comprises: Providing a semiconductor substrate, forming an epitaxial layer on one side of the semiconductor substrate, and forming a trench region on a side of the epitaxial layer away from the semiconductor substrate; A gate oxide layer and a gate polysilicon layer are sequentially grown inside the trench region, and source elements are body-implanted into the epitaxial layers on both sides of the gate polysilicon layer to form a source region; Processing the gate polysilicon layer by an etching process to form a gate region; Filling gate metal in the gate region to fill the gate region with the gate metal; Forming a dielectric layer on the surface of the gate metal and the source region, and etching to form a contact hole; A source metal is deposited on the surfaces of the dielectric layer and the contact hole to form the semiconductor device.

2. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that The gate polysilicon layer is processed by an etching process to form a gate region, including: coating a photoresist on the gate polysilicon layer; The photoresist is sequentially exposed, developed and etched through a first mask, and residual photoresist is removed to form the gate region.

3. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that A gate oxide layer and a gate polysilicon layer are sequentially grown inside the trench region, and a body implantation is performed on the epitaxial layer on both sides of the gate polysilicon to deposit source elements to form a source region, including: At a first preset temperature, reacting the epitaxial layer inside the trench region with oxygen to form a gate oxide layer; At the first preset temperature, depositing a gate element on the gate oxide layer to form a gate polysilicon layer; At a second preset temperature, the epitaxial layers on both sides of the gate polysilicon layer are body-implanted and diffused to form an implantation region, and source elements are deposited in the implantation region to form the source region; the second preset temperature is lower than the first preset temperature.

4. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that Forming a dielectric layer on the surface of the gate metal and the source region, and etching to form a contact hole, specifically comprising: Depositing a dielectric compound on the surface of the gate metal and the source region to form the dielectric layer; coating a photoresist on the dielectric layer; The photoresist is sequentially exposed, developed and etched through a second mask, and residual photoresist is removed to form the contact hole.

5. The method for manufacturing a semiconductor device according to claim 4, It is characterized in that The thickness of the dielectric layer is 0.5um-1.2um.

6. The method for manufacturing a semiconductor device according to claim 1, It is characterized in that The groove depth of the groove area is 0.3um-0.5um.

7. The method for manufacturing a semiconductor device according to claim 3, It is characterized in that The gate element is boron, the source element is arsenic or phosphorus, the gate metal material is tungsten or aluminum, and the source metal material is aluminum.

8. A semiconductor device, It is characterized in that Obtained by the method for manufacturing a semiconductor device according to any one of claims 1 to 7, the semiconductor device comprising: Semiconductor substrate; An epitaxial layer, the epitaxial layer is located on one side of the semiconductor substrate, and a trench region is provided on a side of the epitaxial layer away from the semiconductor substrate; A gate region, the gate region is located in the trench region, the gate region includes a gate oxide layer and a gate polysilicon layer connected to the gate oxide layer, and the gate region is filled with a gate metal; A source region, the source region is located in the epitaxial layer on both sides of the gate polysilicon layer and is filled with source elements; A dielectric layer is provided on the surfaces of the gate metal and the source region, a contact hole is opened on the dielectric layer, and source metal is provided on the surfaces of the dielectric layer and the contact hole.

9. The semiconductor device according to claim 8, It is characterized in that The groove depth of the groove area is 0.3um-0.5um.

10. The semiconductor device according to claim 8, It is characterized in that The gate element is boron, the source element is arsenic or phosphorus, the gate metal material is tungsten or aluminum, and the source metal material is aluminum.

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