Multi-chip substrate level packaging method, packaging structure and radio frequency chip

Abstract

The embodiment of the invention discloses a multi-chip substrate-level packaging method, a packaging structure and a radio frequency chip. The packaging method comprises the following steps: firstly, providing a substrate; wherein the substrate comprises a first surface and a second surface which are deviated from each other, the first surface comprises a plurality of groove accommodating areas and cutting areas located between every two adjacent groove accommodating areas, then different types of chips are placed in the groove accommodating areas in a one-to-one correspondence mode, and third surfaces of the chips face the bottoms of the groove accommodating areas; wherein the third surface of each chip comprises an electrode structure, and then carrying out injection molding and plastic packaging treatment on each chip so as to wrap each chip in a plastic packaging layer; wherein in the thickness direction of the substrate, the concave depth of the groove accommodating area is the same as the thickness of the plastic packaging layer, then through hole manufacturing processing is carried out on the second surface until part of the electrode structure of each chip is exposed, finally, a metal interconnection circuit is formed on the second surface, and the metal interconnection circuit is electrically connected with the corresponding electrode structure through a through hole.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor packaging technology, and in particular to a multi-chip substrate-level packaging method, a packaging structure, and a radio frequency chip. Background Art

[0002] With the continuous advancement of semiconductor technology, RF chip products have also ushered in huge market demand and rapid development opportunities, and the product structure is designed towards higher integration, smaller package size, and more comprehensive performance. In order to cater to this development trend and improve packaging efficiency, multiple RF chips of different types need to be highly integrated in a packaging structure with a limited area. On the one hand, chip packaging can isolate the chip from the outside world and prevent impurities in the air from corroding the chip circuit and causing a decrease in electrical performance; on the other hand, the packaged chip is also easier to install and transport.

[0003] In the existing chip packaging process, in order to reduce the overall product size, organic insulating materials are used as plastic layers on the front and back of the chip to achieve the chip's six-sided encapsulation effect. However, due to the large difference in thermal expansion coefficient between the organic insulating material of the plastic layer and the chip, the multi-chip integrated packaging structure will be greatly warped, which makes the packaging process more difficult. In addition, the dielectric constant of the organic insulating material of the plastic layer is limited, resulting in insufficient high-frequency chip performance, which is not suitable for high-frequency performance chip packaging. Summary of the invention

[0004] The embodiments of the present invention provide a multi-chip substrate-level packaging method, a packaging structure, and a radio frequency chip to improve the warpage of multi-chip integration, reduce the difficulty of the packaging process, and effectively improve the reliability and durability of chip packaging.

[0005] In a first aspect, an embodiment of the present invention provides a multi-chip substrate-level packaging method, comprising: A substrate is provided; wherein the substrate comprises a first surface and a second surface which are opposite to each other, the first surface comprises a plurality of groove accommodating areas and a cutting area located between two adjacent groove accommodating areas; Placing chips of different types in the groove accommodating area in a one-to-one correspondence, and the third surface of each chip faces the bottom of the groove accommodating area; wherein the number of the chips is the same as the number of the groove accommodating areas, the third surface of the chip includes an electrode structure, and in the thickness direction of the substrate, the recessed depth of the groove accommodating area is greater than the thickness of each chip; Performing injection molding on each of the chips to encapsulate each of the chips in a plastic layer; wherein, in the thickness direction of the substrate, the depression depth of the groove accommodating area is the same as the thickness of the plastic layer; Performing a through-hole manufacturing process on the second surface until a portion of the electrode structure of each chip is exposed; A metal interconnection line is formed on the second surface, and the metal interconnection line is electrically connected to the corresponding electrode structure through a through hole.

[0006] Optionally, the third surface of the chip further includes a key functional structure; Placing chips of different types in the groove accommodating area one by one, with the third surface of each chip facing the bottom of the groove accommodating area, comprising: An annular wall structure is provided in the groove accommodating area; The corresponding chip is placed in the groove accommodating area, and a sealed cavity structure is formed by the annular wall structure, the bottom of the groove accommodating area and the key functional structure of the chip; wherein, in the thickness direction of the substrate, the sum of the thickness of the chip and the thickness of the annular wall structure is less than the depression depth of the corresponding groove accommodating area.

[0007] Optionally, performing injection molding on each of the chips to encapsulate each of the chips in a plastic packaging layer includes: Performing injection molding on each of the chips to form a plastic encapsulation layer covering the first surface of the substrate and each of the chips; The plastic sealing layer is thinned until the cutting area on the first surface is exposed.

[0008] Optionally, while thinning the plastic sealing layer until the cutting area on the first surface is exposed, the method further includes: The second surface of the substrate is thinned.

[0009] Optionally, the metal interconnection circuit includes a plurality of metal interconnection lines and a rewiring layer; A metal interconnection circuit is formed on the second surface, and the metal interconnection circuit is electrically connected to the corresponding electrode structure through a through hole, comprising: Filling each of the through holes with conductive metal to form the corresponding metal interconnection lines; A rewiring process is performed on the second surface to redefine the position of each metal interconnection line to form the rewiring layer, and the rewiring layer is connected to the through hole and is electrically connected to the corresponding electrode structure through the conductive metal in the through hole.

[0010] Optionally, after performing a rewiring process on the second surface to redefine the position of each metal interconnection line to form the rewiring layer, and the rewiring layer is connected to the through hole and electrically connected to the corresponding electrode structure through the conductive metal in the through hole, the method further includes: A solder resist insulating layer is formed on a side of the rewiring layer away from the second surface, and windows are opened on the solder resist insulating layer to form convex solder balls; wherein the convex solder balls are electrically connected to the rewiring layer.

[0011] Optionally, the substrate includes a glass substrate and a silicon-based substrate.

[0012] In a second aspect, an embodiment of the present invention further provides a multi-chip substrate-level packaging structure, which is manufactured using the multi-chip substrate-level packaging method as described in any one of the first aspects, and the multi-chip substrate-level packaging structure includes: A substrate, the substrate comprising a first surface and a second surface facing away from each other, the first surface comprising a plurality of groove accommodating areas and a cutting area located between two adjacent groove accommodating areas; Different types of chips are placed in the groove accommodating area in a one-to-one correspondence, and the third surface of each chip faces the bottom of the groove accommodating area; wherein the number of the chips is the same as the number of the groove accommodating areas, the third surface of the chip includes an electrode structure, and in the thickness direction of the substrate, the recessed depth of the groove accommodating area is greater than the thickness of each chip; A plastic encapsulation layer, the plastic encapsulation layer covers each of the chips; wherein, in the thickness direction of the substrate, the depression depth of the groove accommodating area is the same as the thickness of the plastic encapsulation layer; A metal interconnection circuit is disposed on the second surface and is electrically connected to the corresponding electrode structure through a through hole.

[0013] In a third aspect, an embodiment of the present invention further provides a radio frequency chip obtained by cutting along a cutting area in the multi-chip substrate-level packaging structure described in any one of the second aspects.

[0014] An embodiment of the present invention provides a multi-chip substrate-level packaging method, a packaging structure and a radio frequency chip. The packaging method first provides a substrate; wherein the substrate includes a first surface and a second surface that are opposite to each other, the first surface includes a plurality of groove accommodating areas and a cutting area located between two adjacent groove accommodating areas, and then different types of chips are placed one by one in the groove accommodating areas, and the third surface of each chip faces the bottom of the groove accommodating area; wherein the number of chips is the same as the number of groove accommodating areas, the third surface of the chip includes an electrode structure, and in the thickness direction of the substrate, the recessed depth of the groove accommodating area is greater than the thickness of each chip, and then each chip is injection molded to encapsulate each chip in a plastic layer; wherein, in the thickness direction of the substrate, the recessed depth of the groove accommodating area is the same as the thickness of the plastic layer, and then a through-hole manufacturing process is performed on the second surface until a portion of the electrode structure of each chip is exposed, and finally a metal interconnection line is formed on the second surface, and the metal interconnection line is electrically connected to the corresponding electrode structure through the through hole. By using the above method, a plurality of groove accommodating areas are set on the substrate, and a plurality of chips of different types are placed in the corresponding groove accommodating areas respectively. After each chip is injection molded and sealed, the depression depth of the groove accommodating area is the same as the thickness of the sealing layer, that is, the sealing layer is filled and formed in each groove accommodating area. The main body of the packaging structure corresponding to each chip is the substrate, and the chip in each groove accommodating area is actually wrapped by the substrate material to achieve packaging, which effectively improves the warpage of multi-chip integration, reduces the difficulty of packaging process, improves the preparation yield, reliability and durability of chip packaging, avoids the processing difficulties and stress caused by large warping during packaging, and affects the chip reliability. The glass substrate has excellent electrical insulation performance and is suitable for high-frequency performance chip packaging, which is conducive to reducing interference between metal interconnection lines. In addition, the multi-chip packaging process is a one-time packaging of multiple chips, and different types of chips can be freely combined. While integrating multiple chip packages, the package size is relatively reduced, which simplifies the packaging process of multiple chips, improves the chip packaging efficiency, and reduces production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 It is a schematic flow chart of a multi-chip substrate-level packaging method provided by an embodiment of the present invention; Figure 2 yes Figure 1 The structural flow chart of the multi-chip substrate level packaging method shown; Figure 3 It is a flow chart of another multi-chip substrate-level packaging method provided by an embodiment of the present invention; Figure 4 yes Figure 3 The structural flow chart of the multi-chip substrate level packaging method shown; Figure 5 It is a flow chart of another multi-chip substrate-level packaging method provided by an embodiment of the present invention; Figure 6 yes Figure 5 The structural flow chart of the multi-chip substrate level packaging method shown; Figure 7 It is a flow chart of another multi-chip substrate-level packaging method provided by an embodiment of the present invention; Figure 8 yes Figure 7 The structural flow chart of the multi-chip substrate level packaging method shown; Fig. 9 It is a structural schematic diagram of a multi-chip substrate-level packaging structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0018] Figure 1 is a flow chart of a multi-chip substrate-level packaging method provided by an embodiment of the present invention, Figure 2 yes Figure 1 The structure flow chart of the multi-chip substrate level packaging method shown in FIG. 1 is applicable to the processing process of the multi-chip packaging process, and the multi-chip substrate level packaging method can be used to prepare a multi-chip substrate level packaging structure. Figure 1 and Figure 2 As shown, the packaging method includes: S110, providing a substrate; wherein the substrate comprises a first surface and a second surface which are opposite to each other, and the first surface comprises a plurality of groove accommodating areas and a cutting area located between two adjacent groove accommodating areas.

[0019] Specifically, refer to Figure 2 a) part, providing a substrate 101. The substrate 101 includes first surfaces (which can be understood as Figure 2 a) shows the upper surface of the substrate 101) and the second surface (which can be understood as Figure 2The lower surface of the substrate 101 shown in part a) of the figure). The first surface includes a plurality of groove accommodating areas 102 and a cutting area located between two adjacent groove accommodating areas 102. The groove accommodating area 102 can be used to accommodate the chip to be packaged later. After the chip packaging is completed, the cutting area can be cut to obtain the package body corresponding to the separated single chip. Exemplarily, the substrate 101 can be a substrate 101 that has been smoothly polished and has a flat surface, and then a groove-shaped groove accommodating area 102 is processed on the first surface of the substrate 101 through laser and wet etching processes. Exemplarily, Figure 2 In part a), only the first surface of the substrate 101 including three groove accommodating areas 102 is used as an example for drawing and explanation. This embodiment does not make specific requirements and special restrictions on the type of the substrate 101, which can be reasonably selected according to the operation requirements. For example, the material of the substrate 101 can be glass, silicon-based, etc. Also, this embodiment does not make specific requirements and special restrictions on the size of the substrate 101, which can be reasonably selected according to the operation requirements. For example, the thickness of the substrate 101 can be 150μm-200μm.

[0020] S120. Place chips of different types in the groove accommodating area one by one, and the third surface of each chip faces the bottom of the groove accommodating area; wherein the number of chips is the same as the number of groove accommodating areas, the third surface of the chip includes an electrode structure, and in the thickness direction of the substrate, the depression depth of the groove accommodating area is greater than the thickness of each chip.

[0021] Specifically, refer to Figure 2 Part b) of this embodiment relates to the packaging process of radio frequency chips. For example, radio frequency chips include filter chips, power amplifier chips, low noise amplifier chips, radio frequency switch chips, antenna tuning switch chips, etc. It should be noted that the chip descriptions involved in this embodiment can be understood as radio frequency chips. The chip mounting process can be used to place different types of chips in the groove accommodating area 102 one by one. The number of chips is the same as the number of groove accommodating areas 102. For example, Figure 2 In part b), only three groove accommodating areas 102 and three chips (201, 202, 203) are used as examples for drawing and explanation. Of course, the number of chips and the number of groove accommodating areas 102 can be flexibly matched. In addition, in order to achieve the reliability and sealing of chip packaging, in the thickness direction of the substrate 101, the depression depth of the groove accommodating area 102 is greater than the thickness of each chip, and the spatial volume of the groove accommodating area 102 is greater than the volume of each chip, so that each groove accommodating area 102 can wrap the corresponding chip, thereby achieving a substrate-level packaging effect of multiple chips.

[0022] Different types of chips are placed in the groove receiving area 102 in a one-to-one correspondence, and the third surface (which can be understood as Figure 2 b) of the chip) faces the bottom of the groove accommodating area 102. Wherein, the third surface of the chip includes a key functional structure m and an electrode structure n. The third surface of the chip can also be understood as the front side of the chip, that is, the chip is flipped in the corresponding groove accommodating area 102. Exemplarily, each chip includes a key functional structure m, and the key functional structure m includes the interdigital transducer area of ​​the surface acoustic wave filter, the resonant cavity area of ​​the bulk acoustic wave filter, etc. The key functional structure m is the working area of ​​the chip. In a specific embodiment, a cavity structure is provided at the key functional structure m of the chip to protect the key functional structure m from being contacted by the plastic packaging material. Exemplarily, each chip includes two electrode structures n, which can be understood as a positive electrode and a negative electrode, respectively. The electrode structure n is the area where the chip is electrically connected.

[0023] S130, performing injection molding on each chip to encapsulate each chip in a plastic encapsulation layer; wherein, in the thickness direction of the substrate, the depression depth of the groove accommodating area is the same as the thickness of the plastic encapsulation layer.

[0024] Specifically, refer to Figure 2c) part, an injection molding process can be used to form a plastic encapsulation layer 104 on the surface side of the chip away from the bottom of the groove accommodating area 102, and due to the fluidity of the plastic encapsulation layer 104, each surface of the chip can contact the plastic encapsulation layer 104, so that each chip is encapsulated in the plastic encapsulation layer 104. The plastic encapsulation layer 104 can not only protect the chip, but also fix the position of the chip, effectively improving the reliability of chip packaging. It should be noted that in the thickness direction of the substrate 101, the depression depth of the groove accommodating area 102 is the same as the thickness of the plastic encapsulation layer 104, that is, at this time it can be understood that the plastic encapsulation layer 104 is filled and formed in each groove accommodating area 102, and the main body of the packaging structure corresponding to each chip is the substrate 101, and the chip in each groove accommodating area 102 is actually wrapped by the substrate 101 material to achieve packaging. In this way, each chip is fixed in the corresponding plastic layer 104 to form a separate package, and the cutting area of ​​the substrate 101 also separates the plastic layer 104 into separate film layer areas. The plastic layer 104 is not a whole layer, and the plastic layers 104 between adjacent groove accommodating areas 102 do not contact each other, which can effectively avoid the influence of the high warpage of the plastic layer 104 set as a whole layer on the difficulty of the chip packaging process. The comparison of the warpage described in this embodiment is based on the fact that the material of the plastic layer 104 is different from that of the substrate 101. The result of the comparison between the two is that the warpage generated by the substrate 101 is lower, and the warpage generated by the plastic layer 104 is higher. This embodiment does not make specific requirements and special limitations on the material of the plastic layer 104, and it can be reasonably selected according to the operation requirements. For example, the material of the plastic layer 104 can be a plastic material, a polymer, a resin, etc.

[0025] In addition, illustratively, in order to further realize the ultra-thin design of the overall package product, in the thickness direction of the substrate 101, under the premise that the thickness of each chip is constant, the thickness of the plastic encapsulation layer 104 on the side of the surface of the chip away from the bottom of the groove accommodating area 102 can be reduced as much as possible, that is, the distance between the top surface of the plastic encapsulation layer 104 and the bottom of the groove accommodating area 102 is reduced. In other words, the closer the concave depth of the groove accommodating area 102 is to the thickness of the chip, the thinner the overall package product thickness is.

[0026] S140, performing through-hole fabrication processing on the second surface until a portion of the electrode structure of each chip is exposed.

[0027] Specifically, refer to Figure 2d) part, a through-hole manufacturing process is performed on the second surface of the substrate 101 until a portion of the electrode structure n of each chip is exposed. Exemplarily, the substrate 101 may be a glass substrate 101, and a through-hole 301 may be processed on the second surface of the substrate 101 at a position corresponding to the electrode structure n of each chip according to the TGV (through glass via) through-hole manufacturing process and a laser-induced humidification etching process. It can be understood that the through-hole 301 extends from the second surface of the substrate 101 to the electrode structure n of the corresponding chip. The TGV process can realize ultra-thin glass processing. Exemplarily, in the extension direction from the second surface of the substrate 101 to the electrode structure n of the corresponding chip, if there is a plastic sealing layer 104, a laser may be additionally used to burn through the plastic sealing layer 104 at this position, so as to expose the electrode structure n of the chip corresponding to the position of the plastic sealing layer 104.

[0028] S150, forming a metal interconnection circuit on the second surface, and the metal interconnection circuit is electrically connected to the corresponding electrode structure through the through hole.

[0029] Specifically, refer to Figure 2 e) part, a metal interconnection line is formed on the second surface of the substrate 101, and the metal interconnection line is electrically connected to the electrode structure n of the corresponding chip through the through hole 301, so that the electrode structure n of the subsequent chip is electrically connected to other lines via the metal interconnection line, thereby realizing the conversion of the chip to the entire packaged product. Exemplarily, at least part of the structure of the metal interconnection line can be filled in each through hole 301 (the filling material can be a conductive metal 302), and at least part of the other structure of the metal interconnection line can be formed on the second surface of the substrate 101. In fact, the layout position of the metal interconnection line can be determined according to the electrical connection requirements of the chip and the actual operation requirements. This embodiment does not make specific requirements and special restrictions on the material of the metal interconnection line, and it can be reasonably selected according to the operation requirements. Exemplarily, the material of the metal interconnection line can be Al, Cu, Ti, Ni, Sn metal or its alloy, etc., to ensure that the metal interconnection line has high conductivity.

[0030] According to the technical solution in the embodiment of the present invention, a plurality of groove accommodating areas are arranged on the substrate, and a plurality of chips of different types are placed in the corresponding groove accommodating areas respectively. After each chip is subjected to injection molding and plastic encapsulation, the depression depth of the groove accommodating area is the same as the thickness of the plastic encapsulation layer, that is, the plastic encapsulation layer is filled and formed in each groove accommodating area. The main body of the packaging structure corresponding to each chip is the substrate, and the chip in each groove accommodating area is actually wrapped by the substrate material to achieve packaging, which effectively improves the warpage of multi-chip integration, reduces the difficulty of the packaging process, improves the preparation yield, reliability and durability of chip packaging, avoids the processing difficulties and stress caused by the large warping during the packaging process that affect the chip reliability, the glass substrate has excellent electrical insulation performance, is suitable for high-frequency performance chip packaging, and is conducive to reducing interference between metal interconnection lines, and the multi-chip packaging process is a one-time packaging of multiple chips, different types of chips can be freely combined, and multiple chip packages are integrated while relatively reducing the package size, simplifying the packaging process of multiple chips, improving the chip packaging efficiency, and reducing production costs.

[0031] Figure 3 is a flow chart of another multi-chip substrate-level packaging method provided by an embodiment of the present invention, Figure 4 yes Figure 3 The structural flow chart of the multi-chip substrate level packaging method shown in the figure is optimized on the basis of the above embodiment. Optionally, the third surface of the chip also includes a key functional structure; Placing different types of chips in the groove accommodating area one by one, with the third surface of each chip facing the bottom of the groove accommodating area, including: An annular wall structure is provided in the groove accommodation area; The corresponding chip is placed in the groove accommodating area, and a sealed cavity structure is formed by an annular wall structure, the bottom of the groove accommodating area and the key functional structure of the chip; wherein, in the thickness direction of the substrate, the sum of the thickness of the chip and the thickness of the annular wall structure is less than the depression depth of the corresponding groove accommodating area.

[0032] For details not yet provided in this embodiment, please refer to the above embodiments. Figure 3 and Figure 4 As shown, the packaging method includes: S210, providing a substrate; wherein the substrate comprises a first surface and a second surface which are opposite to each other, and the first surface comprises a plurality of groove accommodating areas and a cutting area located between two adjacent groove accommodating areas.

[0033] S220. Set up a ring-shaped wall structure in the groove accommodating area.

[0034] Specifically, refer to Figure 4b) part, the third surface of the chip includes the key functional structure m and the electrode structure n, and the third surface of the chip can also be understood as the front of the chip. Exemplarily, each chip includes a key functional structure m, and the key functional structure m includes the interdigital transducer area of ​​the surface acoustic wave filter, the resonant cavity area of ​​the bulk acoustic wave filter, etc. The key functional structure m is the working area of ​​the chip. In a specific embodiment, a cavity structure is provided at the key functional structure m of the chip to protect the key functional structure m from being contacted by the plastic packaging material. That is, a cavity structure can be first provided at the key functional structure m of the chip, and then the chip can be flipped and placed in the corresponding groove accommodating area 102.

[0035] In another specific embodiment, if the key functional structure m of the chip is not provided with a cavity structure, an additional annular wall structure 103 may be provided in the groove accommodating area 102, so that the annular wall structure 103 can subsequently seal and protect the key functional structure m of the chip, thereby preventing the subsequent plastic encapsulation layer 104 from contacting the key functional structure m of the chip and causing the normal operation of the chip to fail. Exemplarily, the annular wall structure 103 may be processed at the bottom of the groove accommodating area 102, corresponding to the area of ​​the key functional structure m of the chip that needs to be protected, by a photolithography process.

[0036] S230, placing the corresponding chip in the groove accommodating area, and forming a sealed cavity structure consisting of an annular wall structure, the bottom of the groove accommodating area and the key functional structure of the chip; wherein, in the thickness direction of the substrate, the sum of the thickness of the chip and the thickness of the annular wall structure is less than the depression depth of the corresponding groove accommodating area.

[0037] Specifically, refer to Figure 4 c) part, the corresponding chip is placed in the groove receiving area 102, and a sealed cavity structure consisting of the annular wall structure 103, the bottom of the groove receiving area 102 and the key functional structure m of the chip is formed. That is, the third surface of the chip (which can be understood as Figure 4c) of the chip) faces the bottom of the groove accommodating area 102. At this time, the sealed cavity structure can protect the key functional structure m of the chip, separate the key functional structure m of the chip from the subsequent plastic encapsulation layer 104, and avoid the key functional structure m of the subsequent chip from contacting the plastic encapsulation layer 104 and affecting the operation of the chip. It should be noted that, exemplarily, the substrate 101 can be a glass substrate, and the cavity formed by the glass substrate has a large strength, which is beneficial to the sealing protection of the chip and improves the reliability of the chip packaging. In addition, in order to achieve the reliability and sealing of the chip packaging, in the thickness direction of the substrate 101, the sum of the thickness of the chip and the thickness of the annular wall structure 103 is less than the depression depth of the corresponding groove accommodating area 102, so that each groove accommodating area 102 can wrap the corresponding chip, thereby achieving the substrate-level packaging effect of multiple chips.

[0038] S240, performing injection molding on each chip to encapsulate each chip in a plastic encapsulation layer; wherein, in the thickness direction of the substrate, the depression depth of the groove accommodating area is the same as the thickness of the plastic encapsulation layer.

[0039] S250, performing through-hole fabrication processing on the second surface until a portion of the electrode structure of each chip is exposed.

[0040] S260, forming a metal interconnection circuit on the second surface, and the metal interconnection circuit is electrically connected to the corresponding electrode structure through the through hole.

[0041] Figure 5 is a flow chart of another multi-chip substrate-level packaging method provided by an embodiment of the present invention. Figure 6 yes Figure 5 The structural flow chart of the multi-chip substrate-level packaging method shown in the figure is optimized on the basis of the above embodiment. Optionally, each chip is subjected to injection molding to encapsulate each chip in a plastic layer, including: Performing injection molding on each chip to form a plastic packaging layer covering the first surface of the substrate and each chip; The plastic sealing layer is thinned until the cutting area on the first surface is exposed.

[0042] For details not yet provided in this embodiment, please refer to the above embodiments. Figure 5 and Figure 6 As shown, the packaging method includes: S310, providing a substrate; wherein the substrate comprises a first surface and a second surface which are opposite to each other, and the first surface comprises a plurality of groove accommodating areas and a cutting area located between two adjacent groove accommodating areas.

[0043] S320. Place chips of different types in the groove accommodating area one by one, and the third surface of each chip faces the bottom of the groove accommodating area; wherein the number of chips is the same as the number of groove accommodating areas, the third surface of the chip includes an electrode structure, and in the thickness direction of the substrate, the depression depth of the groove accommodating area is greater than the thickness of each chip.

[0044] S330, performing injection molding and encapsulation processing on each chip to form an encapsulation layer covering the first surface of the substrate and each chip.

[0045] Specifically, refer to Figure 6 c) of the substrate 101, an injection molding process can be used to form a molding layer 104 on the surface of the chip away from the bottom of the groove accommodating area 102, and due to the fluidity of the molding layer 104, each surface of the chip can contact the molding layer 104, so that each chip is covered in the molding layer 104. At the same time, in order to ensure the sealing effect of the molding layer 104 on each chip, a molding layer 104 is also formed on the first surface of the substrate 101. Each chip has a third surface (which can be understood as Figure 6 c) shows the lower surface of the chip) and the fourth surface (which can be understood as Figure 6 The upper surface of the chip shown in part c) of the substrate 101 is covered by the plastic layer 104, and each chip is in the groove accommodating area 102 corresponding to the substrate 101. At this time, there is a plastic layer 104 that is in contact with each other and is similar to a whole layer above the first surface of the substrate 101. This part of the plastic layer 104 is not conducive to the ultra-thin design of the chip package, and there will be a problem of large warpage after multi-chip integration due to the large difference in thermal expansion coefficient between the plastic layer 104 and the chip. Therefore, this part of the plastic layer 104 can be thinned.

[0046] S340, thinning the plastic sealing layer until the cutting area on the first surface is exposed.

[0047] Specifically, refer to Figure 6 d) part, the plastic encapsulation layer 104 can be thinned by a thinning process until the cutting area on the first surface of the substrate 101 is exposed. Exemplarily, the thinning process includes grinding, etching, etc. Exemplarily, the plastic encapsulation layer 104 on one side of the first surface of the substrate 101 can be grinded by a grinding process to remove part of the structure of the plastic encapsulation layer 104 in the thickness direction, so that the plastic encapsulation layer 104 on one side of the first surface of the substrate 101 is thinned to a target thickness, that is, in the thickness direction of the substrate 101, the thickness of the plastic encapsulation layer 104 is the same as the depression depth of the groove accommodating area 102, wherein the target thickness can be determined according to different depression depths of the groove accommodating area 102.

[0048] In addition, illustratively, in order to further realize the ultra-thin design of the overall packaged product, in the thickness direction of the substrate 101, under the premise that the thickness of each chip is constant, the thickness of the plastic encapsulation layer 104 on the side of the surface of the chip away from the bottom of the groove accommodating area 102 can be reduced as much as possible, that is, the distance between the top surface of the plastic encapsulation layer 104 and the bottom of the groove accommodating area 102 is reduced. In other words, the closer the depth of the depression of the groove accommodating area 102 is to the thickness of the chip, the thinner the thickness of the overall packaged product. In other words, after the plastic encapsulation layer 104 is thinned until the cutting area on the first surface of the substrate 101 is exposed, the plastic encapsulation layer 104 and the first surface of the substrate 101 can continue to be thinned, but the fourth surface of the chip cannot be exposed at this time. In this way, the thickness of the chip packaging structure can be further reduced.

[0049] Optionally, while thinning the plastic encapsulation layer until the cutting area on the first surface is exposed, the method further includes: thinning one side of the second surface of the substrate.

[0050] Specifically, if there is a need for ultra-thin packaging of the chip in this embodiment, a double-sided thinning process can also be used to thin the plastic sealing layer on the first surface side of the substrate and the second surface side of the substrate at the same time, but the key functional structure m of the chip cannot be exposed at this time. In this way, the thickness of the chip packaging structure can be further reduced to meet the packaging requirements of different thicknesses. In addition, the thinning process sequence of the first surface and the second surface of the substrate in this embodiment is only for example and not for limitation. For example, the plastic sealing layer on the first surface side of the substrate can be thinned first, and then the second surface side of the substrate can be thinned, or the second surface side of the substrate can be thinned first, and then the plastic sealing layer on the first surface side of the substrate can be thinned.

[0051] S350, performing through-hole fabrication processing on the second surface until a portion of the electrode structure of each chip is exposed.

[0052] S360, forming a metal interconnection circuit on the second surface, and the metal interconnection circuit is electrically connected to the corresponding electrode structure through the through hole.

[0053] Figure 7 is a flow chart of another multi-chip substrate-level packaging method provided by an embodiment of the present invention. Figure 8 yes Figure 7 The structural flow chart of the multi-chip substrate level packaging method shown in the figure is optimized on the basis of the above embodiment. Optionally, the metal interconnection line includes a plurality of metal interconnection lines and a rewiring layer; A metal interconnection circuit is formed on the second surface, and the metal interconnection circuit is electrically connected to the corresponding electrode structure through a through hole, including: Filling each through hole with a conductive metal to form a corresponding metal interconnection line; A rewiring process is performed on the second surface to redefine the positions of the metal interconnection lines to form a rewiring layer, and the rewiring layer is connected to the through hole and is electrically connected to the corresponding electrode structure through the conductive metal in the through hole.

[0054] Further, after performing a rewiring process on the second surface to redefine the position of each metal interconnection line to form a rewiring layer, and the rewiring layer is connected to the through hole and electrically connected to the corresponding electrode structure through the conductive metal in the through hole, it also includes: A solder resist insulating layer is formed on a side of the rewiring layer away from the second surface, and windows are opened on the solder resist insulating layer to form convex solder balls, wherein the convex solder balls are electrically connected to the rewiring layer.

[0055] For details not yet provided in this embodiment, please refer to the above embodiments. Figure 7 and Figure 8 As shown, the packaging method includes: S410, providing a substrate; wherein the substrate comprises a first surface and a second surface which are opposite to each other, and the first surface comprises a plurality of groove accommodating areas and a cutting area located between two adjacent groove accommodating areas.

[0056] S420. Place chips of different types in the groove accommodating area in a one-to-one correspondence, with the third surface of each chip facing the bottom of the groove accommodating area; wherein the number of chips is the same as the number of groove accommodating areas, the third surface of the chip includes an electrode structure, and in the thickness direction of the substrate, the depression depth of the groove accommodating area is greater than the thickness of each chip.

[0057] S430, performing injection molding on each chip to encapsulate each chip in a plastic encapsulation layer; wherein, in the thickness direction of the substrate, the depression depth of the groove accommodating area is the same as the thickness of the plastic encapsulation layer.

[0058] S440, performing through-hole fabrication processing on the second surface until a portion of the electrode structure of each chip is exposed.

[0059] S450, filling each of the manufactured through holes with a conductive metal to form corresponding metal interconnection lines.

[0060] Specifically, refer to Figure 8 e) of the chip, the conductive metal 302 may be filled in each through hole 301 by deposition, photolithography, electroplating, degumming and etching processes to form a corresponding metal interconnection line, which is electrically connected to the electrode structure n of the corresponding chip. Exemplarily, the metal interconnection line can be understood as a structure formed by filling the conductive metal 302 in the through hole 301. Exemplarily, the conductive metal 302 may be a metal such as copper.

[0061] S460, performing rewiring processing on the second surface to redefine the position of each metal interconnection line to form a rewiring layer, and the rewiring layer is connected to the through hole and is electrically connected to the corresponding electrode structure through the conductive metal in the through hole.

[0062] Specifically, refer to Figure 8 f) part, a rewiring process can be performed on the second surface of the substrate 101 by using processes such as deposition, electroplating, photolithography and etching to redefine the position of each metal interconnection line to form a rewiring layer, and the rewiring layer is connected to the through hole 301, and is electrically connected to the corresponding electrode structure n through the conductive metal 302 in the through hole 301. Exemplarily, the metal interconnection line is electrically connected to the electrode structure n of the corresponding chip, and the rewiring layer is electrically connected to the metal interconnection line. In this way, the electrode structure n of the subsequent chip can be electrically connected to other lines in sequence through the metal interconnection line, the rewiring layer, so as to achieve normal operation of the chip. Exemplarily, the thickness of the rewiring layer can be 1μm-2μm.

[0063] S470, forming a solder resist insulating layer on a side of the rewiring layer away from the second surface, opening windows on the solder resist insulating layer and making raised solder balls; wherein the raised solder balls are electrically connected to the rewiring layer.

[0064] Specifically, refer to Figure 8 g) part, photolithography and ball planting processes can be used to form a solder resist insulating layer 303 on the side of the rewiring layer away from the second surface of the substrate 101, and a window is opened on the solder resist insulating layer 303 to make a raised solder ball 304; wherein the raised solder ball 304 is electrically connected to the rewiring layer. The solder resist insulating layer 303 can protect the metal interconnection line and the rewiring layer, and the raised solder ball 304 can position the metal interconnection line and the rewiring layer, so that other subsequent circuits can be electrically connected to the corresponding metal interconnection line and the rewiring layer through the raised solder ball 304, and then realize the electrical connection relationship with the electrode structure n of the corresponding chip.

[0065] After completing the preparation process of the solder resist insulating layer 303 and the raised solder balls 304, the main packaging process is completed. Then, it can be separated into single packages through a cutting process. Then, through a cutting process, the cutting area on the first surface of the substrate 101 is cut to separate into single packages corresponding to each chip. At this time, the five surfaces of each package are wrapped and packaged by the substrate 101, and the other side of the package is wrapped and packaged by the plastic layer 104, and the chip corresponding to the package is completely wrapped and packaged by the substrate 101. Based on the excellent performance of the substrate 101, the reliability of the package is also effectively improved, and the warping of the package is reduced, which is conducive to the realization of the ultra-thin size design of the package.

[0066] Based on the same inventive concept, an embodiment of the present invention further provides a multi-chip substrate-level packaging structure. Fig. 9 is a schematic diagram of a multi-chip substrate-level packaging structure provided by an embodiment of the present invention, such as Fig. 9 As shown, the multi-chip substrate-level packaging structure can be manufactured by a multi-chip substrate-level packaging method as provided in any one of the embodiments of the present invention. It can be understood that since the multi-chip substrate-level packaging structure provided in the embodiment of the present invention is manufactured by the multi-chip substrate-level packaging method described in any one of the embodiments of the present invention, the multi-chip substrate-level packaging structure provided in the embodiment of the present invention has the technical features of the structure of each preparation process in the multi-chip substrate-level packaging method provided in the embodiment of the present invention, and can achieve similar beneficial effects as the multi-chip substrate-level packaging method provided in the embodiment of the present invention. The similarities can be referred to the above description and will not be repeated here.

[0067] Optionally, continue to refer to Figure 2 and Fig. 9 The multi-chip substrate-level packaging structure prepared by the multi-chip substrate-level packaging method according to the embodiment of the present invention comprises a substrate 101, chips of different types (exemplarily, Fig. 9 Only three chips (201, 202, 203) are taken as examples for drawing and explanation), a plastic encapsulation layer 104 and metal interconnection lines; wherein, the substrate 101 includes a first surface and a second surface which are opposite to each other, the first surface includes a plurality of groove accommodating areas 102 and a cutting area located between two adjacent groove accommodating areas 102; the chips are placed one by one in the groove accommodating areas 102, and the third surface of each chip faces the bottom of the groove accommodating area 102; wherein, the number of chips is the same as the number of groove accommodating areas 102, the third surface of the chip includes an electrode structure n, and in the thickness direction of the substrate 101, the recessed depth of the groove accommodating area 102 is greater than the thickness of each chip; the plastic encapsulation layer 104 covers each chip; wherein, in the thickness direction of the substrate 101, the recessed depth of the groove accommodating area 102 is the same as the thickness of the plastic encapsulation layer 104; the metal interconnection lines are arranged on the second surface, and the metal interconnection lines are electrically connected to the corresponding electrode structure n through the through hole 301.

[0068] Optionally, the substrate 101 includes a glass substrate and a silicon-based substrate. It should be noted that the glass substrate has excellent performance, the plastic sealing layer 104 is filled and formed in each groove accommodating area 102, the main body of the packaging structure corresponding to each chip is the substrate 101, and the chip in each groove accommodating area 102 is actually wrapped by the substrate 101 material to achieve packaging. Based on the obvious advantages of the glass substrate in terms of hardness and thermal expansion coefficient, the warpage of the multi-chip integration can be reduced, the warpage of the multi-chip package is improved, and it is conducive to reducing the processing difficulty of chip packaging, avoiding the processing difficulties and stress caused by the large warpage during the packaging process that affect the chip reliability. In addition, the advantages of the glass substrate in terms of dielectric constant, the insulation performance of the glass substrate is more conducive to the electron migration process in the metal circuit, and is also suitable for high-frequency performance chip packaging. It has excellent electrical insulation performance for high-frequency chip packaging, which can reduce interference between circuits. The glass substrate has better sealing and higher packaging strength. The glass substrate can be processed into a through hole 301 using the TGV process to realize the processing of ultra-thin glass, that is, to realize the ultra-thin packaging design of the chip.

[0069] Optionally, continue to refer to Fig. 9 , the third surface of the chip includes a key functional structure m and an electrode structure n, and the third surface of the chip can also be understood as the front of the chip. Exemplarily, each chip includes a key functional structure m, and the key functional structure m includes the interdigital transducer area of ​​the surface acoustic wave filter, the resonant cavity area of ​​the bulk acoustic wave filter, etc. The key functional structure m is the area where the chip works. In a specific embodiment, the multi-chip substrate-level packaging structure also includes an annular wall structure 103, and the annular wall structure 103 is located at the bottom of the groove accommodating area 102. The corresponding chip is placed in the groove accommodating area 102, and the annular wall structure 103, the bottom of the groove accommodating area 102 and the key functional structure m of the chip can form a sealed cavity structure. The sealed cavity structure can protect the key functional structure m of the chip, separate the key functional structure m of the chip from the subsequent plastic sealing layer 104, and prevent the key functional structure m of the subsequent chip from contacting the plastic sealing layer 104 and affecting the operation of the chip. In the thickness direction of the substrate 101 , the sum of the thickness of the chip and the thickness of the annular wall structure 103 is less than the depression depth of the corresponding groove accommodating area 102 .

[0070] Optionally, continue to refer to Fig. 9, the metal interconnection line includes a plurality of metal interconnection lines and a rewiring layer. Among them, when the conductive metal 302 is filled in each through hole 301, a metal interconnection line is formed accordingly, and the metal interconnection line is electrically connected to the electrode structure n of the corresponding chip. The rewiring layer is located on the second surface of the substrate 101, and the rewiring layer is connected to the through hole 301, and is electrically connected to the corresponding electrode structure n through the conductive metal 302 in the through hole 301. Exemplarily, the metal interconnection line is electrically connected to the electrode structure n of the corresponding chip, and the rewiring layer is electrically connected to the metal interconnection line. In this way, the electrode structure n of the subsequent chip can be electrically connected to other lines in sequence via the metal interconnection line, the rewiring layer, so as to achieve normal operation of the chip.

[0071] Optionally, continue to refer to Fig. 9 The multi-chip substrate-level packaging structure also includes a solder resist insulating layer 303 and a bump solder ball 304. The solder resist insulating layer 303 is located on the side of the rewiring layer away from the second surface of the substrate 101, a window is opened on the solder resist insulating layer 303 and a bump solder ball 304 is made, and the bump solder ball 304 is electrically connected to the rewiring layer. The solder resist insulating layer 303 can protect the metal interconnection line and the rewiring layer, and the bump solder ball 304 can position the metal interconnection line and the rewiring layer, so that other subsequent circuits can be electrically connected to the corresponding metal interconnection line and the rewiring layer through the bump solder ball 304, and then realize the electrical connection relationship with the electrode structure n of the corresponding chip.

[0072] Based on the same inventive concept, an embodiment of the present invention further provides a radio frequency chip, which can be obtained by cutting along the cutting area in the multi-chip substrate-level packaging structure provided in any one of the embodiments of the present invention. Exemplarily, the radio frequency chip includes a filter chip, a power amplifier chip, a low-noise amplifier chip, a radio frequency switch chip, an antenna tuning switch chip, etc. It can be understood that since the radio frequency chip provided by the embodiment of the present invention is made by cutting along the cutting area of ​​the multi-chip substrate-level packaging structure described in any embodiment of the present invention, the radio frequency chip provided by the embodiment of the present invention has the technical characteristics of the multi-chip substrate-level packaging structure provided by the embodiment of the present invention, and can achieve the beneficial effects of the filter wafer-level packaging structure provided by the embodiment of the present invention. The similarities can be referred to the above description and will not be repeated here.

[0073] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A multi-chip substrate level packaging method, It is characterized in that include: A substrate is provided; wherein the substrate comprises a first surface and a second surface which are opposite to each other, the first surface comprises a plurality of groove accommodating areas and a cutting area located between two adjacent groove accommodating areas; Placing chips of different types in the groove accommodating area in a one-to-one correspondence, and the third surface of each chip faces the bottom of the groove accommodating area; wherein the number of the chips is the same as the number of the groove accommodating areas, the third surface of the chip includes an electrode structure, and in the thickness direction of the substrate, the recessed depth of the groove accommodating area is greater than the thickness of each chip; Performing injection molding on each of the chips to encapsulate each of the chips in a plastic layer; wherein, in the thickness direction of the substrate, the depression depth of the groove accommodating area is the same as the thickness of the plastic layer; Performing a through-hole manufacturing process on the second surface until a portion of the electrode structure of each chip is exposed; A metal interconnection line is formed on the second surface, and the metal interconnection line is electrically connected to the corresponding electrode structure through a through hole.

2. The multi-chip substrate level packaging method according to claim 1, It is characterized in that The third surface of the chip also includes a key functional structure; Placing different types of chips in the groove accommodating area one by one, with the third surface of each chip facing the bottom of the groove accommodating area, comprising: An annular wall structure is provided in the groove accommodating area; The corresponding chip is placed in the groove accommodating area, and a sealed cavity structure is formed by the annular wall structure, the bottom of the groove accommodating area and the key functional structure of the chip; wherein, in the thickness direction of the substrate, the sum of the thickness of the chip and the thickness of the annular wall structure is less than the depression depth of the corresponding groove accommodating area.

3. The multi-chip substrate level packaging method according to claim 1, It is characterized in that Performing injection molding on each of the chips to encapsulate each of the chips in a plastic layer, including: Performing injection molding on each of the chips to form a plastic encapsulation layer covering the first surface of the substrate and each of the chips; The plastic sealing layer is thinned until the cutting area on the first surface is exposed.

4. The multi-chip substrate level packaging method according to claim 3, It is characterized in that The method further comprises: performing a thinning process on the plastic sealing layer until the cutting area on the first surface is exposed; The second surface of the substrate is thinned.

5. The multi-chip substrate level packaging method according to claim 1, It is characterized in that The metal interconnection circuit includes a plurality of metal interconnection lines and a rewiring layer; A metal interconnection circuit is formed on the second surface, and the metal interconnection circuit is electrically connected to the corresponding electrode structure through a through hole, comprising: Filling each of the through holes with conductive metal to form the corresponding metal interconnection lines; A rewiring process is performed on the second surface to redefine the position of each metal interconnection line to form the rewiring layer, and the rewiring layer is connected to the through hole and is electrically connected to the corresponding electrode structure through the conductive metal in the through hole.

6. The multi-chip substrate level packaging method according to claim 5, It is characterized in that After performing rewiring processing on the second surface to redefine the position of each metal interconnection line to form the rewiring layer, and the rewiring layer is connected to the through hole and electrically connected to the corresponding electrode structure through the conductive metal in the through hole, the method further includes: A solder resist insulating layer is formed on a side of the rewiring layer away from the second surface, and windows are opened on the solder resist insulating layer to form convex solder balls; wherein the convex solder balls are electrically connected to the rewiring layer.

7. The multi-chip substrate level packaging method according to claim 1, It is characterized in that The substrate includes a glass substrate and a silicon-based substrate.

8. A multi-chip substrate level packaging structure, It is characterized in that The multi-chip substrate-level packaging method is used as described in any one of claims 1 to 7.

9. The multi-chip substrate level packaging structure according to claim 8, It is characterized in that include: A substrate, the substrate comprising a first surface and a second surface facing away from each other, the first surface comprising a plurality of groove accommodating areas and a cutting area located between two adjacent groove accommodating areas; Different types of chips are placed in the groove accommodating area in a one-to-one correspondence, and the third surface of each chip faces the bottom of the groove accommodating area; wherein the number of the chips is the same as the number of the groove accommodating areas, the third surface of the chip includes an electrode structure, and in the thickness direction of the substrate, the recessed depth of the groove accommodating area is greater than the thickness of each chip; A plastic encapsulation layer, the plastic encapsulation layer covers each of the chips; wherein, in the thickness direction of the substrate, the depression depth of the groove accommodating area is the same as the thickness of the plastic encapsulation layer; A metal interconnection circuit is disposed on the second surface and is electrically connected to the corresponding electrode structure through a through hole.

10. A radio frequency chip, It is characterized in that The method is obtained by cutting along the cutting area in the multi-chip substrate level packaging structure according to any one of claims 8 to 9.

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