Semiconductor wafer and method for manufacturing same
Through a series of etching processes and back-side invisible segmentation processes, the cracks and fragmentation problems during semiconductor wafer segmentation are solved, and higher segmentation accuracy and quality are achieved.
Patent Information
- Application Number
- CN202311230690.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-09
- Filing Date
- 2023-09-22
- Publication Date
- 2024-12-10
AI Technical Summary
During the semiconductor wafer processing process, the top metal pad is prone to unnecessary cracks, fragmentation or errors when dividing the wafer, resulting in problems during the manufacturing process.
Using a series of etching processes including first dry etching, first wet etching, second wet etching and second dry etching, the interconnect structure and metallization layer are gradually removed, forming hollow channels, and in the substrate through the back side invisible segmentation process. Induces cracks, thereby segmenting the semiconductor wafer.
It effectively reduces fragmentation and errors when separating semiconductor wafers, and improves segmentation accuracy and quality.
Smart Images
Figure CN119108345A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor chip and a method for manufacturing the semiconductor chip. Background Art
[0002] In semiconductor wafer processing, integrated circuits are formed on wafers (also called substrates) made of silicon or other semiconductor materials. During the formation of integrated circuits, the wafer is "sliced" to separate the individual chips from each other for packaging. However, the top metal pads present in the scribe line area may cause unwanted crack propagation, chipping, or errors when slicing the wafer.
[0003] Therefore, how to provide a wafer manufacturing method to solve the above problems has become an important issue that needs to be solved urgently in the industry. Summary of the invention
[0004] The present disclosure provides a method for manufacturing a semiconductor wafer, comprising the following steps. A first dry etching process is performed to remove a top metallization layer, so that after removing the top metallization layer, a portion of an interconnect structure is exposed through a scribe opening, wherein the interconnect structure is embedded in a dielectric layer. A first wet etching process is performed using a first etchant to remove a filling layer of the interconnect structure. After performing the first wet etching process, a second wet etching process is performed using a second etchant to remove a glue layer of the interconnect structure. A second dry etching process is performed to remove the dielectric layer and stop at the bottom metallization layer, wherein the scribe opening is deepened and a scribe opening area is formed. A back side invisible splitting process is performed to induce cracks in the substrate from the back side to the front side, thereby splitting the semiconductor wafer into semiconductor chips.
[0005] In some embodiments, the method further comprises forming a photoresist to protect the device region and define a scribe line opening before the first dry etching process, wherein the top metallization layer is exposed in the scribe line opening.
[0006] In some embodiments, the method further includes stripping the photoresist after the second dry etching process.
[0007] In some embodiments, the interconnect structure includes multiple wires extending laterally in the dielectric layer, each wire including a filling layer and a glue layer; and multiple conductive vias extending vertically in the dielectric layer, each conductive via including a filling layer and a glue layer; wherein the conductive vias connect wires of different layers.
[0008] In some embodiments, the method further includes repeating the first wet etching process and the second wet etching process more than once until the interconnect structure is completely removed, wherein the filling layer and the glue layer of each conductive line are removed respectively, and the filling layer and the glue layer of each conductive via are removed respectively.
[0009] In some embodiments, after performing the first wet etching process and the second wet etching process more than once, the interconnect structure is completely removed and a hollow channel is formed, wherein the hollow channel includes a plurality of lateral cavities extending laterally in the dielectric layer; and a plurality of vertical cavities extending vertically in the dielectric layer.
[0010] In some embodiments, the first etchant includes H3PO4 and H2O2.
[0011] In some embodiments, the second etchant includes KOH and H2O2.
[0012] In some embodiments, the fill layer includes copper and the glue layer includes titanium and tantalum.
[0013] In some embodiments, after the backside stealth singulation process, cracks inside the semiconductor wafer reach the bottom dielectric layer of the bottom metallization layer, and when the semiconductor wafer is observed from the front side, a plurality of cutting lines can be observed.
[0014] In some embodiments, the backside stealth singulation process includes applying a pulling force to the semiconductor wafer to separate the semiconductor wafer into semiconductor dies.
[0015] In some embodiments, wherein the dicing tape is adhered to the substrate and the step of applying the pulling force to the semiconductor wafer includes expanding the dicing tape outward.
[0016] The present disclosure provides a semiconductor chip including: a substrate; a protection ring structure located on the substrate, including: a side wall having a plurality of grooves, wherein the grooves extend in a direction parallel to the substrate; a grain located on the substrate, wherein the grain is surrounded by the protection ring structure, and the grooves extend toward the grain; and a flange located on the substrate and protruding from the side wall of the protection ring structure.
[0017] In some embodiments, the flange includes: a metal pad close to a sidewall of the guard ring structure; and a dielectric portion away from the sidewall of the guard ring structure.
[0018] In some embodiments, the metal pad comprises tungsten.
[0019] It is to be understood that both the foregoing general description and the following detailed description are by way of example, and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The present invention may be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings.
[0021] Figure 1 is a schematic top view of a semiconductor wafer according to some embodiments.
[0022] Figure 2According to some embodiments Figure 1 A partial cross-sectional schematic diagram of a semiconductor wafer.
[0023] Figure 3 is a partial cross-sectional schematic diagram of a semiconductor wafer after photoresist is formed according to some embodiments.
[0024] Figure 4 is a partial cross-sectional schematic diagram of a semiconductor wafer after a first dry etching process is performed according to some embodiments.
[0025] Figure 5 is a partial cross-sectional schematic diagram of a semiconductor wafer after a first wet etching process is performed according to some embodiments.
[0026] Figure 6 is a partial cross-sectional schematic diagram of a semiconductor wafer after a second wet etching process is performed according to some embodiments.
[0027] Figure 7 is a partial cross-sectional schematic diagram of a semiconductor wafer after a first wet etching process and a second wet etching process are repeatedly performed several times according to some embodiments.
[0028] Figure 8 is a partial cross-sectional schematic diagram of a semiconductor wafer after a second dry etching process is performed according to some embodiments.
[0029] Fig.9A , Fig. 9B The figures are respectively a cross-sectional view and a top view of a semiconductor wafer after a backside invisible splitting process is performed according to some embodiments.
[0030] Fig. 10A , Fig. 10B The figures are respectively a cross-sectional view and a top view of a semiconductor wafer after a tensile force is applied to the semiconductor wafer according to some embodiments. DETAILED DESCRIPTION
[0031] In order to describe the disclosure in detail and completely, the embodiments and specific examples of the disclosure are provided with exemplary description, but this is not the only form of realization or use of the specific examples of the disclosure. The embodiments disclosed herein can be combined or replaced with each other in an advantageous manner, and other embodiments can be added to the embodiments without further description. In the description below, many specific details will be described in detail so that the reader fully understands the following embodiments. However, embodiments of the disclosure can be put into practice without these specific details.
[0032] In addition, for ease of description, spatially relative terms, such as "below", "beneath", "lower", "above", "upper", etc., may be used herein to describe the relationship of a component or feature to one or more other components or features as illustrated in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.
[0033] Figure 1 1 is a schematic top view of a semiconductor wafer 100 according to some embodiments. As shown, the semiconductor wafer 100 includes a plurality of device regions 110 and a plurality of scribe regions 120, wherein each scribe region 120 is disposed between two device regions 110. In some embodiments, each device region 110 may include a die 112. The die 112 may include semiconductor devices such as memory, microprocessor, application-specific integrated circuits (ASICs), etc. In some embodiments, the die 112 is a dynamic random access memory (DRAM) wafer. Each scribe region 120 may include a test element group 120a. The scribe region 120 is used to separate or otherwise separate each wafer at the end of wafer processing. In such an embodiment, the test element group 120a may not be present on the divided wafer.
[0034] Figure 2 According to some embodiments Figure 1 1 is a schematic diagram of a partial cross-section of a semiconductor wafer 100. As shown in the figure, the semiconductor wafer 100 has a front side 102F and a back side 102B. In some embodiments, each device region 110 of the semiconductor wafer 100 may include a grain 112 deposited on a substrate 170. In some embodiments, the substrate 170 may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, etc., a silicon on insulator (SOI) substrate, etc. A guard ring structure 118 may surround the grain 112, and a mask 114 may cover the grain 112.
[0035] As shown, each scribe line region 120 may include a top metallization layer 130, a dielectric layer 150, and a bottom metallization layer 160 from the front side 102F to the back side 102B. The top metallization layer 130 may include a metal pad 132, a plurality of plugs 134, and a top dielectric layer 136, wherein the metal pad 132 is deposited on the top dielectric layer 136 and the plug 134 is embedded in the top dielectric layer 136. For example, the metal pad 132 and the plug 134 may include aluminum (Al). The top dielectric layer 136 may be a silicon oxide layer, a low-k dielectric layer, etc.
[0036] The dielectric layer 150 may be a silicon oxide layer, a low-k dielectric layer, etc. For example, the dielectric layer 150 may include an inter-metal dielectric (IMD) in which the interconnect structure 140 is formed. In other words, the interconnect structure 140 is embedded in the dielectric layer 150. The interconnect structure 140 is used to provide electrical interconnection between the top metallization layer 130 and the bottom metallization layer 160, and the interconnect structure 140 is made of a conductive material.
[0037] The interconnect structure 140 may include a plurality of wires and a plurality of conductive vias. The wires extend laterally in the dielectric layer 150. As shown, the wires may include a first wire 140L-1, a second wire 140L-2, and a third wire 140L-3. The conductive vias connect wires of different levels, in other words, the conductive vias extend vertically in the dielectric layer 150. As shown, the conductive vias may include a first conductive via 140V-1, a second conductive via 140V-2, and a third conductive via 140V-3. For example, the first conductive via 140V-1 connects the first wire 140L-1 and the second wire 140L-2. The bottom metallization layer 160 is formed between the dielectric layer 150 and the substrate 170. The dicing tape 180 is adhered to the substrate 170 of the semiconductor wafer 100.
[0038] Figure 3 FIG. 1 is a schematic cross-sectional view of a portion of the semiconductor wafer 100 after the photoresist 116 is formed according to some embodiments. As shown in the figure, the photoresist 116 is formed at the front surface 102F and can completely cover the mask 114. In some embodiments, the photoresist 116 is patterned to define a scribe opening 122 in each scribe area 120, wherein the scribe opening 122 exposes the metal pad 132. The metal pad 132 exposed by the scribe opening 122 can be used as a test pad and can be a test element group 120a (such as Figure 1 The photoresist 116 may be patterned by a suitable method, such as photoresist patterning and etching. The photoresist 116 is formed to protect each device region 110 from the subsequent etching process, which will be described below. Figures 4 to 8 Further discussion in.
[0039] Figure 4 1 is a partial cross-sectional schematic diagram of a semiconductor wafer 100 after a first dry etching process is performed according to some embodiments. Each conductor may include a filling layer 142 and a glue layer 144. Each conductive via may include a filling layer 142 and a glue layer 144. In order to simplify the drawings, only the filling layer 142 and the glue layer 144 of the first conductor 140L-1 are shown, and other figures are omitted. As shown in the figure, the top metallization layer 130 is removed by the first dry etching process, and after the top metallization layer 130 is removed, the scribe opening 122 exposes a portion of the filling layer 142 of the first conductor 140L-1 and a portion of the dielectric layer 150. For example, the first dry etching process may be a reactive ion etching (RIE) process, or other suitable anisotropic etching processes.
[0040] Figure 5 1 is a partial cross-sectional schematic diagram of a semiconductor wafer 100 after a first wet etching process is performed according to some embodiments. In some embodiments, the filling layer may be copper (Cu). Since it is difficult to remove Cu by a dry etching process and undesirable products may be produced, a first wet etching process using a first etchant is performed to remove the filling layer 142 of the first wire 140L-1. After removing the filling layer 142, the glue layer 144 of the first wire 140L-1 is exposed. As shown in the figure, the glue layer 144 is in a thin shell shape, making it easier to deposit the filling layer 142. For example, the first etchant may include H3PO4 and H2O2. Due to the etching selectivity, after the first wet etching process, the dielectric layer 150 and the glue layer 144 made of low-k material are still retained.
[0041] Figure 6 1 is a schematic cross-sectional view of a portion of the semiconductor wafer 100 after performing a second wet etching process according to some embodiments. In some embodiments, the glue layer 144 may include titanium (Ti) and tantalum (Ta). As shown, a second wet etching process using a second etchant is performed to remove the glue layer 144 of the first wire 140L-1. After removing the glue layer 144 of the first wire 140L-1, the first conductive via 140V-1 is exposed. For example, the second etchant may include KOH and H2O2. The dielectric layer 150 is still retained after the second wet etching process.
[0042] Figure 71 is a partial cross-sectional schematic diagram of the semiconductor wafer 100 after the first wet etching process and the second wet etching process are repeatedly performed several times according to some embodiments. In some embodiments, the first wet etching process and the second wet etching process are repeated several times to completely remove the interconnect structure 140. Since the dielectric layer 150 is still retained after the first wet etching process and the second wet etching process, a hollow channel (hallow trace) 146 is formed after the interconnect structure 140 is completely removed. The hollow channel 146 may include a lateral cavity 146L and a vertical cavity 146V. The lateral cavity 146L extends laterally in the dielectric layer 150. The vertical cavity 146V extends vertically in the dielectric layer 150, and the lateral cavities 146L of different layers are connected by the vertical cavity 146V. The hollow channel 146 exposes a portion of the bottom metallization layer 160. A portion of the lateral cavity 146L will remain on the sidewall of the guard ring structure 118 and will be described in detail below.
[0043] Figure 8 1 is a partial cross-sectional schematic diagram of the semiconductor wafer 100 after performing the second dry etching process according to some embodiments. After the interconnect structure 140 is completely removed, it is easy to perform the dry etching process. As shown in the figure, the second dry etching process is performed to remove the dielectric layer 150, and the second dry etching process stops at the bottom metallization layer 160, wherein the scribe opening 122 is deepened and the scribe opening area 124 is formed. The scribe opening area 124 exposes the bottom metallization layer 160. For example, the second dry etching process can be a reactive ion etching (RIE) process, or other suitable anisotropic etching processes. In some embodiments, the method also includes stripping the photoresist 116 after performing the second dry etching process. The above-mentioned etching process thins the layers of the scribe area 120 from the front side 102F, which is beneficial to the subsequent back side stealth dicing process.
[0044] Fig.9A , Fig. 9B They are respectively a cross-sectional view and a top view of a semiconductor wafer after performing a backside invisible splitting process according to some embodiments. As shown in the figure, the bottom metallization layer 160 may further include a metal pad 162 and a bottom dielectric layer 164, wherein the metal pad 162 may include tungsten (W). The material of the dielectric layer 150 and the material of the bottom dielectric layer 164 may be the same or different. The backside invisible splitting process includes irradiating a laser beam Bm at the scribe area 120 from the back side 102B. The laser beam Bm may induce a crack Cr from the back side 102B toward the front side 102F inside the substrate 170. The crack Cr may eventually reach the bottom dielectric layer 164 of the bottom metallization layer 160. As shown in FIG. Fig. 9BAs shown, when the crack Cr reaches the bottom dielectric layer 164 , a plurality of thermal cutting lines H can be observed when observing the semiconductor wafer 100 from the front side 102F.
[0045] Fig. 10A , Fig. 10B 1 and 2 are cross-sectional views and top views of a semiconductor wafer after a tensile force is applied to the semiconductor wafer according to some embodiments. In this step, a tensile force F is applied to expand the dicing tape 180 outward. Then, as Fig. 10B As shown, the semiconductor wafer 100 is separated into individual semiconductor chips 110A.
[0046] Each semiconductor wafer 110A includes a die 112, a protection ring structure 118, a substrate 170, and a flange 160R. The die 112, the protection ring structure 118, and the flange 160R are disposed on the substrate 170. The die 112 is surrounded by the protection ring structure 118. The sidewall 118S of the protection ring structure 118 has a plurality of grooves 148. The grooves 148 are formed after the semiconductor wafer 100 is separated into individual semiconductor wafers 110A. Figure 7 The groove 148 extends laterally toward the die 112. In other words, the groove 148 extends in a direction that is almost parallel to the substrate 170. The flange 160R protrudes from the sidewall 118S of the guard ring structure 118, wherein the flange 160R is the remaining portion of the bottom metallization layer 160 after the semiconductor wafer 100 is separated into individual semiconductor chips 110A.
[0047] The embodiments of the present disclosure have some advantageous features. By configuring a first dry etching process, a first wet etching process, a second wet etching process, and a second dry etching process, the method proposed by the present disclosure can appropriately thin the number of layers in the scribe line area. Specifically, inserting a wet etching process between dry etching processes can reduce the generation of undesirable products when etching metal wires. In addition, the method provided by the present disclosure can reduce the generation of errors and reduce the occurrence of fragmentation when separating semiconductor wafers.
[0048] Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0049] It is obvious to those skilled in the art that various modifications and changes can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and changes of the present disclosure that fall within the scope of the appended claims.
[0050]
Explanation of symbols
[0051] 100:Semiconductor wafer
[0052] 102F: Front
[0053] 102B: Back
[0054] 110: Installation area
[0055] 110A:Semiconductor wafer
[0056] 112: Grain
[0057] 114: Mask
[0058] 116: Photoresist
[0059] 118: Guard ring structure
[0060] 118S: Sidewall
[0061] 120: Line area
[0062] 120a: Test element group
[0063] 122: Marking opening
[0064] 124: Marking opening area
[0065] 130: Top metallization layer
[0066] 132:Metal pad
[0067] 134: Plug
[0068] 136: Top dielectric layer
[0069] 140: Interconnection structure
[0070] 140L-1: First conductor
[0071] 140L-2: Second conductor
[0072] 140L-3: The third conductor
[0073] 140V-1: First conductive via
[0074] 140V-2: Second conductive via
[0075] 140V-3: The third conductive via
[0076] 142: Filling layer
[0077] 144: Adhesive layer
[0078] 146: Hollow Channel
[0079] 146V: Vertical Cavity
[0080] 146L: lateral cavity
[0081] 148: Groove
[0082] 150: Dielectric layer
[0083] 160: Bottom metallization layer
[0084] 160R: Flange
[0085] 162:Metal pad
[0086] 164: Bottom dielectric layer
[0087] 170:Substrate
[0088] 180: Cutting tape
[0089] Bm: Laser beam
[0090] Cr: Crack
[0091] H: Hot cutting wire
[0092] F: Tensile force.
Claims
1. A method for manufacturing a semiconductor wafer, characterized in that: include: performing a first dry etching process to remove the top metallization layer so that a portion of an interconnect structure is exposed through a scribe opening after removing the top metallization layer, wherein the interconnect structure is embedded in the dielectric layer; performing a first wet etching process using a first etchant to remove the filling layer of the interconnect structure; After performing the first wet etching process, performing a second wet etching process using a second etchant to remove the glue layer of the interconnect structure; Performing a second dry etching process to remove the dielectric layer and stop at the bottom metallization layer, wherein the scribe opening is deepened and a scribe opening area is formed; and A backside stealth singulation process is performed to induce cracks in the substrate from the backside to the frontside, thereby singulating the semiconductor wafer into the semiconductor chips.
2. The method according to claim 1, characterized in that Further including: Before the first dry etching process, a photoresist is formed to protect the device area and define the scribe opening, wherein the top metallization layer is exposed in the scribe opening.
3. The method according to claim 2, characterized in that Further including: After the second dry etching process, the photoresist is stripped.
4. The method according to claim 1, characterized in that: The interconnect structure includes: A plurality of conductive lines extending laterally in the dielectric layer, each of the conductive lines comprising the filling layer and the adhesive layer; and A plurality of conductive vias extending vertically in the dielectric layer, each of the conductive vias comprising the filling layer and the adhesive layer; The conductive through holes connect the conductive lines of different layers.
5. The method according to claim 1, characterized in that Further including: Repeating the first wet etching process and the second wet etching process more than once until the interconnect structure is completely removed, The filling layer and the glue layer of each of the conductive lines are removed respectively, and the filling layer and the glue layer of each of the conductive through holes are removed respectively.
6. The method according to claim 5, characterized in that wherein after performing the first wet etching process and the second wet etching process more than once, the interconnect structure is completely removed and a hollow channel is formed, The hollow channel comprises: A plurality of lateral cavities extend laterally in the dielectric layer; and A plurality of vertical cavities extend vertically in the dielectric layer.
7. The method according to claim 1, characterized in that The first etchant includes phosphoric acid and hydrogen peroxide.
8. The method according to claim 1, characterized in that The second etchant includes potassium hydroxide and hydrogen peroxide.
9. The method according to claim 1, characterized in that: The filling layer includes copper, and the glue layer includes titanium and tantalum.
10. The method according to claim 1, characterized in that After the backside invisible segmentation process, the cracks inside the semiconductor wafer reach the bottom dielectric layer of the bottom metallization layer, and when the semiconductor wafer is observed from the front side, a plurality of cutting lines can be observed.
11. The method according to claim 1, characterized in that: The back side invisible segmentation process includes: A pulling force is applied to the semiconductor wafer to separate the semiconductor wafer into semiconductor chips.
12. The method according to claim 11, characterized in that The step of adhering a dicing tape to the substrate and applying a tensile force to the semiconductor wafer includes expanding the dicing tape outward.
13. A semiconductor wafer, characterized in that: include: substrate; A guard ring structure, located on the substrate, includes: A side wall having a plurality of grooves, wherein the grooves extend parallel to a direction of the substrate; A die is located on the substrate, wherein the die is surrounded by the guard ring structure, and the grooves extend toward the die; and The flange is located on the substrate and protrudes from the side wall of the protection ring structure.
14. The semiconductor wafer according to claim 13, characterized in that The flange comprises: A metal pad is proximate to the sidewall of the guard ring structure; and The dielectric portion is away from the sidewall of the guard ring structure.
15. The semiconductor wafer according to claim 14, characterized in that The metal pad includes tungsten.