Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof. A method according to an embodiment of the present disclosure includes receiving a workpiece including an active region over a substrate and having a first semiconductor layer interleaved with a second semiconductor layer, and a dummy gate stack over a channel region of the active region; etching a source / drain region of the active region to form a source / drain trench exposing sidewalls of the active region; selectively and partially etching the second semiconductor layer to form an internal spacer recess; forming an inner spacer component in the inner spacer recess; forming a channel extension feature on the exposed sidewalls of the first semiconductor layer; forming a source / drain feature over the source / drain trench; removing the dummy gate stack; selectively removing the second semiconductor layer to form a nanostructure in the channel region; and forming a gate structure to wrap each of the nanostructures. The channel extension feature includes undoped silicon.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. A full-all-around gate (GAA) transistor is an example of a multi-gate device, which has become a popular and promising candidate device for high-performance and low-leakage applications. A GAA transistor has a gate structure that can extend partially or completely around a channel region to provide access to a channel region on two or more sides. Because its gate structure surrounds the channel region, a GAA transistor may also be referred to as a gate-around transistor (SGT). Because the channel region of a GAA transistor may include a nanowire or a nanosheet, and its configuration is similar to a bridge, a GAA transistor may also be referred to as a multi-bridge channel (MBC) transistor, a nanowire transistor, or a nanosheet transistor. Nanosheets and nanowires may generally be referred to as nanostructures.

[0004] GAA transistors can implement different functions in an IC device. Some functions can be best implemented by transistors with low resistance, and some functions can be best implemented by transistors with low capacitance. Although manufacturing a single type of GAA transistor to implement all functions saves cost, it may sacrifice the performance or energy efficiency of the IC device. Summary of the invention

[0005] Some embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: receiving a workpiece, comprising: an active area, located above a substrate and comprising a plurality of first semiconductor layers interlaced with a plurality of second semiconductor layers, and a dummy gate stack, located above a channel area of ​​the active area; etching a source / drain area of ​​the active area to form a source / drain trench exposing a sidewall of the active area; selectively and partially etching the plurality of second semiconductor layers to form an internal spacer groove; forming an internal spacer component in the internal spacer groove; forming a channel extension component on the exposed sidewalls of the plurality of first semiconductor layers; after forming the channel extension component, forming a source / drain component above the source / drain trench; removing the dummy gate stack; selectively removing the plurality of second semiconductor layers to form a plurality of nanostructures in the channel area; and forming a gate structure to wrap each of the plurality of nanostructures, wherein the channel extension component comprises undoped silicon.

[0006] Some other embodiments of the present application provide a semiconductor structure, including: a substrate; and a first transistor and a second transistor, arranged above the substrate, wherein the first transistor includes: a first source / drain component and a second source / drain component, a first plurality of channel components, extending between the first source / drain component and the second source / drain component along a direction, a first gate structure, wrapping each of the first plurality of channel components, and a first gate spacer layer pair, arranged above the first plurality of channel components and sandwiching a top portion of the first gate structure in the middle, wherein the second transistor includes: a third source / drain component and a fourth source / drain component, a second plurality of channel components, extending between the third source / drain component and the fourth source / drain component along the direction, a second gate structure, wrapping each of the second plurality of channel components, and a second gate spacer layer pair, arranged above the second plurality of channel components and sandwiching a top portion of the second gate structure in the middle, wherein, along the direction, the thickness of each of the second gate spacer layer pair is less than the thickness of each of the first gate spacer layer pair.

[0007] Some other embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: receiving a workpiece, comprising: a substrate, comprising a first region and a second region, a first active region, located above the first region, and comprising a plurality of first semiconductor layers interlaced with a plurality of second semiconductor layers, the first active region extending between a first source / drain component and a second source / drain component, a second active region, located above the second region, and comprising the plurality of first semiconductor layers interlaced with the plurality of second semiconductor layers, the second active region extending between a third source / drain component and a fourth source / drain component, a first dummy gate stack, located above a channel region of the first active region, a first gate spacer layer pair, disposed above the first active region and separating the first dummy gate stack from the first active region; The top portion of the stack is sandwiched in the middle, a second dummy gate stack is located above the channel region of the second active region, and a second gate spacer layer pair is arranged above the second active region and sandwiches the top portion of the second dummy gate stack in the middle; remove the first dummy gate stack and the second dummy gate stack; selectively remove the multiple second semiconductor layers to form a first multiple nanostructures in the first region and a second multiple nanostructures in the second region; selectively trim the first gate spacer layer pair and the second gate spacer layer pair in the second region; and after the trimming, form a first gate structure to wrap each of the first multiple nanostructures and form a second gate structure to wrap each of the second multiple nanostructures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0009] Figure 1 A flow chart of a method for forming a semiconductor device according to one or more aspects of an embodiment of the present disclosure is shown.

[0010] Figures 2 to 14 The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 A partial cross-sectional view during the manufacturing process of the method.

[0011] Figure 15 to Figure 16 A schematic cross-sectional view of a workpiece having one region masked out for differential processing of another region is shown in accordance with one or more aspects of an embodiment of the present disclosure.

[0012] Fig.17A flow chart of a method for forming a semiconductor device with an extended channel length according to one or more aspects of an embodiment of the present disclosure is shown.

[0013] Figures 18 to 21 The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Fig.17 A partial cross-sectional view during the manufacturing process of the method.

[0014] Fig. 22 A flow chart of a method for forming a semiconductor device with an extended channel length according to one or more aspects of an embodiment of the present disclosure is shown.

[0015] Figure 23 to Figure 29 The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Fig. 22 A partial cross-sectional view during the manufacturing process of the method.

[0016] Fig.30 A flow chart of a method for forming a semiconductor device with an extended gate length according to one or more aspects of an embodiment of the present disclosure is shown.

[0017] Figure 31 to Figure 33 The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Fig.30 A partial cross-sectional view during the manufacturing process of the method.

[0018] Fig.34 is a schematic top view of a circuit device including more than one type of transistors according to one or more aspects of an embodiment of the present disclosure.

[0019] Fig.35 is a schematic top view of a standard cell including more than one type of transistors according to one or more aspects of the embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0022] In addition, when "about," "approximately," or the like is used to describe a value or a range of values, as understood by one of ordinary skill in the art, the term is intended to encompass values ​​within a reasonable range that take into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the values, the values ​​or ranges of values ​​encompass a reasonable range that includes the described values, such as within + / -10% of the described values. For example, a material layer having a thickness of "about 5 nm" may cover a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to one of ordinary skill in the art is + / -15%. When two values ​​are described as being the same, it should be understood that the two values ​​differ from each other by less than 10%, such that they are substantially the same. As used herein, a source / drain region may refer to a source or a drain, either individually or together depending on the context.

[0023] Transistors in IC devices can be entrusted to serve different functions. In addition, IC devices for different applications may require transistors with different properties. For example, when it comes to mobile applications that require long standby time, transistors are expected to have low capacitance. When high-power or high-performance transistors are desired, having low resistance may be more beneficial than having low capacitance. Depending on whether the memory device is embedded or external, it may require low resistance or low capacitance. The simple solution is to manufacture low resistance and low capacitance devices to meet all design requirements. However, achieving low resistance and low capacitance at the same time can be challenging.

[0024] The disclosed embodiments provide an exemplary process for selectively manufacturing GAA transistors of different properties in different regions to meet different design requirements. In a first embodiment, an undoped silicon channel extension component can be deposited above the end surface of the channel component. In a second embodiment, the total thickness of the top gate spacer can be increased or reduced to achieve different gate lengths. In a third embodiment, after releasing the channel component in the channel region, the thickness of the top gate spacer component and the internal spacer component can be reduced. GAA transistors according to different embodiments can be manufactured on a single substrate to implement different circuit functions.

[0025] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1 , Fig.17 , Fig. 22 and Fig.30 1 is a flow chart illustrating a method 100, 300, 400, or 500 of forming a semiconductor device from a workpiece according to an embodiment of the present disclosure. The methods 100, 300, 400, or 500 are merely examples and are not intended to limit the disclosed embodiments to what is explicitly shown in the methods 100, 300, 400, or 500. Additional steps may be provided before, during, and after each of the methods 100, 300, 400, or 500, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. Figures 2 to 14 Describing method 100, Figures 2 to 14 is based on Figure 1 The following is a partial cross-sectional view of a workpiece 200 at different manufacturing stages of an embodiment of the method 100. Figures 2 to 10 and Figures 18 to 21 Describing method 300, Figures 2 to 10 and Figures 18 to 21 is based on Fig.17 The following is a partial cross-sectional view of a workpiece 200 at different manufacturing stages of an embodiment of the method 300. Figures 2 to 6 and Figure 23 to Figure 29 Describing method 400, Figures 2 to 6 and Figure 23 to Figure 29 is based on Fig. 22 The following is a partial cross-sectional view of the workpiece 200 at different manufacturing stages of the embodiment of the method 400. Figures 2 to 13 and Figure 31 to Figure 33 Describing method 500, Figures 2 to 13 and Figure 31 to Figure 33 is based on Fig.30 5. The workpiece 200 of the embodiment of the method 500 in FIG. 5 is a partial cross-sectional view at different manufacturing stages. Because the workpiece 200 is to be manufactured as a semiconductor device, the workpiece 200 may be referred to as a semiconductor device 200 herein as the context requires. For the avoidance of doubt, Figures 2 to 16 , Figures 18 to 21 , Figure 23 to Figure 29 and Figure 31 to Figure 33 The X, Y and Z directions in FIG. 1 are perpendicular to each other. In addition, the same reference numerals may denote the same components throughout the disclosure.

[0026] refer to Figure 1 and Figure 2 , the method 100 includes a block 102, in which a stack 204 of alternating semiconductor layers is formed above a workpiece 200. Figure 2As shown in , workpiece 200 includes substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include various doping configurations, depending on design requirements as known in the art. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) may be formed on substrate 202. In some embodiments, an n-type dopant for forming an n-type well may include phosphorus (P) or arsenic (As). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) may be formed on substrate 202. In some embodiments, an n-type dopant for forming a p-type well may include boron (B) or gallium (Ga). Suitable doping may be implemented using ion implantation and / or diffusion processes of dopants. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Additionally, the substrate 202 may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0027] In some embodiments, the stack 204 includes sacrificial layers 206 of a first semiconductor composition interleaved with channel layers 208 of a second semiconductor composition. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layers 206 include silicon germanium (SiGe) and the channel layers 208 include silicon (Si). It should be noted that the three (3) layers of sacrificial layers 206 and the three (3) layers of channel layers 208 are arranged alternately, as shown in FIG. Figure 2 , which is for illustrative purposes only and is not intended to be limiting beyond the specific enumeration in the claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the desired number of channel components for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0028] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness, and all channel layers 208 may have a substantially uniform second thickness. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layer 208 or a portion thereof may be used as a channel member for a subsequently formed multi-gate device, and the thickness of each of the channel layers 208 is selected based on device performance considerations. The sacrificial layer 206 in the channel region may eventually be removed and used to define the vertical distance (along the Z direction) between adjacent channel regions for a subsequently formed multi-gate device, and the thickness of each of the sacrificial layers 206 is selected based on device performance considerations.

[0029] The layers in stack 204 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE) process, and / or other suitable epitaxial growth processes. As described above, in at least some examples, sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and channel layer 208 includes an epitaxially grown silicon (Si) layer. In some embodiments, sacrificial layer 206 and channel layer 208 are substantially free of dopants (i.e., have a dopant content of from about 0 cm -3 About 1×10 17 cm -3 extrinsic dopant concentration), where, for example, no intentional doping is performed during the epitaxial growth process for the stack 204 .

[0030] Still reference Figure 1 , Figure 2 and Figure 3 , the method 100 includes a block 104, in which a fin structure 212 is formed from the stack 204 and the substrate 202. To pattern the stack 204, a hard mask layer 210 ( Figure 2 ) to form an etching mask. The hard mask layer 210 may be a single layer or a multilayer. For example, the hard mask layer 210 may include a pad oxide layer and a pad nitride layer above the pad oxide layer. The fin structure 212 may be patterned by the stack 204 and the substrate 202 using a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. As Figure 3 As shown in , the etching process in box 104 forms a trench that extends through the stack 204 and a portion of the substrate 202. The trench defines a fin structure 212. In some embodiments, a double patterning or multiple patterning process can be used to define a fin structure having, for example, a pitch that is less than that obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 212 by etching the stack 204. As shown in FIG. Figure 3 As shown in FIG. 1 , the fin structure 212 , together with the sacrificial layer 206 and the channel layer 208 therein, vertically extends along the Z direction, and longitudinally extends along the X direction.

[0031] An isolation component 214 is formed adjacent to the fin structure 212. In some embodiments, the isolation component 214 may be formed in a trench to isolate the fin structure 212 from an adjacent active area. The isolation component 214 may also be referred to as a shallow trench isolation (STI) component 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various instances, the dielectric layer may be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form the STI component 214. After being recessed, the fin structure 212 rises above the STI feature 214 .

[0032] refer to Figure 1 , Figure 4 and Figure 5 The method 100 includes a block 106 in which a dummy gate stack 220 is formed over the channel region 212C of the fin structure 212. In some embodiments, a gate replacement process (or a gate-last process) is used, in which the dummy gate stack 220 ( Figure 4 and Figure 5 ) is used as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 5 In some embodiments shown in , the dummy gate stack 220 is formed above the fin structure 212, and the fin structure 212 can be divided into a channel region 212C below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 5 As shown in FIG. 2 , the channel region 212C is disposed between two source / drain regions 212SD along the X direction.

[0033] The formation of the dummy gate stack 220 may include depositing the layers in the dummy gate stack 220 and patterning the layers. Figure 4, a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 may be blanket deposited over the workpiece 200. In some embodiments, the dummy dielectric layer 216 may be formed on the fin structure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable process. In some instances, the dummy dielectric layer 216 may include silicon oxide. Thereafter, the dummy electrode layer 218 may be deposited over the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable process. In some instances, the dummy electrode layer 218 may include polycrystalline silicon (poly-Si). For patterning purposes, the gate top hard mask layer 222 may be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable process. The gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 may then be patterned to form a dummy gate stack 220, such as Figure 4 and Figure 5 As shown in . For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography), which may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 above the silicon oxide layer 223. As shown in Figure 5 As shown in FIG. 2 , no dummy gate stack 220 is disposed over the source / drain region 212SD of the fin structure 212 .

[0034] refer to Figure 1 and Figure 6 , the method 100 includes a frame 108, wherein a top spacer layer 226 is deposited over the dummy gate stack 220. In some embodiments, the top spacer layer 226 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 220. The term "conformal" is used herein to facilitate describing a layer having a substantially uniform thickness over various regions. The top spacer layer 226 can be a single layer or multiple layers. The top spacer layer 226 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. In some embodiments, the top spacer layer 226 may be deposited over the dummy gate stack 220 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, an ALD process, or other suitable process.

[0035] refer to Figure 1 and Figure 7The method 100 includes block 110, where the source / drain region 212SD of the fin structure 212 is recessed to form a source / drain trench 228. Figure 7 As shown in , the recess in frame 110 can remove the top-facing portion of the top spacer layer 226 to form a top spacer 2260 disposed along the sidewall of the dummy gate stack 220. In some embodiments, the source / drain region 212SD not covered by the dummy gate stack 220 is etched by dry etching or a suitable etching process to form a source / drain trench 228. For example, the dry etching process can be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. In Figure 7 In some embodiments shown in , the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. In some embodiments, the source / drain trench 228 extends into the substrate 202 under the stack 204. Figure 7 As shown in FIG. 1 , in block 110 , the sacrificial layer 206 and the channel layer 208 in the source / drain region 212SD are removed, exposing the substrate 202 and the sidewalls of the sacrificial layer 206 and the channel layer 208 .

[0036] refer to Figure 1 , Figure 8 , Fig. 9 and Fig.10 , the method 100 includes block 112, in which an inner spacer feature 234 is formed. Although not explicitly shown, the operations in block 112 may include: selectively and partially removing the sacrificial layer 206 to form the inner spacer recess 230 ( Figure 8 ); depositing an inner spacer material 232 over the workpiece 200 ( Fig. 9 and etching back the inner spacer material 232 to form an inner spacer member 234 in the inner spacer recess 230 ( Fig.10 ). refer to Figure 8. The sacrificial layer 206 exposed in the source / drain trench 228 is selectively and partially recessed to form the inner spacer recess 230, while the top spacer 2260, the exposed portion of the substrate 202, and the channel layer 208 are substantially not etched. In an embodiment where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), the selective recessing of the sacrificial layer 206 can be implemented using a selective wet etching process or a selective dry etching process. The selective and partial recessing of the sacrificial layer 206 can include a SiGe oxidation process and subsequent SiGe oxide removal. In this embodiment, the SiGe oxidation process can include the use of ozone. In some other embodiments, the selective dry etching process can include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process can include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0037] refer to Fig. 9 , after forming the internal spacer recess 230, an internal spacer material 232 is deposited over the workpiece 200, including over the internal spacer recess 230. The internal spacer material 232 may include a metal oxide, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxide may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly shown, the internal spacer material 232 may be a single layer or multiple layers. In some embodiments, the internal spacer material 232 may be deposited using CVD, PECVD, SACVD, ALD, or other suitable methods. The internal spacer material 232 is deposited into the internal spacer recess 230 and over the sidewalls of the channel layer 208 exposed in the source / drain trench 228. Reference Fig.10 , and then etch back the deposited internal spacer material 232 to remove the internal spacer material 232 from the sidewalls of the channel layer 208 to form an internal spacer feature 234 in the internal spacer recess 230. In block 112, the internal spacer material 232 may also be removed from the top surface and / or sidewalls of the gate top hard mask layer 222 and the top spacer 2260. In some embodiments, the etch back operation performed in block 112 may include using hydrogen fluoride (HF), fluorine gas (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. Fig.10 As shown in FIG. 2 , each of the inner spacer members 234 is in direct contact with the recessed sacrificial layer 206 and is disposed between two adjacent channel layers 208. That is, the inner spacer members 234 are interleaved with the channel layers 208.

[0038] refer to Figure 1 and Fig.11, the method 100 includes block 114, where a source / drain feature 240 is formed. Fig.11 In some embodiments shown in , the source / drain features 240 can be epitaxially grown and selectively formed from the exposed sidewalls of the channel layer 208 and the exposed portions of the substrate 202, while the sidewalls of the sacrificial layer 206 remain covered by the internal spacer features 234. Suitable epitaxial processes for block 114 include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process in block 114 can use gaseous precursors that interact with the channel layer 208 and the substrate 202. In some embodiments, the parameters of the epitaxial growth process in block 114 are selected so that the source / drain features 240 are not epitaxially deposited on the internal spacer features 234. It should be noted that although each of the source / drain features 240 is epitaxially grown, the source / drain features 240 are epitaxially grown on the internal spacer features 234. Fig.11 208 and 209. The source / drain components 240 are shown as having a uniform continuous structure, but it can include multiple epitaxial layers with different dopant concentrations or germanium (Ge) content (if germanium (Ge) is desired). Depending on the design, the source / drain components 240 can be n-type or p-type. When the source / drain components 240 are n-type, they can include silicon (Si) and at least one n-type dopant (e.g., phosphorus (P)). When the source / drain components 240 are p-type, they can include silicon germanium (SiGe) and at least one p-type dopant (e.g., boron (B)). In an example where the source / drain component 240 includes a first epitaxial layer adjacent to the channel layer 208 and the substrate 202, a second epitaxial layer above the first epitaxial layer, and a third epitaxial layer above the second epitaxial layer, the second epitaxial layer can have a dopant concentration greater than the dopant concentration of the first epitaxial layer or the third epitaxial layer. In this example, when the source / drain component 240 is p-type, the germanium content in the first epitaxial layer can be lower than the germanium content in the second epitaxial layer or the third epitaxial layer.

[0039] In some embodiments, an annealing process may be performed to anneal the source / drain features 240. The annealing process may include a rapid thermal annealing (RTA) process, a laser spike annealing process, a flash annealing process, or a furnace annealing process. In some instances, the annealing process may include a peak annealing temperature between about 900°C and about 1000°C. In these embodiments, the peak annealing temperature may be maintained for a duration measured in seconds or microseconds. Throughout the annealing process, a desired electron contribution of a dopant (such as a p-type dopant boron (B) or an n-type dopant phosphorus (P)) in a semiconductor body (such as silicon (Si) or silicon germanium (SiGe)) may be obtained. The annealing process may generate vacancies that promote the movement of p-type dopants from interstitial positions to alternative lattice positions and reduce damage or defects in the lattice of the semiconductor body.

[0040] refer to Figure 1 , Fig.12 and Fig.13 , the method 100 includes block 116, wherein the dummy gate stack 220 is removed. The operations in block 116 may include depositing a contact etch stop layer (CESL) 242 ( Fig.12 ); an interlayer dielectric (ILD) layer 244 is deposited over the CESL 242 ( Fig.12 ); and removing the dummy gate stack 220 ( Fig.13 ). Now refer to Fig.12 , before depositing the ILD layer 244, the CESL 242 is deposited. In some instances, the CESL 242 includes silicon nitride, silicon oxynitride, and / or other materials known in the art. The CESL 242 may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition processes. The ILD layer 244 is then deposited over the CESL 242. In some embodiments, the ILD layer 244 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 244 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 244, the workpiece 200 may be annealed to improve the integrity of the ILD layer 244. Fig.12 As shown in , the CESL 242 may be disposed directly on the top surface of the source / drain features 240 .

[0041] Still reference Fig.12 After depositing the CESL 242 and the ILD layer 244, the workpiece 200 may be planarized by a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. Exposing the dummy gate stack 220 allows the dummy gate stack 220 to be removed, such as Fig.13 . In some embodiments, removing the dummy gate stack 220 creates a gate trench 248 above the channel region 212C. Removing the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 220. For example, removing the dummy gate stack 220 may be implemented using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 220. After removing the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed in the gate trench 248.

[0042] refer to Figure 1 and Fig.14 , the method 100 includes block 118, where the channel layer 208 is released as a channel member 2080. Fig.14 After removing the dummy gate stack 220 to form the gate trench 248, the method 100 selectively removes the sacrificial layer 206 between the channel layers 208 in the channel region 212C. The selective removal of the sacrificial layer 206 releases Fig.13 The channel layer 208 is formed Fig.14 The channel member 2080 in the channel member 2080 is selectively removed. The selective removal of the sacrificial layer 206 also leaves a gap between the channel members 2080. The selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching or other selective etching processes. An exemplary selective dry etching process can include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process can include APM etching (e.g., ammonia hydroxide-hydrogen peroxide-water mixture).

[0043] refer to Figure 1 and Fig.14, the method 100 includes a frame 120, in which a gate structure 250 is formed. In frame 120, the gate structure 250 is formed in the gate trench 248 and in the space left by removing the sacrificial layer 206. The gate structure 250 includes a gate dielectric layer 252 and a gate electrode layer 254 above the gate dielectric layer 252. In some embodiments, although not explicitly shown in the figure, the gate dielectric layer 252 includes an interface layer disposed on the channel member 2080 and a high-K gate dielectric layer above the interface layer. High-K dielectric materials (as used and described herein) include dielectric materials having a high dielectric constant, for example, a dielectric constant greater than that of thermally oxidized silicon (~3.9). The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K gate dielectric layer may include hafnium oxide. Alternatively, the high-K gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0044] The gate electrode layer 254 of the gate structure 250 may include a single layer or optionally a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or various combinations of metal silicides. For example, the gate electrode layer 254 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer 254 may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a substantially flat top surface of the gate structure 250. An upper portion of the gate structure 250 is sandwiched between a pair of top spacer features 2260, and a lower portion of the gate structure 250 is isolated from the source / drain features 240 by a plurality of inner spacer features 234.

[0045] Reference again Fig.14 . At the end of method 100, a first transistor 2000A is formed. According to embodiments of the present disclosure, more than one type of GAA transistor may be fabricated on a single substrate to have different characteristics suitable for different functions or applications. The first transistor 2000A includes a first top gate length TGL1 for an upper portion of the gate structure 250 located above the channel member 2080, a first gate length GL1 for a lower portion of the gate structure 250 located between the channel members 2080, a first channel length CL1, and a first source / drain component width SDW1. The first transistor 2000A represents one type of GAA transistor and may be considered a reference device for other transistors formed using methods 300, 400, or 500.

[0046] To form a particular type of GAA transistor in one region of a substrate, another region of the substrate is masked off with a patterned mask during at least a portion of the fabrication process. Fig.15 and Fig.16 An exemplary process for masking off the first region 50 of the substrate 202 while exposing the second region 60 of the substrate 202 is shown. Fig.15, first, a mask layer 20 is blanket deposited over the first region 50 and the second region 60 of the substrate 202. In some embodiments, the mask layer 20 may include aluminum oxide or a dielectric material that can be selectively etched without substantially etching dielectric materials such as silicon oxide or silicon nitride. The mask layer 20 may be deposited using CVD, low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), or atmospheric pressure CVD (APCVD). After the blanket deposition of the mask layer 20, a photoresist layer 10 is deposited over the mask layer 20 using spin coating and patterned using photolithography techniques. As shown in FIG. Fig.16 As shown in FIG. 1 , in the case where the patterned photoresist layer 10 is used as an etching mask, the mask layer 20 is etched to form a patterned mask layer 20 ′ to cover the first region 50. The transistors in the first region 50 and the transistors in the second region 60 may share some process steps. When the process starts to be different, it can be implemented Fig.15 and Fig.16 A selective masking process is representatively shown in FIG.

[0047] Fig.17 Shown is the method for forming Fig.21 The second transistor 2000B shown in the method 300. Fig.14 Compared to the first transistor 2000A shown in FIG. , the second transistor 2000B has an extended channel length, which may result in higher resistance, lower capacitance, and lower leakage current. Figure 1 and Fig.17 As shown in , method 300 shares the operations in blocks 102 - 112 and 114 - 120 , and also includes block 313 .

[0048] refer to Fig.17 and Fig.18 , method 300 includes box 313, in which a channel extension feature 236 is formed. After the internal spacer feature 234 is formed in box 112, the channel extension feature 236 can be selectively deposited on the end sidewalls of the channel layer 208 and the portion of the substrate 202 exposed in the source / drain trench 228. For ease of reference, the channel extension feature 236 above the substrate 202 can be referred to as the bottom channel extension feature 236B. In some embodiments, the channel extension feature 236 may include undoped silicon (Si) and may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. As used herein, undoped silicon (Si) is substantially free of dopants (i.e., having a dopant content from about 0 cm -3 About 1×10 17 cm -3extrinsic dopant concentration), where, for example, no intentional doping is performed during the epitaxial growth process for the channel extension member 236. Because the channel layer 208 is also formed of undoped silicon (Si), the channel extension member 236 effectively increases the length of the channel layer 208.

[0049] refer to Fig.17 and Fig.19 After forming the channel extension feature 236, the method 300 proceeds to block 114 where the source / drain feature 240 is formed. In addition, the patterned hard mask used to selectively form the channel extension feature 236 in certain regions of the substrate 202 may be removed at this time, so that the operations in block 114 may be performed on all regions of the substrate 202. Fig.19 As shown in FIG. 1 , in block 114, source / drain features 240 are epitaxially and selectively formed from the surface of channel extension features 236 (including bottom channel extension features 236B). Fig.19 , the channel extension feature 236 can substantially cover the exposed surface of the channel layer 208 and the exposed portion of the substrate 202. The sidewalls of the sacrificial layer 206 remain covered by the internal spacer feature 234. Suitable epitaxial processes for frame 114 include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The epitaxial growth process in frame 114 can use a gaseous precursor that interacts with the surface of the channel extension feature 236. In some embodiments, the parameters of the epitaxial growth process in frame 114 are selected so that the source / drain feature 240 is not epitaxially deposited on the internal spacer feature 234. As similarly described above, each of the source / drain features 240 can include multiple epitaxial layers having different dopant concentrations or germanium (Ge) contents (if germanium (Ge) is desired), the source / drain features 240 can be n-type or p-type, and an annealing process can be performed to anneal the source / drain features 240. As Fig.19 As shown in FIG. 1 , when viewed along the Y direction, the source / drain feature 240 wraps over the surface of the channel extension feature 236, rather than the surface interfacing with the channel layer 208. In other words, the channel extension feature 236 extends laterally into the source / drain feature 240.

[0050] After forming the source / drain features 240, similar operations in blocks 116, 118, and 120 may be performed on the workpiece 200 to form Fig.21200B. In block 116, CESL 242 and ILD layer 244 are sequentially deposited over workpiece 200, and workpiece 200 is planarized to expose dummy gate stack 220. After removing dummy gate stack 220, after selectively removing sacrificial layer 206, channel layer 208 in channel region 212C is released to form channel member 2080. After forming channel member 2080, gate structure 250 ( Fig.21 ) to wrap each of the channel members 2080. The operations in blocks 116, 118, and 120 have been described in detail above, and for the sake of brevity, their details will not be repeated here.

[0051] like Fig.21 As shown in , the second transistor 2000B may include the same first top gate length TGL1, the same first gate length GL1, and a second channel length CL2 greater than the first channel length CL1. Forming the channel extension component 236 does not affect the dimensions of the gate structure 250, including the gate length. Fig.21 As shown in FIG. 1 , when each of the channel extension components 236 has an extension amount E along the X direction, the second channel length CL2 exceeds the extension amount E of the first channel length CL1 by about 2 times. The second transistor 2000B includes a second source / drain width (SDW2). Due to the formation of the channel extension component 236, the second source / drain width (SDW2) at the channel extension component 236 is less than Fig.14 The first source / drain width (SDW1) is shown in FIG.

[0052] Fig. 22 Shown is the method for forming Fig.29 The third transistor 2000C shown in the method 400. Fig.14 Compared to the first transistor 2000A shown in FIG. 1 , the third transistor 2000C has a longer channel length and a smaller source / drain feature width, which may result in higher resistance, lower capacitance, and lower leakage current. Figure 1 and Fig. 22 As shown in FIG. 4 , method 400 shares the operations in blocks 102 - 106 and 110 - 120 , and also includes blocks 408 and 409 .

[0053] refer to Fig. 22 and Fig.23, method 400 includes box 408, in which a first top spacer layer 225 is deposited over the dummy gate stack 220. The first top spacer layer 225 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 220. The term "conformal" is used herein for convenience to describe a layer having a substantially uniform thickness over various regions. The first top spacer layer 225 can share the same composition and thickness of the top spacer layer 226 described above with respect to method 100. In fact, in some embodiments, the first top spacer layer 225 can be the same as the top spacer layer 226, and no area of ​​the workpiece 200 is masked off in box 408. In some other embodiments where the first top spacer layer 225 and the top spacer layer 226 have different compositions, the above combination can be used. Fig.15 and Fig.16 The process described above is used to mask out areas that do not receive the first top spacer layer 225. In some embodiments, the first top spacer layer 225 may include silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, or silicon nitride. In some embodiments, the first top spacer layer 225 may be deposited over the dummy gate stack 220 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, an ALD process, or other suitable process.

[0054] refer to Fig. 22 and Fig.23 , the method 400 includes block 409, where a second top spacer layer 227 is deposited over the first top spacer layer 225. The second top spacer layer 227 is conformally deposited over the first top spacer layer 225. The second top spacer layer 227 may share the same composition and thickness of the top spacer layer 226 described above with respect to the method 100. Fig.23 In some embodiments shown in , the second top spacer layer 227 can be used as a thickening agent to increase the total thickness of the top spacer layer. For example, when each of the first top spacer layer 225 and the second top spacer layer 227 has the same thickness as the top spacer layer 226, the total thickness of the first top spacer layer 225 and the second top spacer layer 227 can be Figure 6 In some embodiments, the second top spacer layer 227 may also include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride, and may be deposited over the dummy gate stack 220 using a CVD process, a sub-atmospheric pressure CVD (SACVD) process, an ALD process, or other suitable process.

[0055] refer to Fig. 22 and Fig.24After depositing the second top spacer layer 227 , the method 400 proceeds to block 110 where the source / drain region 212SD of the fin structure 212 is recessed to form a narrow source / drain trench 2280 . Fig.24 As shown in , the recess in frame 110 can remove the top facing portions of the first top spacer layer 225 and the second top spacer layer 227 to form a thick top spacer 2270 disposed along the sidewalls of the dummy gate stack 220. In some embodiments, the source / drain region 212SD not covered by the dummy gate stack 220 is etched by dry etching or a suitable etching process to form a narrow source / drain trench 2280. For example, the dry etching process can be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. In Fig.24 In some embodiments shown in , the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. In some embodiments, the narrow source / drain trench 2280 extends into the substrate 202 under the stack 204. Due to the increased thickness of the thick top spacer 2270, along the X direction, Fig.24 Each of the narrow source / drain trenches 2280 is Figure 7 The source / drain trenches 228 in are narrow.

[0056] After forming the narrow source / drain trenches 2280, similar operations in blocks 112, 114, 116, 118, and 120 may be performed on the workpiece 200 to form Fig.29 200C. In block 112, inner spacer features 234 are formed to intersect the channel layer 208. In block 114, narrow source / drain features 2400 are formed in the narrow source / drain trenches 2280. In block 116, CESL 242 and ILD layer 244 are sequentially deposited over the workpiece 200, and the workpiece 200 is planarized to expose the dummy gate stack 220, as shown in FIG. Fig.28 After removing the dummy gate stack 220, after selectively removing the sacrificial layer 206, the channel layer 208 in the channel region 212C is released to form a channel member 2080. After forming the channel member 2080, the gate structure 250 ( Fig.29) to wrap each of the channel members 2080. An upper portion of the gate structure 250 is sandwiched between a pair of thick top spacers 2270, and a lower portion of the gate structure 250 is isolated from the source / drain features 2400 by a plurality of inner spacer features 234. The operations in blocks 112, 114, 116, 118, and 120 have been described in detail above, and for the sake of brevity, their details will not be repeated here.

[0057] like Fig.29 As shown in , the third transistor 2000C may include the same first top gate length TGL1, second gate length GL2, third channel length CL3 greater than the first channel length CL1, and third source / drain width (SDW3) less than the first source / drain feature width (SDW1). Because the X-direction dimension of the dummy gate stack 220 remains unchanged, the increased thickness of the thick top spacer 2270 results in a larger third channel length CL3. Because the thickness of the inner spacer feature 234 is substantially the same, the third channel length CL3 may also be increased by the thickness of the second top spacer layer 227.

[0058] Fig.30 Shown is the method for forming Fig.33 The fourth transistor 2000D shown in the method 500. Fig.14 Compared to the first transistor 2000A shown in FIG. 1 , the fourth transistor 2000D has a longer gate length, the same source / drain feature width, and the same channel length, which may result in higher resistance, lower capacitance, and lower leakage current. Figure 1 and Fig.30 As shown in , method 500 shares the operations in blocks 102 - 118 and 120 , and also includes block 519 .

[0059] refer to Fig.30 , Fig.31 and Fig.32 , method 500 includes frame 519, wherein the top spacer 2260 and the internal spacer component 234 are trimmed. After method 500 enters frame 102-118 to release the channel layer 208 as the channel member 2080 above the channel region 212C, the sidewalls of the top spacer 2260 and the internal spacer component 234 are exposed in the channel region 212C. In frame 519, the top spacer 2260 and the internal spacer component 234 are selectively trimmed without substantially etching the channel member 2080. In some embodiments, an isotropic wet etching process can be used to trim the top spacer 2260 and the internal spacer component 234. An exemplary isotropic wet etching process can include using hydrogen fluoride (HF) vapor. As Fig.32As shown in , trimming produces a thin top spacer 2300, a thin inner spacer component 2340, and a thin channel member 2080'. Although the channel member 2080 may be slightly etched during its release from the sacrificial layer 206, the trimming in frame 519 further trims and etches the channel member 2080 to form a thin channel member 2080'. In some embodiments, along the X direction, the top spacer 2260 includes a first thickness T1, and the inner spacer component 234 includes a second thickness (T2). The thin top spacer 2300 includes a third thickness T3, and the thin inner spacer component 2340 includes a fourth thickness (T4). In some embodiments, the ratio of the third thickness (T3) to the first thickness (T1) can be between about 0.5 and 0.85, and the ratio of the fourth thickness (T4) to the second thickness (T2) can be between about 0.5 and 0.85.

[0060] After trimming the top spacer 2260 and the inner spacer member 234, similar operations in block 120 may be performed on the workpiece 200 to form Fig.33 2000D. In block 120, a gate structure 250 is formed to wrap each of the thin channel members 2080'. An upper portion of the gate structure 250 is sandwiched between a pair of thin top spacers 2300, and a lower portion of the gate structure 250 is isolated from the source / drain member 240 by a plurality of thin inner spacer members 2340. The operations in block 120 have been described in detail above, and for the sake of brevity, its details will not be repeated here.

[0061] like Fig.33 As shown in , the fourth transistor 2000D may include a second top gate length TGL2 greater than the first top gate length TGL1, a third gate length GL3 greater than the first gate length GL1, the same first channel length CL1, and the same first source / drain component width (SDW1). Without pushing the channel-source / drain boundary to the source / drain region, the trimming widens the gate trench, increases the top gate length to the second top gate length TGL2, and increases the gate length to the third gate length GL3. The increase in the second top gate length TGL2 and the third gate length GL3 is achieved without sacrificing the first channel length CL1 and the first source / drain component width (SDW1).

[0062] The method of the embodiment of the present disclosure may be used to form different types of devices in a circuit device or a standard cell. Fig.34 A circuit device 600 is shown including a first macro 610 and a second macro 620. In some embodiments, the transistors in the first macro 610 and the second macro 620 are different. For example, all transistors in the first macro 610 may be Fig.14The first transistor 2000A in the second macro 620 may be Fig.21 The second transistor 2000B in Fig.29 The third transistor 2000C or Fig.33 The fourth transistor 2000D in. Fig.35 A standard cell 700 is shown that includes a first array 710 of transistors and a second array 720 of transistors. In some embodiments, the transistors in the first array 710 and the second array 720 are different. For example, all transistors in the first array 710 may be Fig.14 The first transistor 2000A in the second array 720 may be Fig.21 The second transistor 2000B in Fig.29 The third transistor 2000C or Fig.33 In some embodiments, each of the first transistor 2000A, the second transistor 2000B, the third transistor 2000C, and the fourth transistor 2000D has the same footprint and the same gate-to-gate spacing (i.e., gate spacing), which makes it easier to combine different types of transistors in a single circuit device or standard cell.

[0063] In one exemplary aspect, the disclosed embodiments relate to a method. The method includes: receiving a workpiece, the workpiece including an active region located above a substrate and having a plurality of first semiconductor layers interlaced with a plurality of second semiconductor layers and a dummy gate stack located above a channel region of the active region; etching a source / drain region of the active region to form a source / drain trench exposing a sidewall of the active region; selectively and partially etching the plurality of second semiconductor layers to form an internal spacer recess; forming an internal spacer component in the internal spacer recess; forming a channel extension component on the exposed sidewalls of the plurality of first semiconductor layers; after forming the channel extension component, forming a source / drain component above the source / drain trench; removing the dummy gate stack; selectively removing the plurality of second semiconductor layers to form a plurality of nanostructures in the channel region; and forming a gate structure to wrap each of the plurality of nanostructures. The channel extension component includes undoped silicon.

[0064] In some embodiments, the formation of the channel extension feature is selective to the surface of the semiconductor material. In some embodiments, after forming the source / drain feature, the channel extension feature extends laterally into the source / drain feature. In some embodiments, the source / drain trench exposes a portion of the substrate, and forming the channel extension feature also forms a bottom semiconductor layer on the exposed portion of the substrate. In some examples, the plurality of first semiconductor layers include silicon, and the plurality of second semiconductor layers include silicon germanium.

[0065] In another exemplary aspect, the disclosed embodiments relate to a semiconductor structure. The semiconductor structure includes a substrate and a first transistor and a second transistor disposed above the substrate. The first transistor includes: a first source / drain component and a second source / drain component; a first plurality of channel components extending between the first source / drain component and the second source / drain component along a direction; a first gate structure wrapping each of the first plurality of channel components; and a first gate spacer layer pair disposed above the first plurality of channel components and sandwiching a top portion of the first gate structure. The second transistor includes: a third source / drain component and a fourth source / drain component; a second plurality of channel components extending between the third source / drain component and the fourth source / drain component along a direction; a second gate structure wrapping each of the second plurality of channel components; and a second gate spacer layer pair disposed above the second plurality of channel components and sandwiching a top portion of the second gate structure. Along a direction, the thickness of each of the second gate spacer layer pair is less than the thickness of each of the first gate spacer layer pair.

[0066] In some embodiments, the top portion of the first gate structure includes a first gate length along the direction, the top portion of the second gate structure includes a second gate length along the direction, and the second gate length is greater than the first gate length. In some embodiments, the first transistor also includes a first internal spacer component interlaced with the first plurality of channel components, the second transistor also includes a second internal spacer component interlaced with the second plurality of channel components, and along the direction, the thickness of each of the second internal spacer components is less than the thickness of each of the first internal spacer components. In some embodiments, the first plurality of channel components include a first channel length, the second plurality of channel components include a second channel length, and the first channel length is substantially the same as the second channel length. In some instances, each of the first source / drain component and the second source / drain component includes a first width along the direction, each of the third source / drain component and the fourth source / drain component includes a second width along the direction, and the first width is substantially the same as the second width. In some embodiments, the first plurality of channel components include silicon. In some instances, the first transistor and the second transistor have the same footprint.

[0067] In another exemplary aspect, the disclosed embodiments relate to a method. The method includes: receiving a workpiece, the workpiece including: a substrate having a first region and a second region; a first active region located above the first region and including a plurality of first semiconductor layers interlaced with a plurality of second semiconductor layers, the first active region extending between a first source / drain component and a second source / drain component; a second active region located above the second region and including a plurality of first semiconductor layers interlaced with a plurality of second semiconductor layers, the second active region extending between a third source / drain component and a fourth source / drain component; a first dummy gate stack located above a channel region of the first active region; a first gate spacer layer pair disposed above the first active region and connecting a top portion of the first dummy gate stack to a bottom portion of the first active region; The invention relates to a method of selectively trimming the first and second semiconductor layers in the second region, wherein the first and second gate spacer layers are partially sandwiched in the middle; a second dummy gate stack, located above the channel region of the second active region; and a second gate spacer layer pair, arranged above the second active region and sandwiching the top portion of the second dummy gate stack in the middle; removing the first dummy gate stack and the second dummy gate stack; selectively removing the plurality of second semiconductor layers to form a first plurality of nanostructures in the first region and a second plurality of nanostructures in the second region; selectively trimming the first and second gate spacer layer pairs in the second region; and after trimming, forming a first gate structure to wrap each of the first plurality of nanostructures and forming a second gate structure to wrap each of the second plurality of nanostructures.

[0068] In some embodiments, the workpiece further comprises: a first internal spacer component interlaced with the plurality of first semiconductor layers in the first region and a second internal spacer component interlaced with the plurality of first semiconductor layers in the second region. In some embodiments, the selective trimming further comprises trimming the second internal spacer component. In some embodiments, the selective trimming etches the dielectric material faster than it etches the semiconductor material. In some embodiments, the first internal spacer component and the second internal spacer component comprise silicon oxycarbonitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbide. In some embodiments, the selective trimming comprises: blanket depositing a mask layer over the first region and the second region; and patterning the mask layer to form a patterned mask layer over the first region while the second region is exposed. In some instances, the mask layer comprises aluminum oxide. In some embodiments, the plurality of first semiconductor layers comprise silicon, and the plurality of second semiconductor layers comprise silicon oxide.

[0069] Some embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: receiving a workpiece, comprising: an active area, located above a substrate and comprising a plurality of first semiconductor layers interlaced with a plurality of second semiconductor layers, and a dummy gate stack, located above a channel area of ​​the active area; etching a source / drain area of ​​the active area to form a source / drain trench exposing a sidewall of the active area; selectively and partially etching the plurality of second semiconductor layers to form an internal spacer groove; forming an internal spacer component in the internal spacer groove; forming a channel extension component on the exposed sidewalls of the plurality of first semiconductor layers; after forming the channel extension component, forming a source / drain component above the source / drain trench; removing the dummy gate stack; selectively removing the plurality of second semiconductor layers to form a plurality of nanostructures in the channel area; and forming a gate structure to wrap each of the plurality of nanostructures, wherein the channel extension component comprises undoped silicon.

[0070] In some embodiments, the formation of the channel extension feature is selective to the surface of the semiconductor material.

[0071] In some embodiments, after forming the source / drain features, the channel extension features extend laterally into the source / drain features.

[0072] In some embodiments, the source / drain trench exposes a portion of the substrate,

[0073] Wherein, forming the channel extension feature also forms a bottom semiconductor layer on the exposed portion of the substrate.

[0074] In some embodiments, the plurality of first semiconductor layers include silicon, and the plurality of second semiconductor layers include silicon germanium.

[0075] Some other embodiments of the present application provide a semiconductor structure, including: a substrate; and a first transistor and a second transistor, arranged above the substrate, wherein the first transistor includes: a first source / drain component and a second source / drain component, a first plurality of channel components, extending between the first source / drain component and the second source / drain component along a direction, a first gate structure, wrapping each of the first plurality of channel components, and a first gate spacer layer pair, arranged above the first plurality of channel components and sandwiching a top portion of the first gate structure in the middle, wherein the second transistor includes: a third source / drain component and a fourth source / drain component, a second plurality of channel components, extending between the third source / drain component and the fourth source / drain component along the direction, a second gate structure, wrapping each of the second plurality of channel components, and a second gate spacer layer pair, arranged above the second plurality of channel components and sandwiching a top portion of the second gate structure in the middle, wherein, along the direction, the thickness of each of the second gate spacer layer pair is less than the thickness of each of the first gate spacer layer pair.

[0076] In some embodiments, wherein the top portion of the first gate structure includes a first gate length along the direction,

[0077] wherein the top portion of the second gate structure comprises a second gate length along the direction,

[0078] Wherein, the second gate length is greater than the first gate length.

[0079] In some embodiments, wherein the first transistor further comprises first inner spacer features interleaved with the first plurality of channel members,

[0080] wherein the second transistor further comprises second inner spacer features interlaced with the second plurality of channel members,

[0081] Wherein, along said direction, a thickness of each of the second inner spacer components is less than a thickness of each of the first inner spacer components.

[0082] In some embodiments, wherein the first plurality of channel members comprises a first channel length,

[0083] wherein the second plurality of channel members comprises a second channel length,

[0084] Wherein, the first channel length is substantially the same as the second channel length.

[0085] In some embodiments, wherein each of the first source / drain feature and the second source / drain feature comprises a first width along the direction,

[0086] wherein each of the third source / drain feature and the fourth source / drain feature comprises a second width along the direction,

[0087] The first width is substantially the same as the second width.

[0088] In some embodiments, the first plurality of channel members include silicon.

[0089] In some embodiments, the first transistor and the second transistor include the same footprint.

[0090] Some other embodiments of the present application provide a method for manufacturing a semiconductor structure, comprising: receiving a workpiece, comprising: a substrate, comprising a first region and a second region, a first active region, located above the first region, and comprising a plurality of first semiconductor layers interlaced with a plurality of second semiconductor layers, the first active region extending between a first source / drain component and a second source / drain component, a second active region, located above the second region, and comprising the plurality of first semiconductor layers interlaced with the plurality of second semiconductor layers, the second active region extending between a third source / drain component and a fourth source / drain component, a first dummy gate stack, located above a channel region of the first active region, a first gate spacer layer pair, disposed above the first active region and separating the first dummy gate stack from the first active region; The top portion of the stack is sandwiched in the middle, a second dummy gate stack is located above the channel region of the second active region, and a second gate spacer layer pair is arranged above the second active region and sandwiches the top portion of the second dummy gate stack in the middle; remove the first dummy gate stack and the second dummy gate stack; selectively remove the multiple second semiconductor layers to form a first multiple nanostructures in the first region and a second multiple nanostructures in the second region; selectively trim the first gate spacer layer pair and the second gate spacer layer pair in the second region; and after the trimming, form a first gate structure to wrap each of the first multiple nanostructures and form a second gate structure to wrap each of the second multiple nanostructures.

[0091] In some embodiments, the workpiece further includes first interior spacer features interleaved with the plurality of first semiconductor layers in the first region and second interior spacer features interleaved with the plurality of first semiconductor layers in the second region.

[0092] In some embodiments, the selective trimming further comprises trimming the second inner spacer component.

[0093] In some embodiments, the selective trim etches dielectric material faster than it etches semiconductor material.

[0094] In some embodiments, the first inner spacer component and the second inner spacer component include silicon oxycarbonitride, silicon oxynitride, silicon carbonitride, or silicon oxycarbide.

[0095] In some embodiments, the selective trimming includes:

[0096] blanket depositing a mask layer over the first region and the second region; and

[0097] The mask layer is patterned to form a patterned mask layer over the first region while the second region is exposed.

[0098] In some embodiments, the mask layer includes aluminum oxide.

[0099] In some embodiments, the plurality of first semiconductor layers include silicon, and the plurality of second semiconductor layers include silicon oxide.

[0100] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Receive artifacts, including: an active region located above the substrate and comprising a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers, and a dummy gate stack located above the channel region of the active region; Etching the source / drain region of the active region to form a source / drain trench exposing the sidewall of the active region; selectively and partially etching the plurality of second semiconductor layers to form inner spacer recesses; forming an inner spacer member in the inner spacer groove; forming a channel extension feature on the exposed sidewalls of the plurality of first semiconductor layers; After forming the channel extension feature, forming a source / drain feature over the source / drain trench; removing the dummy gate stack; selectively removing the plurality of second semiconductor layers to form a plurality of nanostructures in the channel region; and forming a gate structure to wrap each of the plurality of nanostructures, Wherein, the channel extension component comprises undoped silicon.

2. The method according to claim 1, wherein: The formation of the channel extension feature is selective to the surface of the semiconductor material.

3. The method according to claim 1, wherein: After forming the source / drain features, the channel extension features extend laterally into the source / drain features.

4. The method according to claim 1, in, The source / drain trench exposes a portion of the substrate, Wherein, forming the channel extension feature also forms a bottom semiconductor layer on the exposed portion of the substrate.

5. The method according to claim 1, wherein: The plurality of first semiconductor layers include silicon, and the plurality of second semiconductor layers include silicon germanium.

6. A semiconductor structure comprising: substrate; as well as A first transistor and a second transistor are disposed above the substrate, Wherein, the first transistor comprises: a first source / drain feature and a second source / drain feature, a first plurality of channel members extending between said first source / drain features and said second source / drain features in a direction, a first gate structure wrapping each of the first plurality of channel members, and a first gate spacer layer pair disposed over the first plurality of channel members and sandwiching a top portion of the first gate structure, Wherein, the second transistor comprises: a third source / drain component and a fourth source / drain component, a second plurality of channel members extending along said direction between said third source / drain feature and said fourth source / drain feature, a second gate structure wrapping around each of the second plurality of channel members, and a second gate spacer layer pair disposed over the second plurality of channel members and sandwiching a top portion of the second gate structure, Wherein, along the direction, a thickness of each of the second gate spacer layer pairs is less than a thickness of each of the first gate spacer layer pairs.

7. The semiconductor structure according to claim 6, in, The top portion of the first gate structure includes a first gate length along the direction, wherein the top portion of the second gate structure comprises a second gate length along the direction, Wherein, the second gate length is greater than the first gate length.

8. The semiconductor structure according to claim 6, in, The first transistor also includes first inner spacer features interleaved with the first plurality of channel members, wherein the second transistor further comprises second inner spacer features interlaced with the second plurality of channel members, Wherein, along said direction, a thickness of each of the second inner spacer components is less than a thickness of each of the first inner spacer components.

9. The semiconductor structure according to claim 6, in, the first plurality of channel members comprising a first channel length, wherein the second plurality of channel members comprises a second channel length, Wherein, the first channel length is substantially the same as the second channel length.

10. A method for manufacturing a semiconductor structure, comprising: Receive artifacts, including: a substrate including a first region and a second region, a first active region located above the first region and comprising a plurality of first semiconductor layers interleaved with a plurality of second semiconductor layers, the first active region extending between a first source / drain feature and a second source / drain feature, a second active region located above the second region and comprising the plurality of first semiconductor layers interleaved with the plurality of second semiconductor layers, the second active region extending between a third source / drain feature and a fourth source / drain feature, a first dummy gate stack located above the channel region of the first active region, a first gate spacer layer pair disposed above the first active region and sandwiching a top portion of the first dummy gate stack, a second dummy gate stack located above the channel region of the second active region, and a second gate spacer layer pair disposed over the second active region and sandwiching a top portion of the second dummy gate stack; removing the first dummy gate stack and the second dummy gate stack; selectively removing the plurality of second semiconductor layers to form a first plurality of nanostructures in the first region and a second plurality of nanostructures in the second region; selectively trimming the first gate spacer layer pair and the second gate spacer layer pair in the second region; and After the trimming, a first gate structure is formed to wrap around each of the first plurality of nanostructures and a second gate structure is formed to wrap around each of the second plurality of nanostructures.

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