Packaged semiconductor device and manufacturing method thereof

Abstract

Disclosed herein is a packaged semiconductor device having a first main surface and a second main surface and comprising: a semiconductor die; a conductive epoxy in contact with a surface of the semiconductor die and exposed in a central region of the first major surface; a plurality of studs surrounding a peripheral region of the first major surface; a bonding wire between the semiconductor die and a surface of the studs remote from the first main surface, the bonding wire providing an electrical connection between the semiconductor die and the plurality of studs; and an encapsulant defining the second major surface and sidewalls of the packaged semiconductor device, where the first major surface is defined by the conductive epoxy, the encapsulant, and the stud.

Description

Technical Field

[0001] The present disclosure relates to packaged semiconductors and to methods of manufacturing the same. In particular, the present disclosure relates to so-called leadless packages, such as ball grid array (BGA) packages, so-called quad flat no-lead (QFN) packages and similar packages. Background Art

[0002] Excluding the cost of the semiconductor die itself, one of the most expensive components of a packaged semiconductor device is the lead frame, which is conventionally electrically connected to the semiconductor die and provides a means for electrical connection to the package. In addition, conventional lead frames may involve complex geometric patterns, or in the alternative may involve complex and delicate processing. Summary of the invention

[0003] According to a first aspect of the present disclosure, there is provided a packaged semiconductor device having a first main surface and a second main surface and comprising: a semiconductor die; a conductive epoxy in contact with a surface of the semiconductor die and exposed in a central region of the first main surface; a plurality of studs surrounding a peripheral region of the first main surface; a wire bond between the semiconductor die and a surface of the stud away from the first main surface, the wire bond providing an electrical connection between the semiconductor die and the plurality of studs; and an encapsulant defining the second main surface and sidewalls of the packaged semiconductor device, wherein the first main surface is defined by the conductive epoxy, the encapsulant, and the studs. This device may have been assembled without the need for any lead frame. This, in turn, may result in a relatively low bill of materials for the semiconductor assembly.

[0004] In one or more embodiments, the semiconductor device further comprises solder balls attached to the studs at the first major surface. In one or more such embodiments, the semiconductor device package is a ball grid array (BGA) package.

[0005] In one or more embodiments, the stud is a terminal stud. In one or more such embodiments, the terminal stud is composed of copper wire. In one or more embodiments, the stud is a wire solder bump.

[0006] In one or more embodiments, the wire bond bump includes a thermosonic bonding site.

[0007] According to a second aspect of the present disclosure, there is provided a method of manufacturing a packaged semiconductor die, the method comprising: providing a metal foil on a carrier substrate; attaching a semiconductor die to the metal foil by means of a conductive epoxy; bonding a plurality of studs to the metal foil around the semiconductor die; wire bonding the semiconductor die to the plurality of studs; encapsulating the semiconductor die, wirebonds, and studs with an encapsulant; removing the carrier substrate; removing the metal foil; and singulating the packaged semiconductor die. Providing a metal foil on a carrier substrate (both of which are subsequently removed) allows the formation of metal studs on a conventional substrate (that is, a metal substrate) by bump bonding. The studs can replace the functionality of conventional fingers of a lead frame.

[0008] In one or more embodiments, the metal foil is one of aluminum and copper. These two metals are particularly convenient for subsequent bump bonding of the studs, as bump bonding to copper or aluminum is a well-known technique. However, the present disclosure is not limited to any particular metal, and different metals or metal alloys may be used instead of aluminum or copper for cost purposes or for technical reasons (such as but not limited to ease of oxidation or subsequent removal).

[0009] In one or more embodiments, the stud is copper. Using copper as the connection to form the stud bump bonding can be particularly convenient because the chemical properties of copper are well known in the semiconductor industry and copper is a relatively cheap material. However, the present disclosure is not limited thereto, and other metals or alloys may be used instead of copper, such as gold or silver.

[0010] In one or more embodiments, the stud has a diameter in the range of 100 μm to 200 μm. Those skilled in the art will appreciate that the stud preferably has at least the same diameter as or a larger diameter than the wire used for subsequent wire bonding between the stud and the semiconductor die. The diameter of the wire used for wire bonding may be selected to be compatible with any particular application. Wire bonding using wires in the range between 25 μm and 100 μm may be particularly convenient, and therefore a stud diameter equal to or greater than 100 μm may be convenient. However, the present disclosure is not limited thereto, and the size of the stud may depend on the application of the packaged semiconductor device.

[0011] In one or more embodiments, the step of bonding a plurality of studs to the metal foil around the semiconductor die comprises thermosonic bonding.

[0012] In one or more embodiments, the method further includes the step of attaching solder balls to the studs before singulating the packaged semiconductor die. The studs can thus serve as suitable anchor points for solder balls that form a ball grid array of a final device. It will be appreciated that it may be desirable to have a greater number of solder balls than the number of individual electrical connections required for the semiconductor die. In this or other cases, some studs may remain unconnected to the semiconductor die. That is, there may be studs that are not wire bonded to the semiconductor die but serve as anchor points for solder balls. In other embodiments, all studs are wire bonded to the semiconductor die.

[0013] In one or more embodiments, the metal foil is attached to the carrier substrate by an adhesive. In other embodiments, the metal foil may be directly bonded to the carrier substrate.

[0014] In one or more embodiments, the metal foil includes at least one fiducial mark for locating the semiconductor die. Those skilled in the art will appreciate that the metal foil may include multiple fiducial marks for locating multiple semiconductor dies. Alternatively or in addition, the metal foil may include other multiple fiducial marks for locating a second plurality of semiconductor dies, for example but not limited to the case where the second plurality of semiconductor dies have a different size than the first plurality of semiconductor dies. The same metal foil can therefore be used for different applications, and in particular for packaging different types of semiconductor dies. Those skilled in the art will appreciate that this can reduce costs relative to conventional packaging processes, in which the lead frame is typically specific to the size of the semiconductor die.

[0015] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Embodiments will be described, by way of example only, with reference to the accompanying drawings, in which:

[0017] Figure 1 shows a plan view and cross section of an assembly of a sacrificial metal foil mounted on a carrier substrate, which assembly may be used in place of a lead frame;

[0018] Figure 2 shows in plan view and in cross section a partially processed packaged semiconductor device at a later stage of processing according to an embodiment;

[0019] Figure 3 shows in plan view and in cross section a partially processed packaged semiconductor device at a still later stage of processing in accordance with an embodiment;

[0020] Figure 4aFiguratively illustrates a process for making a stud or bump using a process known as stud-bump bonding;

[0021] Figure 4b The resulting stud or bump is schematically shown. The stud comprises a flattened bulb integrally connected to a folded and partially flattened section of the wire;

[0022] Figure 5a showing in cross-section a partially processed packaged semiconductor device at a still later stage of processing in accordance with an embodiment;

[0023] Figure 5b showing details of a stud having a wire bonded thereto;

[0024] Figure 6 , Figure 7 and Figure 8 showing in cross-section a partially processed packaged semiconductor device at a still later stage of processing in accordance with an embodiment;

[0025] Fig. 9 This configuration is shown with the foil removed on only a portion of the device;

[0026] Fig.10 illustrates in cross-section a partially processed packaged semiconductor device at a still later stage of processing according to one or more embodiments;

[0027] Fig.11 (a) shows schematically dividing the device into individual packaged semiconductor devices;

[0028] Fig.11 (b) schematically illustrates a rear cross-section of a packaged semiconductor device according to one or more embodiments;

[0029] Fig.12 illustrates a cross section through a packaged semiconductor device according to one or more embodiments;

[0030] Fig.13 shows a device mounted on a circuit board, such as a printed circuit board, according to one or more embodiments;

[0031] Fig.14 shows a cross section through a packaged semiconductor device, in this case a BGA device, according to one or more other embodiments;

[0032] Fig.15 shows a BGA device mounted to a circuit board, such as a printed circuit board, according to one or more embodiments; and

[0033] Fig.16 A flow chart according to one or more embodiments of the present disclosure is shown.

[0034] It should be noted that the figures are diagrammatic and not drawn to scale. For clarity and convenience in the drawings, the relative sizes and proportions of the parts of these figures have been shown by being enlarged or reduced in size. The same reference numerals are generally used to refer to corresponding or similar features in modified and different embodiments. DETAILED DESCRIPTION

[0035] From one perspective, embodiments of the present disclosure may eliminate the need for a geometrically complex lead frame to be used and divided into two parts during the assembly of a leadless packaged semiconductor device. In a conventional assembly process for a packaged semiconductor device, one or more semiconductor dies are typically mounted to a central portion of a lead frame, which may be referred to as a die plate. Electrical contact pads on the semiconductor die are then wire bonded to other portions of the lead frame (typically referred to as fingers), while the fingers are typically still attached to the die plate. During the multi-stage encapsulation process, the fingers are then electrically isolated from the die plate, and at the end of the multi-stage encapsulation process, at least a portion of the fingers are exposed on a first major surface (which may be a bottom surface) of the packaged device. In the case of a QFN package, the isolated fingers may extend to the edge of the device. Conversely, in the case of a BGA package, the exposed portions of the fingers may be distributed across the bottom of the device and may then have solder balls attached thereto to form a ball grid array.

[0036] Figure 1 A plan view and cross section of an assembly 100 of a sacrificial metal foil 110 mounted on a carrier substrate 120 is shown, which assembly 100 may be used in place of a lead frame. Specifically, the metal foil may be an aluminum foil or a copper foil, but other metals may be used instead. The thickness of the foil may be in the range between 20 μm and 200 μm, with a preferred range of foil thickness being 25 μm to 50 μm. The foil is attached to the carrier substrate 120 by means of an adhesive layer 130. The carrier substrate may be made of any suitable material. Such materials may include a plastic material or a metal material, such as stainless steel. The foil may include one or more reference marks, such as the cutouts shown, on a fiducial mark 140 therein. The fiducial mark 140 may be used to locate one or more semiconductor dies. The assembly may be provided with a plurality of different types of fiducial marks 140 that may be used for different die sizes or different package sizes. A single assembly may therefore be compatible with a range of different types and / or sizes of semiconductor packages, which may simplify the bill of materials for a range of products compared to these conventional packaging processes where lead frames are typically dedicated to a specific package size, QFN contact layout, or BGA design.

[0037] Figure 2A plurality 200 of partially processed packaged semiconductor devices at a later stage of processing according to an embodiment are shown in plan view and in cross section. The figures show an assembly of a carrier substrate 120 and a metal foil 110 with a plurality of semiconductor dies 240 mounted thereon, the semiconductor dies having active circuitry in their upper regions 242. The semiconductor dies 240 are attached to the metal foil 110 by means of a conductive epoxy 245. The conductive epoxy typically covers the entire surface of each die and may extend around the edges of the die through spacers 247 as shown.

[0038] Figure 3 A plurality of 300 partially processed packaged semiconductor devices at a later stage of the process according to an embodiment are shown in plan view and in cross section. The figure shows an assembly of a metal foil 110 mounted on a carrier substrate 120 by an adhesive 130, having a plurality of semiconductor dies 240 attached thereto by means of a conductive epoxy 245. A plurality of metal studs or bumps 350 surround each of the dies. The bumps may conveniently be formed of Cu, but the disclosure is not so limited. Figure 3 As shown in , the studs or bumps 350 can be arranged around all four sides of each of the semiconductor dies. In other embodiments, they can be arranged around fewer sides, such as only two sides. In addition, as shown, the studs or bumps 350 can be arranged in two or more parallel lines, or there can be only one row of studs or bumps 350.

[0039] Figure 4a The process for making a stud or bump 350 using a process known as stud bump bonding is graphically illustrated. Stud bump bonding is a modified wire bonding process in which a bond is formed between the ball end of the wire and the substrate, and the wire is subsequently broken above the bond, leaving a stud or bump. As shown at (i), the wire 430 is extruded through a capillary 420, and the ball is typically formed at the end of the wire by a high-voltage spark that melts the tail of the wire and relies on surface tension to produce a ball with a diameter larger than the wire itself. The tool, which is usually referred to as a bonding head holding the capillary, is then lowered to press the ball end of the wire onto a surface 440. In this case, the surface is the surface of a metal foil. The ball is thereby squeezed to produce a bump bonding portion 410. The tool and capillary are raised as shown at (ii). Next, the tool and capillary are first moved laterally in one direction as shown at (iii) and then in the opposite direction as shown at (iv), thereby creating a fold 450 in the wire immediately above the bump. The tool is then lowered, as shown at (v), which further applies pressure and deforms the wire immediately adjacent to the fold and typically breaks the wire. Finally, the tool and capillary are raised, which breaks the wire if it has not already broken at (v). Figure 4bThe resulting stud or bump 350 is schematically shown. The stud includes a flattened bulb 470 integrally connected to a folded and partially flattened section of a wire 475. The partial flattening resulting from step (v) above causes at least a portion of the top surface of the stud or bump 350 to be flat and horizontal (at least relative to the original, generally circular, wire shape). This flat top surface of the stud or bump is suitable for further wire bonding operations, as will be discussed in more detail below.

[0040] Figure 5a A packaged semiconductor device according to an embodiment is shown in cross section at a later stage of the process in which multiple parts are processed. Wirebonds 560 are formed between individual studs or bumps 350 and semiconductor die 240. Wirebonds are formed between studs, which are typically made of copper, and contact pads on the top surface of the semiconductor die. The contact pads on the top surface of the die are typically made of copper or aluminum. Commonly used are aluminum materials doped or blended with a small amount of copper (e.g., <2%). Wirebonds 560 are conventional wirebonds as those skilled in the art will be familiar with, except that one end of the wirebond is formed directly onto the stud or bump 350.

[0041] Figure 5b Detail of a stud or bump 350 is shown having a wire 565 bonded thereto. The wire bonded to the stud may form part of a wire bond 560. A flat ball 470 forming a lower portion of the stud is visible as a partially flattened section of a wire 475. The stud is formed of a first material, which is typically copper as mentioned above. The wire 565 is bonded to the stud by means of a bond shown at a bonding site 567. At the bonding site 567, the wire is deformed by a bonding tool as will be familiar to those skilled in the art. Bonding may be performed by known bonding techniques such as, but not limited to, thermosonic bonding, thermocompression bonding, or ultrasonic bonding.

[0042] Figure 6 A partially processed packaged semiconductor device at a still later stage of the process according to an embodiment is shown in cross section. Encapsulant 670 has been provided over and around semiconductor die 240, studs or bumps 350, and wire bonds 560 to encapsulate the device. As shown, multiple semiconductor dies that will ultimately form multiple packaged semiconductor devices may be encapsulated together. It should be appreciated that during this encapsulation, the die remains mounted on the assembly of carrier substrate and metal foil.

[0043] Figure 7A plurality of partially processed packaged semiconductor devices at a later stage of the process according to an embodiment are shown in cross section. A carrier has been removed from the partially processed device. The carrier can be removed using any of a variety of means. For example, according to some embodiments, the carrier can be stainless steel. The foil can be attached to the tape 130, and then both are held on the carrier by vacuum during each processing step. After the molding process, the carrier vacuum can be cut or suspended, or the vacuum seal can be broken in other ways, and the foil and tape 130 can then be easily separated from the carrier. Then, the tape 130 can usually be split or removed without difficulty because the entire strip is now supported by the molding compound. Finally, the foil can be removed, for example, by mechanical polishing or chemical mechanical polishing (CMP). Removing the carrier substrate 120 and the adhesive 130 will expose the metal foil 110 on the back side of the device.

[0044] Figure 8 The partially processed packaged semiconductor device according to an embodiment is shown in cross section at a later stage of the process, in particular after the metal foil has been removed. The metal foil may be removed by etching or polishing or grinding processes. Figure 8 As shown in , all of the metal foil may be removed, exposing the studs or bumps 350, portions of the encapsulation, and the conductive epoxy. In other embodiments, the metal foil may only be partially removed. Those skilled in the art will appreciate that such embodiments may not be compatible with grinding or other CMP processes, and therefore will typically rely on patterning the back side of the device and etching through openings in the pattern. Fig. 9 This configuration is shown in FIG. 1 with the foil removed on only a portion of the device.

[0045] Fig.10 A packaged semiconductor device is shown in cross section at a later stage of the process in accordance with one or more embodiments. Specifically, conductive balls, typically solder balls, are disposed on the exposed bottom surface of the stud or bump 350. The balls provide the balls of the final BGA device. It should be appreciated that in some embodiments, such as those where the final device is a QFN package, the step of providing the balls may be omitted. Those skilled in the art will be familiar with the details of the process by which the solder wall may be attached to the stud or bump 350.

[0046] Fig.11 (a) shows schematically singulating the device into individual packaged semiconductor devices. This is done using conventional techniques, such as using saw cuts schematically shown as 1190 in the saw streets between the devices.

[0047] Fig.11(b) schematically illustrates a rear plan view and cross-section of a packaged semiconductor device according to one or more embodiments. The figure shows a plurality of solder balls 1080 arranged around all four sides of the semiconductor device die, and also arranged in two parallel lines in this case. In the illustrated embodiment, the conductive epoxy 245 is exposed in the central region of the packaged device. The encapsulant 670 is between the exposed conductive epoxy 245 and the solder balls attached to the studs or bumps 350, which also defines the sidewalls and top surface of the device.

[0048] Fig.12 A cross section through a packaged semiconductor device 1300 is shown in accordance with one or more embodiments. As can be seen, the encapsulant 670 defines the top surface and sidewalls of the device. The bottom surface of the device is defined by the encapsulant, studs or bumps 350 and conductive epoxy 425.

[0049] Fig.13 The device 1300 is shown mounted to a circuit board 1490, such as a printed circuit board, in accordance with one or more embodiments. As can be seen, the exposed surface on the stud 350 (which may have a plated (electroplated or electroless) surface thereon to aid in the surface mount technology (SMT) plating process) is typically electrically connected to a track 1495 on the circuit board by means of solder paste 1498. Another area of ​​solder paste 1498 on the circuit board 1490 is bonded to a conductive adhesive.

[0050] Fig.14 A cross section through a packaged semiconductor device 1500, in this case a BGA device, is shown according to one or more other embodiments. As can be seen, the encapsulant 670 defines the top surface of the device as well as the sidewalls. The bottom surface of the device is defined by the encapsulant, the studs or bumps 350, and the epoxy 425. Solder balls 1080 are attached to the studs or bumps 350 and protrude below the bottom surface, thereby providing the balls of the BGA device.

[0051] Fig.15 A BGA device 1500 is shown mounted to a circuit board 1490, such as a printed circuit board, in accordance with one or more embodiments. As can be seen, solder balls 1080 provide electrical contact between the BGA device 1500 and tracks 1495 on the circuit board 1490. Additional tracks or tabs 1498 on the circuit board 1490 are connected to the conductive adhesive 425 by means of another solder tab 1497.

[0052] Fig.16A flow chart according to one or more embodiments of the present disclosure is shown. Specifically, the flow chart shows a method of manufacturing a packaged semiconductor die, the method including: at 1710, pre-processing; at 1720, providing a metal foil on a carrier substrate; at 1730, attaching the semiconductor die to the metal foil by a conductive epoxy; at 1740, bonding a plurality of studs to the metal foil around the semiconductor die; at 1750, wire bonding the semiconductor die to the plurality of studs; at 1760, encapsulating the semiconductor die, the wires, and the studs with an encapsulant such as a molding compound; at 1770, removing the carrier substrate; at 1780, removing the metal foil; and at 1790, singulating the packaged semiconductor die. Optionally, the method may include a ball attach process at 1785 to attach solder balls to the exposed surfaces of the studs or bumps.

[0053] Other variations and modifications will be apparent to those skilled in the art from reading this disclosure. Such variations and modifications may involve equivalent and other features which are already known in the art of semiconductor device processing and which may be used as a substitute for or in addition to the features already described herein.

[0054] Although the attached claims are directed to specific feature combinations, it should be understood that the scope of the disclosure of the present invention also includes any novel feature or any combination of novel features or any generalization of the novel features disclosed explicitly or implicitly herein, regardless of whether the novel feature relates to the same invention as the present invention currently claimed in any claim or whether the novel feature alleviates any or all of the same technical problems as the technical problems alleviated by the present invention.

[0055] It should be noted that one or more of the embodiments above have been described with reference to different subject matters. Specifically, some embodiments may have been described with reference to method claims, while other embodiments may have been described with reference to apparatus claims. However, one skilled in the art will appreciate from the foregoing that, unless otherwise indicated, any combination of features relating to different subject matters, in addition to any combination of features belonging to one type of subject matter, and in particular, any combination of features of method claims and features of apparatus claims, are also considered disclosed with this document.

[0056] Features described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable subcombination.

[0057] For the sake of completeness, it is also provided that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, a single processor or other unit may fulfil the functions of several components recited in the claims [deleted if irrelevant], and the reference numerals in the claims should not be interpreted as limiting the scope of the claims. In addition, the word "may" is used in a permissive sense (i.e., meaning likely) rather than a mandatory sense (i.e., meaning must). Similarly, the words "include", "including" and "includes" mean including but not limited to.

Claims

1. A packaged semiconductor device, characterized in that: The packaged semiconductor device has a first major surface and a second major surface and comprises: Semiconductor die; a conductive epoxy in contact with a surface of the semiconductor die and exposed in a central region of the first major surface; a plurality of studs surrounding a peripheral region of the first major surface; a bonding wire between the semiconductor die and a surface of the stud remote from the first major surface, the bonding wire providing an electrical connection between the semiconductor die and the plurality of studs; and an encapsulant defining the second major surface and sidewalls of the packaged semiconductor device, Wherein the first major surface is defined by the conductive epoxy, the encapsulant and the stud.

2. The packaged semiconductor device according to claim 1, wherein: Also included is a solder ball attached to the stud at the first major surface.

3. The packaged semiconductor device according to claim 1, wherein: The studs are terminal studs.

4. The packaged semiconductor device according to claim 3, wherein: The studs are wire weld bumps.

5. The packaged semiconductor device according to claim 4, wherein: The wire bond bumps include thermosonic bonding sites.

6. A method for manufacturing a packaged semiconductor die, characterized in that: The method comprises: providing a metal foil on a carrier substrate; attaching a semiconductor die to the metal foil via a conductive epoxy; bonding a plurality of studs to the metal foil around the semiconductor die; wire bonding the semiconductor die to the plurality of studs; encapsulating the semiconductor die, bonding wires and studs with an encapsulant; removing the carrier substrate; removing the metal foil; and The packaged semiconductor dies are singulated.

7. The method according to claim 6, characterized in that The stud has a diameter in the range of 100 μm to 200 μm.

8. The method according to claim 6, characterized in that The step of bonding a plurality of studs to the metal foil around the semiconductor die includes thermosonic bonding.

9. The method according to claim 6, characterized in that The method additionally includes the step of attaching solder balls to the studs prior to singulating the packaged semiconductor dies.

10. The method according to claim 6, characterized in that The metal foil includes at least one fiducial mark for positioning the semiconductor die.

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