Packaging structure and chip packaging method

Abstract

The embodiment of the invention provides a packaging structure and a chip packaging method, and the structure comprises a first plastic package body in which a first chip is packaged; a silicon wafer; wherein the silicon wafer is provided with a silicon through hole, and at least one end of the silicon through hole is connected with a bonding pad; the second plastic package body and the first plastic package body are arranged in a stacked manner; a second chip is packaged in the second plastic package body; wherein at least one bonding pad of the second chip is connected to a bonding pad, on the first side of the first plastic package body, of the first chip or the silicon wafer through a first welding piece, and the first side of the first plastic package body is the side adjacent to the second plastic package body; the first rewiring layer is arranged on the second side of the first plastic package body in a stacked mode, the second side of the first plastic package body is opposite to the first side, and bonding pads, on the second side, of the first chip and the silicon wafer are connected to the first rewiring layer through second welding pieces.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip packaging, and more specifically, to a packaging structure and a chip packaging method. Background Art

[0002] Ball Grid Array Package (BGA) is an important packaging form of chip packaging products. Ball grid array packaging generally adopts flip chip technology, connecting the active surface of the chip to the substrate through a solder ball array, and attaching a heat dissipation cover on the back of the chip.

[0003] However, the above chip packaging method requires the use of a substrate, which results in a complicated packaging process and high raw material supply costs. It can be seen that the chip packaging method in the related art has the problem of complicated packaging process and high raw material supply costs due to the need to use a substrate. Summary of the invention

[0004] The embodiments of the present application provide a packaging structure and a chip packaging method to at least solve the problem of complicated packaging process and high raw material supply cost caused by the need to use a substrate in the chip packaging method in the related art.

[0005] According to one embodiment of the present application, a packaging structure is provided, comprising: a first plastic package, wherein the first plastic package encapsulates: a first chip; a silicon wafer; wherein the silicon wafer has a through silicon via, and a solder pad is connected to at least one end of the through silicon via; a second plastic package stacked with the first plastic package, wherein the second plastic package encapsulates: a second chip; wherein at least one solder pad of the second chip is connected to the first chip or the solder pad of the silicon wafer on the first side of the first plastic package through a first welding piece, and the first side of the first plastic package is a side adjacent to the second plastic package; a first rewiring layer stacked on the second side of the first plastic package, wherein the second side of the first plastic package is a side opposite to the first side, and the solder pads of the first chip and the silicon wafer on the second side are connected to the first rewiring layer through a second welding piece.

[0006] According to another embodiment of the present application, a packaging method is provided, comprising: performing plastic encapsulation on a first chip and a silicon wafer to obtain a first plastic encapsulation body, wherein the silicon wafer has a through silicon via, and at least one end of the through silicon via is connected to a pad, and the pads of the first chip and the silicon wafer located on the first side of the first plastic encapsulation body are exposed to the first plastic encapsulation body; welding at least one pad of a second chip to the pad of the first chip or the silicon wafer on the first side of the first plastic encapsulation body through a first welding member, and performing plastic encapsulation on the second chip and the first plastic encapsulation body to obtain a second plastic encapsulation body, wherein the first plastic encapsulation body and the second plastic encapsulation body are stacked, and the first side of the first plastic encapsulation body is a side adjacent to the second plastic encapsulation body; performing rewiring on the second welding member implanted on the pads of the first chip and the silicon wafer located on the second side of the first plastic encapsulation body to obtain a first rewiring layer, wherein the first rewiring layer is stacked on the second side of the first plastic encapsulation body, and the second side of the first plastic encapsulation body is a side opposite to the first side.

[0007] According to another embodiment of the present application, a packaging device is provided, comprising: a first processing unit, configured to perform a plastic encapsulation process on a first chip and a silicon wafer to obtain a first plastic encapsulation body, wherein the silicon wafer has a through silicon via, and at least one end of the through silicon via is connected to a pad, and the pads of the first chip and the silicon wafer located on the first side of the first plastic encapsulation body are exposed to the first plastic encapsulation body; a second processing unit, configured to perform a soldering process on at least one soldering pad of a second chip and a soldering pad of the first chip or the silicon wafer on the first side of the first plastic encapsulation body through a first soldering member, and perform a plastic encapsulation process on the second chip and the first plastic encapsulation body to obtain a second plastic encapsulation body, wherein the first plastic encapsulation body and the second plastic encapsulation body are stacked, and the first side of the first plastic encapsulation body is a side adjacent to the second plastic encapsulation body; a third processing unit, configured to perform a rewiring process on the second soldering member implanted on the soldering pads of the first chip and the silicon wafer located on the second side of the first plastic encapsulation body to obtain a first rewiring layer, wherein the first rewiring layer is stacked on the second side of the first plastic encapsulation body, and the second side of the first plastic encapsulation body is a side opposite to the first side.

[0008] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0009] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0010] Through the present application, by utilizing silicon wafers with through-silicon via structures and bumping interconnection technology, heterogeneous chips of different sizes and quantities are integrated in the same package in a quasi-3D stacked form, and an interface is provided to the outside through a rewiring layer, so that the packaging of the heterogeneous chips can be completed without a substrate. Therefore, the problems of complex packaging process and high raw material supply cost caused by the need to use a substrate in the chip packaging method in the related technology can be solved, thereby achieving the effect of simplifying the chip packaging process and reducing material costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a cross-sectional schematic diagram of an optional packaging structure according to an embodiment of the present invention;

[0012] Figure 2 is a cross-sectional schematic diagram of another optional packaging structure according to an embodiment of the present invention;

[0013] Figure 3 is a cross-sectional schematic diagram of another optional packaging structure according to an embodiment of the present invention;

[0014] Figure 4 is a schematic flow chart of an optional chip packaging method according to an embodiment of the present invention;

[0015] Figure 5 is a schematic diagram of another optional packaging method according to an embodiment of the present invention;

[0016] Figure 6 is a schematic diagram of another optional packaging method according to an embodiment of the present invention;

[0017] Figure 7 is a schematic diagram of another optional packaging method according to an embodiment of the present invention;

[0018] Figure 8 is a schematic diagram of another optional packaging method according to an embodiment of the present invention;

[0019] Fig. 9 is a schematic diagram of another optional packaging method according to an embodiment of the present invention;

[0020] Fig.10 is a schematic diagram of another optional packaging method according to an embodiment of the present invention;

[0021] Fig.11 is a schematic diagram of another optional packaging method according to an embodiment of the present invention;

[0022] Fig.12 is a schematic diagram of another optional packaging method according to an embodiment of the present invention;

[0023] Fig.13 is a schematic diagram of another optional packaging method according to an embodiment of the present invention;

[0024] Fig.14 is a schematic diagram of another optional packaging method according to an embodiment of the present invention;

[0025] Fig.15 is a cross-sectional schematic diagram of another optional packaging structure according to an embodiment of the present invention;

[0026] Fig.16 is a structural block diagram of a chip packaging device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] According to one aspect of an embodiment of the present application, a packaging structure is provided. Optionally, the packaging structure may be a packaging structure obtained by integrating heterogeneous chips in the same package body, and the heterogeneous chip may be a heterogeneous functional chip, which may be a functional chip with different sizes and numbers of I / O (Input / Output) pins. For chip packaging, BGA packaging is an important packaging form of current chip packaging products. BGA packaging generally adopts flip chip technology, connects the active surface of the chip to the substrate through a solder ball array, and mounts a heat dissipation cover on the back of the chip. However, BGA packaging requires the use of a substrate, the packaging process is complicated, and the cost of raw material supply is high.

[0030] In order to at least partially solve the above problems, an embodiment provides a packaging structure that can realize chip packaging without a substrate, and the packaging structure can be a fan-out type high-integration chip packaging structure obtained by chip packaging using a fan-out packaging method. Here, the Fan-out packaging method connects multiple pins (usually 4 or more) to a flat surface, and these pins are scattered over the entire surface, and the shape is similar to a fan, hence the name "Fan-out". Unlike the traditional QFP (QuadFlat Package) that arranges each row of pins at an equal angle, the Fan-out package can provide higher density, smaller models and more flexible wiring capabilities, and is particularly suitable for occasions that require compact space design, such as mobile devices, wireless communication devices and consumer electronics.

[0031] As an optional implementation, Figure 1 is a cross-sectional schematic diagram of an optional packaging structure according to an embodiment of the present invention, such as Figure 1 As shown, the packaging structure includes: a first plastic package body 101, a second plastic package body 102 stacked with the first plastic package body 101, and a first redistribution layer 110 stacked on the second side of the first plastic package body 101, wherein:

[0032] The first plastic package 101 contains:

[0033] A first chip 103; a silicon wafer 104; wherein the silicon wafer 104 has a through silicon via 105, and at least one end of the through silicon via 105 is connected to a pad;

[0034] The second plastic package 102 contains:

[0035] The second chip 107; wherein at least one pad of the second chip 107 is connected to the pad of the first chip 103 or the silicon chip 104 on the first side of the first plastic package 101 through the first welding member 108, and the first side of the first plastic package 101 is a side adjacent to the second plastic package 102;

[0036] The second side of the first plastic package 101 is a side opposite to the first side, and the pads of the first chip 103 and the silicon chip 104 on the second side are connected to the first redistribution layer 110 through the second welding member 109 .

[0037] Compared with the traditional BGA packaging, the packaging structure provided in this embodiment does not require the use of a substrate, which reduces the packaging process and the cost of raw material supply; using wafer-level packaging technology, multiple different chip packaging processes can be performed on the same machine at the same time, reducing the chip packaging time, increasing the number of chip outputs, and improving chip yields, and there is no redundant circuit design, which can reduce power consumption; there is no substrate, which can reduce packaging costs; different functional chips can be directly integrated into a system chip on the wafer, which can improve chip performance and integration. In addition, it can provide a technical route for expanding Moore's Law. Optionally, the packaging structure in this embodiment can be packaged using a Fan-out fan-out packaging method.

[0038] For the first plastic package 101, the first plastic package 101 encapsulates the first chip 103 and the silicon wafer 104. Here, the number of silicon wafers 104 can be one or more, at least one silicon wafer 104 is used as a silicon (Si) dielectric layer, and each silicon wafer 104 can have a circuit laid out by using at least one TSV (Through-silicon via) 105 and at least one corresponding pad, and a pad is connected to at least one end of the through-silicon via. The size and number of TSVs on different silicon wafers can be different. Here, the through-silicon via structure refers to a small hole or deep groove made on a single crystal silicon wafer for circuit connection or gas transmission, etc.

[0039] For the second plastic package 102, a group of second chips 107 are encapsulated in the second plastic package 102, the first chip 103 and the second chip 107 can be heterogeneous chips, the first chip 103 and each second chip 107 can be functional chips with I / O pins of different sizes and numbers, and different second chips 107 can also be functional chips with I / O pins of different sizes and numbers, or functional chips with the same size and number of I / O pins. The number of second chips 107 can be one or two or more. In this embodiment, the chip type and quantity of the first chip 103 and the second chip 107 are not limited.

[0040] Optionally, the first chip and the second chip may both be integrated chips. The types of integrated chips are not limited and they can be freely matched according to integration requirements.

[0041] The first rewiring layer 110 is used to realize the rewiring of the first chip and the second chip. The first rewiring layer 110 is stacked on the second side of the first plastic package 101 and connected to the first chip 103 and the silicon wafer 104 through the second welding piece.

[0042] As an optional solution, depending on different functional integration requirements, the first chip can freely select the chip type, which can be but is not limited to one of the following: ASIC (Application Specific Integrated Circuit) chip (i.e., dedicated integrated chip); Logic IC (logic integrated circuit) chip.

[0043] As an optional solution, depending on the different functional integration requirements, the second chip can be freely selected from different chip types, and different second chips can be freely matched. The number of second chips can be one or more, and can include but is not limited to at least one of the following: Memory chip, NAND chip, integrated circuit (e.g., Analog) chip, RF (Radio Frequency) chip, Wide I / O DRAM chip.

[0044] Optionally, the number of second chips can be two, both of which can be functional chips, one of the second chips is one of the following: Memory, NAND, Analog, RF chip, etc., which can be selected according to needs, and the other second chip is one of the following: Memory, WideI / ODRAM chip, etc., which can be selected according to needs.

[0045] There are many ways to package a chip, such as 2D (Dimensions) packaging, 2.5D packaging, and 3D packaging.

[0046] 2D packaging refers to the packaging that integrates the Die (bare crystal) into the chip in a flat manner on a two-dimensional plane. 2D packaging is limited by the physical limitations of the two-dimensional plane.

[0047] 2.5D packaging refers to laying the die on the interposer on a two-dimensional plane, and using the wiring and TSV vias of the interposer to expand the number of I / Os and interconnect with the substrate. Although 2.5D packaging has expanded the number of I / Os to a certain extent, it still has not broken through the physical limitations of the two-dimensional plane.

[0048] 3D packaging refers to making TSV vias and wiring directly on the die to achieve electrical interconnection between dies in the vertical direction. Although 3D packaging breaks through the physical limitations of the two-dimensional plane, it puts forward requirements for the type and quantity of dies, the number and size of I / Os, and the number and size of TSVs. 3D packaging is mostly used for stacking chips of the same type and matching structural dimensions.

[0049] Optionally, in this embodiment, the silicon wafer interconnection bridging technology can be used to break the physical limitations of the Die on the two-dimensional plane, and the first chip and the second chip are sealed in the vertical direction, that is, the chips with heterogeneous functions are sealed in the vertical direction in a quasi-3D stacking manner. Compared with the aforementioned 2D, 2.5D and 3D packaging, it can improve the integration, reduce the packaging volume, improve the power density of the system, shorten the chip interconnection distance to improve the system performance such as signal integrity and power integrity. At the same time, the packaging structure in this embodiment uses a silicon wafer as the Si dielectric layer, instead of using a whole-chip interposer for line switching. In addition, dies of different types, different I / O numbers and sizes, and different TSV numbers and sizes can be sealed according to needs, and the design is flexible.

[0050] Here, stacking chips in a 3D-like manner based on the existing silicon wafer interconnection bridge technology can shorten the chip interconnection distance and improve system performance such as signal integrity and power integrity. At the same time, by using the design of silicon wafer interconnection bridges with different TSV sizes and numbers, functional chips of different sizes can be integrated, and the integrated design is more flexible.

[0051] Optionally, in this embodiment, one or more silicon chips are encapsulated in the first plastic package to facilitate the sealing of the first chip and at least one second chip in a quasi-3D manner. The size and number of through silicon vias on each silicon chip can match the size and number of pads of the second chip to which each silicon chip is connected, so as to improve the flexibility of chip packaging and adapt to different functional chips or functional chip combinations.

[0052] For the second chip 107 , each pad of each second chip 107 is interconnected with a pad of the first chip 103 or one of the at least one silicon chips 104 on the first side of the first plastic package 101 through a first soldering member 108 .

[0053] Optionally, when the number of silicon wafers is two or more, at least one of the size and number of through silicon vias on at least two silicon wafers is different. For example, the sizes of the through silicon vias on at least two silicon wafers are different. For another example, the numbers of the through silicon vias on at least two silicon wafers are different.

[0054] Optionally, the first welding member 108 may be located in the second plastic package 103, and the number of the first welding member 108 may be one or more, which may match the number of pads of the first chip 103 or at least one silicon chip 104 on the first side of the first plastic package 101, and the number of pads of the second chip 107 that need to be connected to the pads of the first chip 103 or at least one silicon chip 104 on the first side of the first plastic package 101. The first welding member 108 may be of various types, including but not limited to at least one of the following: solder balls, solder columns. The materials of the solder balls include but are not limited to one or a combination of two or more of the metals such as copper, nickel, tin, gold, silver, aluminum and titanium, and the materials of the solder columns include but are not limited to one or a combination of two or more of the metals such as copper, nickel, tin, gold, silver, aluminum and titanium.

[0055] For the first plastic package 101 , the second side of the first plastic package 101 has a first rewiring layer 110 obtained by rewiring the second soldering members 109 implanted on the pads of the first chip 103 and at least one silicon chip 104 on the second side.

[0056] The second welding member 109 may be located in the first plastic package 101, and the number of the second welding member 109 may be one or more, and may match the number of pads on the second side of the first plastic package 101 of the first chip 103 or at least one silicon chip 104. The second welding member 109 may be of various types, including but not limited to at least one of the following: solder balls and solder columns. The materials of the solder balls include but are not limited to one or a combination of two or more of the metals such as copper, nickel, tin, gold, silver, aluminum, and titanium, and the materials of the solder columns include but are not limited to one or a combination of two or more of the metals such as copper, nickel, tin, gold, silver, aluminum, and titanium.

[0057] It should be noted that solder balls of different sizes and quantities can be implanted on the pads on the surface of the first chip 103 and the Si dielectric layer by means of ball implantation. The first chip 103 and the second chip 107 can freely select chip types and specifications according to different requirements of integrated functions, and the interconnection methods between chips and between chips and inner and outer layer circuits can also be freely selected, not limited to solder ball welding and copper column welding between copper and copper.

[0058] In this embodiment, the first re-wiring layer 110 is obtained by RDL (Re-Distribution Layer) processing. The redistribution layer can be used to re-plan the connection path to fall into the expected area, and can also obtain a higher contact density. The redistribution process is actually adding one or more layers to the original wafer. First, a layer of dielectric is deposited for isolation, then the original contacts are exposed, and then a new metal layer is deposited to achieve re-layout wiring.

[0059] It should be noted that the present embodiment provides a packaging structure (fan-out packaging structure) that utilizes silicon wafer interconnection bridging to integrate chips with different functions into the same integrated system-on-chip. Different from the previous silicon wafer bridging, the present embodiment utilizes silicon wafers with TSV silicon through-via structures of different sizes and numbers and bumping interconnection technology to integrate heterogeneous chips with different sizes and numbers of I / O pins in the same package, which is flexible in design; and the heterogeneous functional chips are packaged vertically with functional chips (e.g., ASIC chips) in a quasi-3D stacking manner, which improves integration, reduces packaging volume, increases system power density, and shortens chip interconnection distances to improve system performance such as signal integrity and power integrity.

[0060] At the same time, the fan-out high-integration chip packaging structure provided in this embodiment rewires the circuits of heterogeneous chips through RDL technology, thereby realizing the integration of chips with different functions. Compared with traditional BGA packaging, it has the following characteristics and advantages: no substrate is required, reducing the packaging process and raw material supply costs; using wafer-level packaging technology to improve chip yield; different functional chips can be directly integrated into a system chip on the wafer, improving chip performance and integration.

[0061] The packaging structure provided in the present embodiment includes: a first plastic package body, in which: a first chip is packaged; a silicon wafer; wherein the silicon wafer has a through silicon via, and a pad is connected to at least one end of the through silicon via; a second plastic package body stacked with the first plastic package body, in which: a second chip is packaged; wherein at least one pad of the second chip is connected to the pad of the first chip or silicon wafer on the first side of the first plastic package body through a first welding piece, and the first side of the first plastic package body is a side adjacent to the second plastic package body; a first rewiring layer stacked on the second side of the first plastic package body, wherein the second side of the first plastic package body is a side opposite to the first side, and the pads of the first chip and silicon wafer on the second side are connected to the first rewiring layer through a second welding piece. This can solve the problems of complex packaging process and high raw material supply cost caused by the need to use a substrate in the chip packaging method in the related art, simplify the chip packaging process, and reduce the raw material supply cost.

[0062] As an alternative, Figure 2 As shown, at least one side of the first chip 103 has a second rewiring layer 201 obtained by rewiring the solder bumps of the first chip 103, and at least one side of each second chip 107 has a third rewiring layer 202 obtained by rewiring the solder bumps of each second chip 107.

[0063] The second rewiring layer 201 and the third rewiring layer 202 are formed in a similar manner to the first rewiring layer 110 in the above embodiment, and are not described in detail here. The second rewiring layer 201 can be used to realize the rewiring of the first chip, and the third rewiring layer 202 can be used to realize the rewiring of the second chip.

[0064] Here, the bump and rewiring layer will occupy the plane area where the chip is bonded to the substrate, and TSV can stack the chips to make use of the three-dimensional space. More importantly, stacking technology improves the electrical properties of multi-chip connections, and TSV can achieve lower power consumption and greater bandwidth for transmission between chips.

[0065] According to this embodiment, by rewiring the solder bumps of the sealed chips, heterogeneous chips can be conveniently sealed, thereby improving the convenience of chip packaging.

[0066] As an alternative, Figure 3 As shown, a third welding part 301 is welded on the first re-wiring layer 110, and the number of the third welding parts 301 can be the same as the number of welding pads of the first chip and silicon wafer connected to the first re-wiring layer 110 and located on the second side of the first plastic package, which can be at least one of the following: solder balls, solder columns, wherein the materials of the solder balls and the materials of the solder columns can be similar to those in the aforementioned embodiments and are not elaborated here.

[0067] According to this embodiment, by welding the welding parts on the rewiring layer, an interface can be provided outwardly, thereby improving the convenience of function provision.

[0068] According to another aspect of the embodiment of the present application, a chip packaging method is provided, which can be used to package a heterogeneous chip to obtain the aforementioned packaging structure. Figure 4 As shown, Figure 4 is a flow chart of an optional chip packaging method according to an embodiment of the present invention, such as Figure 4 As shown, the process of the method may include the following steps:

[0069] Step S402, performing plastic packaging processing on the first chip and the silicon wafer to obtain a first plastic packaging body.

[0070] The packaging method in this embodiment can be applied to the scenario of chip packaging, for example, it can be applied to the scenario of integrating heterogeneous functional chips into a system chip to improve the chip processing function. The number of packaged chips can be one or more, the types of packaged chips can be completely the same, partially the same, or completely different, and the packaging method can adopt the Fan-out packaging method, and the lines of the heterogeneous chips are rewired through the RDL technology to achieve the integration of chips with different functions.

[0071] When performing chip packaging, the first chip and the silicon wafer may be plastic-sealed using a plastic packaging material to obtain a first plastic packaging body. The first chip, the silicon wafer and the first plastic packaging body are similar to those in the aforementioned embodiment and are not described in detail herein.

[0072] For example, the functional chip a (LogicIC, corresponding to the first chip) and the Si dielectric layer can be encapsulated with a plastic encapsulation material. At this time, the inner solder balls (corresponding to the second welding parts) are completely wrapped by the plastic encapsulation material, and the plastic encapsulation body 1 (corresponding to the first plastic encapsulation body) plays a good protective and supporting role.

[0073] Step S404, welding at least one pad of the second chip to the pad of the first chip or silicon wafer on the first side of the first plastic package body through the first welding member, and plastic-sealing the second chip and the first plastic package body to obtain a second plastic package body.

[0074] To obtain the first plastic package, at least one pad of the second chip can be welded to the pad of the first chip or silicon wafer on the first side of the first plastic package through the first welding member. Here, the pad to which each pad of each second chip is connected can be preset to achieve automatic welding of the chip.

[0075] After the above-mentioned welding process is completed, the second chip and the first plastic package body can be plastic-packaged to obtain a second plastic package body. The first plastic package body and the second plastic package body are stacked, and the first side of the first plastic package body is the side adjacent to the second plastic package body. The second plastic package body can completely wrap the second chip and the first plastic package body, and a certain thickness needs to be maintained from its edge to ensure the reliability and high performance of the chip.

[0076] For example, after planting the required number of solder balls of different sizes on the pads of the functional chip a and the Si dielectric layer, align and solder the pads of the chip b and chip c (corresponding to a group of second chips) after rewiring with the solder balls, and then perform a second plastic sealing process on the plastic package body. At this time, the plastic package body 2 needs to completely wrap the chip b (Memory1), chip c (Memory2) and the plastic package body 1, and a certain thickness needs to be maintained from the edge to ensure the reliability and high performance of the chip.

[0077] Step S406, rewiring the first chip and the second soldering member implanted on the soldering pads of the silicon wafer on the second side of the first plastic package body to obtain a first rewiring layer.

[0078] After the second plastic packaging, the second welding piece planted on the pads of the first chip and the silicon wafer on the second side of the first plastic packaging body can be re-wired to obtain a first re-wiring layer, the pads of the first chip and the silicon wafer on the second side are connected to the first re-wiring layer through the second welding piece, and the first re-wiring layer is stacked and arranged on the second side of the first plastic packaging body, and the second side of the first plastic packaging body is the side opposite to the first side. The way of performing the re-wiring process is similar to that in the above-mentioned embodiment, and will not be repeated here.

[0079] For example, a Fan-out fan-out packaging method can be used to rewire the balls implanted for the first time on the functional chip a and the Si dielectric layer, and the outer solder balls can be welded on the manufactured outer metal circuits to complete the packaging.

[0080] Through the above steps, the first chip and the silicon wafer are plastic-sealed to obtain a first plastic-sealed body, wherein the silicon wafer has a through silicon via, at least one end of the through silicon via is connected to a pad, and the pads of the first chip and the silicon wafer located on the first side of the first plastic-sealed body are exposed to the first plastic-sealed body; at least one pad of the second chip is welded to the pad of the first chip or the silicon wafer on the first side of the first plastic-sealed body through a first welding member, and the second chip and the first plastic-sealed body are plastic-sealed to obtain a second plastic-sealed body, wherein the first plastic-sealed body and the second plastic-sealed body are stacked and arranged The first side of the first plastic package is a side adjacent to the second plastic package; the second welding piece planted on the pads of the first chip and the silicon wafer on the second side of the first plastic package is re-wired to obtain a first re-wiring layer, wherein the first re-wiring layer is stacked and arranged on the second side of the first plastic package, and the second side of the first plastic package is a side opposite to the first side. This can solve the problems of complex packaging process and high raw material supply cost caused by the need to use a substrate in the chip packaging method in the related art, simplify the chip packaging process, and reduce material costs.

[0081] As an optional solution, before the first chip and the silicon wafer are plastic-sealed, the method further includes:

[0082] S11, mounting the first chip and the silicon wafer on the first adhesive film in sequence, wherein the first adhesive film is laid flat on the first supporting carrier.

[0083] In order to ensure the stability of the plastic encapsulation, before the first chip and the silicon wafer are plastic encapsulated, a first adhesive film can be laid flat on the first support carrier, and the first chip and the silicon wafer can be mounted on the first adhesive film in sequence to prevent the first chip and the silicon wafer mounted thereon from shifting. Here, the first support carrier can be a carrier wafer, which can be made of silicon, has a flat surface, and can play a supporting role. The first adhesive film can be sticky, and the material of the adhesive film is not limited in this embodiment.

[0084] For example, Figure 5 As shown, a support carrier 1501 with a flat surface and capable of supporting is selected, and a layer of adhesive film 1 (Adhesive film) 502 is laid on it to prevent deviation, wherein the support carrier 1 is a carrier wafer (carrier wafer); then, the functional chip a (Logic IC) and the Si dielectric layer are sequentially mounted on the supportive and adhesive film 1502, as shown in FIG. Figure 6 As shown, the two layers outside the functional chip are RDL, the rectangle outside is a copper column pad, and the I-shape is a TSV silicon through-via, which is located on the Si dielectric layer.

[0085] Then, solder balls of different sizes and quantities can be planted on the pads on the surface of the functional chip a and the Si dielectric layer by means of ball planting, such as Figure 7 Next, the functional chip a and the Si dielectric layer are molded with a molding compound. At this time, the inner solder balls are completely wrapped by the molding compound. Figure 8 shown.

[0086] According to this embodiment, the chip and the silicon wafer are sequentially mounted using the adhesive film laid flat on the support carrier, which can prevent the chip and / or the silicon wafer from being offset and improve the stability of the plastic package.

[0087] As an optional solution, after the first chip and the silicon wafer are plastic-sealed, the method further includes:

[0088] S21, sequentially covering a second adhesive film and a second supporting carrier on a second side of the first plastic packaging body, wherein the sizes of the second adhesive film and the second supporting carrier are larger than the size of the first plastic packaging body;

[0089] S22, performing a flipping operation on the first plastic package body, and removing the first supporting carrier and the first adhesive film in sequence.

[0090] After the first chip and the silicon wafer are plastic-sealed, the pads of the first chip and the silicon wafer that need to be soldered to the pads on the second chip are located on the side connected to the first adhesive film. To this end, the first plastic package can be flipped over, and the first support carrier and the first adhesive film can be removed in sequence to expose the pads on the first chip and the silicon wafer.

[0091] In order to ensure the stability of subsequent processing, before the first plastic packaging body is flipped over, a second adhesive film and a second supporting carrier can be sequentially covered on the second side of the first plastic packaging body. The size of the second adhesive film and the second supporting carrier is larger than that of the first plastic packaging body to facilitate subsequent processing (for example, secondary plastic packaging).

[0092] For example, a layer of adhesive film 2902 and a support carrier 2901 which are slightly larger than the plastic packaging body 1 and have adhesiveness may be covered on the plastic packaging body 1. Fig. 9 Then, the current plastic package body 1 is flipped over to expose the support carrier 1 and the adhesive film 1 originally at the bottom, as shown in FIG. Fig.10 After that, remove the support carrier 1 (RemoveCarrier1) and the adhesive film 1 to expose the pads of the functional chip a and the Si dielectric layer, as shown in FIG. Fig.11 shown.

[0093] After planting the required number of solder balls of different sizes on the pads of the functional chip a and the Si dielectric layer, align the pads of the rewiring chip b (Memory 1 chip) and chip c (Memory 2 chip) with the solder balls and solder them, and then perform a second plastic sealing process on the plastic package. At this time, the plastic package 2 needs to completely wrap the chip b, chip c and plastic package 1, and a certain thickness needs to be maintained from its edge to ensure the reliability and high performance of the chip. Fig.12 shown.

[0094] Through this embodiment, by adding a new support carrier and adhesive film, turning over the plastic package body, and removing the previous support carrier and adhesive film, the stability of subsequent processing can be ensured, and the convenience of plastic packaging processing can be improved.

[0095] As an optional solution, before rewiring the first chip and the second soldering member implanted on the soldering pad of the silicon wafer on the second side of the first plastic package, the method further includes:

[0096] S31, sequentially covering a third adhesive film and a third supporting carrier on a side of the second plastic packaging body opposite to the first plastic packaging body;

[0097] S32, performing a flipping operation on the second plastic package body, and removing the second supporting carrier and the second adhesive film in sequence.

[0098] The second welding part is located in the first plastic package, on a side opposite to a group of second chips. In order to re-wire the second welding part, the second plastic package can be flipped over, and the second supporting carrier and the second adhesive film can be removed in sequence to expose the first chip and the second welding part implanted on the pads of at least one silicon chip located on the second side of the first plastic package.

[0099] In order to ensure the stability of subsequent processing, before performing the flipping operation on the second plastic packaging body, the third adhesive film and the third supporting carrier can be sequentially covered on the side of the second plastic packaging body opposite to the first plastic packaging body. Optionally, the third adhesive film or other supporting components can also be covered only on the side of the second plastic packaging body opposite to the first plastic packaging body, which is not limited in this embodiment.

[0100] For example, after a layer of adhesive film 31301 is attached to the surface of the plastic package on one side of chip b and chip c, the plastic package is turned over to expose the support carrier 2 and the adhesive film 2, which are then removed. Fig.13 shown.

[0101] According to this embodiment, a layer of adhesive film is added to stabilize the plastic package body, so that the stability of the plastic package body can be improved, and subsequent processing procedures can be performed more easily.

[0102] Optionally, before rewiring the first chip and the second soldering member implanted on the soldering pad of the silicon wafer on the second side of the first plastic package body, the method further comprises:

[0103] S41, thinning the second side of the first plastic package body to expose the first chip and the second welding member implanted by the welding pad of the silicon wafer located on the second side of the first plastic package body.

[0104] During the plastic encapsulation, if the plastic encapsulation position is precisely controlled, that is, the plastic encapsulation is performed to a position where the second welding part is exposed, the precision of the plastic encapsulation is required to be high, which not only increases the cost, but also easily leads to the problem of inaccurate plastic encapsulation. In this embodiment, the second side of the first plastic encapsulation body can be thinned to expose the second welding part implanted by the pads of the first chip and the silicon wafer located on the second side of the first plastic encapsulation body. Here, the rewiring process can be implemented by adopting the Fan-out fan-out packaging method, and the thinning process can be implemented by cutting, grinding, etc., which is not limited in this embodiment.

[0105] For example, the upper layer of the plastic package 1 can be thinned (MoldGrinding) to expose the functional chip a and the first implanted balls on the Si dielectric layer, and a fan-out fan-out packaging method is used to rewire them, and the outer solder balls are welded on the manufactured outer metal circuits, and finally the film 3 is removed to complete the packaging. Fig.14 shown.

[0106] According to this embodiment, by thinning the plastic package body to expose the required welding parts, the requirements for the plastic packaging process can be reduced, the convenience of chip plastic packaging can be improved, and the cost can be reduced.

[0107] As an optional solution, before the first chip and the silicon wafer are plastic-sealed, the method further includes:

[0108] S51, performing TSV processing and pad processing on the silicon wafer to obtain a silicon wafer with TSVs, wherein the size and number of the TSVs on the silicon wafer match the size and number of pads of a second chip connected to the silicon wafer.

[0109] In this embodiment, in order to achieve sealing with chips of different specifications, each silicon wafer in at least one silicon wafer can be processed with silicon vias and pads to obtain each silicon wafer having a circuit laid out by at least one silicon via and at least one pad.

[0110] Here, the pads on each silicon wafer may correspond to the TSVs one by one, and the TSV silicon through-via structures may be of different sizes, and their sizes may match the size of the pads of the second chip to which each silicon wafer is connected, or the TSVs on each silicon wafer may be of the same size, and the sizes of the TSVs on different silicon wafers may be different. Optionally, the number of TSVs on each silicon wafer may match the number of pads of the second chip to which each silicon wafer is connected, or the number of TSVs on each silicon wafer may be fixed, and the number of silicon wafers may be adjusted to match the number of TSVs on the silicon wafer with the number of pads of the second chip to which the silicon wafer is connected, which is not limited in this embodiment.

[0111] For example, the functional chip a is processed with the rewiring layer RDL and copper pillar pads in sequence, and the Si dielectric layer is processed with TSV silicon through via technology to make circuits and pads. The number and size of TSV silicon through vias can be matched according to the different sizes and numbers of I / O pins of the chip to be sealed.

[0112] Through this embodiment, functional chips of different sizes are integrated by utilizing the design of silicon wafer interconnection bridges with different TSV sizes and numbers, thereby improving the flexibility of integrated design.

[0113] The packaging structure in the embodiment of the present invention is explained below in conjunction with an optional example. In this optional example, a fan-out type highly integrated packaging structure is provided, which can be obtained by a fan-out type highly integrated chip packaging method, and the packaging structure includes: a first chip is a functional chip a (LogicIC), and a group of second chips includes a functional chip b (Memory1 chip) and a functional chip c (Memory2 chip).

[0114] like Fig.15 As shown, the packaging structure includes:

[0115] 1501, support carrier 1 (removed after the process is completed);

[0116] 1502, adhesive film 1 (removed after the process is completed);

[0117] 1503, functional chip a;

[0118] 1504, redistribution layer RDL1;

[0119] 1505, copper pillar pad;

[0120] 1506,TSV;

[0121] 1507, Si dielectric layer;

[0122] 1508, inner solder ball;

[0123] 1509, plastic package 1;

[0124] 1510, support carrier 2 (removed after the process is completed);

[0125] 1511, adhesive film 2 (removed after the process is completed);

[0126] 1512, functional chip b;

[0127] 1513, functional chip c;

[0128] 1514, plastic package 2;

[0129] 1515, adhesive film 3 (removed after the process is completed);

[0130] 1516, redistribution layer RDL2;

[0131] 1517, outer solder balls.

[0132] Here, the chip type, I / O size and quantity in this structure can be replaced with different chip specifications and integrated into the system chip according to different actual application scenarios. The interconnection method between chips and between chips and inner and outer layer circuits in this structure can also be freely selected, not limited to solder ball welding and copper pillar welding between copper and copper.

[0133] Through this optional example, different functional chips of heterogeneous structures are integrated into a chip with multiple signal processing functions using wafer-level packaging technology. The packaging technology used is different from other advanced packaging technologies. For example, unlike the general 2DFan-out packaging technology, the chips can be integrated into a single chip in the vertical direction. Under the same conditions, the integration can be improved and the packaging volume can be reduced. The resulting chip is an integrated system chip, which integrates more functional units per unit volume and can improve the power density of the system.

[0134] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0135] According to another aspect of the embodiments of the present invention, a chip packaging device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0136] Fig.16 is a structural block diagram of a chip packaging device according to an embodiment of the present invention. Fig.16 As shown, the device comprises:

[0137] The first processing unit 1602 is used to perform plastic packaging on the first chip and the silicon wafer to obtain a first plastic packaging body, wherein the silicon wafer has a through silicon via, at least one end of the through silicon via is connected to a pad, and the pads of the first chip and the silicon wafer located on a first side of the first plastic packaging body are exposed to the first plastic packaging body;

[0138] The second processing unit 1604 is used to perform welding processing on at least one welding pad of the second chip and the welding pad of the first chip or silicon wafer on the first side of the first plastic package body through the first welding piece, and perform plastic packaging processing on the second chip and the first plastic package body to obtain a second plastic package body, wherein the first plastic package body and the second plastic package body are stacked and arranged, and the first side of the first plastic package body is a side adjacent to the second plastic package body;

[0139] The third processing unit 1606 is used to re-wire the second welding part implanted on the pad of the first chip and the silicon wafer on the second side of the first plastic package to obtain a first re-wiring layer, wherein the first re-wiring layer is stacked on the second side of the first plastic package, and the second side of the first plastic package is a side opposite to the first side.

[0140] According to the present embodiment, the first chip and the silicon wafer are plastic-sealed to obtain a first plastic-sealed body, wherein the silicon wafer has a through silicon via, and at least one end of the through silicon via is connected to a pad, and the pads of the first chip and the silicon wafer located on the first side of the first plastic-sealed body are exposed to the first plastic-sealed body; at least one pad of the second chip is welded to the pad of the first chip or the silicon wafer on the first side of the first plastic-sealed body through a first welding piece, and the second chip and the first plastic-sealed body are plastic-sealed to obtain a second plastic-sealed body, wherein the first plastic-sealed body and the second plastic-sealed body are stacked, and the first side of the first plastic-sealed body is a side adjacent to the second plastic-sealed body; the second welding piece planted on the pads of the first chip and the silicon wafer located on the second side of the first plastic-sealed body is re-wired to obtain a first re-wiring layer, wherein the first re-wiring layer is stacked on the second side of the first plastic-sealed body, and the second side of the first plastic-sealed body is a side opposite to the first side, which can solve the problem of complicated packaging process and high raw material supply cost caused by the need to use a substrate in the chip packaging method in the related art, simplify the chip packaging process, and reduce material cost.

[0141] Optionally, the above device further includes:

[0142] The mounting unit is used to mount the first chip and the silicon wafer in sequence on the first adhesive film before performing plastic packaging on the first chip and the silicon wafer, wherein the first adhesive film is laid flat on the first supporting carrier.

[0143] Optionally, the above device further includes:

[0144] A first covering unit is used to sequentially cover a second adhesive film and a second supporting carrier on a second side of the first plastic packaging body after the first chip and the silicon wafer are plastic-sealed, wherein the size of the second adhesive film and the second supporting carrier is larger than the size of the first plastic packaging body;

[0145] The first execution unit is used to perform a flipping operation on the first plastic package body and remove the first supporting carrier and the first adhesive film in sequence.

[0146] Optionally, the above device further includes:

[0147] A second covering unit is used to sequentially cover a third adhesive film and a third support carrier on a side of the second plastic package body opposite to the first plastic package body before rewiring the first chip and the second welding member planted on the pad of the silicon wafer on the second side of the first plastic package body;

[0148] The second execution unit is used to perform a flipping operation on the second plastic package body and remove the second supporting carrier and the second adhesive film in sequence.

[0149] Optionally, the above device further includes:

[0150] The fourth processing unit is used to thin the second side of the first plastic package body before rewiring the second welding parts planted on the welding pads of the first chip and the silicon wafer on the second side of the first plastic package body to expose the second welding parts planted on the welding pads of the first chip and the silicon wafer on the second side of the first plastic package body.

[0151] Optionally, the above device further includes:

[0152] The fifth processing unit is used to perform through silicon via processing and pad processing on the silicon wafer before plastic-sealing the first chip and the silicon wafer to obtain a silicon wafer with through silicon vias, wherein the size and number of the through silicon vias on the silicon wafer match the size and number of pads of the second chip to which the silicon wafer is connected.

[0153] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0154] According to another aspect of the embodiments of the present invention, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0155] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0156] According to another aspect of an embodiment of the present invention, there is provided an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0157] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0158] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0159] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0160] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A packaging structure, It is characterized in that include: A first plastic package body, wherein the first plastic package body encapsulates: a first chip; A silicon wafer; wherein the silicon wafer has a through silicon via, and at least one end of the through silicon via is connected to a pad; A second plastic package body stacked with the first plastic package body, wherein the second plastic package body encapsulates: a second chip; wherein at least one pad of the second chip is connected to the pad of the first chip or the silicon wafer on the first side of the first plastic package body through a first welding member, and the first side of the first plastic package body is a side adjacent to the second plastic package body; A first rewiring layer is stacked on the second side of the first plastic package, wherein the second side of the first plastic package is opposite to the first side, and the pads of the first chip and the silicon wafer on the second side are connected to the first rewiring layer through a second welding member.

2. The packaging structure according to claim 1, It is characterized in that At least one side of the first chip has a second rewiring layer obtained by rewiring the solder bumps of the first chip, and at least one side of the second chip has a third rewiring layer obtained by rewiring the solder bumps of the second chip.

3. The packaging structure according to claim 1, It is characterized in that The first chip and the second chip are sealed in a vertical direction.

4. The packaging structure according to claim 1, It is characterized in that The first welding component is located in the second plastic package body, and the second welding component is located in the first plastic package body.

5. The packaging structure according to claim 1, It is characterized in that The first welding member is at least one of the following: a solder ball, a solder column; the second welding member is at least one of the following: a solder ball, a solder column.

6. The packaging structure according to claim 1, It is characterized in that The first chip is a dedicated integrated chip or a logic integrated circuit chip.

7. The packaging structure according to claim 1, It is characterized in that The number of the second chips is two, one of the second chips is at least one of the following: a memory chip, a NAND flash memory chip, an integrated circuit chip, a radio frequency chip, and the other second chip is at least one of the following: a memory chip, a broadband input and output dynamic random access memory chip.

8. The packaging structure according to claim 1, It is characterized in that The size and number of the through silicon vias on the silicon wafer match the size and number of the pads of the second chip connected to the silicon wafer.

9. The packaging structure according to claim 1, It is characterized in that There are multiple silicon wafers, and at least two of the silicon wafers have different sizes and numbers of through silicon vias.

10. The packaging structure according to any one of claims 1 to 9, It is characterized in that A third welding member is welded on the first redistribution layer, and the third welding member is at least one of the following: a solder ball, a solder column.

11. A chip packaging method, It is characterized in that include: Performing plastic encapsulation on the first chip and the silicon wafer to obtain a first plastic encapsulation body, wherein the silicon wafer has a through silicon via, at least one end of the through silicon via is connected to a pad, and the pads of the first chip and the silicon wafer located on a first side of the first plastic encapsulation body are exposed to the first plastic encapsulation body; Welding at least one pad of the second chip to the pad of the first chip or the silicon wafer on the first side of the first plastic package body through a first welding member, and plastic-sealing the second chip and the first plastic package body to obtain a second plastic package body, wherein the first plastic package body and the second plastic package body are stacked, and the first side of the first plastic package body is a side adjacent to the second plastic package body; The first chip and the second welding part implanted on the pad of the silicon wafer on the second side of the first plastic package are re-wired to obtain a first re-wiring layer, wherein the first re-wiring layer is stacked on the second side of the first plastic package, and the second side of the first plastic package is the side opposite to the first side.

12. The method according to claim 11, It is characterized in that Before the first chip and the silicon wafer are plastic-sealed, the method further includes: The first chip and the silicon wafer are sequentially mounted on a first adhesive film, wherein the first adhesive film is laid flat on a first supporting carrier.

13. The method according to claim 12, It is characterized in that After the first chip and the silicon wafer are plastic-sealed, the method further includes: A second adhesive film and a second supporting carrier are sequentially covered on the second side of the first plastic packaging body, wherein the sizes of the second adhesive film and the second supporting carrier are larger than the size of the first plastic packaging body; The first plastic package body is turned over, and the first supporting carrier and the first adhesive film are removed in sequence.

14. The method according to claim 13, It is characterized in that Before rewiring the first chip and the second soldering member planted on the pad of the silicon wafer on the second side of the first plastic package, the method further includes: Sequentially covering a third adhesive film and a third supporting carrier on a side of the second plastic packaging body opposite to the first plastic packaging body; The second plastic package body is turned over, and the second supporting carrier and the second adhesive film are removed in sequence.

15. The method according to claim 11, It is characterized in that Before rewiring the first chip and the second soldering member planted on the pad of the silicon wafer on the second side of the first plastic package, the method further includes: The second side of the first plastic package is thinned to expose the first chip and the second welding member implanted on the pad of the silicon wafer located on the second side of the first plastic package.

16. The method according to any one of claims 11 to 15, It is characterized in that Before the first chip and the silicon wafer are plastic-sealed, the method further includes: The silicon wafer is subjected to through silicon via processing and pad processing to obtain the silicon wafer having the through silicon via, wherein the size and number of the through silicon vias on the silicon wafer match the size and number of the pads of the second chip connected to the silicon wafer.

Images