Three-dimensional integrated circuit structure

Abstract

The invention provides a three-dimensional integrated circuit structure formed by stacking a plurality of semiconductor structures, and the plurality of semiconductor structures form a multi-chip heterogeneous three-dimensional packaging configuration through bonding pads of a redistribution layer by a direct bonding technology. A plurality of semiconductor structures are manufactured by using the same or different chips through a back-end packaging manufacturing process, and then the plurality of semiconductor structures are stacked and interconnected by using a hybrid bonding technology. The position of the bonding pad can be redefined through the rewiring layer, and the limitation of the position of the chip bonding pad, the size and the number of chips in the past is broken through.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional integrated circuit structure and a manufacturing method thereof. Background Art

[0002] Three-dimensional (3D) integration technology can reduce interconnect delays by reducing the length and number of interconnect lines on electronic integrated circuit (IC) chips, enabling heterogeneous integration of technologies and systems.

[0003] 3D integration offers higher performance, higher density, increased functionality, smaller form factors and potential cost reductions. With this emerging field comes the need for new and improved technologies to address the associated manufacturing challenges. Summary of the invention

[0004] The main purpose of the present invention is to provide a three-dimensional integrated circuit structure and a method for manufacturing the same to solve the deficiencies or shortcomings of the prior art.

[0005] On the one hand, the present invention provides a three-dimensional integrated circuit structure, comprising: a first semiconductor structure, comprising a plurality of first grains encapsulated by a first gap filling material, and a first redistribution layer electrically connected to the plurality of first grains, wherein the first redistribution layer comprises a plurality of first bonding pads, and a first insulating layer surrounding the plurality of first bonding pads; and a second semiconductor structure, comprising a plurality of second grains encapsulated by a second gap filling material, wherein the plurality of second grains comprise at least one through silicon via (TSV) grain, and a second redistribution layer electrically connected to the plurality of second grains, wherein the second redistribution layer comprises a plurality of second bonding pads and a second insulating layer surrounding the plurality of second bonding pads, wherein the plurality of first bonding pads are directly bonded to the plurality of second bonding pads respectively.

[0006] According to an embodiment of the present invention, the plurality of first bonding pads and the plurality of second bonding pads include copper pads.

[0007] According to an embodiment of the present invention, the first insulating layer and the second insulating layer include silicon oxide, silicon nitride or silicon carbonitride.

[0008] According to an embodiment of the present invention, the first insulating layer is directly bonded to the second insulating layer.

[0009] According to an embodiment of the present invention, the three-dimensional integrated circuit structure further includes a third redistribution layer disposed on a side of the second semiconductor structure opposite to the second redistribution layer.

[0010] According to an embodiment of the present invention, the three-dimensional integrated circuit structure further includes a plurality of connecting members disposed on the third redistribution layer.

[0011] According to an embodiment of the present invention, the plurality of connecting members include solder bumps or solder balls.

[0012] According to an embodiment of the present invention, the TSV die includes a plurality of through silicon vias for electrically connecting the second redistribution layer with the third redistribution layer.

[0013] According to an embodiment of the present invention, the three-dimensional integrated circuit structure further includes a plurality of conductive pillars embedded in the second gap filling material and electrically connected to the second redistribution layer.

[0014] According to an embodiment of the present invention, the first gap filling material and the second gap filling material include dielectric material or molding compound.

[0015] On the other hand, the present invention provides a method for manufacturing a three-dimensional integrated circuit structure, comprising: forming a first semiconductor structure, comprising a plurality of first grains encapsulated by a first gap filling material, and a first redistribution layer electrically connected to the plurality of first grains, wherein the first redistribution layer comprises a plurality of first bonding pads, and a first insulating layer surrounding the plurality of first bonding pads; forming a second semiconductor structure, comprising a plurality of second grains encapsulated by a second gap filling material, and a second redistribution layer electrically connected to the plurality of second grains, wherein the second redistribution layer comprises a plurality of second bonding pads, and a second insulating layer surrounding the plurality of second bonding pads; and hybrid bonding of the first semiconductor structure and the second semiconductor structure, wherein the plurality of first bonding pads are directly bonded to the plurality of second bonding pads respectively.

[0016] According to an embodiment of the present invention, the plurality of first bonding pads and the plurality of second bonding pads include copper pads.

[0017] According to an embodiment of the present invention, the first insulating layer and the second insulating layer include silicon oxide, silicon nitride or silicon carbonitride.

[0018] According to an embodiment of the present invention, the first insulating layer is directly combined with the second insulating layer.

[0019] According to an embodiment of the present invention, the method further includes: forming a third redistribution layer on a side of the second semiconductor structure opposite to the second redistribution layer.

[0020] According to an embodiment of the present invention, the method further includes: forming a plurality of connectors on the third redistribution layer.

[0021] According to an embodiment of the present invention, the plurality of connecting members include solder bumps or solder balls.

[0022] According to an embodiment of the present invention, the plurality of second dies include a through silicon via (TSV) die, wherein the TSV die includes a plurality of through silicon vias for electrically connecting the second redistribution layer and the third redistribution layer.

[0023] According to an embodiment of the present invention, the method further includes: forming a plurality of conductive pillars in the second gap filling material, electrically connected to the second redistribution layer.

[0024] According to an embodiment of the present invention, the first gap filling material and the second gap filling material include dielectric material or molding compound.

[0025] In another aspect, the present invention provides a three-dimensional integrated circuit structure, comprising: a first semiconductor structure, comprising a plurality of first dies and a plurality of conductive pillars encapsulated by a first gap filling material, and a first redistribution layer electrically connected to the plurality of first dies and the plurality of conductive pillars, wherein the first redistribution layer comprises a plurality of first bonding pads, and a first insulating layer surrounding the plurality of first bonding pads; and a second semiconductor structure, comprising a plurality of second dies encapsulated by a second gap filling material, a second redistribution layer electrically connected to the plurality of second dies, and a third redistribution layer disposed on a side of the second semiconductor structure opposite to the second redistribution layer, wherein the plurality of second dies comprise through silicon via (TSV) dies. The second redistribution layer comprises a plurality of second bonding pads and a second insulating layer surrounding the plurality of second bonding pads, wherein the plurality of first bonding pads are directly bonded to the plurality of second bonding pads, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic cross-sectional view of a three-dimensional integrated circuit structure according to an embodiment of the present invention;

[0027] Figure 2 A schematic cross-sectional view of a three-dimensional integrated circuit structure according to another embodiment of the present invention;

[0028] Figure 3 A schematic cross-sectional view of a three-dimensional integrated circuit structure according to another embodiment of the present invention;

[0029] Figure 4 A schematic cross-sectional view of a three-dimensional integrated circuit structure according to another embodiment of the present invention;

[0030] Figure 5 A schematic cross-sectional view of a three-dimensional integrated circuit structure according to another embodiment of the present invention;

[0031] Figures 6 to 10 A schematic diagram of a method for manufacturing a three-dimensional integrated circuit structure according to an embodiment of the present invention;

[0032] Figures 11 to 15 A schematic diagram of a method for manufacturing a three-dimensional integrated circuit structure according to another embodiment of the present invention;

[0033] Figures 16 to 18A schematic diagram illustrating a method for forming a three-dimensional integrated circuit structure by hybrid bonding of module-to-reconstructed module wafers;

[0034] Figures 19 to 21 A schematic diagram illustrating a method for manufacturing a reconstruction module wafer;

[0035] Figure 22 to Figure 25 A schematic diagram illustrating a method for manufacturing a reconstruction module wafer;

[0036] Figure 26 to Figure 29 A schematic diagram illustrating another method for manufacturing a reconstruction module wafer.

[0037] Explanation of symbols

[0038] 1~8 three-dimensional integrated circuit structure

[0039] 10 Semiconductor structure

[0040] 101 Grain

[0041] 110 Gap filling material

[0042] 120 Rewiring Layer

[0043] 121 Bonding pad

[0044] 122 Insulation layer

[0045] 20 Semiconductor Structure

[0046] 201 Grain

[0047] 201a Through Silicon Via (TSV) Die

[0048] 201s active surface

[0049] 210 Gap Filling Material

[0050] 211 Through Silicon Via

[0051] 220 Rewiring Layer

[0052] 221 Bonding pad

[0053] 222 Insulation layer

[0054] 230 Rewiring Layer

[0055] 231 Solder ball pad

[0056] 232 Insulation layer

[0057] 233 Internal Link Structure

[0058] 30 Semiconductor Structure

[0059] 301 Grain

[0060] 301a TSV die

[0061] 302 Conductive Column

[0062] 310 Gap Filling Material

[0063] 320 Rewiring Layer

[0064] 321 Bonding pad

[0065] 322 Insulation layer

[0066] 330 Rewiring Layer

[0067] 331 Bonding pad

[0068] 332 Insulation layer

[0069] 40 Semiconductor Structure

[0070] 401 Grain

[0071] 402 Conductive Column

[0072] 401a TSV die

[0073] 410 Gap Filling Material

[0074] 420 Rewiring Layer

[0075] 421 Bonding Pad

[0076] 422 Insulation layer

[0077] 430 Rewiring Layer

[0078] 431 Bonding pad

[0079] 432 Insulation layer

[0080] BS Connectors

[0081] RW1 Reconstruction Module Chip

[0082] RW2 Reconstruction Module Chip

[0083] RW3 Reconstruction Module Chip

[0084] RW4 Reconstruction Module Chip

[0085] TP Temporary Carrier Plate DETAILED DESCRIPTION

[0086] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0087] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0088] The present invention provides a three-dimensional integrated circuit structure formed by stacking multiple semiconductor structures (reconstructed intermediate packages or reconstructed intermediate modules), wherein the multiple semiconductor structures are directly bonded to each other through bonding pads of a redistribution layer using direct bonding technology to form a multi-chip heterogeneous three-dimensional packaging configuration.

[0089] The present invention uses the same or different chips to form multiple semiconductor structures through the back-end packaging process, and then uses hybrid bonding technology to stack and interconnect multiple semiconductor structures. The bonding pad position can be redefined through the re-distribution layer, breaking through the previous limitations of chip bonding pad position, chip size and quantity. After stacking is completed, a bumping process is performed, and then a cutting process is performed to complete the final three-dimensional multi-chip heterogeneous packaging product.

[0090] See also Figure 1 , which is a schematic cross-sectional view of a three-dimensional integrated circuit structure according to an embodiment of the present invention. Figure 1 As shown, the three-dimensional integrated circuit structure 1 includes a semiconductor structure 10, including a plurality of dies 101 encapsulated by a gap filling material 110, and a redistribution layer 120 electrically connected to the plurality of dies 101, wherein the redistribution layer 120 includes a plurality of bonding pads 121 and an insulating layer 122 surrounding the plurality of bonding pads 121.

[0091] According to an embodiment of the present invention, the plurality of dies 101 may include the same function die and different function die. The above-mentioned function die include, but are not limited to, memory, sensor, processor, wireless communication circuit, micro-electromechanical system (MEMS), digital circuit, analog circuit, etc. According to an embodiment of the present invention, the plurality of dies 101 may include dummy die or bridging die.

[0092] According to an embodiment of the present invention, the three-dimensional integrated circuit structure 1 further includes a semiconductor structure 20, including a plurality of crystal grains 201 encapsulated by a gap filling material 210, and a redistribution layer 220 electrically connected to the plurality of crystal grains 201. The plurality of crystal grains 201 include at least one through silicon via (TSV) crystal grain 201a. The redistribution layer 220 includes a plurality of bonding pads 221 and an insulating layer 222 surrounding the plurality of bonding pads 221. The plurality of bonding pads 121 are directly bonded to the plurality of bonding pads 221 respectively by direct bonding technology. The direct bonding of the bonding pads may include Cu-to-Cu direct bonding.

[0093] According to an embodiment of the present invention, the plurality of dies 201 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 201 may include dummy dies or bridge dies.

[0094] According to the embodiment of the present invention, the semiconductor structure 10 and the semiconductor structure 20 are both re-constructed intermediate packages or re-constructed intermediate modules.

[0095] According to an embodiment of the present invention, the three-dimensional integrated circuit structure 1 further includes a redistribution layer 230, which is disposed on a side of the semiconductor structure 20 relative to the redistribution layer 220. According to an embodiment of the present invention, the three-dimensional integrated circuit structure 1 further includes a plurality of connectors BS, which are disposed on the redistribution layer 230. According to an embodiment of the present invention, the plurality of connectors BS may include solder bumps or solder balls. According to an embodiment of the present invention, the redistribution layer 230 includes a plurality of solder ball pads 231 and an insulating layer 232 surrounding the plurality of solder ball pads 231. According to an embodiment of the present invention, the redistribution layer 230 further includes an inner connection structure 233, which is connected to the active surfaces 201s of the plurality of grains 201.

[0096] According to an embodiment of the present invention, the plurality of bonding pads 121 and the plurality of bonding pads 221 may include copper pads, but are not limited thereto. According to an embodiment of the present invention, the insulating layer 122 and the insulating layer 222 may include silicon oxide, silicon nitride or silicon carbonitride (SiCN). According to an embodiment of the present invention, for example, the insulating layer 122 and the insulating layer 222 are silicon carbonitride layers. According to an embodiment of the present invention, the insulating layer 122 directly bonds to the insulating layer 222. According to an embodiment of the present invention, the insulating layer 122 directly contacts the insulating layer 222.

[0097] According to the embodiment of the present invention, the TSV die 201 a includes a plurality of through silicon vias 211 for electrically connecting the redistribution layer 220 with the redistribution layer 230 .

[0098] According to an embodiment of the present invention, the gap filling material 110 and the gap filling material 210 may include a dielectric material or a molding compound, but is not limited thereto.

[0099] See also Figure 2 , which is a schematic cross-sectional view of a three-dimensional integrated circuit structure according to another embodiment of the present invention, wherein the same regions, layers or components are still represented by the same symbols. Figure 2 As shown, the three-dimensional integrated circuit structure 2 includes a semiconductor structure 10, a semiconductor structure 20, and a semiconductor structure 30 located between the semiconductor structure 10 and the semiconductor structure 20. According to an embodiment of the present invention, the semiconductor structures 10, 20, and 30 are all reconstructed intermediate packages or reconstructed intermediate modules.

[0100] According to an embodiment of the present invention, the semiconductor structure 30 includes a plurality of dies 301 encapsulated by a gap filling material 310, and a redistribution layer 320 electrically connected to the plurality of dies 301. The plurality of dies 301 include at least one TSV die 301a. The redistribution layer 320 includes a plurality of bonding pads 321 and an insulating layer 322 surrounding the plurality of bonding pads 321. The plurality of bonding pads 121 of the semiconductor structure 10 are directly bonded to the plurality of bonding pads 321 of the semiconductor structure 30, respectively.

[0101] According to an embodiment of the present invention, the semiconductor structure 30 is further provided with a redistribution layer 330 relative to the redistribution layer 320. The redistribution layer 330 also includes a plurality of bonding pads 331 and an insulating layer 332 surrounding the plurality of bonding pads 331. The plurality of bonding pads 221 of the semiconductor structure 20 are directly bonded to the plurality of bonding pads 331 of the semiconductor structure 30 respectively by direct bonding technology.

[0102] According to an embodiment of the present invention, the plurality of die 301 may include the same functional die and different functional die. According to an embodiment of the present invention, the plurality of die 301 may include dummy die or bridge die.

[0103] See also Figure 3 , which is a schematic cross-sectional view of a three-dimensional integrated circuit structure according to another embodiment of the present invention, wherein the same regions, layers or components are still represented by the same symbols. Figure 3 As shown, the three-dimensional integrated circuit structure 3 also includes a semiconductor structure 10 and a semiconductor structure 20 stacked on each other. According to an embodiment of the present invention, the semiconductor structure 10 and the semiconductor structure 20 are both reconstructed intermediate packages or reconstructed intermediate modules.

[0104] According to an embodiment of the present invention, the semiconductor structure 10 includes a plurality of dies 101 encapsulated by a gap filling material 110 and a redistribution layer 120 electrically connected to the plurality of dies 101 , wherein the redistribution layer 120 includes a plurality of bonding pads 121 and an insulating layer 122 surrounding the plurality of bonding pads 121 .

[0105] According to an embodiment of the present invention, the plurality of dies 101 may include the same functional dies and different functional dies. The above functional dies include, but are not limited to, memory, sensor, processor, wireless communication circuit, micro-electromechanical system, digital circuit, analog circuit, etc. According to an embodiment of the present invention, the plurality of dies 101 may include dummy dies or bridge dies.

[0106] According to an embodiment of the present invention, the semiconductor structure 20 includes a plurality of dies 201 encapsulated by a gap filling material 210, and a redistribution layer 220 electrically connected to the plurality of dies 201. The redistribution layer 220 includes a plurality of bonding pads 221 and an insulating layer 222 surrounding the plurality of bonding pads 221. The plurality of bonding pads 121 are directly bonded to the plurality of bonding pads 221 respectively by direct bonding technology. The direct bonding of the bonding pads may include copper-to-copper direct bonding.

[0107] According to an embodiment of the present invention, the plurality of dies 201 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 201 may include dummy dies or bridge dies.

[0108] According to an embodiment of the present invention, the three-dimensional integrated circuit structure 3 further includes a redistribution layer 230, which is disposed on a side of the semiconductor structure 20 relative to the redistribution layer 220. According to an embodiment of the present invention, the three-dimensional integrated circuit structure 3 further includes a plurality of connectors BS, which are disposed on the redistribution layer 230. According to an embodiment of the present invention, the plurality of connectors BS may include solder bumps or solder balls. According to an embodiment of the present invention, the redistribution layer 230 includes a plurality of solder ball pads 231 and an insulating layer 232 surrounding the plurality of solder ball pads 231. According to an embodiment of the present invention, the redistribution layer 230 further includes an internal connection structure 233, which is connected to the active surfaces 201s of the plurality of grains 201.

[0109] According to an embodiment of the present invention, the plurality of bonding pads 121 and the plurality of bonding pads 221 may include copper pads, but are not limited thereto. According to an embodiment of the present invention, the insulating layer 122 and the insulating layer 222 may include silicon oxide, silicon nitride or silicon carbonitride. According to an embodiment of the present invention, for example, the insulating layer 122 and the insulating layer 222 are silicon carbonitride layers. According to an embodiment of the present invention, the insulating layer 122 directly bonds to the insulating layer 222. According to an embodiment of the present invention, the insulating layer 122 directly contacts the insulating layer 222.

[0110] According to an embodiment of the present invention, the three-dimensional integrated circuit structure 3 further includes a plurality of conductive pillars 202, such as copper pillars, embedded in the gap filling material 210 to electrically connect the redistribution layer 220 and the redistribution layer 230. According to an embodiment of the present invention, the gap filling material 110 and the gap filling material 210 may include a dielectric material or a molding compound, but is not limited thereto.

[0111] See also Figure 4 , which is a schematic cross-sectional view of a three-dimensional integrated circuit structure according to another embodiment of the present invention, wherein the same regions, layers or components are still represented by the same symbols. Figure 4 As shown, the three-dimensional integrated circuit structure 4 includes a semiconductor structure 10, a semiconductor structure 20, and a semiconductor structure 30 located between the semiconductor structure 10 and the semiconductor structure 20. According to an embodiment of the present invention, the semiconductor structures 10, 20, and 30 are all reconstructed intermediate packages or reconstructed intermediate modules.

[0112] According to an embodiment of the present invention, the semiconductor structure 30 includes a plurality of dies 301 molded by a gap filling material 310, and a redistribution layer 320 electrically connected to the plurality of dies 301. The redistribution layer 320 includes a plurality of bonding pads 321 and an insulating layer 322 surrounding the plurality of bonding pads 321. The plurality of bonding pads 121 of the semiconductor structure 10 are directly bonded to the plurality of bonding pads 321 of the semiconductor structure 30, respectively. According to an embodiment of the present invention, the gap filling material 310 may include a dielectric material or a molding compound, but is not limited thereto.

[0113] According to an embodiment of the present invention, the semiconductor structure 30 is further provided with a redistribution layer 330 relative to the redistribution layer 320. The redistribution layer 330 also includes a plurality of bonding pads 331 and an insulating layer 332 surrounding the plurality of bonding pads 331. The plurality of bonding pads 221 of the semiconductor structure 20 are directly bonded to the plurality of bonding pads 331 of the semiconductor structure 30 respectively by direct bonding technology.

[0114] According to an embodiment of the present invention, the plurality of die 301 may include the same functional die and different functional die. According to an embodiment of the present invention, the plurality of die 301 may include dummy die or bridge die.

[0115] According to an embodiment of the present invention, the three-dimensional integrated circuit structure 4 further includes a plurality of conductive pillars 202, such as copper pillars, embedded in the gap filling material 210 to electrically connect the redistribution layer 220 with the redistribution layer 230. According to an embodiment of the present invention, the three-dimensional integrated circuit structure 4 further includes a plurality of conductive pillars 302, such as copper pillars, embedded in the gap filling material 310 to electrically connect the redistribution layer 320 with the redistribution layer 330.

[0116] See also Figure 5, which is a schematic cross-sectional view of a three-dimensional integrated circuit structure according to another embodiment of the present invention, wherein the same regions, layers or components are still represented by the same symbols. Figure 5 As shown, the three-dimensional integrated circuit structure 5 includes a semiconductor structure 10, a semiconductor structure 20, and a semiconductor structure 30 located between the semiconductor structure 10 and the semiconductor structure 20. According to an embodiment of the present invention, the semiconductor structures 10, 20, and 30 are all reconstructed intermediate packages or reconstructed intermediate modules.

[0117] According to an embodiment of the present invention, the semiconductor structure 10 includes a plurality of dies 101 encapsulated by a gap filling material 110 and a redistribution layer 120 electrically connected to the plurality of dies 101 , wherein the redistribution layer 120 includes a plurality of bonding pads 121 and an insulating layer 122 surrounding the plurality of bonding pads 121 .

[0118] According to an embodiment of the present invention, the plurality of dies 101 may include the same functional dies and different functional dies. The above functional dies include, but are not limited to, memory, sensor, processor, wireless communication circuit, micro-electromechanical system, digital circuit, analog circuit, etc. According to an embodiment of the present invention, the plurality of dies 101 may include dummy dies or bridge dies.

[0119] According to an embodiment of the present invention, a semiconductor structure 20 includes a plurality of dies 201 encapsulated by a gap filling material 210, and a redistribution layer 220 electrically connected to the plurality of dies 201. The plurality of dies 201 include at least one TSV die 201a. The redistribution layer 220 includes a plurality of bonding pads 221 and an insulating layer 222 surrounding the plurality of bonding pads 221. The plurality of bonding pads 121 are directly bonded to the plurality of bonding pads 221 respectively by direct bonding technology. The direct bonding of the bonding pads may include copper-to-copper direct bonding.

[0120] According to an embodiment of the present invention, the plurality of dies 201 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 201 may include dummy dies or bridge dies.

[0121] According to an embodiment of the present invention, the three-dimensional integrated circuit structure 5 further includes a redistribution layer 230, which is disposed on a side of the semiconductor structure 20 relative to the redistribution layer 220. According to an embodiment of the present invention, the three-dimensional integrated circuit structure 5 further includes a plurality of connectors BS, which are disposed on the redistribution layer 230. According to an embodiment of the present invention, the plurality of connectors BS may include solder bumps or solder balls. According to an embodiment of the present invention, the redistribution layer 230 includes a plurality of solder ball pads 231 and an insulating layer 232 surrounding the plurality of solder ball pads 231. According to an embodiment of the present invention, the redistribution layer 230 further includes an internal connection structure 233, which is connected to the active surfaces 201s of the plurality of grains 201.

[0122] According to the embodiment of the present invention, the TSV die 201 a includes a plurality of through silicon vias 211 for electrically connecting the redistribution layer 220 with the redistribution layer 230 .

[0123] According to an embodiment of the present invention, the semiconductor structure 30 includes a plurality of dies 301 molded by a gap filling material 310, and a redistribution layer 320 electrically connected to the plurality of dies 301. The redistribution layer 320 includes a plurality of bonding pads 321 and an insulating layer 322 surrounding the plurality of bonding pads 321. The plurality of bonding pads 121 of the semiconductor structure 10 are directly bonded to the plurality of bonding pads 321 of the semiconductor structure 30, respectively. According to an embodiment of the present invention, the gap filling material 310 may include a dielectric material or a molding compound, but is not limited thereto.

[0124] According to an embodiment of the present invention, the semiconductor structure 30 is further provided with a redistribution layer 330 relative to the redistribution layer 320. The redistribution layer 330 also includes a plurality of bonding pads 331 and an insulating layer 332 surrounding the plurality of bonding pads 331. The plurality of bonding pads 221 of the semiconductor structure 20 are directly bonded to the plurality of bonding pads 331 of the semiconductor structure 30 respectively by direct bonding technology.

[0125] According to an embodiment of the present invention, the plurality of die 301 may include the same functional die and different functional die. According to an embodiment of the present invention, the plurality of die 301 may include dummy die or bridge die.

[0126] According to an embodiment of the present invention, the three-dimensional integrated circuit structure 5 further includes a plurality of conductive pillars 302 , such as copper pillars, embedded in the gap filling material 310 to electrically connect the redistribution layer 320 and the redistribution layer 330 .

[0127] See also Figures 6 to 10 , which is a schematic diagram of a method for manufacturing a three-dimensional integrated circuit structure according to an embodiment of the present invention, wherein the same regions, layers or components are still represented by the same symbols. Figures 6 to 10 A four-layer semiconductor structure stack is used as an example for illustration; however, those skilled in the art should understand that in other embodiments, the three-dimensional integrated circuit structure may be a two-layer, three-layer or more than four-layer semiconductor structure stack.

[0128] First, if Figure 6 As shown, a reconstruction module wafer RW1 and a reconstruction module wafer RW2 are provided, wherein the reconstruction module wafer RW1 and the reconstruction module wafer RW2 respectively include a plurality of Figure 2 The semiconductor structure 20 and the semiconductor structure 30 are bonded together by hybrid bonding technology.

[0129] According to an embodiment of the present invention, the semiconductor structure 20 includes a plurality of dies 201 encapsulated by a gap filling material 210, and a redistribution layer 220 electrically connected to the plurality of dies 201. The plurality of dies 201 include at least one TSV die 201a. The redistribution layer 220 includes a plurality of bonding pads 221 and an insulating layer 222 surrounding the plurality of bonding pads 221.

[0130] According to an embodiment of the present invention, the plurality of dies 201 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 201 may include dummy dies or bridge dies.

[0131] According to an embodiment of the present invention, the semiconductor structure 30 includes a plurality of crystal grains 301 encapsulated by a gap filling material 310, and a redistribution layer 320 electrically connected to the plurality of crystal grains 301. The plurality of crystal grains 301 include at least one TSV crystal grain 301a. The redistribution layer 320 includes a plurality of bonding pads 321 and an insulating layer 322 surrounding the plurality of bonding pads 321. According to an embodiment of the present invention, relative to the redistribution layer 320, the semiconductor structure 30 is further provided with a redistribution layer 330. The redistribution layer 330 includes a plurality of bonding pads 331 and an insulating layer 332 surrounding the plurality of bonding pads 331. The plurality of bonding pads 221 of the semiconductor structure 20 are directly bonded to the plurality of bonding pads 331 of the semiconductor structure 30, respectively.

[0132] According to an embodiment of the present invention, the plurality of die 301 may include the same functional die and different functional die. According to an embodiment of the present invention, the plurality of die 301 may include dummy die or bridge die.

[0133] For example, the manufacturing method of the reconstruction module wafer RW1 can be as follows: Figures 19 to 21 As shown in FIG. 1 , the same regions, layers or components are still represented by the same symbols. Fig.19 As shown, the rearranged die 201 is placed on the temporary carrier TP in a flip-chip manner, wherein the die 201 includes at least one TSV die 201a. The plurality of die 201 are then molded with a gap filling material 210. Fig. 20 As shown, a portion of the gap filling material 210 is removed by grinding to expose the back side of the die 201 and the through silicon via 211 of the TSV die 201a, and then the temporary carrier TP is removed. Fig.21 As shown, a redistribution layer (RDL) manufacturing process is then performed to form a redistribution layer 220 on the exposed back side of the die 201 and the through silicon via 211 of the TSV die 201 a .

[0134] like Figure 7As shown, a reconstructed module wafer RW3 is provided, wherein the reconstructed module wafer RW3 includes a plurality of semiconductor structures 40. The reconstructed module wafer RW3 and the reconstructed module wafer RW2 are bonded together using a hybrid bonding technology.

[0135] According to an embodiment of the present invention, the semiconductor structure 40 includes a plurality of crystal grains 401 encapsulated by a gap filling material 410, and a redistribution layer 420 electrically connected to the plurality of crystal grains 401. The plurality of crystal grains 401 include at least one TSV crystal grain 401a. The redistribution layer 420 includes a plurality of bonding pads 421 and an insulating layer 422 surrounding the plurality of bonding pads 421. According to an embodiment of the present invention, relative to the redistribution layer 420, the semiconductor structure 40 is further provided with a redistribution layer 430. The redistribution layer 430 includes a plurality of bonding pads 431 and an insulating layer 432 surrounding the plurality of bonding pads 431. The plurality of bonding pads 431 of the semiconductor structure 40 are directly bonded to the plurality of bonding pads 321 of the semiconductor structure 30, respectively.

[0136] According to an embodiment of the present invention, the plurality of dies 401 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 401 may include dummy dies or bridge dies.

[0137] like Figure 8 As shown, a reconstruction module chip RW4 is provided, wherein the reconstruction module chip RW4 includes a plurality of Figure 2 The semiconductor structure 10 in the embodiment of the present invention is formed by bonding the reconstructed module wafer RW4 and the reconstructed module wafer RW3 together by using a hybrid bonding technology.

[0138] According to an embodiment of the present invention, the semiconductor structure 10 includes a plurality of dies 101 encapsulated by a gap filling material 110, and a redistribution layer 120 electrically connected to the plurality of dies 101, wherein the redistribution layer 120 includes a plurality of bonding pads 121, and an insulating layer 122 surrounding the plurality of bonding pads 121. The plurality of bonding pads 421 of the semiconductor structure 40 are directly bonded to the plurality of bonding pads 121 of the semiconductor structure 10, respectively.

[0139] According to an embodiment of the present invention, the plurality of dies 101 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 101 may include dummy dies or bridge dies.

[0140] like Fig. 9 As shown, a redistribution layer 230 is then formed on a side of the semiconductor structure 20 opposite to the redistribution layer 220. The redistribution layer 230 includes a plurality of solder ball pads 231 and an insulating layer 232 surrounding the plurality of solder ball pads 231. A plurality of connectors BS are then formed on the redistribution layer 230. According to an embodiment of the present invention, the plurality of connectors BS may include solder bumps or solder balls.

[0141] like Fig.10 As shown, a wafer cutting process is then performed to form a plurality of independent three-dimensional integrated circuit structures 6 .

[0142] See also Figures 11 to 15 , which is a schematic diagram of a method for manufacturing a three-dimensional integrated circuit structure according to another embodiment of the present invention, wherein the same regions, layers or components are still represented by the same symbols. Figures 11 to 15 A four-layer semiconductor structure stack is used as an example for illustration; however, those skilled in the art should understand that in other embodiments, the three-dimensional integrated circuit structure may be a two-layer, three-layer or more than four-layer semiconductor structure stack.

[0143] First, if Fig.11 As shown, a reconstruction module wafer RW1 and a reconstruction module wafer RW2 are provided, wherein the reconstruction module wafer RW1 and the reconstruction module wafer RW2 respectively include a plurality of Figure 4 The semiconductor structure 20 and the semiconductor structure 30 are bonded together by hybrid bonding technology.

[0144] According to an embodiment of the present invention, the semiconductor structure 20 includes a plurality of dies 201 and conductive pillars 202 encapsulated by a gap filling material 210, and a redistribution layer 220 electrically connected to the plurality of dies 201 and the conductive pillars 202. The redistribution layer 220 includes a plurality of bonding pads 221 and an insulating layer 222 surrounding the plurality of bonding pads 221.

[0145] According to an embodiment of the present invention, the plurality of dies 201 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 201 may include dummy dies or bridge dies.

[0146] According to an embodiment of the present invention, the semiconductor structure 30 includes a plurality of crystal grains 301 and conductive pillars 302 encapsulated by a gap filling material 310, and a redistribution layer 320 electrically connected to the plurality of crystal grains 301 and the conductive pillars 302. The redistribution layer 320 includes a plurality of bonding pads 321 and an insulating layer 322 surrounding the plurality of bonding pads 321. According to an embodiment of the present invention, relative to the redistribution layer 320, the semiconductor structure 30 is further provided with a redistribution layer 330. The redistribution layer 330 includes a plurality of bonding pads 331 and an insulating layer 332 surrounding the plurality of bonding pads 331. The plurality of bonding pads 221 of the semiconductor structure 20 are directly bonded to the plurality of bonding pads 331 of the semiconductor structure 30, respectively.

[0147] According to the embodiment of the present invention, the conductive pillar 202 embedded in the gap filling material 210 is electrically connected to the redistribution layer 220 , and the conductive pillar 302 embedded in the gap filling material 310 is electrically connected to the redistribution layers 320 and 330 .

[0148] According to an embodiment of the present invention, the plurality of die 301 may include the same functional die and different functional die. According to an embodiment of the present invention, the plurality of die 301 may include dummy die or bridge die.

[0149] For example, the manufacturing method of the reconstruction module wafer RW2 can be as follows: Figure 22 to Figure 25 As shown in FIG. 1 , the same regions, layers or components are still represented by the same symbols. Fig. 22 As shown in FIG. 1 , the rearranged die 301 are placed on the temporary carrier TP in a flip-chip manner. The plurality of die 301 are then molded with a gap filling material 310. Fig.23 As shown, after removing the temporary carrier TP, hole etching and metallization processes are performed to form conductive pillars 302 in the gap filling material 310 around the grain 301. Fig.24 As shown, the RDL process is then performed to form a redistribution layer 330 on the exposed front surface of the die 301 and the conductive pillar 302. Fig.25 As shown, a portion of the gap filling material 310 is removed by grinding to expose the back side of the die 301 and the conductive pillar 302 , and then an RDL process is performed to form a redistribution layer 320 on the exposed back side of the die 301 and the conductive pillar 302 .

[0150] For example, another method for manufacturing the reconstruction module wafer RW2 may be as follows: Figure 26 to Figure 29 As shown in FIG. 1 , the same regions, layers or components are still represented by the same symbols. Fig.26 As shown in FIG. 1 , a redistribution layer 330 is formed on the temporary carrier TP, and then a conductive column 302 is disposed on the redistribution layer 330. Fig. 27 As shown, the rearranged die 301 is placed on the redistribution layer 330, and then the plurality of die 301 and the conductive pillars 302 are encapsulated with a gap filling material 310. Fig.28 As shown, a portion of the gap filling material 310 is removed by grinding to expose the back side of the die 301 and the conductive pillar 302. Fig.29 As shown, the RDL process is then performed to form a redistribution layer 320 on the back side of the exposed die 301 and the conductive pillar 302. Fig.12 As shown, a reconstructed module wafer RW3 is provided, wherein the reconstructed module wafer RW3 includes a plurality of semiconductor structures 40. The reconstructed module wafer RW3 and the reconstructed module wafer RW2 are bonded together using a hybrid bonding technology.

[0151] According to an embodiment of the present invention, the semiconductor structure 40 includes a plurality of crystal grains 401 and conductive pillars 402 encapsulated by a gap filling material 410, and a redistribution layer 420 electrically connected to the plurality of crystal grains 401 and the conductive pillars 402. The redistribution layer 420 includes a plurality of bonding pads 421 and an insulating layer 422 surrounding the plurality of bonding pads 421. According to an embodiment of the present invention, relative to the redistribution layer 420, the semiconductor structure 40 is further provided with a redistribution layer 430. The redistribution layer 430 includes a plurality of bonding pads 431 and an insulating layer 432 surrounding the plurality of bonding pads 431. The plurality of bonding pads 431 of the semiconductor structure 40 are directly bonded to the plurality of bonding pads 321 of the semiconductor structure 30, respectively. The conductive pillars 402 embedded in the gap filling material 410 are electrically connected to the redistribution layers 420 and 430.

[0152] According to an embodiment of the present invention, the plurality of dies 401 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 401 may include dummy dies or bridge dies.

[0153] like Fig.13 As shown, a reconstruction module chip RW4 is provided, wherein the reconstruction module chip RW4 includes a plurality of Figure 4 The semiconductor structure 10 in the embodiment of the present invention is formed by bonding the reconstructed module wafer RW4 and the reconstructed module wafer RW3 together by using a hybrid bonding technology.

[0154] According to an embodiment of the present invention, the semiconductor structure 10 includes a plurality of dies 101 encapsulated by a gap filling material 110, and a redistribution layer 120 electrically connected to the plurality of dies 101, wherein the redistribution layer 120 includes a plurality of bonding pads 121, and an insulating layer 122 surrounding the plurality of bonding pads 121. The plurality of bonding pads 421 of the semiconductor structure 40 are directly bonded to the plurality of bonding pads 121 of the semiconductor structure 10, respectively.

[0155] According to an embodiment of the present invention, the plurality of dies 101 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 101 may include dummy dies or bridge dies.

[0156] like Fig.14 As shown, a redistribution layer 230 is then formed on a side of the semiconductor structure 20 opposite to the redistribution layer 220. The redistribution layer 230 includes a plurality of solder ball pads 231 and an insulating layer 232 surrounding the plurality of solder ball pads 231. A plurality of connectors BS are then formed on the redistribution layer 230. According to an embodiment of the present invention, the plurality of connectors BS may include solder bumps or solder balls.

[0157] like Fig.15 As shown, a wafer cutting process is then performed to form a plurality of independent three-dimensional integrated circuit structures 7.

[0158] See also Figures 16 to 18 , which illustrates a method of forming a three-dimensional integrated circuit structure by hybrid bonding of module-to-reconstruction module wafers. Fig.16 As shown, a reconstruction module wafer RW1 and a plurality of semiconductor structures 10 are provided, wherein the reconstruction module wafer RW1 comprises a plurality of semiconductor structures 10. Figure 1 The semiconductor structure 20 in the reconstructed module wafer RW1 is then bonded together with the plurality of semiconductor structures 10 using a hybrid bonding technology.

[0159] According to an embodiment of the present invention, the semiconductor structure 10 includes a plurality of dies 101 encapsulated by a gap filling material 110 and a redistribution layer 120 electrically connected to the plurality of dies 101 , wherein the redistribution layer 120 includes a plurality of bonding pads 121 and an insulating layer 122 surrounding the plurality of bonding pads 121 .

[0160] According to an embodiment of the present invention, the plurality of dies 101 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 101 may include dummy dies or bridge dies.

[0161] According to an embodiment of the present invention, the semiconductor structure 20 includes a plurality of dies 201 encapsulated by a gap filling material 210, and a redistribution layer 220 electrically connected to the plurality of dies 201. The plurality of dies 201 include at least one TSV die 201a. The redistribution layer 220 includes a plurality of bonding pads 221 and an insulating layer 222 surrounding the plurality of bonding pads 221. The plurality of bonding pads 221 of the semiconductor structure 20 are directly bonded to the plurality of bonding pads 121 of the semiconductor structure 10, respectively.

[0162] According to an embodiment of the present invention, the plurality of dies 201 may include dies with the same function and dies with different functions. According to an embodiment of the present invention, the plurality of dies 201 may include dummy dies or bridge dies.

[0163] like Fig.17 As shown, a redistribution layer 230 is then formed on a side of the semiconductor structure 20 opposite to the redistribution layer 220. The redistribution layer 230 includes a plurality of solder ball pads 231 and an insulating layer 232 surrounding the plurality of solder ball pads 231. A plurality of connectors BS are then formed on the redistribution layer 230. According to an embodiment of the present invention, the plurality of connectors BS may include solder bumps or solder balls.

[0164] like Fig.18 As shown, a wafer cutting process is then performed to form a plurality of independent three-dimensional integrated circuit structures 8.

[0165] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A three-dimensional integrated circuit structure, comprising: The first semiconductor structure comprises a plurality of first dies molded by a first gap filling material, and a first redistribution layer electrically connected to the plurality of first dies. in, The first redistribution layer includes a plurality of first bonding pads and a first insulating layer surrounding the plurality of first bonding pads; as well as A second semiconductor structure comprises a plurality of second grains encapsulated by a second gap filling material, wherein the plurality of second grains comprise at least one through silicon via grain, and a second redistribution layer electrically connected to the plurality of second grains, wherein the second redistribution layer comprises a plurality of second bonding pads and a second insulating layer surrounding the plurality of second bonding pads, wherein the plurality of first bonding pads are directly bonded to the plurality of second bonding pads respectively.

2. The three-dimensional integrated circuit structure according to claim 1, in, The first bonding pads and the second bonding pads include copper pads.

3. The three-dimensional integrated circuit structure according to claim 1, in, The first insulating layer and the second insulating layer include silicon oxide, silicon nitride or silicon carbonitride.

4. The three-dimensional integrated circuit structure according to claim 1, in, The first insulating layer is directly bonded to the second insulating layer.

5. The three-dimensional integrated circuit structure according to claim 1, in, Also includes: The third redistribution layer is disposed on a side of the second semiconductor structure opposite to the second redistribution layer.

6. The three-dimensional integrated circuit structure according to claim 5, in, Also includes: A plurality of connecting elements are arranged on the third redistribution layer.

7. The three-dimensional integrated circuit structure according to claim 6, in, The plurality of connectors include solder bumps or solder balls.

8. The three-dimensional integrated circuit structure according to claim 5, in, The TSV crystal grain includes a plurality of through silicon vias for electrically connecting the second redistribution layer with the third redistribution layer.

9. The three-dimensional integrated circuit structure according to claim 5, in, Also includes: A plurality of conductive pillars are embedded in the first gap filling material and electrically connected to the second redistribution layer.

10. The three-dimensional integrated circuit structure according to claim 1, in, The first gap-filling material and the second gap-filling material include dielectric materials or molding compounds.

11. A method for manufacturing a three-dimensional integrated circuit structure, comprising: forming a first semiconductor structure including a plurality of first dies molded by a first gap filling material, and a first redistribution layer electrically connected to the plurality of first dies, in, The first redistribution layer includes a plurality of first bonding pads and a first insulating layer surrounding the plurality of first bonding pads; Forming a second semiconductor structure, comprising a plurality of second dies molded by a second gap filling material, and a second redistribution layer electrically connected to the plurality of second dies, wherein the second redistribution layer comprises a plurality of second bonding pads, and a second insulating layer surrounding the plurality of second bonding pads; and The first semiconductor structure and the second semiconductor structure are hybrid-bonded, wherein the plurality of first bonding pads are directly bonded to the plurality of second bonding pads respectively.

12. The method according to claim 11, in, The plurality of first bonding pads and the plurality of second bonding pads include copper pads.

13. The method according to claim 11, in, The first insulating layer and the second insulating layer include silicon oxide, silicon nitride or silicon carbonitride.

14. The method according to claim 11, in, The first insulating layer is directly bonded to the second insulating layer.

15. The method according to claim 11, in, Also includes: A third redistribution layer is formed on a side of the second semiconductor structure opposite to the second redistribution layer.

16. The method of claim 15, in, Also includes: A plurality of connections are formed on the third redistribution layer.

17. The method of claim 16, in, The plurality of connectors include solder bumps or solder balls.

18. The method of claim 15, in, The plurality of second dies include a through silicon via (TSV) die, wherein the TSV die includes a plurality of TSVs for electrically connecting the second redistribution layer and the third redistribution layer.

19. The method of claim 15, in, Also includes: A plurality of conductive pillars are formed in the first gap filling material and electrically connected to the second redistribution layer.

20. The method of claim 11, in, The first gap-filling material and the second gap-filling material include dielectric materials or molding compounds.

21. A three-dimensional integrated circuit structure, comprising: The first semiconductor structure includes a plurality of first dies and a plurality of conductive pillars encapsulated by a first gap filling material, and a first redistribution layer electrically connected to the plurality of first dies and the plurality of conductive pillars. in, The first redistribution layer includes a plurality of first bonding pads and a first insulating layer surrounding the plurality of first bonding pads; as well as A second semiconductor structure comprises a plurality of second dies molded by a second gap filling material, a second redistribution layer electrically connected to the plurality of second dies, and a third redistribution layer disposed on a side of the second semiconductor structure opposite to the second redistribution layer; The second redistribution layer includes a plurality of second bonding pads and a second insulating layer surrounding the plurality of second bonding pads, wherein the plurality of first bonding pads are directly bonded to the plurality of second bonding pads respectively.

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