Semiconductor device having doped source / drain regions

Abstract

A semiconductor device includes: a substrate; an active pattern extending in a first horizontal direction on the substrate; a plurality of nanosheets spaced apart from each other and stacked on the active pattern in a vertical direction; a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets; a source / drain region disposed on at least one side of the gate electrode on the active pattern, the source / drain region including a first layer doped with a metal and a second layer disposed on the first layer; and an internal spacer disposed between the gate electrode and the first layer, the internal spacer contacting the first layer and including a metal oxide of the metal formed by oxidizing the metal.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Specifically, the present disclosure relates to a semiconductor device including an MBCFET TM (Multi-bridge channel field effect transistor) semiconductor device. Background Art

[0002] As an example of a scaling technology for increasing the density of an integrated circuit device, a multi-gate transistor includes a silicon body having a fin or nanowire shape formed on a substrate and a gate formed on a surface of the silicon body.

[0003] Since this multi-gate transistor utilizes a three-dimensional channel, it is easy to scale. In addition, even without increasing the gate length of the multi-gate transistor, the current control capability can be improved. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed. Summary of the invention

[0004] Aspects of the present disclosure provide a semiconductor device having improved reliability of each of source / drain regions and internal spacers.

[0005] However, the aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0006] In general, the innovative aspects of the subject matter described in this specification can be embodied in a semiconductor device comprising: a substrate; an active pattern extending along a first horizontal direction on the substrate; a plurality of nanosheets spaced apart from each other and stacked along a vertical direction on the active pattern; a gate electrode extending along a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets; a source / drain region disposed on the active pattern on at least one side of the gate electrode, the source / drain region comprising a first layer doped with a metal and a second layer disposed on the first layer; and an internal spacer disposed between the gate electrode and the first layer, the internal spacer contacting the first layer and comprising a metal oxide of the metal formed by oxidizing the metal.

[0007] In general, in other aspects, the subject matter of the present disclosure can be embodied in a semiconductor device, which includes: a substrate; an active pattern, the active pattern extending along a first horizontal direction on the substrate; a plurality of nanosheets, the plurality of nanosheets being spaced apart from each other and stacked on the active pattern along a vertical direction; a gate electrode, the gate electrode extending along a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets; a source / drain region, the source / drain region being disposed on at least one side of the gate electrode on the active pattern, the source / drain region comprising a first layer doped with aluminum (Al) or nickel (Ni) and a second layer disposed on the first layer; a gate insulating layer, the gate insulating layer being disposed between adjacent nanosheets among the plurality of nanosheets, between the gate electrode and the first layer; and an internal spacer, the internal spacer being disposed between the gate electrode and the first layer, the internal spacer being disposed between adjacent nanosheets among the plurality of nanosheets, the internal spacer contacting each of the first layer and the gate insulating layer, and the internal spacer comprising any one of aluminum oxide or nickel oxide.

[0008] In general, in other aspects, the subject matter of the present disclosure can be embodied in a semiconductor device, which includes: a substrate; an active pattern, the active pattern extending along a first horizontal direction on the substrate; a plurality of nanosheets, the plurality of nanosheets being spaced apart from each other and stacked on the active pattern along a vertical direction; a gate electrode, the gate electrode extending along a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets; a source / drain region, the source / drain region being disposed on at least one side of the gate electrode on the active pattern, the source / drain region comprising a first layer doped with aluminum (Al) and a second layer disposed on the first layer; and an internal spacer, the internal spacer being disposed between the gate electrode and the first layer, the internal spacer contacting the first layer, the internal spacer comprising aluminum oxide, wherein the first layer does not contact each of the upper and lower surfaces of the plurality of nanosheets. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic layout diagram of an example of a semiconductor device.

[0010] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'.

[0011] Figure 3 yes Figure 2 Magnified view of region R1.

[0012] Figure 4 It is along Figure 1 A cross-sectional view taken along line BB'.

[0013] Figures 5 to 16 is a diagram of intermediate steps of an example of a method of manufacturing a semiconductor device.

[0014] Fig.17 is a cross-sectional view of an example of a semiconductor device.

[0015] Fig.18 yes Fig.17 Magnified view of region R2.

[0016] Fig.19 is a cross-sectional view of an example of a semiconductor device.

[0017] Fig. 20 yes Fig.19 An enlarged view of region R3.

[0018] Fig.21 is a cross-sectional view of an example of a semiconductor device.

[0019] Fig. 22 yes Fig.21 An enlarged view of region R4. DETAILED DESCRIPTION

[0020] Figure 1 is a schematic layout diagram of an example of a semiconductor device. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 yes Figure 2 Magnified view of region R1. Figure 4 It is along Figure 1 A cross-sectional view taken along line BB'.

[0021] Reference Figures 1 to 4 , according to some embodiments of the present disclosure, the semiconductor device includes: a substrate 100, an active pattern 101, a field insulation layer 105, a plurality of nanosheets NW1, NW2, NW3 and NW4, a gate electrode G, a gate spacer 111, a gate insulation layer 112, a capping pattern 113, a source / drain region 120, an internal spacer 130, a first interlayer insulation layer 140, a source / drain contact CA, a silicide layer SL, a gate contact CB, an etch stop layer 150, a second interlayer insulation layer 160, and a first via V1 and a second via V2. In the embodiments shown herein, the phrase source / drain region may be understood to mean a source terminal region and / or a drain terminal region of a transistor. The source / drain contact may be understood to mean a contact for the source terminal region and / or the drain terminal region of a transistor. Source / drain trench (see Fig. 9 ) can be understood to represent a trench associated with a source terminal region and / or a drain terminal region of a transistor.

[0022] The substrate 100 may be a silicon substrate or a silicon on insulator (SOI). In contrast, although the substrate 100 may include silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, the present disclosure is not limited thereto.

[0023] Hereinafter, each of the first horizontal direction DR1 and the second horizontal direction DR2 is defined as a direction parallel to the upper surface of the substrate 100. The second horizontal direction DR2 is defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 is defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 is defined as a direction perpendicular to the upper surface of the substrate 100.

[0024] The active pattern 101 may extend in a first horizontal direction DR1 on the substrate 100. The active pattern 101 may protrude from an upper surface of the substrate 100 in a vertical direction DR3. For example, the active pattern 101 may be a portion of the substrate 100 and may include an epitaxial layer grown from the substrate 100.

[0025] The field insulation layer 105 may be disposed on the upper surface of the substrate 100. The field insulation layer 105 may surround the sidewalls of the active pattern 101. For example, the upper surface of the active pattern 101 may protrude beyond the upper surface of the field insulation layer 105 in the vertical direction DR3. However, the present disclosure is not limited thereto. In some embodiments, the upper surface of the active pattern 101 is formed on the same plane as the upper surface of the field insulation layer 105. The field insulation layer 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof.

[0026] A plurality of nanosheets NW1, NW2, NW3, and NW4 may be disposed on the active pattern 101. The plurality of nanosheets NW1, NW2, NW3, and NW4 may be stacked on the active pattern 101 while being spaced apart from each other in the vertical direction DR3. For example, the plurality of nanosheets NW1, NW2, NW3, and NW4 may include a first nanosheet NW1, a second nanosheet NW2, a third nanosheet NW3, and a fourth nanosheet NW4. The first nanosheet NW1 may be spaced apart from the active pattern 101 along the vertical direction DR3 on the active pattern 101. The second nanosheet NW2 may be spaced apart from the first nanosheet NW1 along the vertical direction DR3 on the first nanosheet NW1. The third nanosheet NW3 may be spaced apart from the second nanosheet NW2 along the vertical direction DR3 on the second nanosheet NW2. The fourth nanosheet NW4 may be spaced apart from the third nanosheet NW3 along the vertical direction DR3 on the third nanosheet NW3.

[0027] Although Figure 2 and Figure 4 It is shown that a plurality of nanosheets NW1, NW2, NW3 and NW4 include four nanosheets spaced apart from each other and stacked in a vertical direction DR3, which is only for convenience of explanation, and the present disclosure is not limited thereto. In some embodiments, a plurality of nanosheets include three nanosheets spaced apart from each other and stacked in a vertical direction DR3. In addition, in some embodiments, a plurality of nanosheets include five or more nanosheets spaced apart from each other and stacked in a vertical direction DR3. For example, each of the first to fourth nanosheets NW1, NW2, NW3 and NW4 may include silicon (Si). However, the present disclosure is not limited thereto. In some embodiments, each of the first to fourth nanosheets NW1, NW2, NW3 and NW4 includes silicon germanium (SiGe).

[0028] The gate electrode G may extend along the second horizontal direction DR2 on the active pattern 101 and the field insulating layer 105. The gate electrode G may surround each of the first to fourth nanosheets NW1, NW2, NW3, and NW4. The gate electrode G may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten The gate electrode G may include at least one of a conductive metal oxide, a conductive metal oxynitride, and the like, and may include an oxidized form of the foregoing materials.

[0029] The gate spacer 111 may extend in the second horizontal direction DR2 along both side walls of the gate electrode G located on the upper surface of the field insulating layer 105 and the uppermost nanosheet among the plurality of nanosheets NW1, NW2, NW3, and NW4. For example, the gate spacer 111 may extend in the second horizontal direction DR2 along both side walls of the gate electrode G located on the upper surface of the field insulating layer 105 and the fourth nanosheet NW4. The gate spacer 111 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. However, the present disclosure is not limited thereto.

[0030] The source / drain region 120 may be disposed on at least one side of the gate electrode G on the active pattern 101. For example, the source / drain region 120 may be disposed on both sides of the gate electrode G on the active pattern 101. The source / drain region 120 may contact both sidewalls of each of the plurality of nanosheets NW1, NW2, NW3, and NW4 in the first horizontal direction DR1. For example, the upper surface of the source / drain region 120 may be formed to be higher than the upper surface of the fourth nanosheet NW4. The source / drain region 120 may include a first layer 121 and a second layer 122 disposed on the first layer 121.

[0031] In a cross section taken along the first horizontal direction DR1, the first layer 121 may be disposed along the sidewalls and the bottom surface of the source / drain region 120. The first layer 121 may contact the upper surface of the active pattern 101 and both sidewalls of each of the plurality of nanosheets NW1, NW2, NW3, and NW4 in the first horizontal direction DR1. The first layer 121 may contact the inner spacer 130 to be described later. For example, the first layer 121 may contact the gate spacer 111. For example, the first layer 121 does not contact the upper and lower surfaces of each of the plurality of nanosheets NW1, NW2, NW3, and NW4.

[0032] The first layer 121 may include, for example, silicon germanium (SiGe). For example, the first layer 121 may include a doped metal. For example, the metal doped in the first layer 121 may be aluminum (Al) or nickel (Ni). For example, when the substrate 100 is a PMOS region, the metal doped in the first layer 121 may be aluminum (Al). For example, if the substrate 100 is an NMOS region, the metal doped in the first layer 121 may be nickel (Ni).

[0033] In a cross section taken along the first horizontal direction DR1, the second layer 122 may be disposed on the first layer 121. For example, the second layer 122 may be in contact with the first layer 121. For example, the second layer 122 may be in contact with the gate spacer 111. For example, an upper surface of the second layer 122 may be formed to be higher than an upper surface of the fourth nanosheet NW4.

[0034] The second layer 122 may include, for example, silicon germanium (SiGe). For example, the concentration of germanium (Ge) contained in the second layer 122 may be greater than the concentration of germanium (Ge) contained in the first layer 121. For example, when the substrate 100 is a PMOS region, the second layer 122 may include doped P-type impurities. For example, the P-type impurities may be boron (B) or carbon (C), but the present disclosure is not limited thereto. For example, when the substrate 100 is an NMOS region, the second layer 122 may include doped N-type impurities. For example, the N-type impurities may include one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi), but the present disclosure is not limited thereto.

[0035] Between adjacent nanosheets among the plurality of nanosheets NW1, NW2, NW3, and NW4, the inner spacer 130 may be disposed between the gate electrode G and the first layer 121. In addition, between the active pattern 101 and the first nanosheet NW1, the inner spacer 130 may be disposed between the gate electrode G and the first layer 121. The inner spacer 130 may contact the first layer 121. For example, the inner spacer 130 may include first to fourth portions 131, 132, 133, and 134.

[0036] For example, between the active pattern 101 and the first nanosheet NW1, the first portion 131 of the internal spacer 130 may be disposed between the gate electrode G and the first layer 121. Between the first nanosheet NW1 and the second nanosheet NW2, the second portion 132 of the internal spacer 130 may be disposed between the gate electrode G and the first layer 121. Between the second nanosheet NW2 and the third nanosheet NW3, the third portion 133 of the internal spacer 130 may be disposed between the gate electrode G and the first layer 121. Between the third nanosheet NW3 and the fourth nanosheet NW4, the fourth portion 134 of the internal spacer 130 may be disposed between the gate electrode G and the first layer 121.

[0037] For example, the internal spacer 130 may be in contact with the active pattern 101 and each of the plurality of nanosheets NW1, NW2, NW3, and NW4. For example, between the active pattern 101 and the first nanosheet NW1, the internal spacer 130 may be in contact with each of the upper surface of the active pattern 101 and the lower surface of the first nanosheet NW1. Between the first nanosheet NW1 and the second nanosheet NW2, the internal spacer 130 may be in contact with each of the upper surface of the first nanosheet NW1 and the lower surface of the second nanosheet NW2. Between the second nanosheet NW2 and the third nanosheet NW3, the internal spacer 130 may be in contact with each of the upper surface of the second nanosheet NW2 and the lower surface of the third nanosheet NW3. Between the third nanosheet NW3 and the fourth nanosheet NW4, the internal spacer 130 may be in contact with each of the upper surface of the third nanosheet NW3 and the lower surface of the fourth nanosheet NW4.

[0038] For example, the sidewall 130s of the inner spacer 130 in contact with the first layer 121 may be formed to be recessed toward the gate electrode G in the first horizontal direction DR1 beyond the sidewall NWs of each of the plurality of nanosheets NW1, NW2, NW3, and NW4. For example, the inner spacer 130 may include a metal oxide formed by oxidizing the metal doped in the first layer 121. For example, the metal oxide included in the inner spacer 130 may be aluminum oxide or nickel oxide. For example, when the metal doped in the first layer 121 is aluminum (Al), the inner spacer 130 may include aluminum oxide. For example, when the metal doped in the first layer 121 is nickel (Ni), the inner spacer 130 may include nickel oxide.

[0039] The gate insulating layer 112 may be disposed between the gate electrode G and the gate spacer 111. The gate insulating layer 112 may be disposed between the gate electrode G and the active pattern 101. The gate insulating layer 112 may be disposed between adjacent nanosheets among the plurality of nanosheets NW1, NW2, NW3, and NW4. The gate insulating layer 112 may be disposed between each of the plurality of nanosheets NW1, NW2, NW3, and NW4 and the gate electrode G. The gate insulating layer 112 may be disposed between the gate electrode G and the first layer 121. The gate insulating layer 112 may be disposed between the gate electrode G and the inner spacer 130. The gate insulating layer 112 may be in contact with the inner spacer 130.

[0040] The gate insulating layer 112 may include at least one of silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, titanium strontium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0041] The semiconductor device according to some embodiments may include an NC (Negative Capacitance) FET using a negative capacitor. For example, the gate insulating layer 112 may include a ferroelectric material film having ferroelectric characteristics and a paraelectric material film having paraelectric characteristics.

[0042] The ferroelectric material film may have a negative capacitance and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is reduced compared to the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may be greater than the absolute value of each individual capacitance while having a positive value.

[0043] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series can be increased. By using the increased total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) of less than 60mV / decade at room temperature.

[0044] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0045] The ferroelectric material film may also include, for example, doped dopants. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0046] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0047] When the dopant is aluminum (Al), the ferroelectric material film may include 3 at % to 8 at % (atomic %) of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0048] When the dopant is silicon (Si), the ferroelectric material film may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50at% to 80at% zirconium.

[0049] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example but not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0050] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film has ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0051] The ferroelectric material film may have a threshold thickness for exhibiting ferroelectric properties, for example, behaving like a bulk version of a crystal. The thickness of the ferroelectric material film may be, for example, but not limited to, 0.5 nm to 10 nm. Since the critical thickness for exhibiting ferroelectric properties may be different for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0052] As an example, each gate insulating layer 112 may include a layer of ferroelectric material film. As another example, the gate insulating layer 112 may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating layer 112 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0053] The capping pattern 113 may extend along the second horizontal direction DR2 on each of the gate spacer 111, the gate insulating layer 112, and the gate electrode G. For example, the capping pattern 113 may contact the upper surface of the gate spacer 111. However, the present disclosure is not limited thereto. In some embodiments, the capping pattern 113 is disposed between the gate spacers 111. The capping pattern 113 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and at least one of a combination thereof. However, the present disclosure is not limited thereto.

[0054] The first interlayer insulating layer 140 may be disposed on the field insulating layer 105. The first interlayer insulating layer 140 may cover the source / drain region 120. The first interlayer insulating layer 140 may surround the sidewalls of each of the gate spacer 111 and the capping pattern 113. For example, the upper surface of the first interlayer insulating layer 140 may be formed on the same plane as the upper surface of the capping pattern 113. However, the present disclosure is not limited thereto. In some embodiments, the first interlayer insulating layer 140 covers the upper surface of the capping pattern 113.

[0055] The first interlayer insulating layer 140 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. Although the low dielectric constant material may include, for example, fluorinated tetraethylorthosilicate (FTEOS), hydrosilicate (HSQ), bisbenzocyclobutene (BCB), tetramethylsilicate (TMOS), octamethyltetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylborosilicate (TMSB), diacetoxyditertiarybutosiloxane (DADBS), trimethylsililphosphate (TMSP), polytetrafluoroethylene (PTFE), Tonen SilaZen (TOSZ), FSG (fluorosilicate glass), polyimide nanofoam (such as polypropylene oxide), CDO (carbon-doped silicon oxide), OSG (organosilicate) glass, SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, the present disclosure is not limited thereto.

[0056] The source / drain contact CA penetrates the first interlayer insulating layer 140 in the vertical direction DR3 and is connected to the source / drain region 120. For example, the source / drain contact CA penetrates the first interlayer insulating layer 140 in the vertical direction DR3 and may be connected to the second layer 122. For example, an upper surface of the source / drain contact CA may be formed on the same plane as an upper surface of the first interlayer insulating layer 140. Figure 2 , although the source / drain contact CA is shown as being formed of a single-layer film, the present disclosure is not limited thereto. In some embodiments, the source / drain contact CA is formed of a plurality of films.

[0057] The source / drain contacts CA may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), aluminum (Al), copper (Cu), and molybdenum (Mo).

[0058] The silicide layer SL may be disposed between the source / drain contacts CA and the source / drain region 120. For example, the silicide layer SL may be disposed between the source / drain contacts CA and the second layer 122. The silicide layer SL may include, for example, a metal silicide material.

[0059] The gate contact CB penetrates the capping pattern 113 in the vertical direction DR3 and may be connected to the gate electrode G. For example, an upper surface of the gate contact CB may be formed on the same plane as an upper surface of the first interlayer insulating layer 140. Figure 4 In the embodiment, although the gate contact CB is shown as being formed of a single layer, the present disclosure is not limited thereto. In some embodiments, the gate contact CB is formed of a multi-layer film.

[0060] The gate contact CB may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), aluminum (Al), copper (Cu), and molybdenum (Mo).

[0061] The etch stop layer 150 may be disposed on an upper surface of each of the first interlayer insulating layer 140, the capping pattern 113, the source / drain contacts CA, and the gate contact CB. Figure 2 and Figure 4 The etch stop layer 150 is shown to be formed of a single layer film, but the present disclosure is not limited thereto. In some embodiments, the etch stop layer 150 is formed of a multilayer film. The etch stop layer 150 may include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The second interlayer insulating layer 160 may be disposed on the etch stop layer 150. The second interlayer insulating layer 160 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material.

[0062] The first via V1 penetrates the second interlayer insulating layer 160 and the etch stop layer 150 in the vertical direction DR3 and may be connected to the source / drain contact CA. The second via V2 penetrates the second interlayer insulating layer 160 and the etch stop layer 150 in the vertical direction DR3 and may be connected to the gate contact CB. Figure 2 and Figure 4 It is shown that each of the first via V1 and the second via V2 is formed of a single-layer film, but the present disclosure is not limited thereto. In some embodiments, each of the first via V1 and the second via V2 is formed of a multi-layer film. Each of the first via V1 and the second via V2 may include a conductive material.

[0063] The following will refer to Figures 2 to 16 A method of manufacturing a semiconductor device according to some embodiments of the present disclosure is described.

[0064] Figures 5 to 16It is a diagram for explaining an intermediate step of a method for manufacturing a semiconductor device.

[0065] Reference Figure 5 and Figure 6 , a stacked structure 10 may be formed on a substrate 100. The stacked structure 10 may include a sacrificial layer 11 and a semiconductor layer 12 alternately stacked on the substrate 100. For example, the sacrificial layer 11 may be formed at the lowermost portion of the stacked structure 10, and the semiconductor layer 12 may be formed at the uppermost portion of the stacked structure 10. However, the present disclosure is not limited thereto. In some embodiments, the sacrificial layer 11 is formed at the uppermost portion of the stacked structure 10. The sacrificial layer 11 may include, for example, silicon germanium (SiGe). The semiconductor layer 12 may include, for example, silicon (Si).

[0066] A portion of the stacked structure 10 may then be etched. While etching the stacked structure 10, a portion of the substrate 100 may also be etched. Through such an etching process, an active pattern 101 may be defined below the stacked structure 10 on the upper surface of the substrate 100. The active pattern 101 may extend in the first horizontal direction DR1. A field insulating layer 105 may then be formed on the upper surface of the substrate 100. The field insulating layer 105 may surround the sidewalls of the active pattern 101. For example, the upper surface of the active pattern 101 may be formed to be higher than the upper surface of the field insulating layer 105.

[0067] Subsequently, a pad oxide layer 20 may be formed to cover the upper surface of the field insulating layer 105, the exposed sidewalls of the active pattern 101, and the sidewalls and upper surface of the stacked structure 10. For example, the pad oxide layer 20 may be conformally formed. The pad oxide layer 20 may include, for example, silicon oxide (SiO 2 ).

[0068] Reference Figure 7 and Figure 8 , a dummy gate DG and a dummy capping pattern DC extending along the second horizontal direction DR2 on the pad oxide layer 20 may be formed on the stacked structure 10 and the field insulating layer 105. The dummy capping pattern DC may be disposed on the dummy gate DG. While forming the dummy gate DG and the dummy capping pattern DC, the remaining pad oxide layer 20 on the substrate 100 except for a portion overlapping the dummy gate DG in the vertical direction DR3 may be removed.

[0069] Next, a spacer material layer SM may be formed to cover the sidewalls of each dummy gate DG, the sidewalls and upper surfaces of each dummy capping pattern DC, the sidewalls and upper surfaces of the exposed stacked structure 10, and the upper surface of the field insulating layer 105. For example, the spacer material layer SM may be conformally formed. The spacer material layer SM may include, for example, at least one of silicon nitride (SiN), silicon oxycarbonitride (SiOCN), boron-containing silicon carbonitride (SiBCN), silicon carbonitride (SiCN), silicon oxynitride (SiON), and combinations thereof.

[0070] Reference Fig. 9 , the stacked structure 10 may be etched using the dummy capping pattern DC and the dummy gate DG as masks (see Figure 7 ), thereby forming the source / drain trench ST. For example, the source / drain trench ST may extend to the inside of the active pattern 101. During the formation of the source / drain trench ST, each spacer material layer SM (see Figure 7 ) and the dummy capping pattern DC may be partially etched. In addition, both sidewalls of the sacrificial layer 11 in the first horizontal direction DR1 may be partially etched during the formation of the source / drain trench ST. Therefore, both sidewalls of the sacrificial layer 11 in the first horizontal direction DR1 may be formed to be recessed toward the center.

[0071] Reference Fig. 9 , the spacer material layer SM remaining on the sidewall of each of the dummy capping pattern DC and the dummy gate DG may be defined as a gate spacer 111. For example, after forming the source / drain trenches ST, each semiconductor layer 12 remaining under the dummy gate DG on the active pattern 101 may be defined as first to fourth nanosheets NW1, NW2, NW3, and NW4.

[0072] Reference Fig.10 , can be along the source / drain trench ST (see Fig. 9 ) is formed on the sidewall and bottom surface of the active pattern 101. For example, the first layer 121 may be epitaxially grown from the active pattern 101, the sacrificial layer 11, and each of the first to fourth nanosheets NW1, NW2, NW3, and NW4. The first layer 121 may be in contact with the active pattern 101, the sacrificial layer 11, and each of the first to fourth nanosheets NW1, NW2, NW3, and NW4.

[0073] For example, at least a portion of the first layer 121 may be formed between the active pattern 101 and the first nanosheet NW1. In addition, at least a portion of the first layer 121 may be formed between adjacent nanosheets among the first to fourth nanosheets NW1, NW2, NW3, and NW4. For example, the first layer 121 may include silicon germanium (SiGe). For example, the first layer 121 may include a doped metal. For example, the metal doped in the first layer 121 may be aluminum (Al) or nickel (Ni). Next, a second layer 122 may be formed on the first layer 121 to fill the source / drain trench ST (see Fig. 9 )’s interior.

[0074] Reference Fig.11 and Fig.12 The first interlayer insulating layer 140 may be formed to cover the first layer 121, the second layer 122, the gate spacer 111, and the dummy capping pattern DC (see Fig.10 ). The upper surface of the dummy gate DG may then be exposed by a planarization process. Subsequently, the dummy gate DG, the pad oxide layer 20, and the sacrificial layer 11 may be etched (see Fig.10 ) in each. The dummy gate DG (see Fig.10 ) portion can be defined as a gate trench GT.

[0075] Reference Fig.13 and Fig.14 The gate insulating layer 112 may be formed on the dummy gate DG (see Fig.10 ), pad oxide layer 20 (see Fig.10 ) and the sacrificial layer 11 (see Fig.10 ) is etched. For example, a gate insulating layer 112 may be formed along the sidewall and bottom surface of the gate trench GT. The gate insulating layer 112 may also be formed on the upper surface of the first interlayer insulating layer 140. For example, the gate insulating layer 112 may be conformally formed.

[0076] For example, during the formation of the gate insulating layer 112, a portion of the first layer 121 in contact with the gate insulating layer 112 may be oxidized to form the inner spacer 130. That is, a portion of the first layer 121 may be transformed into the inner spacer 130. After the inner spacer 130 is formed, the remaining first layer 121 and the second layer 122 may be defined as the source / drain region 120.

[0077] For example, the inner spacer 130 may include a metal oxide formed by oxidizing the metal doped in the first layer 121. For example, the metal oxide included in the inner spacer 130 may be aluminum oxide or nickel oxide. For example, when the metal doped in the first layer 121 is aluminum (Al), the inner spacer 130 may include aluminum oxide. For example, when the metal doped in the first layer 121 is nickel (Ni), the inner spacer 130 may include nickel oxide. For example, the inner spacer 130 may be defined as a portion that does not include silicon germanium (SiGe) but includes aluminum oxide or nickel oxide.

[0078] Reference Fig.15 and Fig.16 , the gate electrode G may be formed on the gate insulating layer 112. Subsequently, the upper surface of the first interlayer insulating layer 140 may be exposed by a planarization process. Subsequently, an upper portion of each of the gate spacer 111, the gate insulating layer 112, and the gate electrode G may be partially etched. A capping pattern 113 may be formed on the etched portion of each of the gate spacer 111, the gate insulating layer 112, and the gate electrode G.

[0079] Reference Figures 2 to 4 , a source / drain contact CA penetrating the first interlayer insulating layer 140 in the vertical direction DR3 and connected to the source / drain region 120 may be formed. In addition, a gate contact CB penetrating the capping pattern 113 in the vertical direction DR3 and connected to the gate electrode G may be formed. Subsequently, an etch stop layer 150 and a second interlayer insulating layer 160 may be sequentially formed on the first interlayer insulating layer 140, the capping pattern 113, the source / drain contact CA, and the gate contact CB.

[0080] Subsequently, a first via V1 penetrating the etch stop layer 150 and the second interlayer insulating layer 160 in the vertical direction DR3 and connected to the source / drain contact CA may be formed. In addition, a second via V2 penetrating the etch stop layer 150 and the second interlayer insulating layer 160 in the vertical direction DR3 and connected to the gate contact CB may be formed. Figures 2 to 4 The semiconductor device shown can be manufactured by such a manufacturing process.

[0081] When the inner spacer 130 is formed on the sidewall of the sacrificial layer 11 before forming the source / drain region 120, the reliability of the source / drain region 120 is affected because the source / drain region 120 is not epitaxially grown from the sacrificial layer 11. However, when the inner spacer 130 is formed on the sidewall of the source / drain region 120 after removing the dummy gate DG, the reliability of the source / drain region 120 can be improved. That is, in some semiconductor devices according to the present disclosure, the inner spacer 130 can be formed on the sidewall of the source / drain region 120 after forming the source / drain region 120.

[0082] In some embodiments, the first layer 121 of the source / drain region 120 adjacent to the plurality of nanosheets NW1, NW2, NW3, and NW4 includes any one of doped aluminum (Al) or nickel (Ni), wherein the doped Al or Ni is oxidized in a process of forming the gate insulating layer 112 to form an internal spacer 130 including aluminum oxide or nickel oxide. Therefore, in some embodiments, the semiconductor device can improve the reliability of each of the source / drain region 120 and the internal spacer 130.

[0083] In some embodiments, the semiconductor device manufactured by this manufacturing method includes the first layer 121 of the source / drain region 120 including one of doped aluminum (Al) and nickel (Ni), and the inner spacer 130 may include one of aluminum oxide and nickel oxide.

[0084] In the following, reference will be made to Fig.17 and Fig.18 Examples of semiconductor devices are described. The description will focus on Figures 1 to 4 The differences in semiconductor devices are shown.

[0085] Fig.17 It is a cross-sectional view for explaining a semiconductor device. Fig.18 yes Fig.17 Magnified view of region R2.

[0086] Reference Fig.17 and Fig.18 In some embodiments, at least a portion of the first layer 221 of the source / drain region 220 is in contact with a lower surface of each of the plurality of nanosheets NW1 , NW2 , NW3 , and NW4 .

[0087] For example, between the active pattern 101 and the first nanosheet NW1, at least a portion of the source / drain region 220 may be in contact with each of the uppermost surface of the active pattern 101 and the lower surface of the first nanosheet NW1. Between the first nanosheet NW1 and the second nanosheet NW2, at least a portion of the source / drain region 220 may be in contact with each of the upper surface of the first nanosheet NW1 and the lower surface of the second nanosheet NW2. Between the second nanosheet NW2 and the third nanosheet NW3, at least a portion of the source / drain region 220 may be in contact with each of the upper surface of the second nanosheet NW2 and the lower surface of the third nanosheet NW3. Between the third nanosheet NW3 and the fourth nanosheet NW4, at least a portion of the source / drain region 220 may be in contact with each of the upper surface of the third nanosheet NW3 and the lower surface of the fourth nanosheet NW4.

[0088] For example, the inner spacer 230 may include first to fourth portions 231, 232, 233, and 234. For example, a sidewall 230s of each of the first to fourth portions 231, 232, 233, and 234 of the inner spacer 230 contacting the first layer 221 may be formed to be recessed toward the gate electrode G in the first horizontal direction DR1 beyond a sidewall NWs of each of the plurality of nanosheets NW1, NW2, NW3, and NW4.

[0089] In the following, reference will be made to Fig.19 and Fig. 20 Examples of semiconductor devices are described. The description will focus on Figures 1 to 4 The differences in semiconductor devices are shown.

[0090] Fig.19 It is a cross-sectional view for explaining a semiconductor device. Fig. 20 yes Fig.19 An enlarged view of region R3.

[0091] Reference Fig.19 and Fig. 20 In some embodiments, a sidewall 330s of the inner spacer 330 contacting the first layer 321 of the source / drain region 320 is formed to protrude toward the first layer 321 in the first horizontal direction DR1 beyond a sidewall NWs of each of the plurality of nanosheets NW1, NW2, NW3, and NW4.

[0092] For example, the inner spacer 330 may include first to fourth portions 331, 332, 333, and 334. For example, a sidewall 330s of each of the first to fourth portions 331, 332, 333, and 334 of the inner spacer 330 contacting the first layer 321 of the source / drain region 320 may be formed to protrude toward the first layer 321 in the first horizontal direction DR1 beyond a sidewall NWs of each of the plurality of nanosheets NW1, NW2, NW3, and NW4.

[0093] In the following, reference will be made to Fig.21 and Fig. 22 Examples of semiconductor devices are described. The description will focus on Figures 1 to 4 The differences in semiconductor devices are shown.

[0094] Fig.21 It is a cross-sectional view for explaining a semiconductor device. Fig. 22 yes Fig.21 An enlarged view of region R4.

[0095] Reference Fig.21 and Fig. 22In the semiconductor device according to still other embodiments of the present disclosure, at least a portion of the inner spacer 430 may be in contact with the sidewall NWs of each of the plurality of nanosheets NW1 , NW2 , NW3 , and NW4 in the first horizontal direction DR1 .

[0096] For example, the inner spacer 430 may include first to fourth portions 431, 432, 433, and 434. For example, a sidewall 430s of each of the first to fourth portions 431, 432, 433, and 434 of the inner spacer 430 contacting the first layer 421 of the source / drain region 420 may be formed to protrude toward the first layer 421 in the first horizontal direction DR1 beyond a sidewall NWs of each of the plurality of nanosheets NW1, NW2, NW3, and NW4.

[0097] For example, at least a portion of the first portion 431 of the inner spacer 430 may contact a sidewall of the active pattern 101 adjacent to the uppermost surface of the active pattern 101. At least a portion of the first portion 431 of the inner spacer 430 may contact a sidewall NWs of the first nanosheet NW1 in the first horizontal direction DR1. At least a portion of the second portion 432 of the inner spacer 430 may contact a sidewall NWs of each of the first nanosheet NW1 and the second nanosheet NW2 in the first horizontal direction DR1. At least a portion of the third portion 433 of the inner spacer 430 may contact a sidewall NWs of each of the second nanosheet NW2 and the third nanosheet NW3 in the first horizontal direction DR1. At least a portion of the fourth portion 434 of the inner spacer 430 may contact a sidewall NWs of each of the third nanosheet NW3 and the fourth nanosheet NW4 in the first horizontal direction DR1.

[0098] For example, between the first portion 431 of the inner spacer 430 and the second portion 432 of the inner spacer 430, the sidewall NWs of the first nanosheet NW1 in the first horizontal direction DR1 may be in contact with the first layer 421. Between the second portion 432 of the inner spacer 430 and the third portion 433 of the inner spacer 430, the sidewall NWs of the second nanosheet NW2 in the first horizontal direction DR1 may be in contact with the first layer 421. Between the third portion 433 of the inner spacer 430 and the fourth portion 434 of the inner spacer 430, the sidewall NWs of the third nanosheet NW3 in the first horizontal direction DR1 may be in contact with the first layer 421. Between the fourth portion 434 of the inner spacer 430 and the gate spacer 111, the sidewall NWs of the fourth nanosheet NW4 in the first horizontal direction DR1 may be in contact with the first layer 421.

[0099] Although the present disclosure includes many specific implementation details, these should not be interpreted as limitations on the scope of possible protection. Certain features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. In addition, although features may be described above as working in certain combinations and even initially claimed as such, one or more features from the combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variant of a sub-combination.

[0100] Although the embodiments according to the present disclosure have been described above with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be manufactured in various forms. It will be understood by those skilled in the art that the present disclosure can be implemented in other specific forms without changing the technical ideas or essential features of the present disclosure. Therefore, the above embodiments should be understood as illustrative rather than restrictive in all aspects.

Claims

1. A semiconductor device, the semiconductor device include: substrate; an active pattern extending along a first horizontal direction on the substrate; a plurality of nanosheets, the plurality of nanosheets being spaced apart from each other and stacked on the active pattern in a vertical direction; a gate electrode extending on the active pattern along a second horizontal direction different from the first horizontal direction, the gate electrode surrounding the plurality of nanosheets; a source / drain region, the source / drain region being disposed on at least one side of the gate electrode on the active pattern, the source / drain region comprising a first layer doped with a metal and a second layer disposed on the first layer; and An inner spacer is disposed between the gate electrode and the first layer, the inner spacer contacts the first layer and includes a metal oxide of the metal formed by oxidizing the metal.

2. The semiconductor device according to claim 1, in, The metal includes aluminum or nickel.

3. The semiconductor device according to claim 2, in, The substrate is a p-channel metal oxide semiconductor region, the metal is aluminum, and the metal oxide is aluminum oxide.

4. The semiconductor device according to claim 2, in, The substrate is an n-channel metal oxide semiconductor region, the metal is nickel, and the metal oxide is nickel oxide. 5 . The semiconductor device according to claim 1 , further comprising a gate insulating layer disposed between the gate electrode and the inner spacer, the gate insulating layer contacting the inner spacer.

6. The semiconductor device according to claim 1, in, Between adjacent nanosheets of the plurality of nanosheets, upper and lower surfaces of the inner spacer contact the plurality of nanosheets.

7. The semiconductor device according to claim 1, in, The first layer does not contact each of upper and lower surfaces of the plurality of nanosheets.

8. The semiconductor device according to claim 1, in, A sidewall of the inner spacer in contact with the first layer is formed to be recessed beyond sidewalls of the plurality of nanosheets toward the gate electrode in the first horizontal direction.

9. The semiconductor device according to claim 1, in, A sidewall of the inner spacer in contact with the first layer is formed to protrude toward the first layer in the first horizontal direction beyond sidewalls of the plurality of nanosheets.

10. The semiconductor device according to claim 1, in, At least a portion of the first layer contacts a lower surface of each of the plurality of nanosheets.

11. The semiconductor device according to claim 1, in, At least a portion of the inner spacer contacts sidewalls of the plurality of nanosheets in the first horizontal direction.

12. A semiconductor device, the semiconductor device include: substrate; an active pattern extending along a first horizontal direction on the substrate; a plurality of nanosheets, the plurality of nanosheets being spaced apart from each other and stacked on the active pattern in a vertical direction; a gate electrode extending on the active pattern along a second horizontal direction different from the first horizontal direction, the gate electrode surrounding the plurality of nanosheets; a source / drain region, the source / drain region being disposed on at least one side of the gate electrode on the active pattern, the source / drain region comprising a first layer doped with aluminum or nickel and a second layer disposed on the first layer; a gate insulating layer disposed between the gate electrode and the first layer, wherein the gate insulating layer is disposed between adjacent nanosheets among the plurality of nanosheets; and An internal spacer is disposed between the gate electrode and the first layer, wherein the internal spacer is disposed between adjacent nanosheets among the plurality of nanosheets, the internal spacer contacts the first layer and the gate insulating layer, and the internal spacer comprises aluminum oxide or nickel oxide.

13. The semiconductor device according to claim 12, in, The substrate is a p-channel metal oxide semiconductor region, the first layer includes doped aluminum, and the inner spacer includes aluminum oxide.

14. The semiconductor device according to claim 12, in, The substrate is an n-channel metal oxide semiconductor region, the first layer includes doped nickel, and the inner spacer includes nickel oxide.

15. The semiconductor device according to claim 12, in, A sidewall of the inner spacer in contact with the first layer is formed to be recessed beyond sidewalls of the plurality of nanosheets toward the gate electrode in the first horizontal direction.

16. The semiconductor device according to claim 12, in, A sidewall of the inner spacer in contact with the first layer is formed to protrude toward the first layer in the first horizontal direction beyond sidewalls of the plurality of nanosheets.

17. The semiconductor device according to claim 12, in, At least a portion of the inner spacer contacts sidewalls of the plurality of nanosheets in the first horizontal direction.

18. A semiconductor device, the semiconductor device include: substrate; an active pattern extending along a first horizontal direction on the substrate; a plurality of nanosheets, the plurality of nanosheets being spaced apart from each other and stacked on the active pattern in a vertical direction; a gate electrode extending on the active pattern along a second horizontal direction different from the first horizontal direction, the gate electrode surrounding the plurality of nanosheets; a source / drain region, the source / drain region being disposed on at least one side of the gate electrode on the active pattern, the source / drain region comprising a first layer doped with aluminum and a second layer disposed on the first layer; as well as an inner spacer disposed between the gate electrode and the first layer, the inner spacer contacting the first layer, the inner spacer comprising aluminum oxide, The first layer does not contact each of the upper surface and the lower surface of the plurality of nanosheets.

19. The semiconductor device according to claim 18, in, A sidewall of the inner spacer in contact with the first layer is formed to be recessed beyond sidewalls of the plurality of nanosheets toward the gate electrode in the first horizontal direction.

20. The semiconductor device according to claim 18, in, A sidewall of the inner spacer in contact with the first layer is formed to protrude toward the first layer in the first horizontal direction beyond sidewalls of the plurality of nanosheets.

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