Semiconductor device

Abstract

A semiconductor device may include insulating patterns spaced apart from each other in a first direction and a second direction crossing the first direction; a substrate insulating layer disposed on a side surface of the insulating pattern in the first direction; a device isolation layer disposed on a side surface of the insulating pattern in the second direction; a plurality of channel layers disposed on the insulating pattern and spaced apart from each other in a vertical direction perpendicular to an upper surface of the device isolation layer; a gate structure configured to vertically overlap with the insulating pattern and surround each of the plurality of channel layers, and extend in a second direction; a source / drain region disposed outside the gate structure; and a back contact structure electrically connected to the source / drain region below the source / drain region, in which the insulation pattern includes a protrusion protruding in a vertical direction from an upper surface of the device isolation layer, and a vertical distance between a lower surface of a lowermost channel layer among the plurality of channel layers and an upper surface of the protrusion is greater than a vertical distance between the plurality of channel layers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0074071 filed in the Korean Intellectual Property Office on June 9, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device. Background Art

[0004] As the demand for high performance, high speed and / or multifunctionalization of semiconductor devices increases, the integration of semiconductor devices is increasing. According to the trend of high integration of semiconductor devices, semiconductor devices having a back side power transmission network (BSPDN) structure in which a power rail is provided on the back surface of a wafer are being developed. In addition, in order to overcome the limitation of operating characteristics due to the size reduction of a planar metal oxide semiconductor FET (MOSFET), efforts are being made to develop a semiconductor device having a channel with a three-dimensional structure. Summary of the invention

[0005] An aspect of the present disclosure is to provide a semiconductor device having improved electrical characteristics and reliability.

[0006] According to one aspect of the present disclosure, a semiconductor device may include: an insulating pattern spaced apart from each other in a first direction and in a second direction intersecting the first direction; a substrate insulating layer located on a side surface of the insulating pattern in the first direction; a device isolation layer located on a side surface of the insulating pattern in the second direction; a plurality of channel layers located on the insulating pattern and spaced apart from each other in a vertical direction perpendicular to an upper surface of the device isolation layer; a gate structure configured to vertically overlap with the insulating pattern and surround each of the plurality of channel layers and extend in the second direction; a source / drain region located outside the gate structure; and a back contact structure electrically connected to the source / drain region below the source / drain region, wherein the insulating pattern may further include a protrusion protruding from an upper surface of the device isolation layer in a vertical direction, and in a region where the insulating pattern and the gate structure vertically overlap with each other, a vertical distance between a lower surface of a lowest channel layer among the plurality of channel layers and an upper surface of the protrusion may be greater than a vertical distance between the plurality of channel layers.

[0007] According to one aspect of the present disclosure, a semiconductor device may include: an insulating pattern spaced apart from each other in a first direction and in a second direction intersecting the first direction; a substrate insulating layer located on a side surface of the insulating pattern in the first direction; a device isolation layer located on a side surface of the insulating pattern in the second direction; a plurality of channel layers located on the insulating pattern and spaced apart from each other in a vertical direction perpendicular to an upper surface of the device isolation layer; a gate structure configured to vertically overlap the insulating pattern and surround each of the plurality of channel layers and extend in the second direction; a source / drain region disposed on the insulating pattern; and The outside of the gate structure; and a contact structure connected to the source / drain region, wherein the source / drain region may include a first source / drain region configured to vertically overlap with and be disposed on a substrate insulating layer and a second source / drain region spaced apart from the first source / drain region in a first direction, the contact structure may include a first contact structure connected to the first source / drain region above the first source / drain region and a second contact structure connected to the second source / drain region by penetrating an insulating pattern below the second source / drain region, and the insulating pattern may partially penetrate a lower portion of the gate structure.

[0008] According to one aspect of the present disclosure, a semiconductor device may include: an insulating pattern, which is spaced apart from each other in one direction; a plurality of channel layers, which are spaced apart from each other on the insulating pattern; a gate structure, which is configured to vertically overlap with the insulating pattern and surround the plurality of channel layers, respectively; a source / drain region, which is disposed outside the gate structure; and a back contact structure, which is electrically connected to the source / drain region below the source / drain region, wherein the insulating pattern may include a protrusion that partially penetrates the lower portion of the gate structure, and in a region where the insulating pattern and the gate structure vertically overlap with each other, a vertical distance between a lower surface of a lowest channel layer among the plurality of channel layers and an upper surface of the protrusion is greater than a vertical distance between the plurality of channel layers.

[0009] The advantages and effects of the present application are not limited to the above and may be more easily understood in the course of describing specific exemplary embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view showing an example of a semiconductor device according to an example embodiment;

[0012] Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments;

[0013] Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments;

[0014] Figure 4 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments;

[0015] Figure 5 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments;

[0016] Figure 6 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments;

[0017] Figure 7 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments;

[0018] Figure 8 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments;

[0019] FIG. 9A to FIG. 9M is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0020] Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings. Hereinafter, it will be understood that expressions such as "on", "above", "above", "below", "below", "lower" and "side" are only indicated based on the accompanying drawings unless they are indicated by the accompanying drawings and quoted separately.

[0021] Figure 1 is a plan view illustrating a semiconductor device according to example embodiments.

[0022] Figure 2 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 2 Shown are Figure 1 The cross-section of the semiconductor device taken along the cutting lines Ⅰ-Ⅰ', Ⅱ-Ⅱ' and Ⅲ-Ⅲ'. Figure 1 and Figure 2 Only major components of the semiconductor device are shown.

[0023] Reference Figure 1 and Figure 2, the semiconductor device 100 may include: an insulating pattern 102; a device isolation layer 110 disposed on a side surface of the insulating pattern 102; a substrate insulating layer 194; a channel structure 140 including first to third channel layers 141, 142, and 143 vertically spaced apart from each other on the insulating pattern 102; a gate structure 160 vertically overlapping the insulating pattern 102, surrounding each of the plurality of channel layers 141, 142, and 143, and extending in the Y direction; a source / drain region 150 in contact with the channel structure 140; and contact structures 180 and 210 connected to the source / drain region 150. The semiconductor device 100 may also include a gate contact structure 185, an interlayer insulating layer 190, a first upper insulating layer 192 and a second upper insulating layer 193, a lower insulating layer 196, a via VA, a metal wiring ML, and a backside power structure 195.

[0024] The insulating patterns 102 may be spaced apart from each other in a first direction (e.g., X direction) and a second direction (e.g., Y direction) intersecting the first direction. The insulating patterns 102 may be formed in a region from which an active region 105 described below is removed. The device isolation layer 110 may be disposed between adjacent insulating patterns 102 in the Y direction. The upper surface of the insulating pattern 102 may be disposed at a level different from that of the upper surface of the device isolation layer 110, but the present disclosure is not limited thereto. The insulating pattern 102 may include, for example, an oxide, a nitride, or a combination thereof.

[0025] The insulating pattern 102 may include a protrusion 102P that partially penetrates the lower portion of the gate structure 160. According to example embodiments, the insulating pattern 102 may include a protrusion 102P that protrudes from the upper surface of the device isolation layer 110 in a vertical direction (e.g., in the Z direction). The cross-section of the protrusion 102P in the X direction may have various shapes. According to example embodiments, the cross-section of the protrusion 102P in the X direction may be at least one of a dome shape and a mushroom shape. In addition, the cross-section of the protrusion 102P in the Y direction may be at least one of a dome shape and a mushroom shape. The shape of the cross-section of the protrusion 102P in the X direction and the shape of the cross-section of the protrusion 102P in the Y direction may be independent of each other.

[0026] The insulating pattern 102 may partially penetrate the lower portion of the gate structure 160. The insulating pattern 102 may vertically overlap the plurality of channel layers 141, 142, and 143, and may be disposed below the plurality of channel layers 141, 142, and 143 to be spaced apart from the plurality of channel layers 141, 142, and 143. According to example embodiments, a vertical distance D2 between an upper surface of the insulating pattern 102 and a lower surface of a lowermost channel layer 141 among the plurality of channel layers 141, 142, and 143 may be greater than a vertical distance D1 between the plurality of channel layers 141, 142, and 143. For example, a vertical distance D2 between an uppermost end of the insulating pattern 102 and a lower surface of a lowermost channel layer 141 among the plurality of channel layers 141, 142, and 143 may be greater than a vertical distance D1 between the plurality of channel layers 141, 142, and 143. According to example embodiments, in a region where the insulating pattern 102 and the gate structure 160 vertically overlap each other, a vertical distance D2 between a lower surface of a lowermost channel layer 141 among the plurality of channel layers 141 , 142 , and 143 and the protrusion 102P may be greater than a vertical distance D1 between the plurality of channel layers 141 , 142 , and 143 .

[0027] The device isolation layer 110 may be disposed on the side surface of the insulating pattern 102 in the Y direction. The device isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. According to example embodiments, the device isolation layer 110 may be disposed on the side surface of the back contact structure 210 described below. The device isolation layer 110 may be formed of an insulating material. The device isolation layer 110 may be, for example, an oxide, a nitride, or a combination thereof.

[0028] The substrate insulating layer 194 may be disposed on the side surface of the insulating pattern 102 in the X direction. The substrate insulating layers 194 may be spaced apart from each other in the Y direction by the insulating pattern 102 or the back contact structure 210, but the present disclosure is not limited thereto. In an area not shown, the substrate insulating layer 194 may extend in the Y direction. The substrate insulating layer 194 may be a substrate 101 (see FIG. 1 ) formed of a semiconductor material by removing and / or oxidizing the substrate 101 during a manufacturing process. Fig.9A ). The substrate insulating layer 194 may be formed of an insulating material, for example, oxide, nitride, or a combination thereof. According to example embodiments, the substrate insulating layer 194 may include a plurality of insulating layers.

[0029] According to example embodiments, a level L3 of a surface where the substrate insulating layer 194 and the first source / drain region 150A contact each other may be lower than a level L2 of an uppermost end of each of the protrusions 102P. The substrate insulating layer 194 may cover a lower surface of the device isolation layer 110 and a side surface of the second portion 210B, but the present disclosure is not limited thereto.

[0030] The channel structure 140 may be disposed on the insulating pattern 102 to intersect the gate structure 160. Each of the channel structures 140 may include first to third channel layers 141, 142, and 143 as two or more channel layers spaced apart from each other in the Z direction. The channel structure 140 may be connected to the source / drain region 150. The channel structure 140 may have a width equal to or similar to that of the gate structure 160 in the X direction. In a cross section in the Y direction, a width of a channel layer disposed in a lower portion among the first to third channel layers 141, 142, and 143 may be equal to or greater than a width of a channel layer disposed in an upper portion among the first to third channel layers 141, 142, and 143. However, according to example embodiments, the first to third channel layers 141, 142, and 143 may have a reduced width such that a side surface thereof is disposed below the gate structure 160 in the X direction. Therefore, a contact area of ​​the source / drain region 150 contacting the plurality of channel layers 141 , 142 , and 143 may be reduced.

[0031] The channel structure 140 may be formed of a semiconductor material, and may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). In example embodiments, the number and shape of channel layers constituting one channel structure 140 may be variously changed.

[0032] In the semiconductor device 100, the gate electrode 165 may be disposed between the first to third channel layers 141, 142, and 143 of the channel structure 140 and on the channel structure 140. Therefore, the semiconductor device 100 may include a multi-bridge channel FET (MBCFET). TM ) structure, which is a ring-gate field effect transistor. According to example embodiments, the present disclosure may also be applied to a transistor having a three-dimensional stacked FET (3D-SFET) structure in which a plurality of transistors are vertically stacked.

[0033] The gate structure 160 may be disposed to vertically overlap the insulating pattern 102 and extend in one direction (e.g., in the Y direction). A channel region of the transistor may be formed in the channel structure 140 intersecting the gate electrode 165 of the gate structure 160. The gate structures 160 may be spaced apart from each other in the X direction. Each of the gate structures 160 may include a gate dielectric layer 162, a gate spacer layer 164, a gate electrode 165, and a gate capping layer 166 on an upper surface of the gate electrode 165.

[0034] The gate dielectric layer 162 may be disposed between the gate electrode 165 and the source / drain region 150, and between the channel structure 140 and the gate electrode 165, and may be disposed to cover at least some surfaces of the gate electrode 165. The gate dielectric layer 162 may cover the upper surface of the device isolation layer 110. For example, the gate dielectric layer 162 may be disposed to surround all surfaces except the uppermost surface of the gate electrode 165. The gate dielectric layer 162 may extend between the gate electrode 165 and the gate spacer layer 164, but the present disclosure is not limited thereto. The gate dielectric layer 162 may include an oxide, a nitride, or a high-κ material. The high-κ material may refer to a material having a higher κ than a silicon oxide film (SiO 2 ) Dielectric materials with higher dielectric constants. High κ materials can be, for example, aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and praseodymium oxide (Pr 2 O 3 According to example embodiments, the gate dielectric layer 162 may have a multi-layer structure.

[0035] The gate electrode 165 may include a conductive material, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN) and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. According to example embodiments, the gate electrode 165 may have a multi-layer structure. The gate electrode 165 may be connected to a gate contact structure 185.

[0036] The gate spacer layer 164 may be disposed on both side surfaces of the gate electrode 165 on the channel structure 140. The gate spacer layer 164 may insulate the source / drain region 150 from the gate electrode 165. According to example embodiments, the shape of the upper end of the gate spacer layer 164 may be variously changed, and the gate spacer layer 164 may have a multi-layer structure. The gate spacer layer 164 may include at least one of oxide, nitride, and oxynitride, for example, may be formed of a low dielectric constant film.

[0037] According to an example embodiment, Fig.9A In the embodiment of the present invention, the lowermost sacrificial layer 120 may be thicker than the thickness of the other sacrificial layers 120, and therefore, in a region where the gate structure 160 and the plurality of channel layers 141, 142, and 143 vertically overlap each other, a vertical distance T1 between a lower surface of the lowermost channel layer 141 and an upper surface of the device isolation layer 110 may be greater than a vertical distance T2 between an uppermost surface of the gate electrode 165 and an upper surface of the uppermost channel layer 143 among the plurality of channel layers 141, 142, and 143. However, the present disclosure is not limited thereto. The vertical distance T1 between the lower surface of the lowermost channel layer 141 and the upper surface of the device isolation layer 110 may represent a vertical distance between a level of a lower surface of the lowermost channel layer 141 and a level of an upper surface of the device isolation layer 110.

[0038] The source / drain region 150 may be disposed on both sides of the gate structure 160 to contact the channel structure 140, respectively. The source / drain region 150 may be disposed as a source region or a drain region of a transistor. The source / drain region 150 may include a first source / drain region 150A vertically overlapping with the substrate insulating layer 194 and disposed on the substrate insulating layer 194, and a second source / drain region 150B spaced apart from the first source / drain region 150A in the X direction. The source / drain region 150 may also include a third source / drain region 150C spaced apart from the second source / drain region 150B in the Y direction. The second source / drain region 150B and the third source / drain region 150C may be connected to the back contact structure 210 through their lower surfaces or lower ends. The lower region of the first source / drain region 150A may have a shape recessed by the substrate insulating layer 194, and the lower regions of the second source / drain region 150B and the third source / drain region 150C may have a shape recessed by the back contact structure 210. The second source / drain region 150B and the third source / drain region 150C may be electrically connected to the back power structure 195 to receive power through the back contact structure 210. The upper surface of the source / drain region 150 may be disposed at the same or similar height as the lower surface of the gate electrode 165 on the channel structure 140, and in example embodiments, the height may be variously changed.

[0039] The source / drain regions 150 may include a semiconductor material, for example, at least one of silicon (Si) and germanium (Ge), and may further include impurities.

[0040] When the semiconductor device 100 is a pFET, the impurity may be at least one of boron (B), gallium (Ga), and indium (In), and when the semiconductor device 100 is an nFET, the impurity may be at least one of phosphorus (P), arsenic (As), and antimony (Sb).

[0041] The source / drain region 150 may include an epitaxial layer disposed along the side surface of each of the first to third channel layers 141, 142, and 143 of the channel structure 140. The source / drain region 150 may include a plurality of epitaxial layers, but the present disclosure is not limited thereto. The source / drain region 150 may be a semiconductor layer including silicon (Si) and / or germanium (SiGe). The source / drain region 150 may include impurities of different types and / or concentrations. For example, the source / drain region 150 may include N-type doped silicon (Si) and / or P-type doped silicon germanium (SiGe). According to example embodiments, the first source / drain region 150A and the second source / drain region 150B may include P-type doped silicon germanium (SiGe), and the third source / drain region 150C may include N-type doped silicon (Si), but the present disclosure is not limited thereto. According to example embodiments, the source / drain region 150 may include a plurality of regions including elements and / or doping elements having different concentrations. The source / drain region 150 may have a circular, elliptical, pentagonal, hexagonal, or similar cross-section in the Y direction. However, in example embodiments, the source / drain region 150 may have various shapes, for example, any one of a polygon, a circle, and a rectangle.

[0042] The contact structures 180 and 210 may be connected to the source / drain region 150. According to example embodiments, the contact structures 180 and 210 may include a first contact structure 180 connected to the first source / drain region 150A above the first source / drain region 150A, and a second contact structure 210 penetrating the insulating pattern 102 below the second source / drain region 150B and connected to the second source / drain region 150B. The second contact structure 210 may not vertically overlap the first contact structure 180. In this specification, the second contact structure 210 may be referred to as a backside contact structure 210.

[0043] The first contact structure 180 may penetrate at least a portion of the interlayer insulating layer 190 to contact the first source / drain region 150A, and an electrical signal may be applied to the first source / drain region 150A. The first contact structure 180 may be disposed on the first source / drain region 150A, and according to example embodiments, the first contact structure 180 may be disposed to have a length in the Y direction that is longer than that of the first source / drain region 150A. The first contact structure 180 may have an inclined side surface, wherein the width of the lower portion of the first contact structure 180 is narrower than the width of the upper portion of the first contact structure 180 according to an aspect ratio, but the present disclosure is not limited thereto. The first contact structure 180 may be disposed to recess the first source / drain region 150A by a predetermined depth.

[0044] The first contact structure 180 may include a first metal semiconductor compound layer 182 disposed on the bottom, a barrier layer 184 disposed along the sidewall thereof, and a plug conductive layer 186. The first metal semiconductor compound layer 182 may be, for example, a metal silicide layer. The barrier layer 184 may include, for example, a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The plug conductive layer 186 may include, for example, a metal material, such as aluminum (Al), tungsten (W), or molybdenum (Mo). In example embodiments, the first contact structure 180 may be disposed to penetrate at least a portion of the first source / drain region 150A. In example embodiments, the number and arrangement shape of the conductive layers constituting the first contact structure 180 may be changed differently. In addition, a wiring structure such as a contact plug may be disposed on the gate electrode 165, and a wiring structure including a via VA and a metal wiring ML connected to the first contact structure 180 may be disposed on the first contact structure 180.

[0045] The back contact structure 210 may be disposed under the source / drain region 150. According to example embodiments, the back contact structure 210 may be electrically connected to the second and third source / drain regions 150B and 150C under the second and third source / drain regions 150B and 150C.

[0046] The back contact structure 210 may extend vertically by penetrating the insulating pattern 102. The side surface of the back contact structure 210 and the side surface of the insulating pattern 102 may contact each other. The back contact structure 210 may be a self-aligned contact (SAC) aligned by the insulating pattern 102. Therefore, the contact margin between the back contact structure 210 and the source / drain region 150 may be ensured. The back contact structure 210 may be connected to the second source / drain region 150B and the third source / drain region 150C by penetrating the insulating pattern 102. The back contact structure 210 may be arranged to partially recess the lower region of the second source / drain region 150B and the third source / drain region 150C, and contact the recessed lower surface of the second source / drain region 150B and the third source / drain region 150C. The level of the upper end of the back contact structure 210 may be higher than the level of the lower end of the second source / drain region 150B and the third source / drain region 150C. According to example embodiments, a level L1 of an uppermost end of the back contact structure 210 may be higher than a level L2 of an uppermost end of the insulating pattern 102, and may be lower than a level of a lower surface of a lowermost channel layer among the plurality of channel layers 141, 142, and 143. An upper surface of the back contact structure 210 may be disposed at a level higher than a level of a surface where the substrate insulating layer 194 and the first source / drain region 150A contact each other. According to example embodiments, a level L1 of an uppermost end of the back contact structure 210 may be higher than a level L3 of an uppermost end of the substrate insulating layer 194.

[0047] According to an example embodiment, since Fig.9A The lowermost sacrificial layer 120 may be formed thicker than other sacrificial layers 120, and thus the level L1 of the uppermost end of each of the back contact structures 210 may be lower than the level of the lower surface of the lowermost channel layer 141. The level L1 of the uppermost end of each of the back contact structures 210 may be higher than the level L2 of the uppermost end of each of the protrusions 102P.

[0048] The back contact structure 210 may contact the gate dielectric layer 162 , but the disclosure is not limited thereto. The back contact structure 210 may be spaced apart from the gate electrode 165 by the gate dielectric layer 162 .

[0049] The back contact structure 210 may include a first portion 210A disposed at a level higher than the level of the lower surface of the device isolation layer 110 and a second portion 210B disposed at a level lower than the level of the lower surface of the device isolation layer 110. The back contact structure 210 may include a portion where the width of the first portion 210A is increased because the portion is formed in an area where a portion of the lower portion of the second source / drain region 150B and the third source / drain region 150C is removed. The back contact structure 210 may have a bent portion 210V for connecting the first portion 210A and the second portion 210B. The cross section of the bent portion 210V may have an angular shape, but the present disclosure is not limited thereto. The bent portion 210V may be formed along the circumference of the back contact structure 210. Therefore, based on the bent portion 210V, the width of the back contact structure 210 may be discontinuously reduced from above and below. According to example embodiments, the width of the second portion 210B may be greater than the width of the first portion 210A.

[0050] The back contact structure 210 may include a liner layer 214, a second metal semiconductor compound layer 212, and a conductive layer 216. The liner layer 214 may form an outer surface of the back contact structure 210, and may form a portion of an upper surface of the back contact structure 210. However, in example embodiments, the extension range of the liner layer 214 may be variously changed. The liner layer 214 may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0051] The second metal semiconductor compound layer 212 may be disposed on the upper end of the back contact structure 210 and may form at least a portion of the upper surface of the back contact structure 210. The second metal semiconductor compound layer 212 may be disposed on the surface of the back contact structure 210 in contact with the source / drain region 150. However, in example embodiments, the range of the second metal semiconductor compound layer 212 is not limited to the range shown. The second metal semiconductor compound layer 212 may be, for example, a metal silicide layer. The conductive layer 216 may be provided to fill the contact hole surrounded by the liner layer 214 and the second metal semiconductor compound layer 212. The conductive layer 216 may include, for example, a metal material such as aluminum (Al), tungsten (W) or molybdenum (Mo). In example embodiments, the number and arrangement shape of the conductive layers constituting the back contact structure 210 may be changed differently. In some example embodiments, the liner layer 214 and / or the second metal semiconductor compound layer 212 may be omitted.

[0052] The gate contact structure 185 may penetrate the gate capping layer 166 in a vertical direction (e.g., in the Z direction) and may be connected to the gate electrode 165. The gate contact structure 185 may include a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), but the present disclosure is not limited thereto. The gate contact structure 185 may include a metal material such as at least one of aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0053] The interlayer insulating layer 190 may be provided to cover the source / drain regions 150, the gate structure 160, and the device isolation layer 110. The interlayer insulating layer 190 may include, for example, at least one of oxide, nitride, oxide, and a low-κ dielectric.

[0054] The first upper insulating layer 192 may be provided to cover the interlayer insulating layer 190 and the gate structure 160. The second upper insulating layer 193 may be provided on the first upper insulating layer 192. The lower insulating layer 196 may be provided to cover the insulating pattern 102 and the substrate insulating layer 194. The first upper insulating layer 192 and the second upper insulating layer 193 and the lower insulating layer 196 may include at least one of an oxide, a nitride, and an oxynitride, for example, a low dielectric constant material. According to example embodiments, each of the first upper insulating layer 192 and the second upper insulating layer 193 and the lower insulating layer 196 may include a plurality of insulating layers.

[0055] The via VA may penetrate the first upper insulating layer 192. The via VA may be connected to the first contact structure 180 or the gate contact structure 185. The via VA may be formed of a conductive material.

[0056] The metal wiring ML may constitute a back-end of line (BEOL) together with the via VA. The metal wiring ML and the via VA may be provided as a wiring portion for signal transmission. According to example embodiments, a signal network may be constructed by connecting from the metal wiring ML and the via VA to a device region (e.g., source / drain region 150 and gate electrode 165) via a first contact structure 180 or a gate contact structure 185.

[0057] The back power structure 195 may be connected to the lower end or lower surface of the back contact structure 210. The back power structure 195 may form a BSPDN that applies power or ground voltage together with the back contact structure 210, and may also be referred to as a backside power rail or a buried power rail. For example, the back power structure 195 may be a buried wiring extending in one direction (e.g., in the Y direction) from the bottom of the back contact structure 210, but the shape of the back power structure 195 is not limited thereto. For example, in some example embodiments, the back power structure 195 may include a via region and / or a line region. The width of the back power structure 195 may be constant when facing downward, but the present disclosure is not limited thereto, and the width of the back power structure 195 may increase continuously. The back power structure 195 may include a conductive material, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), titanium (Ti), and molybdenum (Mo).

[0058] Figure 3 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 3 shows that along with Figure 1 The area corresponding to the cross-sections taken by lines Ⅰ-Ⅰ' and Ⅱ-Ⅱ'.

[0059] Reference Figure 3 , in the semiconductor device 100a, the cross section of the protrusion 102P in the X direction may have a rectangular shape. The cross section of the protrusion 102P in the Y direction may have a rectangular shape. According to example embodiments, the back contact structure 210 may be spaced apart from the gate structure 160 by the insulating pattern 102 and the source / drain region 150. The source / drain region 150 may be in contact with the substrate insulating layer 194 and the insulating pattern 102. Since the gate electrode 165 and the back contact structure 210 are spaced apart from each other by an appropriate distance, a short margin may be ensured between the back contact structure 210 and the gate electrode 165. Therefore, a semiconductor device 100a having improved electrical characteristics may be provided.

[0060] Figure 4 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 4 shows that along with Figure 1 The area corresponding to the cross-sections taken by lines Ⅰ-Ⅰ' and Ⅱ-Ⅱ'.

[0061] Reference Figure 4 In the semiconductor device 100b, the cross section of the protrusion 102P in the X direction may have a triangular shape. The cross section of the protrusion 102P in the Y direction may have a triangular shape. The cross section of the protrusion 102P in the X direction and the cross section of the protrusion 102P in the Y direction are shown as having a triangular shape, but the present disclosure is not limited thereto. The shape of the cross section of the protrusion 102P in the X direction and the shape of the cross section thereof in the Y direction may be independent of each other.

[0062] Figure 5 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 5 shows that along with Figure 1 The area corresponding to the cross-sections taken by lines Ⅰ-Ⅰ' and Ⅱ-Ⅱ'.

[0063] Reference Figure 5 In the semiconductor device 100c, the cross section of the protrusion 102P in the X direction may have a trapezoidal shape. The cross section of the protrusion 102P in the Y direction may have a trapezoidal shape. The shape of the cross section of the protrusion 102P in the X direction and the shape of the cross section thereof in the Y direction may be independent of each other. According to another example embodiment, the shape of the cross section of the protrusion 102P in the X direction may be at least one of a dome shape, a mushroom shape, a triangle, and a quadrilateral, and the shape of the cross section of the protrusion 102P in the Y direction may be different from the shape of the cross section of the protrusion 102P in the X direction.

[0064] Figure 6 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 6 shows that along with Figure 1 The area corresponding to the cross-sections taken by lines Ⅰ-Ⅰ' and Ⅲ-Ⅲ'.

[0065] Reference Figure 6 In the semiconductor device 100d, the side surface of the bent portion 210V may be inclined on the second portion 210B of the back contact structure 210. Figure 9L In the process of forming the through hole TH, a portion of the substrate insulating layer 194 on the device isolation layer 110 may be removed. In the process of removing a portion of the substrate insulating layer 194, a side surface of the substrate insulating layer 194 may be inclined.

[0066] Figure 7 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 7 shows that along with Figure 1 The area corresponding to the cross section taken by line Ⅰ-Ⅰ'.

[0067] Reference Figure 7 The semiconductor device 100e may further include Figure 2In the example embodiment of the present invention, an internal spacer layer 130 is disposed on the lower surface of each of the plurality of channel layers 141, 142, and 143 on both sides of the gate structure 160 in the first direction (i.e., the X direction). The internal spacer layer 130 may be disposed in parallel with the gate electrode 165 between the plurality of channel layers 141, 142, and 143. The internal spacer layer 130 may be in contact with the gate dielectric layer 162. The internal spacer layer 130 may be disposed between the gate structure 160 and the source / drain region 150. The side surface of the internal spacer layer 130 may be in contact with the source / drain region 150. In the lower portion of each of the plurality of channel layers 141, 142, and 143, the gate electrode 165 may be spaced apart and electrically isolated from the source / drain region 150 by the internal spacer layer 130. The internal spacer layer 130 may have a shape in which the side surface facing the gate electrode 165 is convex toward the gate electrode 165. The inner spacer layer 130 may be formed of oxide, nitride, and oxynitride, and in particular, may be formed of a low dielectric constant film.

[0068] The inner spacer layer 130 may be formed of the same material as the gate spacer layer 164, but the present disclosure is not limited thereto. For example, the inner spacer layer 130 may include at least one of SiN, SiCN, SiOCN, SiBCN, and SiBN. The inner spacer layer 130 may also be applied to other example embodiments.

[0069] According to example embodiments, side surfaces of the back contact structure 210 and the side surfaces of the insulating pattern 102 may contact each other. The inner spacer layer 130 may be disposed between the protrusion 102P and the upper portion of each back contact structure 210. To this end, the back contact structure 210 may be spaced apart from the gate electrode 165, and the occurrence of leakage current may be prevented and a short margin may be ensured. The protrusion 102P may be spaced apart from the upper portion of each of the back contact structures 210 by the inner spacer layer 130.

[0070] Figure 8 is a schematic cross-sectional view illustrating a semiconductor device according to example embodiments. Figure 8 Shown with Figure 2 The area corresponding to the cross section.

[0071] and Figure 2 Unlike the semiconductor device 100 of FIG. 1 , in the semiconductor device 100 f , the backside power structure 195 may be in contact with the lower surface of the device isolation layer 110 . Figure 9M After the process of forming the back contact structure 210, the substrate insulating layer 194 on the device isolation layer 110 may be removed by a planarization process. Figure 9M In the embodiment, the upper surface of the device isolation layer 110 may be exposed. Figure 9MIn the embodiment, the upper surface of the device isolation layer 110, the upper surface of the insulating pattern 102 and the upper surface of the back contact structure 210 can form a coplanar surface. In addition, the first portion 210A (see FIG. 2 ) for connecting the back contact structure 210 Figure 2 ) and the second part 210B (see Figure 2 ) bend 210V (see Figure 2 ) may be removed.

[0072] Next, after forming the lower insulating layer 196, a portion of the lower insulating layer 196 may be removed to form a backside power structure 195. The lower insulating layer 196 may cover the device isolation layer 110, the insulating pattern 102, the substrate insulating layer 194, and the backside contact structure 210.

[0073] FIG. 9A to FIG. 9M is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to example embodiments. FIG. 9A to FIG. 9M Shown with Figure 2 The corresponding cross section.

[0074] Reference Fig.9A , the sacrificial layers 120 and the first to third channel layers 141 , 142 , and 143 may be alternately stacked on the substrate 101 .

[0075] The substrate 101 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate 101 may include a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer.

[0076] like Figure 2 As shown, the sacrificial layer 120 may be a layer replaced by the gate dielectric layer 162 and the gate electrode 165 under the third channel layer 143 through a subsequent process. The lowermost sacrificial layer 120 disposed under the first channel layer 141 among the sacrificial layers 120 may be formed to be thicker than the thickness of the other sacrificial layers 120. The lowermost sacrificial layer 120 may be thicker than the thickness of each of the first to third channel layers 141, 142, and 143. When forming the subsequent back contact structure 210 (see Figure 9M), by forming the lowermost sacrificial layer 120 thickly, the loss of the source / drain region 150 can be reduced. By enabling the source / drain region 150 to remain below the lower surface of the first channel layer 141, a semiconductor device 100 with improved electrical characteristics can be provided. The sacrificial layer 120 may be formed of a material having an etching selectivity relative to the first to third channel layers 141, 142, and 143, respectively. The first to third channel layers 141, 142, and 143 may include a material different from that of the sacrificial layer 120. The sacrificial layer 120 and the first to third channel layers 141, 142, and 143 may include a semiconductor material including at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may include different materials and may or may not include impurities. For example, the sacrificial layer 120 may include silicon germanium (SiGe), and the first to third channel layers 141, 142, and 143 may include silicon (Si).

[0077] The sacrificial layer 120 and the first to third channel layers 141, 142, and 143 may be formed by performing an epitaxial growth process on the stack structure. In example embodiments, the number of layers of the channel layers alternately stacked with the sacrificial layer 120 may be variously changed.

[0078] Reference Fig. 9B , the sacrificial layer 120 , the first to third channel layers 141 , 142 , and 143 , and the substrate 101 may be partially removed to form an active structure including the active region 105 , and the device isolation layer 110 may be formed.

[0079] The active structure may include an active region 105, a sacrificial layer 120, and first to third channel layers 141, 142, and 143. The active structure may be formed in one direction, for example, in a linear shape extending in the X direction, and may be formed to be spaced apart from adjacent active structures in the Y direction. Side surfaces of the active structures in the Y direction are coplanar with each other and may be arranged in a straight line.

[0080] In the region where some of the active region 105, the sacrificial layer 120, and the first to third channel layers 141, 142, and 143 are removed, after burying the insulating material, a device isolation layer 110 may be formed by partially removing the insulating material to protrude the active region 105. An upper surface of the device isolation layer 110 may be formed to be lower than an upper surface of the active region 105.

[0081] The device isolation layer 110 may define the active region 105 in the substrate 101. The device isolation layer 110 may be formed by, for example, a shallow trench isolation (STI) process. According to example embodiments, the device isolation layer 110 may further include a region having a stepped portion in a lower portion of the substrate 101 and extending deeper. The device isolation layer 110 may partially expose an upper portion of the active region 105. According to example embodiments, the device isolation layer 110 may have a curved upper surface having a higher height as it approaches the active region 105.

[0082] Reference Fig. 9C , a sacrificial gate structure 200 and a gate spacer layer 164 may be formed on the active structure.

[0083] like Figure 2 As shown, the sacrificial gate structure 200 may be a sacrificial structure formed by a subsequent process in a region where the gate dielectric layer 162 and the gate electrode 165 are disposed on the channel structure 140. The sacrificial gate structure 200 may have a line shape that intersects the active structure and extends in one direction. The sacrificial gate structures 200 may extend in the Y direction, for example, and may be spaced apart from each other in the X direction.

[0084] The sacrificial gate structure 200 may include a first sacrificial gate layer 202 and a second sacrificial gate layer 205 sequentially stacked on each other and a mask pattern layer 206. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be patterned using the mask pattern layer 206. The first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be an insulating layer and a conductive layer, respectively, but the present disclosure is not limited thereto, and the first sacrificial gate layer 202 and the second sacrificial gate layer 205 may be formed as a single layer. For example, the first sacrificial gate layer 202 may include silicon oxide, and the second sacrificial gate layer 205 may include polysilicon. The mask pattern layer 206 may include silicon oxide and / or silicon nitride.

[0085] The gate spacer layer 164 may be formed on both sidewalls of the sacrificial gate structure 200. The gate spacer layer 164 may be formed of a low dielectric constant material, and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0086] Reference Fig.9D , the sacrificial layer 120 and the first to third channel layers 141 , 142 , and 143 exposed from the sacrificial gate structure 200 may be partially removed to form a first recess region RC1 , and some of the active region 105 may be removed.

[0087] The first recessed region RC1 may be formed by removing a portion of the exposed sacrificial layer 120 and a portion of the exposed first to third channel layers 141, 142, and 143 using the sacrificial gate structure 200 and the gate spacer layer 164 as a mask. Therefore, the first to third channel layers 141, 142, and 143 may form a channel structure 140 having a limited length in the X direction.

[0088] The sacrificial layer 120 may be selectively etched relative to the channel structure 140 by, for example, a wet etching process, and removed to a certain depth from its side surface in the X direction. The sacrificial layer 120 may have a side surface that is concave inwardly by etching the side surface as described above. However, the specific shape of the side surface of the sacrificial layer 120 is not limited to Fig.9D Those shapes shown in .

[0089] According to example embodiments, since the lowermost sacrificial layer 120 is formed thicker than the other sacrificial layers 120, the first recessed region RC1 (see Fig.9D ) can make the upper portion of the active region 105 recessed.

[0090] Reference Fig.9E , the source / drain region 150 may be formed by forming an epitaxial layer in the first recess region RC1.

[0091] The source / drain region 150 may be formed by an appropriate epitaxial growth process. The source / drain region 150 may be formed by epitaxial growth and may extend to contact the plurality of channel layers 141, 142, and 143 and the sacrificial layer 120 within the first recessed region RC1. The surface of the source / drain region 150 in contact with the plurality of channel layers 141, 142, and 143 and the sacrificial layer 120 may have a wavy shape. The source / drain region 150 may include impurities by in-situ doping. Since the source / drain region 150 may be formed at a level lower than the level of the lower surface of the first channel layer 141, in the process of forming the subsequent back contact structure 210, the second source / drain region 150B and the third source / drain region 150C may remain at a level lower than the level of the lower surface of the first channel layer 141.

[0092] Reference Fig.9F , an interlayer insulating layer 190 covering the source / drain regions 150 may be formed, and the sacrificial gate structure 200 and the sacrificial layer 120 may be removed.

[0093] The interlayer insulating layer 190 may be formed by forming an insulating film covering the sacrificial gate structure 200 and the source / drain regions 150 and performing a planarization process.

[0094] The sacrificial gate structure 200 and the sacrificial layer 120 may be selectively removed relative to the gate spacer layer 164, the interlayer insulating layer 190, and the channel structure 140. First, the sacrificial gate structure 200 may be removed to form an upper gap region UR, and then the sacrificial layer 120 exposed by the upper gap region UR may be removed to form a lower gap region LR.

[0095] For example, when the sacrificial layer 120 includes silicon germanium (SiGe) and the channel structure 140 includes silicon (Si), the sacrificial layer 120 may be removed selectively with respect to the channel structure 140 by performing a wet etching process.

[0096] Reference Figure 9G , a gate structure 160 may be formed in the upper gap region UR and the lower gap region LR.

[0097] The gate dielectric layer 162 may be formed to conformally cover the inner surfaces of the upper gap region UR and the lower gap region LR. The gate electrode 165 may be formed to bury the upper gap region UR and the lower gap region LR. The gate electrode 165 and the gate spacer layer 164 may be removed from the upper gap region UR by a predetermined depth. The gate capping layer 166 may be formed in the region where the gate electrode 165 and the gate spacer layer 164 are removed from the upper gap region UR. Thus, a gate structure 160 including the gate dielectric layer 162, the gate electrode 165, the gate spacer layer 164, and the gate capping layer 166 may be formed.

[0098] Reference Figure 9H , a first contact structure 180 , a gate contact structure 185 , a first upper insulating layer 192 , a second upper insulating layer 193 , a via VA and a metal wiring ML may be formed.

[0099] A contact hole connected to the source / drain region 150 may be formed in the interlayer insulating layer 190, and a barrier layer 184 and a plug conductive layer 186 may be sequentially formed to fill the contact hole. Specifically, after depositing a material forming the barrier layer 184 in the contact hole, a silicidation process may be performed to form a first metal semiconductor compound layer 182, such as a silicide layer, at the lower end of the contact hole. Next, the upper surface of the contact structure 180 and the upper surface of the interlayer insulating layer 190 may be formed into a substantially flat coplanar surface by performing a planarization process such as CMP.

[0100] Next, a gate contact structure 185 connected to the gate electrode 165 by penetrating the gate capping layer 166 may be formed.

[0101] A first upper insulating layer 192 may be formed to cover the first contact structure 180 and the gate contact structure 185, and a via may be formed by penetrating the first upper insulating layer 192 so that the via is connected to the first contact structure 180 and the gate contact structure 185. A second upper insulating layer 193 may be formed to cover the first upper insulating layer 192 and the via VA, and the second upper insulating layer 193 may be patterned and filled with a conductive material to form a metal wiring ML. The metal wiring ML is not limited to the above process and may be formed by a subtractive process.

[0102] Reference Fig.9I , you can refer to 9A to 9H The entire structure formed is attached to the carrier substrate SUB, the substrate 101 may be removed, and a substrate insulating layer 194 may be formed.

[0103] For the sake of Figure 9H The process is performed on the lower surface of the substrate 101 in the embodiment of the present invention, and the carrier substrate SUB can be attached to the second upper insulating layer 193 or the metal wiring ML. In the following figures, for better understanding, the entire structure is shown as follows: Figure 9H The structure shown is rotated or flipped in a mirrored form.

[0104] The substrate 101 may be removed from the upper surface of the substrate 101. For example, the substrate 101 may be removed by a wrapping process, a grinding process, or a polishing process, and may be thinned, and its remaining area may also be removed by an etching process and / or an oxidation process. According to example embodiments, since the source / drain region 150 may include the same material as that of the substrate 101, some of the source / drain region 150 may be removed in the process of removing the substrate 101. A substrate insulating layer 194 may be formed in the region where the substrate 101 is removed.

[0105] Reference Figure 9J , a portion of the substrate insulating layer 194 and a portion of the lower portion of the gate structure 160 may be removed to form a second recessed region RC2.

[0106] First, a mask layer may be formed to cover the upper surface of the substrate insulating layer 194 except for the region where the plurality of channel layers 141, 142, and 143 and the gate structure 160 vertically overlap each other. For example, in the region where the plurality of channel layers 141, 142, and 143 vertically overlap the gate structure 160, the upper surface of the substrate insulating layer 194 may be exposed. The mask layer and the exposed substrate insulating layer 194 may be partially removed using an etching process. In the process of partially removing the substrate insulating layer 194, the upper portion of the gate structure 160 may be exposed, and the second recessed region RC2 may be formed at a level lower than the level of the surface where the substrate insulating layer 194 and the source / drain region 150 contact each other. Therefore, the upper surface of the gate electrode 165 may be exposed. By partially removing the gate electrode 165, the back contact structure 210 described below may ensure a short margin with the gate electrode 165. According to example embodiments, the upper portion of the gate structure 160 may have various shapes, and in the drawings, the upper portion of the gate structure 160 is illustrated as having a shape that is recessed downward, but the present disclosure is not limited thereto.

[0107] Reference Figure 9K , an insulating pattern 102 may be formed in the second recessed region RC2.

[0108] The insulating patterns 102 may be spaced apart from each other in the X direction by the substrate insulating layer 194. The insulating patterns 102 may be spaced apart from each other in the Y direction by the device isolation layer 110. The insulating patterns 102 may be disposed on side surfaces of the substrate insulating layer 194, and may be disposed on side surfaces of the device isolation layer 110.

[0109] Reference Figure 9L , a through hole TH can be formed.

[0110] The mask layer may cover the upper surfaces of the substrate insulating layer 194 and the insulating pattern 102, but may be formed to expose the upper portion of the region corresponding to the back contact structure 210 (see FIG. 2 ). Figure 9M ). Except for the substrate insulating layer 194 disposed on the first source / drain region 150A connected to the first contact structure 180, the substrate insulating layer 194 vertically overlapping the second source / drain region 150B and the third source / drain region 150C may be removed. The substrate insulating layer 194 may be selectively removed relative to the insulating pattern 102. Therefore, the substrate insulating layer 194 may be removed in the region connected to the second contact structure 210 (see Figure 9M ) is formed in a region corresponding to the source / drain region 150. According to the method of removing the substrate insulating layer 194, the second contact structure 210 may have a bent portion 210V. The through hole TH may be formed at a level lower than that of the lower end of the insulating pattern 102. The through hole TH may be formed by removing the substrate insulating layer 194 above the source / drain region 150. In the process of forming the through hole TH, the upper portion of the source / drain region 150 may be partially removed. Fig.9AIn the embodiment, since the lowermost sacrificial layer 120 is formed thick, the level of the lowermost end of the through hole TH may be higher than the level of the upper surface of the first channel layer 141. A contact margin may be ensured between the second contact structure 210 described below and the second source / drain region 150B.

[0111] Reference Figure 9M , a second contact structure 210 may be formed to fill the through hole TH.

[0112] The second metal semiconductor compound layer 212 may be formed by performing a metal semiconductor process such as a silicidation process using the source / drain region 150 exposed by the through hole TH. The second contact structure 210 may be formed by forming a conductive layer 216 on the side surface of the through hole TH to fill the liner layer 214 and the inside of the through hole TH. Figure 2 , a back power structure 195 can be formed.

[0113] After forming the lower insulating layer 196, a portion of the lower insulating layer 196 may be removed to form the back power structure 195, and the carrier substrate SUB may be removed. Figure 1 and Figure 2 The semiconductor device 100 may be packaged in a state where the back side power structure 195 is disposed on an upper portion thereof, but the present disclosure is not limited thereto.

[0114] The present disclosure is not limited to the above embodiments and the accompanying drawings, but is limited by the appended claims. Therefore, those skilled in the art may make various substitutions, modifications or changes without departing from the scope of the present disclosure defined by the appended claims, and these substitutions, modifications or changes should be interpreted as being included within the scope of the present disclosure.

Claims

1. A semiconductor device, include: insulating patterns spaced apart from each other in a first direction and in a second direction crossing the first direction; a substrate insulating layer, which is located on a side surface of the insulating pattern in the first direction; a device isolation layer, which is located on a side surface of the insulation pattern in the second direction; a plurality of channel layers, the plurality of channel layers being located on the insulating pattern and spaced apart from each other in a vertical direction perpendicular to an upper surface of the device isolation layer; a gate structure configured to vertically overlap the insulating pattern and surround each of the plurality of channel layers and to extend in the second direction; a source / drain region located outside the gate structure; as well as a back contact structure electrically connected to the source / drain region below the source / drain region, Wherein, the insulating pattern further includes a protrusion protruding from the upper surface of the device isolation layer along the vertical direction, and In a region where the insulating pattern and the gate structure vertically overlap each other, a vertical distance between a lower surface of a lowermost channel layer among the plurality of channel layers and an upper surface of the protrusion is greater than a vertical distance between the plurality of channel layers.

2. The semiconductor device according to claim 1, in, An uppermost end of each of the back contact structures is at a level lower than a level of a lower surface of the lowermost channel layer.

3. The semiconductor device according to claim 1, in, The level of the uppermost end of each of the back contact structures is higher than the level of the uppermost end of each of the protrusions.

4. The semiconductor device according to claim 1, in, The substrate insulating layer is in contact with the source / drain region, and A level of a surface where the substrate insulating layer and the source / drain regions contact each other is lower than a level of an uppermost end of each of the protrusions.

5. The semiconductor device according to claim 1, in, The source / drain region contacts the substrate insulating layer and the insulating pattern.

6. The semiconductor device according to claim 1, in, A cross section of the protrusion in at least one of the first direction and the second direction has at least one of a dome shape, a mushroom shape, a triangle shape, a square shape, and a trapezoid shape.

7. The semiconductor device according to claim 1, in, The gate structure includes a gate dielectric layer and a gate electrode, and In the area where the gate structure and the multiple channel layers vertically overlap each other, the vertical distance between the lower surface of the lowermost channel layer and the upper surface of the device isolation layer is greater than the vertical distance between the uppermost surface of the gate electrode and the upper surface of the uppermost channel layer among the multiple channel layers.

8. The semiconductor device according to claim 7, in, The back contact structure contacts the gate dielectric layer and is spaced apart from the gate electrode by the gate dielectric layer.

9. The semiconductor device according to claim 1, further comprising: include: An inner spacer layer is disposed between the gate structure and the source / drain region in the first direction.

10. The semiconductor device according to claim 9, in, A side surface of the back contact structure and a side surface of the insulating pattern are in contact with each other, The inner spacer layer is disposed between an upper portion of each of the back contact structures and the protrusion, and The protrusion is spaced apart from an upper portion of each of the back contact structures by the inner spacer layer.

11. The semiconductor device according to claim 1, in, The back contact structure includes a first portion disposed at a level higher than that of a lower surface of the device isolation layer and a second portion disposed at a level lower than that of the lower surface of the device isolation layer, The back contact structure has a bent portion for connecting the first portion and the second portion, and The width of the second portion is greater than the width of the first portion.

12. The semiconductor device according to claim 11, in, The substrate insulating layer covers a lower surface of the device isolation layer and a side surface of the second portion.

13. The semiconductor device according to claim 11, in, A side surface of the bent portion is inclined on the second portion.

14. The semiconductor device according to claim 1, further comprising: include: A backside power structure is disposed below the backside contact structure, connected to the backside contact structure, and configured to apply power to the source / drain regions.

15. The semiconductor device according to claim 14, in, The back side power structure contacts a lower surface of the device isolation layer.

16. A semiconductor device, include: insulating patterns spaced apart from each other in a first direction and in a second direction crossing the first direction; a substrate insulating layer, which is located on a side surface of the insulating pattern in the first direction; a device isolation layer, which is located on a side surface of the insulation pattern in the second direction; a plurality of channel layers, the plurality of channel layers being located on the insulating pattern and spaced apart from each other in a vertical direction perpendicular to an upper surface of the device isolation layer; a gate structure configured to vertically overlap the insulating pattern and surround each of the plurality of channel layers and to extend in the second direction; a source / drain region disposed outside the gate structure; as well as contact structures connected to the source / drain regions, The source / drain region includes a first source / drain region and a second source / drain region, the first source / drain region is configured to vertically overlap with the substrate insulating layer and be disposed on the substrate insulating layer, and the second source / drain region is spaced apart from the first source / drain region in the first direction, The contact structure includes a first contact structure and a second contact structure, the first contact structure is connected to the first source / drain region above the first source / drain region, and the second contact structure is connected to the second source / drain region below the second source / drain region by penetrating the insulating pattern, and The insulating pattern partially penetrates a lower portion of the gate structure.

17. The semiconductor device according to claim 16, in, The insulating pattern is spaced apart from the plurality of channel layers under the plurality of channel layers, and A vertical distance between an upper surface of the insulation pattern and a lower surface of a lowermost channel layer among the plurality of channel layers is greater than a vertical distance between the plurality of channel layers.

18. The semiconductor device according to claim 16, in, The second contact structure does not vertically overlap the first contact structure.

19. The semiconductor device according to claim 16, in, The level of the uppermost end of the second contact structure is higher than that of the uppermost end of the insulation pattern and lower than that of a lower surface of a lowermost channel layer among the plurality of channel layers.

20. A semiconductor device, include: insulating patterns which are spaced apart from each other in one direction; a plurality of channel layers spaced apart from each other on the insulating pattern; a gate structure configured to vertically overlap the insulating patterns and surround the plurality of channel layers, respectively; a source / drain region disposed outside the gate structure; as well as a back contact structure electrically connected to the source / drain region below the source / drain region, wherein the insulating pattern includes a protrusion that partially penetrates the lower portion of the gate structure, and In a region where the insulating pattern and the gate structure vertically overlap each other, a vertical distance between a lower surface of a lowermost channel layer among the plurality of channel layers and an upper surface of the protrusion is greater than a vertical distance between the plurality of channel layers.

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