A super junction semiconductor device and a method for manufacturing the same

Abstract

The present invention discloses a super junction semiconductor device and a manufacturing method, belonging to the field of semiconductor technology. The super junction semiconductor device includes a cell region, a transition region and a terminal region, wherein the transition region is between the cell region and the terminal region, and the cell region, the transition region and the terminal region are provided with a first conductive type semiconductor substrate, a first conductive type buffer layer located above the first conductive type semiconductor substrate, a first conductive type multiple epitaxial layer located above the first conductive type buffer layer, and a second conductive type longitudinal strip region located in the first conductive type epitaxial layer; the second conductive type longitudinal strip region is greater in height in the terminal region and the transition region than in the cell region in the longitudinal direction. The present invention enables the breakdown point to be transferred to the cell region when avalanche breakdown occurs, thereby improving the device E AS Performance, reduce the sensitivity of charge balance in the terminal area to improve device reliability; optimize the reverse withstand voltage characteristics of super junction devices and increase the safe operating area of ​​the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a super junction semiconductor device and a manufacturing method thereof. Background Art

[0002] Power MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) devices are widely used in power systems due to their superior characteristics (unipolarity + gate voltage control + negative temperature coefficient, etc.). Energy loss needs to be controlled during power processing, and the conduction loss requires a lower on-resistance of power MOS devices. As high-power systems have higher requirements for breakdown voltage, the specific on-resistance (R ON，SP ) and breakdown voltage (BV) have a contradictory relationship R ON，SP ∝ BV 2.4-2.6 , that is, the specific on-resistance increases exponentially with the increase of breakdown voltage. Traditional power MOS has a "silicon limit". Super junction power MOS devices use a new voltage-resistant layer structure and use alternating P-type and N-type semiconductor regions to form a charge compensation structure to break through the so-called silicon limit problem in the field of ordinary power MOS devices in the industry, and then achieve a higher breakdown voltage and lower specific on-resistance in the drift region of the N-type semiconductor region with a higher doping concentration.

[0003] Conventional superjunction MOS devices consist of a cell region, a transition region, and a terminal region. As mentioned in the literature (Z. Fan, Z.Chu, J. Luo, G. Cao, and S. Liao, “Study of Reliability in SuperjunctionPower VDMOSFE”), the transition region and the terminal region are more susceptible to the interface positive charge from the surface field oxide layer (the surface positive charge comes from the back-end process and packaging process), and the device withstand voltage characteristics are easily affected by the charge imbalance, which is manifested as the avalanche breakdown point occurring in advance in the transition region and the terminal region, and the surface electric field of the device in the transition region and the terminal region will increase due to the charge imbalance effect, which will lead to walk-out phenomenon and reliability problems. In addition, the reference (K.Takahashi, H. Kuribayashi, T. Kawashima, S. Wakimoto, K. Mochizuki and H.Nakazawa, "20 mΩ∙cm 2660V Super Junction MOSFETs Fabricated by Deep TrenchEtching and Epitaxial Growth7") mentioned that the field oxide layer in the transition region and the terminal region is generally formed by thermal oxidation, which is easy to form an accumulation effect of surface doping concentration during the thermal oxidation process, which will further aggravate the charge imbalance problem in the transition region and the terminal region. Under high voltage and high current applications, it is more beneficial for the application of the device if the breakdown occurs in a large area of ​​active area, while small current devices are more inclined to breakdown in a larger area of ​​non-active area.

[0004] In order to solve this problem, some solutions are proposed in patent CN117012831A (invention name: a power semiconductor device) and literature (R. Wang, M. Qiao, Y. Wang, Z. Li and B. Zhang, "Novel High-Tolerance Termination With Resistive Field Plate for 600 V SuperJunction Vertical Double-Diffused MOSFET"). However, these solutions have problems such as complex process, difficult processing, and leakage of drain series resistance, which will affect the actual manufacturing and application of superjunction semiconductor devices.

[0005] As mentioned in the literature (Tian Bo, Cheng Xu, Kang Baowei, "The Origin and Development of Superjunction Theory and Its Impact on the Design of High-Voltage MOSFET Devices"), conventional superjunction semiconductor devices still have a disadvantage: the body diode has high reverse hardness. This body diode plays a freewheeling role when working in anti-parallel. The transverse alternating P-type and N-type semiconductor PN structure of the superjunction device will cause the minority carriers stored in the body diode in the forward conduction state to be quickly extracted, which results in poor reverse recovery and other characteristics: higher current peak, greater electromagnetic interference and greater power consumption. Summary of the invention

[0006] In view of the above problems, the present invention aims to provide a super junction semiconductor device and a method for manufacturing the same. On the one hand, the present invention is based on a high current application device. In order to transfer the breakdown position to the inside of the cell, the cell region, transition region and terminal region structure of the device are designed so that the longitudinal withstand voltage buffer layer height of the transition region and the terminal region is higher than that of the cell region, so as to improve the breakdown characteristics (obtain a stable avalanche breakdown point), and the high device E ASCharacteristics and reliability. If a small current is used, the same principle can be used with the opposite design direction to achieve the transfer of the breakdown point position. On the other hand, because there is an extra epitaxial layer under the longitudinal voltage-resistant buffer layer of the cell area of ​​the present invention, this epitaxial layer acts as a "semi" super junction structure, which can effectively improve the reverse recovery characteristics of the body diode and further improve the safe working area of ​​the device.

[0007] The specific technical solutions of the present invention are as follows:

[0008] A super junction semiconductor device, comprising:

[0009] Cell region; terminal region, surrounding the cell region.

[0010] The transition region is located between the device cell region and the terminal region.

[0011] The device cell region, transition region and terminal region have a common substrate structure, which includes a drain metal layer, a semiconductor substrate of the first conductivity type located above the drain metal layer, a buffer layer of the first conductivity type located above the semiconductor substrate of the first conductivity type; a first epitaxial layer of the first conductivity type located above the buffer layer of the first conductivity type; and an epitaxial layer of the first conductivity type located above the first epitaxial layer of the first conductivity type, wherein the epitaxial layer of the first conductivity type is formed by multiple epitaxy.

[0012] Definition: The direction from the first conductivity type epitaxial layer to the first conductivity type semiconductor substrate is the longitudinal direction of the device, and the direction from the cell region to the terminal region is the lateral direction of the device.

[0013] In the cell region:

[0014] The first conductive type epitaxial layer is provided with a plurality of longitudinal strip regions of the first conductive type and longitudinal strip regions of the second conductive type which are alternately distributed in the laterally direction; the longitudinal strip regions of the first conductive type are located in the first conductive type epitaxial layer; the longitudinal strip regions of the second conductive type are located in the first conductive type epitaxial layer and above the first conductive type epitaxial layer; the body regions of the second conductive type are located above the longitudinal strip regions of the first conductive type and the longitudinal strip regions of the second conductive type.

[0015] In the transition zone:

[0016] A plurality of longitudinal strip regions of the first conductivity type and the second conductivity type are alternately distributed in the laterally direction, wherein the longitudinal strip regions of the first conductivity type are located in the epitaxial layer of the first conductivity type and the first epitaxial layer of the first conductivity type, and the longitudinal strip regions of the second conductivity type are located in the epitaxial layer of the first conductivity type and the first epitaxial layer of the first conductivity type and are located above the buffer layer of the first conductivity type.

[0017] The second conductive type isolation layer is located on top of the first conductive type longitudinal strip region and the second conductive type longitudinal strip region, and the first conductive type longitudinal strip region and the second conductive type longitudinal strip region are both longitudinally connected to the second conductive type isolation layer.

[0018] The field oxide layer is located above the isolation layer of the second conductivity type.

[0019] In the terminal area:

[0020] A plurality of longitudinal strip regions of the first conductivity type and the second conductivity type are alternately distributed in the laterally direction, wherein the longitudinal strip regions of the first conductivity type are located in the first conductivity type epitaxial layer and the first epitaxial layer of the first conductivity type, and the longitudinal strip regions of the second conductivity type are located in the first conductivity type epitaxial layer and the first epitaxial layer of the first conductivity type and are located above the first conductivity type buffer layer.

[0021] The second conductive type transverse strip region is located above the first conductive type longitudinal strip region and the second conductive type longitudinal strip region, and the left boundary of the second conductive type transverse strip region is connected to the second conductive type isolation layer in the transition region, the lower boundary of the second conductive type transverse strip region is not higher than the lower boundary of the second conductive type isolation layer, and the lower boundary of the second conductive type isolation layer is not higher than the lower boundary of the second conductive type body region.

[0022] A lateral strip region of the first conductivity type is disposed above the lateral strip region of the second conductivity type, and a field oxide layer is disposed above the lateral strip region of the first conductivity type.

[0023] The height of the second conductive type longitudinal strip region in the terminal region and the transition region is greater in the longitudinal direction than that in the cell region.

[0024] As a preferred embodiment, the cell region further comprises:

[0025] The source ohmic contact region of the first conductivity type and the body ohmic contact region of the second conductivity type are located in the body region of the second conductivity type. The source ohmic contact region of the first conductivity type and the body ohmic contact region of the second conductivity type are both connected to the source metal layer.

[0026] A gate structure, comprising a gate oxide layer and a gate polycrystalline structure located above the longitudinal strip regions of the first conductivity type and the body regions of the second conductivity type; an insulating layer located above a plurality of the gate structures and a plurality of source ohmic contact regions of the first conductivity type and body ohmic contact regions of the second conductivity type; and a source-level metal layer penetrating the insulating layer and respectively contacting the source ohmic contact regions of the first conductivity type and the body ohmic contact regions of the second conductivity type or the gate structure.

[0027] As a preferred embodiment, the transition zone further comprises:

[0028] The body region of the second conductivity type is located above the longitudinal strip region of the first conductivity type and the longitudinal strip region of the second conductivity type.

[0029] The source muncontact region of the first conductivity type and the body muncontact region of the second conductivity type are located in the body region of the second conductivity type. The source muncontact region of the first conductivity type and the body muncontact region of the second conductivity type are both connected to the source metal layer.

[0030] The gate structure includes a gate oxide layer and a gate polycrystalline structure located above the longitudinal strip region of the first conductivity type and the field oxide layer; an insulating layer located above the multiple gate structures and the multiple second conductivity type body regions and the field oxide layer; the source-level metal layer penetrates the insulating layer and contacts the source ohmic contact region of the first conductivity type and the body region ohmic contact region of the second conductivity type or the gate structure respectively; the gate structure is partially located above the field oxide layer and acts as a field plate.

[0031] As a preferred embodiment, the terminal area further comprises:

[0032] The second conductive type body region is located on top of the first conductive type lateral strip region.

[0033] The first conductive type source ohmic contact region and the second conductive type body region ohmic contact region are located in the second conductive type body region. The first conductive type source ohmic contact region and the second conductive type body region ohmic contact region are both connected to the source metal layer.

[0034] The insulating layer is located above the first conductive type lateral strip region and the plurality of second conductive type body regions and the field oxide layer; the source level metal layer penetrates the insulating layer and contacts the first conductive type source ohmic contact region and the second conductive type body region ohmic contact region respectively.

[0035] The second conductivity type transverse strip region may not cover the top of all the second conductivity type longitudinal strip regions, that is, the top of the second conductivity type longitudinal strip region in the terminal region may be an epitaxial layer of the first conductivity type.

[0036] As a preferred embodiment, the first conductivity type epitaxial layer is formed by multiple epitaxy, each epitaxial layer has a thickness of 3.0-5.0 μm, and the number of epitaxy is 10-15 times; the first conductivity type first epitaxial layer is located above the first conductivity type buffer layer.

[0037] As a preferred manner, in order to reduce the lateral interdiffusion between the longitudinal strip regions of the first conductivity type and the longitudinal strip regions of the second conductivity type, the first conductivity type ion implantation may be increased after each epitaxial formation of the multiple epitaxial layers.

[0038] As a preferred embodiment, the longitudinal strip region of the second conductivity type in the cell region is located above the first epitaxial layer of the first conductivity type, the thickness of the first epitaxial layer is 3.0-5.0 μm, and the resistivity of the first epitaxial layer is 1.0-5.0 Ω∙cm.

[0039] As a preferred embodiment, the first conductivity type longitudinal strip region in the cell region has the same or different concentration as the first conductivity type epitaxial layer, and / or a first conductivity type JFET injection region is provided on the top of the first conductivity type longitudinal strip region (05).

[0040] As a preferred embodiment, the structure includes an N-type power semiconductor device and its terminal structure and a P-type power semiconductor device and its terminal structure; for the terminal structure of the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type; for the terminal structure of the P-type semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

[0041] The present invention also provides a method for manufacturing a super junction semiconductor device, comprising the following steps:

[0042] Step S1: selecting a semiconductor substrate of a first conductivity type, and epitaxially forming a buffer layer of a first conductivity type on the semiconductor substrate of the first conductivity type.

[0043] Step S2: performing general implantation of first conductivity type ions on the first conductivity type buffer layer, that is, ion implantation without a photomask.

[0044] Step S3: Photolithography and ion implantation are performed in the transition area and the terminal area to form a longitudinal strip area of ​​the second conductivity type (longitudinal voltage-resistant buffer layer); the remaining area in the middle of the transversely alternating longitudinal strip areas of the second conductivity type automatically forms a transversely alternating longitudinal strip area of ​​the first conductivity type, and the doping of the longitudinal strip area of ​​the first conductivity type is composed of a buffer layer of the first conductivity type and general implantation of ions of the first conductivity type.

[0045] Step S4: epitaxially form a first epitaxial layer on the first conductive type buffer layer, and repeat the steps of first conductive type ion general implantation, photolithography and ion implantation to form second conductive type longitudinal strip regions in the cell region, transition region and terminal region, thereby forming laterally alternatingly distributed second conductive type longitudinal strip regions and laterally alternatingly distributed first conductive type longitudinal strip regions.

[0046] Step S5: Repeat the steps of epitaxy, first conductivity type ion implantation, photolithography and ion implantation to form a second conductivity type longitudinal strip region in the cell region, transition region and terminal region to form n-2 epitaxial layers and patterns on the epitaxial layers.

[0047] Step S6: n-1 times of epitaxy are fabricated, and then the first conductive type ion general implantation is performed, and the second conductive type longitudinal strip regions and the first conductive type longitudinal strip regions are formed by photolithography and ion implantation in a transversely alternating manner. The morphology of the photoresist in the terminal region (including the window size and spacing) can be flexibly adjusted according to the doping concentration distribution of the transverse strip regions of the second conductive type formed subsequently.

[0048] Step S7: manufacture n epitaxy, that is, the last epitaxy, and then perform general ion implantation of the first conductivity type; the last epitaxial layer and the general ion implantation of the first conductivity type together form a lateral strip region of the first conductivity type; then photolithography and ion implantation form an isolation layer of the second conductivity type.

[0049] Step S8: Form a field oxide layer region by oxidation, photolithography and etching steps; oxidation can be formed by deposition or thermal oxidation. After the field oxide layer is formed, high temperature furnace tube annealing and push-up procedures are performed to activate ion implantation; by pushing-up the implantation layer, the second conductive type longitudinal strip regions are connected to each other in the longitudinal direction, and the second conductive type transverse strip regions are connected to each other in the transverse direction.

[0050] Step S9: forming a gate structure, including a gate oxide layer and a polycrystalline structure on the gate oxide layer, and then performing an injection and push-in process of a second conductivity type body region, and then photolithography and injection to form a first conductivity type source ohmic contact region and a second conductivity type body region ohmic contact region, and then deposition to form an insulating layer; the insulating layer may be a silicon dioxide or silicon nitride layer insulating material.

[0051] Step S10: A source metal layer is formed on the surface of the device through etching of metal holes, aluminum deposition, photolithography and etching steps; then the semiconductor substrate is thinned so that the thickness of the semiconductor substrate reaches 200-300um, and then a drain metal layer is formed on the back of the semiconductor substrate, thereby finally forming a complete device structure.

[0052] Compared with the prior art, the present invention has the following beneficial technical effects:

[0053] 1) Based on the optimization of breakdown voltage and specific on-resistance of super junction devices as switching devices, the present invention designs the cell region, transition region and terminal region structures of the device. In the cell region, the longitudinal strip region of the second conductivity type is located in the epitaxial layer of the first conductivity type and above the first epitaxial layer of the first conductivity type; in the transition region and the terminal region, the longitudinal strip region of the second conductivity type is located in the epitaxial layer of the first conductivity type and above the buffer layer of the first conductivity type; so that the height of the longitudinal strip region of the second conductivity type in the terminal region and the transition region is larger in the longitudinal direction than that in the cell region, and the longitudinal withstand voltage buffer layer height in the transition region and the terminal region is higher than that in the cell region, so that the avalanche breakdown point stably occurs in the cell region, and then the avalanche current is completely discharged through the large area of ​​the cell region, which not only overcomes the charge balance sensitivity of the terminal region of the device and the problem of voltage resistance reduction and reliability caused by easy breakdown in the transition region and the terminal region, but also improves the EAS performance and robustness of the device.

[0054] 2) An additional epitaxial layer is provided below the longitudinal voltage-resistant buffer layer in the cell region of the present invention. This epitaxial layer acts as a "semi" super junction structure, which can effectively improve the reverse recovery characteristics of the body diode and further improve the forward bias safe operating area (FBSOA) of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0056] Figure 1 This is a schematic diagram of the basic structure of a super junction semiconductor device according to Example 1 of the present invention.

[0057] Figure 2A This is a schematic diagram of a variant structure of a super junction semiconductor device according to Embodiment 1 of the present invention.

[0058] Figure 2B Schematic diagram of another variant structure of the super junction semiconductor device according to the first embodiment of the present invention.

[0059] Figure 3 Schematic diagram of simulation results of Example 1 of the present invention. FIG. 4A to FIG. 4J The cross-sectional views at different stages of a method for manufacturing a super junction device according to an embodiment of the present application are shown.

[0060] Markings in the figure are as follows: 100 is a cell region, 200 is a transition region, 300 is a terminal region, 01 is a semiconductor substrate of the first conductivity type, 02 is a buffer layer of the first conductivity type, 03 is an epitaxial layer of the first conductivity type, 031 is a first epitaxial layer of the first conductivity type, 04 is a longitudinal strip region of the second conductivity type, 05 is a longitudinal strip region of the first conductivity type, 06 is a transverse strip region of the second conductivity type, 07 is a transverse strip region of the first conductivity type, 08 is an isolation layer of the second conductivity type, 09 is a field oxide layer, 10 is a gate structure, 11 is a body region of the second conductivity type, 12A is a source ohmic contact region of the first conductivity type, 12B is a body region ohmic contact region of the second conductivity type, 13 is an insulating layer, 14 is a source metal layer, and 15 is a drain metal layer. DETAILED DESCRIPTION

[0061] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, a semiconductor structure obtained after several steps can be described in one figure. It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "above" or "above" another layer or another region, it can refer to being directly above another layer or another region, or containing other layers or regions between it and another layer or another region. In addition, if the device is turned over, the layer or a region will be "below" or "below" another layer or another region. If it is to describe the situation of being directly above another layer or another region, the expression "directly above..." or "above and adjacent to..." will be adopted herein.

[0063] The present invention may be embodied in various forms, some embodiments of which will be described below.

[0064] Example 1

[0065] As a preferred embodiment of the present invention, the present invention discloses a super junction semiconductor device structure, referring to Figure 1 1 is a schematic cross-sectional view of a super junction semiconductor device according to an embodiment of the present invention, wherein the super junction semiconductor device structure comprises:

[0066] Cell area 100;

[0067] A terminal region 300, surrounding the cell region 100;

[0068] The transition region 200 is located between the device cell region 100 and the terminal region 300 .

[0069] The device cell region 100, transition region 200 and terminal region 300 have a common substrate structure, which includes a drain metal layer 15, a semiconductor substrate 01 of the first conductivity type located above the drain metal layer 15, a buffer layer 02 of the first conductivity type located above the semiconductor substrate of the first conductivity type; a first epitaxial layer 031 of the first conductivity type located above the buffer layer 02 of the first conductivity type; and an epitaxial layer 03 of the first conductivity type located above the first epitaxial layer 031 of the first conductivity type, wherein the epitaxial layer 03 of the first conductivity type is formed by multiple epitaxy.

[0070] Definition: The direction from the first conductivity type epitaxial layer 03 to the first conductivity type semiconductor substrate 01 is the longitudinal direction of the device, and the direction from the cell region 100 to the terminal region 300 is the lateral direction of the device.

[0071] In the cell area 100:

[0072] The first conductive type epitaxial layer 03 is provided with a plurality of first conductive type longitudinal strip regions 05 and second conductive type longitudinal strip regions 04 which are alternately distributed in the laterally direction; the first conductive type longitudinal strip regions 05 are located in the first conductive type epitaxial layer 03; the second conductive type longitudinal strip regions 04 are located in the first conductive type epitaxial layer 03 and above the first conductive type first epitaxial layer 031; the second conductive type body region 11 is located above the first conductive type longitudinal strip regions 05 and the second conductive type longitudinal strip regions 04.

[0073] The second conductive type longitudinal strip region 04 functions as a longitudinal voltage-resistant buffer layer.

[0074] In the transition zone 200:

[0075] A plurality of longitudinal strip regions 05 of the first conductivity type and longitudinal strip regions 04 of the second conductivity type are alternately distributed in the laterally direction, wherein the longitudinal strip regions 05 of the first conductivity type are located in the epitaxial layer 03 of the first conductivity type and the first epitaxial layer 031 of the first conductivity type, and the longitudinal strip regions 04 of the second conductivity type are located in the epitaxial layer 03 of the first conductivity type and the first epitaxial layer 031 of the first conductivity type and above the buffer layer 02 of the first conductivity type.

[0076] The second conductive type isolation layer 08 is located on top of the first conductive type longitudinal strip region 05 and the second conductive type longitudinal strip region 04, and the first conductive type longitudinal strip region 05 and the second conductive type longitudinal strip region 04 are both longitudinally connected to the second conductive type isolation layer 08.

[0077] The field oxide layer 09 is located above the isolation layer 08 of the second conductivity type.

[0078] In the terminal area 300:

[0079] A plurality of longitudinal strip regions 05 of the first conductivity type and longitudinal strip regions 04 of the second conductivity type are alternately distributed in the laterally direction, wherein the longitudinal strip regions 05 of the first conductivity type are located in the first conductivity type epitaxial layer 03 and the first conductivity type first epitaxial layer 031, and the longitudinal strip regions 04 of the second conductivity type are located in the first conductivity type epitaxial layer 03 and the first conductivity type first epitaxial layer 031 and above the first conductivity type buffer layer 02.

[0080] The second conductive type transverse strip region 06 is located above the first conductive type longitudinal strip region 05 and the second conductive type longitudinal strip region 04, and the left boundary of the second conductive type transverse strip region 06 is connected to the second conductive type isolation layer 08 in the transition region 200, the lower boundary of the second conductive type transverse strip region 06 is not higher than the lower boundary of the second conductive type isolation layer 08, and the lower boundary of the second conductive type isolation layer 08 is not higher than the lower boundary of the second conductive type body region 11.

[0081] A lateral strip region 07 of the first conductivity type is disposed above the lateral strip region 06 of the second conductivity type, and a field oxide layer 09 is disposed above the lateral strip region 07 of the first conductivity type.

[0082] Since in the cell region 100, the second conductive type longitudinal strip region 04 is located in the first conductive type epitaxial layer 03 and above the first conductive type first epitaxial layer 031; in the transition region 200 and the terminal region 300, the second conductive type longitudinal strip region 04 is located in the first conductive type epitaxial layer 03 and the first conductive type first epitaxial layer 031 and above the first conductive type buffer layer 02; so that the height of the second conductive type longitudinal strip region 04 in the terminal region 300 and the transition region 200 is higher than that in the cell region 100 in the longitudinal direction. Through this design, the avalanche breakdown point can be stably generated in the cell area, so that the avalanche current can be completely discharged through the large-area cell area. This not only overcomes the charge balance sensitivity in the terminal area of ​​the device and the problem of voltage reduction and reliability caused by breakdown in the transition area and the terminal area, but also improves the EAS performance and robustness of the device. Moreover, an epitaxial layer is added under the longitudinal voltage-withstand buffer layer in the cell area. This epitaxial layer acts as a "semi" super junction structure, which can effectively improve the reverse recovery characteristics of the body diode and further improve the forward-biased safe operating area (FBSOA) of the device.

[0083] As a preferred embodiment, the cell region further comprises:

[0084] The first conductivity type source ohmic contact region 12A and the second conductivity type body region ohmic contact region 12B are located in the second conductivity type body region 11. The first conductivity type source ohmic contact region 12A and the second conductivity type body region ohmic contact region 12B are both connected to the source metal layer 14.

[0085] The gate structure 10 includes a gate oxide layer and a gate polycrystalline structure located above the longitudinal strip region 05 of the first conductivity type and the body region 11 of the second conductivity type; the insulating layer 13 is located above multiple gate structures 10 and multiple source ohmic contact regions 12A of the first conductivity type and body ohmic contact regions 12B of the second conductivity type; the source-level metal layer 14 penetrates the insulating layer 13 and contacts the source ohmic contact regions 12A of the first conductivity type and the body ohmic contact regions 12B of the second conductivity type or the gate structure respectively.

[0086] As a preferred embodiment, the cell region further comprises:

[0087] The second conductivity type body region ohmic contact region 12B is located in the second conductivity type body region 11 . The second conductivity type body region ohmic contact region 12B is connected to the source metal layer 14 .

[0088] The gate structure 10 includes a gate oxide layer and a gate polycrystalline structure located above the longitudinal strip region 05 of the first conductivity type and the body region 11 of the second conductivity type; the insulating layer 13 is located above multiple gate structures 10 and multiple body region ohmic contact regions 12B of the second conductivity type; the source-level metal layer 14 penetrates the insulating layer 13 and contacts the body region ohmic contact regions 12B of the second conductivity type or the gate structure respectively.

[0089] As a preferred embodiment, the transition zone further comprises:

[0090] The second conductivity type body region 11 is located above the first conductivity type longitudinal strip region 05 and the second conductivity type longitudinal strip region 04 .

[0091] The first conductivity type source 12A and the second conductivity type body 12B are located in the second conductivity type body 11. Both the first conductivity type source 12A and the second conductivity type body 12B are connected to the source metal layer 14.

[0092] The gate structure 10 includes a gate oxide layer and a gate polycrystalline structure located above the longitudinal strip region 05 of the first conductivity type and the field oxide layer 09; the insulating layer 13 is located above the multiple gate structures 10 and the multiple body regions 11 of the second conductivity type and the field oxide layer 09; the source-level metal layer 14 penetrates the insulating layer and contacts the source ohmic contact region 12A of the first conductivity type and the body region ohmic contact region 12B of the second conductivity type or the gate structure respectively; the gate structure 10 is partially located above the field oxide layer 09 and acts as a field plate.

[0093] As a preferred embodiment, the transition zone further comprises:

[0094] The second conductivity type body region 11 is located above the first conductivity type longitudinal strip region 05 and the second conductivity type longitudinal strip region 04 .

[0095] The second conductivity type body region contact region 12B is located in the second conductivity type body region 11. The second conductivity type body region contact region 12B is connected to the source metal layer 14.

[0096] The gate structure 10 includes a gate oxide layer and a gate polycrystalline structure located above the longitudinal strip region 05 of the first conductivity type and the field oxide layer 09; the insulating layer 13 is located above the multiple gate structures 10 and the multiple second conductivity type body regions 11 and the field oxide layer 09; the source-level metal layer 14 penetrates the insulating layer and contacts the second conductivity type body region ohmic contact region 12B or the gate structure respectively; the gate structure 10 is partially located above the field oxide layer 09 and acts as a field plate.

[0097] As a preferred embodiment, the terminal area further comprises:

[0098] The second conductive type body region 11 is located on the top of the first conductive type lateral strip region 07;

[0099] The first conductivity type source ohmic contact region 12A and the second conductivity type body region ohmic contact region 12B are located in the second conductivity type body region 11. The first conductivity type source ohmic contact region 12A and the second conductivity type body region ohmic contact region 12B are both connected to the source metal layer 14.

[0100] The insulating layer 13 is located above the first conductive type lateral strip region 07 and the plurality of second conductive type body regions 11 and the field oxide layer 09; the source level metal layer 14 penetrates the insulating layer 13 and contacts the first conductive type source ohmic contact region 12A and the second conductive type body region ohmic contact region 12B respectively.

[0101] The second conductive type transverse strip region 06 may not cover the top of all the second conductive type longitudinal strip regions 04, that is, the top of the second conductive type longitudinal strip region 04 in the terminal region may be the first conductive type epitaxial layer 03, such as Figure 2A shown.

[0102] As a preferred embodiment, the terminal area further comprises:

[0103] The second conductive type body region 11 is located on the top of the first conductive type lateral strip region 07;

[0104] The first conductivity type source ohmic contact region 12A and the second conductivity type body region ohmic contact region 12B are located in the second conductivity type body region 11. The first conductivity type source ohmic contact region 12A and the second conductivity type body region ohmic contact region 12B are both connected to the source metal layer 14.

[0105] The gate structure 10 includes a gate oxide layer and a gate polycrystalline structure located above the longitudinal strip region 05 of the first conductivity type and the field oxide layer 09 .

[0106] The insulating layer 13 is located above the first conductive type lateral strip region 07 and the plurality of second conductive type body regions 11 and the field oxide layer 09; the source level metal layer 14 penetrates the insulating layer 13 and contacts the first conductive type source ohmic contact region 12A and the second conductive type body region ohmic contact region 12B or the gate structure respectively.

[0107] The second conductivity type transverse strip region 06 may not cover the top of all the second conductivity type longitudinal strip regions 04 , that is, the top of the second conductivity type longitudinal strip region 04 in the terminal region may be the first conductivity type epitaxial layer 03 .

[0108] As a preferred method,

[0109] In the transition region 200, the isolation layer 08 of the second conductivity type may also be removed, and the left boundary of the lateral strip region 06 of the second conductivity type is connected to the body region 11 of the second conductivity type in the transition region 200, as shown in FIG. Figure 2B As shown, the lower boundary of the second conductivity type lateral strip region 06 is not higher than the lower boundary of the second conductivity type body region 11.

[0110] As a preferred method,

[0111] The first conductivity type epitaxial layer 03 is formed by multiple epitaxy, each epitaxial layer has a thickness of 3.0-5.0 μm, and the number of epitaxy is 10-15 times; the first conductivity type first epitaxial layer 031 is located above the first conductivity type buffer layer 02.

[0112] As a preferred method,

[0113] In order to reduce the lateral interdiffusion between the longitudinal strip regions 05 of the first conductivity type and the longitudinal strip regions 04 of the second conductivity type, the first conductivity type ion implantation may be increased after each epitaxial formation of the multiple epitaxial layers.

[0114] As a preferred method,

[0115] The second conductivity type longitudinal strip region 04 in the cell region 100 is located above the first conductivity type first epitaxial layer 031 , the first epitaxial layer has a thickness of 3.0-5.0 μm, and a resistivity of 1.0-5.0 Ω∙cm.

[0116] As a preferred method,

[0117] In the super junction semiconductor device, the first conductivity type longitudinal strip region 05 in the cell region 100 has the same or different concentration as the first conductivity type epitaxial layer 03, and / or a first conductivity type JFET injection region is provided on the top of the first conductivity type longitudinal strip region 05.

[0118] As a preferred method,

[0119] The super junction semiconductor device is characterized in that: the structure includes an N-type super junction semiconductor device and its terminal structure and a P-type super junction semiconductor device and its terminal structure; for the terminal structure of the N-type super junction semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type; for the terminal structure of the P-type semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

[0120] As a preferred method,

[0121] The super junction semiconductor device, wherein the semiconductor material used for the semiconductor drift region includes silicon, germanium, silicon carbide or gallium arsenide; and the insulating material used for the gate structure includes silicon dioxide or high-K dielectric.

[0122] The working principle and technical effect of this embodiment are as follows: by designing the structure of the cell region, transition region and terminal region of the device, the height of the longitudinal withstand voltage buffer layer in the transition region and the terminal region is higher than that in the cell region, so that the avalanche breakdown point occurs stably in the cell region, and then the avalanche current is completely discharged through the large-area cell region, which not only overcomes the charge balance sensitivity of the device terminal region and the problem of voltage resistance reduction and reliability caused by breakdown in the transition region and the terminal region, but also improves the E AS performance and robustness; and an additional epitaxial layer 031 is provided below the longitudinal voltage-resistant buffer layer in the cell region of the present invention, and this epitaxial layer acts as a "semi" super junction structure, which can effectively improve the reverse recovery characteristics of the body diode and further improve the forward bias safe operating area (FBSOA) of the device.

[0123] See also Figure 3 It is a simulation schematic diagram of the structure of the present invention, such as Figure 3 As shown: since the height of the longitudinal voltage-resistant buffer layer in the cell region of the device of the present invention is smaller than that in other regions, the boundary of the voltage-resistant depletion layer is spread around the longitudinal voltage-resistant buffer layer, so that the voltage resistance of the cell region is lower than that of other regions, thereby making the avalanche breakdown point stably occur in the cell region.

[0124] Example 2

[0125] FIG. 4A to FIG. 4J A schematic diagram showing different stages of a method for manufacturing a super junction semiconductor device according to Embodiment 1 of the present invention is shown. The method for manufacturing a super junction semiconductor device is used to prepare the super junction semiconductor device, and comprises the following steps:

[0126] Step S1: Reference Figure 4A , a semiconductor substrate 01 of a first conductivity type is selected, and a buffer layer of a first conductivity type is epitaxially formed on the semiconductor substrate 01 of the first conductivity type.

[0127] Step S2: Reference Figure 4B , first conductivity type ion general implantation is performed on the first conductivity type buffer layer 02, and the first conductivity type ion general implantation is performed without a photomask.

[0128] Step S3: Reference Figure 4C , photolithography and ion implantation are performed in the transition region and the terminal region to form a second conductive type longitudinal strip region (longitudinal voltage-resistant buffer layer); the remaining area in the middle of the transversely alternatingly distributed second conductive type longitudinal strip regions 040 automatically forms a transversely alternatingly distributed first conductive type longitudinal strip region 050, and the doping of the first conductive type longitudinal strip region is composed of a first conductive type buffer layer and a first conductive type ion general implantation, the purpose of which is to reduce the on-resistance of the super junction device and reduce the lateral diffusion of the second conductive type longitudinal strip region.

[0129] Step S4: Reference Figure 4D , epitaxially forming a first epitaxial layer 031 on the first conductive type buffer layer 02, and then repeating Figure 4B and Figure 4C The steps of first conductive type ion implantation, photolithography and ion implantation are performed to form second conductive type longitudinal strip regions in the cell region, transition region and terminal region to form transversely alternatingly distributed second conductive type longitudinal strip regions 041 and transversely alternatingly distributed first conductive type longitudinal strip regions 051.

[0130] Step S5: Reference Figure 4E Repeat the steps of epitaxy, first conductive type ion implantation, photolithography and ion implantation in the cell region, transition region and terminal region to form multiple (n-2) epitaxial layers and patterns on the epitaxial layers.

[0131] Step S6: Reference Figure 4F , n-1 times of epitaxy are formed, and then the first conductive type ions are implanted, and then photolithography and ion implantation are performed to form the second conductive type longitudinal strip regions 04n-1 and the first conductive type longitudinal strip regions 05n-1. The morphology of the photoresist in the terminal region (including the window size and spacing) can be flexibly adjusted according to the doping concentration distribution of the second conductive type transverse strip region 06 formed later.

[0132] Step S7: Reference Figure 4G, manufacturing forms n times of epitaxy (that is, the last epitaxy), and then the first conductivity type ion general implantation is performed; the first conductivity type lateral strip region 07 is composed of the epitaxial layer 03n and the first conductivity type ion general implantation; then photolithography and ion implantation form the second conductivity type isolation layer 08.

[0133] Step S8: Reference Figure 4H , a field oxide layer region 09 is formed by oxidation, photolithography and etching; oxidation can be formed by deposition or thermal oxidation. After the field oxide layer is formed, a high temperature furnace tube annealing and a push-in process are performed to activate the previous ion implantation; by pushing the implantation layer, the second conductive type longitudinal strip regions 04 are connected to each other in the longitudinal direction, and the second conductive type transverse strip regions 06 are connected to each other in the transverse direction.

[0134] Step S9: Reference Fig. 4I , forming a gate structure 10, including a gate oxide layer and a polycrystalline structure on the gate oxide layer, and then completing the injection and push-in process of the second conductivity type body region 11, and then photolithography and injection to form a first conductivity type source ohmic contact region 12A and a second conductivity type body region ohmic contact region 12B, and then deposition to form an insulating layer 13; the insulating layer can be a silicon dioxide or silicon nitride layer insulating material.

[0135] The gate structure is formed by conventional techniques in the art, such as forming a gate oxide layer by thermal oxidation, polycrystalline deposition on the gate oxide layer, photolithography and etching of the polycrystalline, and finally forming a complete gate structure.

[0136] Step S10: Reference Figure 4J , a source metal layer 14 is formed on the surface of the device through steps such as etching of metal holes, aluminum deposition, photolithography and etching; then the semiconductor substrate is thinned so that the thickness of the semiconductor substrate 01 reaches 200-300um, and then a drain metal layer 15 is deposited on the back of the semiconductor substrate, thereby finally forming a complete device structure.

[0137] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A super junction semiconductor device, characterized in that: include Cell area (100); A terminal region (300) surrounding the cellular region (100); A transition region (200), wherein the transition region (200) is located between the device cell region (100) and the terminal region (300); The device cell region (100), transition region (200) and terminal region (300) have a common substrate structure, the substrate structure comprising a drain metal layer (15), a semiconductor substrate (01) of the first conductivity type located above the drain metal layer (15), a buffer layer (02) of the first conductivity type located above the semiconductor substrate of the first conductivity type; a first epitaxial layer (031) of the first conductivity type located above the buffer layer (02) of the first conductivity type; and an epitaxial layer (03) of the first conductivity type located above the first epitaxial layer (031) of the first conductivity type, wherein the epitaxial layer (03) of the first conductivity type is formed by multiple epitaxy processes; In the cell region (100): A plurality of first conductivity type longitudinal strip regions (05) and second conductivity type longitudinal strip regions (04) are arranged in the epitaxial layer (03) of the first conductivity type and are alternately distributed in the transverse direction; the first conductivity type longitudinal strip regions (05) are located in the epitaxial layer (03) of the first conductivity type; the second conductivity type longitudinal strip regions (04) are located in the epitaxial layer (03) of the first conductivity type and are located above the first epitaxial layer (031) of the first conductivity type; and the second conductivity type body region (11) is located above the first conductivity type longitudinal strip regions (05) and the second conductivity type longitudinal strip regions (04); In the transition zone (200): A plurality of longitudinal strip regions (05) of the first conductivity type and longitudinal strip regions (04) of the second conductivity type that are alternately distributed in the transverse direction, wherein the longitudinal strip regions (05) of the first conductivity type are located in the epitaxial layer (03) of the first conductivity type and the first epitaxial layer (031) of the first conductivity type, and the longitudinal strip regions (04) of the second conductivity type are located in the epitaxial layer (03) of the first conductivity type and the first epitaxial layer (031) of the first conductivity type and are located above the buffer layer (02) of the first conductivity type; The isolation layer (08) of the second conductivity type is located on top of the longitudinal strip region (05) of the first conductivity type and the longitudinal strip region (04) of the second conductivity type, and the longitudinal strip region (05) of the first conductivity type and the longitudinal strip region (04) of the second conductivity type are both connected to the isolation layer (08) of the second conductivity type in the longitudinal direction; The field oxide layer (09) is located above the isolation layer (08) of the second conductivity type; In the terminal area (300): A plurality of longitudinal strip regions (05) of the first conductivity type and longitudinal strip regions (04) of the second conductivity type that are alternately distributed in the transverse direction, wherein the longitudinal strip regions (05) of the first conductivity type are located in the epitaxial layer (03) of the first conductivity type and the first epitaxial layer (031) of the first conductivity type, and the longitudinal strip regions (04) of the second conductivity type are located in the epitaxial layer (03) of the first conductivity type and the first epitaxial layer (031) of the first conductivity type and are located above the buffer layer (02) of the first conductivity type; The second conductive type transverse strip region (06) is located above the first conductive type longitudinal strip region (05) and the second conductive type longitudinal strip region (04), and the left edge of the second conductive type transverse strip region (06) is connected to the second conductive type isolation layer (08) in the transition region (200), the lower edge of the second conductive type transverse strip region (06) is not higher than the lower edge of the second conductive type isolation layer (08), and the lower edge of the second conductive type isolation layer (08) is not higher than the lower edge of the second conductive type body region (11); A lateral strip region (07) of the first conductivity type is provided above the lateral strip region (06) of the second conductivity type, and a field oxide layer (09) is provided above the lateral strip region (07) of the first conductivity type; The height of the second conductive type longitudinal strip region (04) in the terminal region (300) and the transition region (200) is greater in the longitudinal direction than that in the cell region (100).

2. The super junction semiconductor device according to claim 1, characterized in that: The cell region also includes: A source ohmic contact region (12A) of a first conductivity type and a body region ohmic contact region (12B) of a second conductivity type are located in a body region (11) of the second conductivity type; the source ohmic contact region (12A) of the first conductivity type and the body region ohmic contact region (12B) of the second conductivity type are both connected to a source metal layer (14); A gate structure (10) comprising a gate oxide layer and a gate polycrystalline structure located above a longitudinal strip region (05) of the first conductivity type and a body region (11) of the second conductivity type; an insulating layer (13) located above a plurality of the gate structures (10) and a plurality of source ohmic contact regions (12A) of the first conductivity type and body region ohmic contact regions (12B) of the second conductivity type; and a source metal layer (14) penetrating the insulating layer (13) and respectively contacting the source ohmic contact regions (12A) of the first conductivity type and the body region ohmic contact regions (12B) of the second conductivity type or the gate structure.

3. The super junction semiconductor device according to claim 1, characterized in that: The transition zone also includes: The second conductive type body region (11) is located above the first conductive type longitudinal strip region (05) and the second conductive type longitudinal strip region (04); A source ohm contact region (12A) of a first conductivity type and a body ohm contact region (12B) of a second conductivity type are located in the body region (11) of the second conductivity type; the source ohm contact region (12A) of the first conductivity type and the body ohm contact region (12B) of the second conductivity type are both connected to the source metal layer (14); A gate structure (10) comprising a gate oxide layer and a gate polycrystalline structure located above the longitudinal strip region (05) of the first conductivity type and the field oxide layer (09); an insulating layer (13) located above the multiple gate structures (10) and the multiple body regions (11) of the second conductivity type and the field oxide layer (09); the source metal layer (14) penetrates the insulating layer and is in contact with the source ohmic contact region (12A) of the first conductivity type and the body region ohmic contact region (12B) of the second conductivity type or the gate structure respectively; the gate structure (10) is partially located above the field oxide layer (09) and acts as a field plate.

4. The super junction semiconductor device according to claim 1, characterized in that: The terminal area also includes: The second conductive type body region (11) is located on top of the first conductive type lateral strip region (07); A first conductivity type source ohmic contact region (12A) and a second conductivity type body region ohmic contact region (12B), located in the second conductivity type body region (11); the first conductivity type source ohmic contact region (12A) and the second conductivity type body region ohmic contact region (12B) are both connected to the source metal layer (14); an insulating layer (13) located above the first conductive type lateral strip region (07) and the plurality of second conductive type body regions (11) and the field oxide layer (09); the source metal layer (14) penetrates the insulating layer (13) and is in contact with the first conductive type source ohmic contact region (12A) and the second conductive type body region ohmic contact region (12B), respectively; The second conductivity type transverse strip region (06) may not cover the top of all the second conductivity type longitudinal strip regions (04), that is, the top of the second conductivity type longitudinal strip region (04) in the terminal region may be the first conductivity type epitaxial layer (03).

5. The super junction semiconductor device according to claim 1, characterized in that: The first conductivity type epitaxial layer (03) is formed by multiple epitaxy processes, the thickness of each epitaxial layer is 3.0-5.0 μm, and the number of epitaxy processes is 10-15 times; the first conductivity type first epitaxial layer (031) is located above the first conductivity type buffer layer (02).

6. The super junction semiconductor device according to claim 1, characterized in that: In order to reduce the lateral mutual diffusion between the longitudinal strip regions (05) of the first conductivity type and the longitudinal strip regions (04) of the second conductivity type, the first conductivity type ion general implantation may be added after each epitaxial formation of the multiple epitaxial layers.

7. The super junction semiconductor device according to claim 1, characterized in that: The second conductivity type longitudinal strip region (04) in the cell region (100) is located above a first epitaxial layer (031) of the first conductivity type, the first epitaxial layer has a thickness of 3.0-5.0 μm, and a resistivity of 1.0-5.0 Ω∙cm.

8. The super junction semiconductor device according to claim 1, characterized in that: The first conductivity type longitudinal strip region (05) in the cell region (100) has the same or different concentration as the first conductivity type epitaxial layer (03), and / or a first conductivity type JFET injection region is provided on the top of the first conductivity type longitudinal strip region (05).

9. The super junction semiconductor device according to claim 1, characterized in that: The structure includes an N-type power semiconductor device and its terminal structure and a P-type power semiconductor device and its terminal structure; for the terminal structure of the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type; for the terminal structure of the P-type semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

10. A method for manufacturing a super junction semiconductor device, characterized in that: The method for preparing the super junction semiconductor device according to any one of claims 1 to 9 comprises the following steps: Step S1: selecting a semiconductor substrate (01) of a first conductivity type, and epitaxially forming a buffer layer (02) of a first conductivity type on the semiconductor substrate (01) of the first conductivity type; Step S2: performing a first conductivity type ion implantation on the first conductivity type buffer layer (02); Step S3: forming a second conductive type longitudinal strip region by photolithography and ion implantation in the transition region and the terminal region; the remaining area in the middle of the transversely alternately distributed second conductive type longitudinal strip regions (040) automatically forms a transversely alternately distributed first conductive type longitudinal strip region (050), wherein the doping of the first conductive type longitudinal strip region is formed by a first conductive type buffer layer and first conductive type ion implantation; Step S4: epitaxially forming a first epitaxial layer (031) on the buffer layer of the first conductivity type, and repeatedly performing the steps of first conductivity type ion general implantation, photolithography and ion implantation to form a second conductivity type longitudinal strip region in the cell region, transition region and terminal region, so as to form a transversely alternating distribution of the second conductivity type longitudinal strip region (041) and a transversely alternating distribution of the first conductivity type longitudinal strip region (051); Step S5: Repeat the steps of epitaxy, first conductivity type ion implantation, photolithography and ion implantation to form a second conductivity type longitudinal strip region in the cell region, transition region and terminal region to form n-2 epitaxial layers and patterns on the epitaxial layers; Step S6: manufacturing n-1 times of epitaxy, and then performing general implantation of first conductive type ions, photolithography and ion implantation to form transversely alternatingly distributed second conductive type longitudinal strip regions (04n-1) and transversely alternatingly distributed first conductive type longitudinal strip regions (05n-1); wherein the window size and spacing of the photoresist in the terminal region can be flexibly adjusted according to the doping concentration distribution of the transverse strip regions (06) of the second conductive type to be formed subsequently; Step S7: forming n epitaxy, i.e., the last epitaxy, and then performing general ion implantation of the first conductive type; the last epitaxial layer (03n) and the general ion implantation of the first conductive type together form a first conductive type lateral strip region (07); and then photolithography and ion implantation form a second conductive type isolation layer (08); Step S8: forming a field oxide layer region (09) by oxidation, photolithography and etching steps; after the field oxide layer is formed, performing high temperature furnace tube annealing and push-up procedures to activate ion implantation; by pushing-up the implantation layer, the second conductive type longitudinal strip regions (04) are connected to each other in the longitudinal direction, and the second conductive type transverse strip regions (06) are connected to each other in the transverse direction; Step S9: forming a gate structure (10) including a gate oxide layer and a polycrystalline structure on the gate oxide layer, then performing an implantation and a push-in process on a body region (11) of a second conductivity type, then performing photolithography and implantation to form a source ohmic contact region (12A) of a first conductivity type and a body region ohmic contact region (12B) of a second conductivity type, and then depositing to form an insulating layer (13); the insulating layer is a silicon dioxide or silicon nitride insulating material; Step S10: A source metal layer (14) is formed on the surface of the device by etching the metal hole, aluminum deposition, photolithography and etching; then the semiconductor substrate is thinned so that the thickness of the semiconductor substrate (01) reaches 200-300 um, and then a drain metal layer (15) is deposited on the back of the semiconductor substrate, thereby finally forming a complete device structure.

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