Asynchronous successive approximation register capable of resisting single event upset

Abstract

The invention discloses an asynchronous successive approximation register capable of resisting single event upset, relates to the technical field of analog integrated circuits, and is used for solving the reliability problem that single event upset cannot be resisted in the prior art. Comprising a chain structure composed of upper and lower rows of TSPC type D triggers; the TSPC type D trigger resists single event upset and has resetting and setting functions; the TSPC type D flip-flop comprises a first-stage anti-phase logic circuit, a second-stage anti-phase logic circuit, a third-stage anti-phase logic circuit, an anti-SEU asynchronous reset structure and an anti-SEU asynchronous setting structure; the input end of the anti-SEU asynchronous reset structure is connected with an input reset signal; the input end of the anti-SEU asynchronous setting structure is connected with an input setting signal. According to the method, large-area error upset of the SAR logic is avoided, the reliability problem that the existing SAR logic cannot resist single event upset is solved, and the anti-interference capability of the SAR logic in a high-radiation environment is improved.

Description

Technical Field

[0001] The invention relates to the technical field of analog integrated circuits, and in particular to an asynchronous successive approximation register capable of resisting single particle upset. Background Art

[0002] Successive approximation register analog-to-digital converter (SAR ADC) has a wide range of application prospects in spacecraft and aerospace applications, and can provide high-performance, low-power, reliable data acquisition and processing functions for various missions of spacecraft. However, high-energy protons, neutrons, alpha particles, heavy ions, etc. in the space radiation environment can cause single-particle effects in semiconductor devices in analog-to-digital conversion systems, seriously affecting the reliability and life of the system. [1] All kinds of soft errors in single event effects are caused by transient currents generated by particle incidence and are closely related to single event upsets (SEUs). [1] .

[0003] The Successive Approximation Register (SAR) is composed of a series of True Single Phase Clock (TSPC) type D flip-flops, and the output of each flip-flop is the input of the next flip-flop. When a sensitive node is hit by a single particle, it may cause the flip-flop state to flip, leading to a disruptive error. In particular, the asynchronous reset and set signals in the TSPC type D flip-flop are independently controlled, and its SEU will directly lead to trigger output errors and cause large-area flips. Therefore, this mechanism is an important factor causing SEU in TSPC type D flip-flops and SAR logic circuits.

[0004] Therefore, there is an urgent need to provide an asynchronous successive approximation register that is more reliable and resistant to single-particle upsets. Summary of the invention

[0005] The object of the present invention is to provide an asynchronous successive approximation register resistant to single particle upset, so as to solve the reliability problem of the prior art that cannot resist single particle upset.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides an asynchronous successive approximation register resistant to single event upset, comprising:

[0008] Two rows of TSPC-type D flip-flops;

[0009] The upper and lower rows of TSPC-type D flip-flops form a chain structure; the TSPC-type D flip-flops are resistant to single-particle upsets and have reset and set functions;

[0010] The TSPC-type D flip-flop comprises a first-level inverting logic circuit, a second-level inverting logic circuit, a third-level inverting logic circuit, an anti-SEU asynchronous reset structure and an anti-SEU asynchronous set structure; an input end of the anti-SEU asynchronous reset structure is connected to an input reset signal; an input end of the anti-SEU asynchronous set structure is connected to an input set signal.

[0011] Optionally, the first-stage inverting logic circuit includes a first NMOS tube, a first PMOS tube, a second PMOS tube and a third PMOS tube;

[0012] The gate of the first NMOS tube is connected to the gate of the second PMOS tube and serves as a data input terminal of the first-stage inverting logic circuit; the drain of the first NMOS tube is connected to the source of the first PMOS tube and serves as a first output terminal of the first-stage inverting logic circuit;

[0013] The source of the first NMOS tube is grounded; the gate of the first PMOS tube is connected to the clock input signal, and the source of the first PMOS tube is connected to the drain of the second PMOS tube; the source of the second PMOS tube is connected to the drain of the third PMOS tube and serves as the second output end of the first-stage inverting logic circuit; the gate of the third PMOS tube is connected to the clock input signal.

[0014] Optionally, the first output end of the first-stage inverting logic circuit corresponds to the first node; the second output end of the first-stage inverting logic circuit corresponds to the second node;

[0015] The second-stage inverting logic circuit includes a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a fourth PMOS tube;

[0016] The gate of the second NMOS tube is connected to the first node, the drain of the second NMOS tube is connected to the second node, and the source of the second NMOS tube is connected to the drain of the fifth NMOS tube; the gate of the third NMOS tube is connected to the clock input signal, the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube and serves as the output end of the second-stage inverting logic circuit; the source of the third NMOS tube is connected to the drain of the fourth NMOS tube; the gate of the fourth NMOS tube is connected to the gate of the fourth PMOS tube and connected to the second node, and the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube; the gate of the fifth NMOS tube is connected to the clock input signal, and the source of the fifth NMOS tube is connected to the ground; the source of the fourth PMOS tube is connected to the power supply.

[0017] Optionally, the first output terminal of the second-stage inverting logic circuit corresponds to the third node;

[0018] The third-stage inverting logic circuit includes a sixth NMOS tube, a fifth PMOS tube and an inverter;

[0019] The gate of the sixth NMOS tube is connected to the gate of the fifth PMOS tube and connected to the third node; the drain of the sixth NMOS tube is connected to the drain of the fifth PMOS tube and serves as the first output end of the third-stage inverting logic circuit;

[0020] The source of the sixth NMOS tube is grounded, and the source of the fifth PMOS tube is connected to the power supply; the first output end of the third-stage inverting logic circuit corresponds to the fourth node; the input end of the inverter is connected to the fourth node, and the output end of the inverter is the second output end of the third-stage inverting logic circuit.

[0021] Optionally, the anti-SEU asynchronous reset structure includes a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a sixth PMOS tube;

[0022] The gate of the seventh NMOS tube is connected to the gate of the eighth NMOS tube and serves as the first input terminal of the anti-SEU asynchronous reset structure;

[0023] The drain of the seventh NMOS tube and the gate of the ninth NMOS tube are respectively connected to the second node;

[0024] The source of the seventh NMOS tube, the source of the ninth NMOS tube and the drain of the eighth NMOS tube are connected;

[0025] The source of the eighth NMOS tube is grounded, and the drain of the ninth NMOS tube is connected to a power supply; the gate of the sixth PMOS tube serves as the second input terminal of the anti-SEU asynchronous reset structure and is connected to input a first reset signal, the drain of the sixth PMOS tube is connected to the source of the third PMOS tube, and the source of the sixth PMOS tube is connected to a power supply; the first input terminal of the anti-SEU asynchronous reset structure is connected to input a second reset signal.

[0026] Optionally, the anti-SEU asynchronous setting structure includes a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube and a seventh PMOS tube;

[0027] The gate terminal of the NMOS tube is connected to the gate terminal of the eleventh NMOS tube and serves as the first input terminal of the anti-SEU asynchronous setting structure;

[0028] The drain of the tenth NMOS tube and the gate of the twelfth NMOS tube are connected to the third node respectively, and the source of the tenth NMOS tube and the source of the twelfth NMOS tube are connected to the drain of the eleventh NMOS tube;

[0029] The source of the eleventh NMOS tube is connected to the ground, and the drain of the twelfth NMOS tube is connected to the power supply; the gate of the seventh PMOS tube serves as the second input terminal of the anti-SEU asynchronous setting structure and is connected to the input first setting signal, the drain of the seventh PMOS tube is connected to the second node, and the source of the seventh PMOS tube is connected to the power supply; the first input terminal of the anti-SEU asynchronous setting structure is connected to the input second setting signal.

[0030] Optionally, the size of the ninth NMOS tube is greater than a preset threshold value to ensure a stronger single-particle upset resistance capability.

[0031] Optionally, the size of the twelfth NMOS tube is greater than a preset threshold value to ensure a stronger single-particle upset resistance capability.

[0032] Optionally, the size of the pull-up PMOS tube is increased to improve the single event upset resistance of the TSPC type D flip-flop.

[0033] Optionally, the upper row of registers controls the TSPC-type D flip-flops in the lower row of registers to be set in sequence, and the lower row of registers stores the digital output results of the step-by-step approximation.

[0034] Compared with the prior art, the present invention provides an asynchronous successive approximation register resistant to single particle upset, comprising: two rows of TSPC type D flip-flops; two rows of TSPC type D flip-flops forming a chain structure; TSPC type D flip-flops resistant to single particle upset and with reset and set; TSPC type D flip-flops comprising a first-level inverting logic circuit, a second-level inverting logic circuit, a third-level inverting logic circuit, an anti-SEU asynchronous reset structure and an anti-SEU asynchronous set structure; the input end of the anti-SEU asynchronous reset structure is connected to an input reset signal; the input end of the anti-SEU asynchronous set structure is connected to an input set signal. When the asynchronous successive approximation register is enabled by a reset signal or a set signal, there is a delay in the pull-down node, which ensures that erroneous data is not transmitted to the output end, avoids large-scale erroneous flipping of SAR logic, solves the reliability problem that the existing SAR logic cannot resist single particle upset, and improves its anti-interference ability in a high radiation environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0036] Figure 1 It is a circuit schematic diagram of a TSPC type D flip-flop with a reset function in the prior art;

[0037] Figure 2 It is a structural diagram of a TSPC type D flip-flop resistant to single-particle upset and single-particle transient in the prior art;

[0038] Figure 3 It is a schematic diagram of an asynchronous successive approximation register resistant to single-particle upset provided by the present invention;

[0039] Figure 4 It is a schematic diagram of a TSPC-type D flip-flop with single-particle upset resistance and reset and set provided by the present invention;

[0040] Figure 5 This is the SEU fault injection simulation result diagram of the unreinforced TSPC type D flip-flop;

[0041] Figure 6 It is a simulation result diagram of SEU fault injection at the asynchronous reset and asynchronous set signal terminals of the TSPC-type D flip-flop resistant to single-particle upset and with reset and set of the present invention;

[0042] Figure 7 This is a diagram of SEU fault injection simulation results of the asynchronous successive approximation register resistant to single-particle upset of the present invention.

[0043] Reference numerals:

[0044] MN1-first NMOS tube, MN2-second NMOS tube, MN3-third NMOS tube, MN4-fourth NMOS tube, MN5-fifth NMOS tube, MN6-sixth NMOS tube, MN7-seventh NMOS tube, MN8-eighth NMOS tube, MN9-ninth NMOS tube, MN10-tenth NMOS tube, MN11-eleventh NMOS tube, MN12-twelfth NMOS tube, MP1-first PMOS tube, MP2-second PMOS tube, MP3-third PMOS tube, MP4-fourth PMOS tube, MP5-fifth PMOS tube, MP6-sixth PMOS tube, MP7-seventh PMOS tube, CLK-clock input signal, X-first node, Y-second node, Z-third node, Q-fourth node, OUT1-first reset signal, RST-second reset signal, SETN-first set signal, SET-second set signal. DETAILED DESCRIPTION

[0045] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0046] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0047] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0048] First, the abbreviations, English and key term definitions used in this manual are explained:

[0049] Successive Approximation RegisterAnalog-to-DigitalConverter (SAR ADC).

[0050] Successive Approximation Register (SAR).

[0051] Single Event Upset (SEU).

[0052] True Single Phase Clock (TSPC).

[0053] True single-phase clock D flip-flop, TSPC type D flip-flop.

[0054] In the prior art, there are some TSPC type D flip-flops. Figure 1 and Figure 2 For example, Figure 1 The figure shows a TSPC type D flip-flop with reduced glitch. Figure 1 As shown, by making the size of the second NMOS transistor MN2 larger than the size of the third NMOS transistor MN3 and the fourth NMOS transistor MN4, the burr can be effectively reduced. The gates of the sixth PMOS transistor MP6 and the seventh NMOS transistor MN7 are respectively connected to the asynchronous reset signal R, so that the TSPC type D flip-flop has a reset function. Figure 1 The TSPC-type D flip-flop does not have a set function, and will output erroneous latched data when the asynchronous reset signal R generates a 0-1-0 type transient pulse. Figure 2 The figure shows a TSPC type D flip-flop that is resistant to single event upset and single event transient. Figure 2 As shown in the figure, the method of time redundancy design is used to improve the fault tolerance of the TSPC type D flip-flop, which has a simple structure and has the function of resisting single-particle upset and single-particle transient at the same time. Figure 2 The solution in the paper has the problems of reducing the data sampling and holding speed, introducing more floating nodes, and not having the reset and set functions.

[0055] In order to solve the problems in the prior art, the purpose of the present invention is to provide an asynchronous successive approximation register that is resistant to single-particle upsets, so as to solve the reliability problem that the existing SAR logic cannot resist single-particle upsets, so as to improve its anti-interference ability in a high-radiation environment. Next, the solution provided in the embodiment of this specification is described in conjunction with the accompanying drawings:

[0056] like Figure 3 As shown, the asynchronous successive approximation register may include:

[0057] Two rows of TSPC-type D flip-flops;

[0058] The upper and lower rows of TSPC-type D flip-flops form a chain structure; the TSPC-type D flip-flops are resistant to single-particle upsets and have reset and set functions;

[0059] like Figure 4 As shown, the TSPC type D flip-flop includes a first-level inverting logic circuit, a second-level inverting logic circuit, a third-level inverting logic circuit, an anti-SEU asynchronous reset structure and an anti-SEU asynchronous set structure;

[0060] An input terminal of the SEU-resistant asynchronous reset structure is connected to an input reset signal;

[0061] An input terminal of the SEU-resistant asynchronous setting structure is connected to an input setting signal.

[0062] The upper register row controls the triggers in the lower register row to be set in sequence, and the lower register row stores the gradually approached digital output results.

[0063] The asynchronous successive approximation register provided by the present invention has a delay in pulling down a node when a reset signal or a set signal is enabled, thereby ensuring that erroneous data is not transmitted to the output end, avoiding large-scale erroneous flipping of SAR logic, and solving the reliability problem that the existing SAR logic cannot resist single-particle flipping, so as to improve its anti-interference ability in a high-radiation environment.

[0064] based on Figure 3 The present specification also provides some specific structures of the structure. Next, Figure 3 The various structures in are described below.

[0065] like Figure 4 As shown, the first-stage inverting logic circuit may include a first NMOS transistor MN1, a first PMOS transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3.

[0066] Among them, the gate of the first NMOS tube MN1 is connected to the gate of the second PMOS tube MP2 and serves as the data input end of the first-stage inverting logic circuit, the drain of the first NMOS tube MN1 is connected to the source of the first PMOS tube MP1 and serves as the first output end of the first-stage inverting logic circuit, and the source of the first NMOS tube MN1 is grounded; the gate of the first PMOS tube MP1 is connected to the clock input signal CLK, the source of the first PMOS tube MP1 is connected to the drain of the second PMOS tube MP2; the source of the second PMOS tube MP2 is connected to the drain of the third PMOS tube MP3 and serves as the second output end of the first-stage inverting logic circuit.

[0067] The gate of the third PMOS transistor MP3 is connected to the clock input signal CLK; the first output end of the first-stage inverting logic circuit corresponds to the first node X; and the second output end of the first-stage inverting logic circuit corresponds to the second node Y.

[0068] The second-stage inverting logic circuit may include a second NMOS transistor MN2 , a third NMOS transistor MN3 , a fourth NMOS transistor MN4 , a fifth NMOS transistor MN5 and a fourth PMOS transistor MP4 .

[0069] Among them, the gate of the second NMOS tube MN2 is connected to the first node X, the drain of the second NMOS tube MN2 is connected to the second node Y, and the source of the second NMOS tube MN2 is connected to the drain of the fifth NMOS tube MN5; the gate of the third NMOS tube MN3 is connected to the clock input signal CLK, the drain of the third NMOS tube MN3 is connected to the drain of the fourth PMOS tube MP4 and serves as the output end of the second-stage inverting logic circuit, and the source of the third NMOS tube MN3 is connected to the drain of the fourth NMOS tube MN4; the gate of the fourth NMOS tube MN4 is connected to the gate of the fourth PMOS tube MP4 and connected to the second node Y, and the source of the fourth NMOS tube MN4 is connected to the drain of the fifth NMOS tube MN5; the gate of the fifth NMOS tube MN5 is connected to the clock input signal CLK, and the source of the fifth NMOS tube MN5 is connected to the ground; the source of the fourth PMOS tube MP4 is connected to the power supply; the first output end of the second inverting logic circuit corresponds to the third node Z.

[0070] The third-level inverting logic circuit may include a sixth NMOS tube MN6, a fifth PMOS tube MP5 and an inverter; wherein the gate of the sixth NMOS tube MN6 is connected to the gate of the fifth PMOS tube MP5 and to the third node Z, the drain of the sixth NMOS tube MN6 is connected to the drain of the fifth PMOS tube MP5 and serves as the first output end of the third-level inverting logic circuit, the source of the sixth NMOS tube MN6 is grounded; the source of the fifth PMOS tube MP5 is connected to the power supply; the first output end of the third-level inverting logic circuit corresponds to the fourth node Q; the input end of the inverter is connected to the fourth node Q, the output end of the inverter is the second output end of the third-level inverting logic circuit; the second output end of the third-level inverting logic circuit corresponds to the output end Qbar.

[0071] The anti-SEU asynchronous reset structure may include a seventh NMOS tube MN7, an eighth NMOS tube MN8, a ninth NMOS tube MN9 and a sixth PMOS tube MP6; wherein the gate of the seventh NMOS tube MN7 is connected to the gate of the eighth NMOS tube MN8 and serves as the first input terminal of the anti-SEU asynchronous reset structure, the drain of the seventh NMOS tube MN7 and the gate of the ninth NMOS tube MN9 are respectively connected to the second node Y, the source of the seventh NMOS tube MN7, the source of the ninth NMOS tube MN9 and the drain of the eighth NMOS tube MN8 are connected; the source of the eighth NMOS tube MN8 is grounded; the drain of the ninth NMOS tube MN9 is connected to the power supply; the gate of the sixth PMOS tube MP6 serves as the second input terminal of the anti-SEU asynchronous reset structure and is connected to the input of the first reset signal OUT1, the drain of the sixth PMOS tube MP6 is connected to the source of the third PMOS tube MP3, and the source of the sixth PMOS tube MP6 is connected to the power supply; the first input terminal of the anti-SEU asynchronous reset structure is connected to the input of the second reset signal RST.

[0072] The anti-SEU asynchronous setting structure may include a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12 and a seventh PMOS transistor MP7; wherein the gate terminal of the tenth NMOS transistor MN10 is connected to the gate terminal of the eleventh NMOS transistor MN11 and serves as the first input terminal of the anti-SEU asynchronous setting structure, the drain of the tenth NMOS transistor MN10 and the gate of the twelfth NMOS transistor MN12 are respectively connected to the third node Z, the source of the tenth NMOS transistor, the source of the twelfth NMOS transistor MN12 and the drain of the eleventh NMOS transistor MN11 are connected; the source of the eleventh NMOS transistor MN11 is connected to the ground; the drain of the twelfth NMOS transistor MN12 is connected to the power supply; the gate of the seventh PMOS transistor MP7 serves as the second input terminal of the anti-SEU asynchronous setting structure and is connected to the input first setting signal SETN, the drain of the seventh PMOS transistor MP7 is connected to the second node Y, and the source of the seventh PMOS transistor MP7 is connected to the power supply; the first input terminal of the anti-SEU asynchronous setting structure is connected to the input second setting signal SET.

[0073] Figure 4 In the embodiment, except for MN8 and MN 11, the number of transistors in modules A and B (for example, MN7, MN9, MN10, and MN12) cannot be adjusted, but the size of these transistors can be adjusted. The larger the size, the better the single-particle upset resistance.

[0074] Further, as an optional embodiment, the ninth NMOS transistor MN9 and the twelfth NMOS transistor MN12 are larger in size to ensure that a stronger single-particle upset resistance capability is provided while reducing the delay.

[0075] As an optional embodiment, the size of the pull-up PMOS tube can be increased (for example Figure 4 The fourth PMOS tube MP4 in the middle can also improve the single-particle upset resistance of the TSPC type D trigger to a certain extent, but it will reduce the speed of data sampling and holding.

[0076] The present invention provides an asynchronous successive approximation register resistant to single-particle upset. Through simulation comparison, the simulation diagram is as follows: Figure 5-7 As shown, Figure 5 The simulation results of the unhardened TSPC-type D flip-flop under SEU fault injection conditions are shown. Specifically, Figure 5 As shown in the figure, at 20ns, an SEU fault is introduced into the asynchronous set terminal ( / I / SET), accompanied by a typical 0-1-0 transient current waveform, which directly causes the output terminal Q to be set. Subsequently, at 90ns, an SEU fault is injected into the asynchronous reset terminal ( / I / RESET), which is also accompanied by the generation of a 0-1-0 transient current, causing the output terminal Q to be reset. Figure 5 The simulation results in show the vulnerability of the unhardened TSPC-type D flip-flop in dealing with SEUs, especially when dealing with SEUs on asynchronous reset and set signals, where its fault tolerance is significantly insufficient.

[0077] Figure 6 The simulation results of the SEU-resistant TSPC D-type flip-flop with integrated reset and set functions of the present invention are presented, and the SEU fault injection is performed at the asynchronous reset and set signal terminals. Figure 5 The simulation results of the unreinforced circuit shown in the figure show that under the same fault injection conditions, the TSPC-type D flip-flop of the present invention has no erroneous data latching, and effectively resists the transient impact caused by SEU.

[0078] Figure 7 This is a SEU fault injection simulation result diagram of the asynchronous successive approximation register resistant to single-particle upset of the present invention. The test environment is set to a clock frequency of 100MHz, a power supply voltage of 1.8V, and the data input terminal (q[10:1]) is sequentially set to a high level state. At 65ns, the SEU fault simulation is introduced through the asynchronous reset terminal ( / I / RESET). The results show that the output terminal (b[9:0]) of the asynchronous successive approximation register of the present invention does not have an erroneous flip, and continues to output a high level in sequence, which effectively verifies its SEU fault tolerance capability.

[0079] After verification, the present invention provides a TSPC-type D flip-flop structure with reset and set and anti-single-particle upset for asynchronous successive approximation registers, which solves the reliability problem that the existing SAR logic cannot resist single-particle upset, so as to improve its anti-interference ability in high-radiation environments. Specifically, it includes at least the following technical effects:

[0080] 1) When the asynchronous successive approximation register is enabled by the reset signal or the set signal, there is a delay in pulling down the node Y or the node Z, which ensures that the erroneous data is not transmitted to the output end, avoids the large-scale error flip of the SAR logic, and achieves the ability to resist single-particle flip.

[0081] 2) Based on the existing TSPC-type D flip-flop, the present invention adds a small number of transistors (eg, MN7, MN9, MN10, MN12) and realizes the ability to resist single-particle upset, with low implementation complexity and low hardware cost.

[0082] 3) The circuit structure proposed in the present invention only performs a time redundancy reinforcement design for asynchronous signals, so it not only has a strong SEU tolerance capability, but also has the advantages of low latency and no impact on the core operating speed of the system.

[0083] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0084] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. An asynchronous successive approximation register resistant to single event upset, characterized in that: include: Two rows of TSPC-type D flip-flops; The upper and lower rows of TSPC-type D flip-flops form a chain structure; the TSPC-type D flip-flops are resistant to single-particle upsets and have reset and set functions; The TSPC-type D flip-flop comprises a first-level inverting logic circuit, a second-level inverting logic circuit, a third-level inverting logic circuit, an anti-SEU asynchronous reset structure and an anti-SEU asynchronous set structure; an input end of the anti-SEU asynchronous reset structure is connected to an input reset signal; an input end of the anti-SEU asynchronous set structure is connected to an input set signal.

2. The single event upset resistant asynchronous successive approximation register according to claim 1, characterized in that: The first-stage inverting logic circuit includes a first NMOS tube, a first PMOS tube, a second PMOS tube and a third PMOS tube; The gate of the first NMOS tube is connected to the gate of the second PMOS tube and serves as a data input terminal of the first-stage inverting logic circuit; the drain of the first NMOS tube is connected to the source of the first PMOS tube and serves as a first output terminal of the first-stage inverting logic circuit; The source of the first NMOS tube is grounded; the gate of the first PMOS tube is connected to the clock input signal, and the source of the first PMOS tube is connected to the drain of the second PMOS tube; the source of the second PMOS tube is connected to the drain of the third PMOS tube and serves as the second output end of the first-stage inverting logic circuit; the gate of the third PMOS tube is connected to the clock input signal.

3. The single event upset resistant asynchronous successive approximation register according to claim 1, characterized in that: The first output end of the first-stage inverting logic circuit corresponds to the first node; the second output end of the first-stage inverting logic circuit corresponds to the second node; The second-stage inverting logic circuit includes a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a fourth PMOS tube; The gate of the second NMOS tube is connected to the first node, the drain of the second NMOS tube is connected to the second node, and the source of the second NMOS tube is connected to the drain of the fifth NMOS tube; the gate of the third NMOS tube is connected to the clock input signal, the drain of the third NMOS tube is connected to the drain of the fourth PMOS tube and serves as the output end of the second-stage inverting logic circuit; the source of the third NMOS tube is connected to the drain of the fourth NMOS tube; the gate of the fourth NMOS tube is connected to the gate of the fourth PMOS tube and connected to the second node, and the source of the fourth NMOS tube is connected to the drain of the fifth NMOS tube; the gate of the fifth NMOS tube is connected to the clock input signal, and the source of the fifth NMOS tube is connected to the ground; the source of the fourth PMOS tube is connected to the power supply.

4. The single event upset resistant asynchronous successive approximation register according to claim 3, characterized in that: The first output terminal of the second-stage inverting logic circuit corresponds to the third node; The third-stage inverting logic circuit includes a sixth NMOS tube, a fifth PMOS tube and an inverter; The gate of the sixth NMOS tube is connected to the gate of the fifth PMOS tube and connected to the third node; the drain of the sixth NMOS tube is connected to the drain of the fifth PMOS tube and serves as the first output end of the third-stage inverting logic circuit; The source of the sixth NMOS tube is grounded, and the source of the fifth PMOS tube is connected to the power supply; the first output end of the third-stage inverting logic circuit corresponds to the fourth node; the input end of the inverter is connected to the fourth node, and the output end of the inverter is the second output end of the third-stage inverting logic circuit.

5. The single event upset resistant asynchronous successive approximation register according to claim 3, characterized in that: The anti-SEU asynchronous reset structure includes a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and a sixth PMOS tube; The gate of the seventh NMOS tube is connected to the gate of the eighth NMOS tube and serves as the first input terminal of the anti-SEU asynchronous reset structure; The drain of the seventh NMOS tube and the gate of the ninth NMOS tube are respectively connected to the second node; The source of the seventh NMOS tube, the source of the ninth NMOS tube and the drain of the eighth NMOS tube are connected; The source of the eighth NMOS tube is grounded, and the drain of the ninth NMOS tube is connected to a power supply; the gate of the sixth PMOS tube serves as the second input terminal of the anti-SEU asynchronous reset structure and is connected to the input of a first reset signal, the drain of the sixth PMOS tube is connected to the source of the third PMOS tube, and the source of the sixth PMOS tube is connected to a power supply; the first input terminal of the anti-SEU asynchronous reset structure is connected to the input of a second reset signal.

6. The single event upset resistant asynchronous successive approximation register according to claim 4, characterized in that: The anti-SEU asynchronous setting structure includes a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube and a seventh PMOS tube; The gate end of the NMOS tube is connected to the gate end of the eleventh NMOS tube and serves as the first input end of the anti-SEU asynchronous setting structure; The drain of the tenth NMOS tube and the gate of the twelfth NMOS tube are connected to the third node respectively, and the source of the tenth NMOS tube and the source of the twelfth NMOS tube are connected to the drain of the eleventh NMOS tube; The source of the eleventh NMOS tube is connected to the ground, and the drain of the twelfth NMOS tube is connected to the power supply; the gate of the seventh PMOS tube serves as the second input terminal of the anti-SEU asynchronous setting structure and is connected to the input first setting signal, the drain of the seventh PMOS tube is connected to the second node, and the source of the seventh PMOS tube is connected to the power supply; the first input terminal of the anti-SEU asynchronous setting structure is connected to the input second setting signal.

7. The single event upset resistant asynchronous successive approximation register according to claim 5, characterized in that: The size of the ninth NMOS tube is greater than a preset threshold value to ensure a stronger single event upset resistance capability.

8. The single event upset resistant asynchronous successive approximation register according to claim 6, characterized in that: The size of the twelfth NMOS tube is greater than a preset threshold value to ensure a stronger single event upset resistance capability.

9. The single event upset resistant asynchronous successive approximation register according to claim 1, characterized in that: The size of the pull-up PMOS tube is increased to improve the single event upset resistance of the TSPC type D flip-flop.

10. The single event upset resistant asynchronous successive approximation register according to claim 1, characterized in that: The upper register controls the TSPC-type D flip-flops in the lower register to be set in sequence, and the lower register stores the digital output results of the step-by-step approach.

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