Process, voltage and temperature invariance time-to-digital converter with sub-gate level delay resolution

Abstract

The invention relates to a time-to-digital converter with process, voltage and temperature invariance with sub-gate level delay resolution. A control circuit and method for delaying an electronic signal, and a time-to-digital converter including the control circuit are provided. An example control circuit includes a first delay circuit having a first plurality of delay elements electrically connected in series and configured to generate a first control voltage associated with a first delay time. The control circuit further includes a second delay circuit having a second plurality of delay elements electrically connected at least partially in series. The second delay circuit is configured to generate a second control voltage associated with a second delay time. A first group of delay elements within the second plurality of delay elements exhibits a first delay time based on a first control voltage, and a second group of the second plurality of delay elements exhibits a second delay time based at least in part on a second control voltage.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to digital-to-time converters and, more particularly, to digital-to-time converters including delay lines with invariance to production process, supply voltage, and temperature (PVT) with sub-gate delay resolution. Background Art

[0002] Many electronic devices utilize simple logic gates to delay electronic signals. The delay of electronic signals can have a variety of purposes. For example, delay lines can be used to synchronize electronic signals. In addition, delay lines can be used in time-to-digital converters (TDCs) to determine or implement time differences in one or more input signals.

[0003] A number of problems arise with existing delay line electronics. First, delay line devices may be susceptible to process, voltage, and temperature (PVT) variations. In other words, changes in the process, supply voltage, and / or temperature in the electronic device may cause the delay produced by the electronic delay line to vary. Second, the resolution of the delay may be limited by the minimum gate delay of the technology used to manufacture the logic gates. For example, a complementary metal oxide semiconductor (CMOS) gate developed using 130 nanometer technology may have a minimum gate delay of 200 picoseconds, so the resolution of any delay may be limited to 200 picosecond increments.

[0004] Applicants have discovered many technical challenges and difficulties associated with generating PVT-invariant delays with sub-gate resolution. Through hard work, ingenuity, and innovation, Applicants have solved the problems associated with generating delays using electronic components by developing the solutions embodied in the present disclosure, which are described in detail below. Summary of the invention

[0005] Various embodiments relate to example methods, apparatus, and computer program products for generating delays with PVT invariance with sub-gate resolution. According to some embodiments of the present disclosure, an example control circuit is provided. In some embodiments, the example control circuit may include a first delay circuit (loop 1), the first delay circuit including a first plurality of delay elements (N) electrically connected in series, wherein the first delay circuit (loop 1) is configured to generate a first control voltage (Vctrl1), and wherein the first plurality of delay elements (N) exhibit a first delay time (τ1) based at least in part on the first control voltage (Vctrl1). The example control circuit may further include a second delay circuit (loop 2), the second delay circuit including a second plurality of delay elements (N, M1, M2) electrically connected at least in part in series, wherein the second delay circuit (loop 2) is configured to generate a second control voltage (Vctrl2). In some embodiments, a first delay element group (N, M1) of the second plurality of delay elements (N, M1, M2) exhibits a first delay time (τ1) based at least in part on a first control voltage (Vctrl1), and a second delay element group (M2) of the second plurality of delay elements exhibits a second delay time (τ2) based at least in part on a second control voltage (Vctrl2).

[0006] In some embodiments, the control circuit may be configured to receive a reference clock (Tref), wherein the first delay time (τ1) and the second delay time (τ2) are at least partially based on the reference clock (Tref).

[0007] In some embodiments, the reference clock (Tref) may be invariant to variations in process, voltage, and / or temperature.

[0008] In some embodiments, the first delay circuit (Loop 1) may further include a first phase detector, wherein the first plurality of delay elements (N) generates a first delayed signal, and wherein the first control voltage (Vctrl1) is at least partially based on a phase difference between the first delayed signal and a reference clock (Tref).

[0009] In some embodiments, the second delay circuit (loop 2) may further include a first channel and a second channel, the first channel includes a first delay element subset (N), the delay elements of the first subset belong to a first delay element group (N, M1), and the first channel may further include a second delay element group (M2).

[0010] In some embodiments, the second channel may not include a delay element.

[0011] In some embodiments, the number of delay elements of the first subset of delay elements may be different than the number of delay elements of the first plurality of delay elements.

[0012] In some embodiments, the number of delay elements of the first subset of delay elements may be equal to the number of delay elements of the first plurality of delay elements.

[0013] In some embodiments, the second channel may include a second delay element subset (M1), the second delay element subset (M1) belongs to the first delay element group (N, M1), and the first delay element subset and the second delay element subset form the first delay element group.

[0014] In some embodiments, the second delay circuit (Loop 2) may further include a second phase detector configured to receive at input a second delayed signal on the first channel and an additional signal on the second channel, wherein the second control voltage may be based at least in part on a phase difference between the second delayed signal and the additional signal.

[0015] In some embodiments, the example control circuit may further include a multiplexer configured to receive at inputs the first control voltage and the second control voltage and to generate a first command signal based at least in part on the first control voltage and a second command signal based at least in part on the second control voltage.

[0016] In some embodiments, the second delay time (τ2) may be greater than the first delay time (τ1).

[0017] In some embodiments, the difference between the second delay time (τ2) and the first delay time (τ1) may be smaller in absolute value than each of the second delay time (τ2) and the first delay time (τ1).

[0018] An example electronic circuit is further provided, the example electronic circuit comprising an additional delay line, the additional delay line comprising a plurality of additional delay elements and a plurality of control circuits. In some embodiments, the example control circuit may include a first delay circuit (loop 1), the first delay circuit comprising a first plurality of delay elements (N) electrically connected in series, wherein the first delay circuit (loop 1) is configured to generate a first control voltage (Vctrl1), and wherein the first plurality of delay elements (N) exhibit a first delay time (τ1) based at least in part on the first control voltage (Vctrl1). The example control circuit may further include a second delay circuit (loop 2), the second delay circuit comprising a second plurality of delay elements (N, M1, M2) electrically connected at least in part in series, wherein the second delay circuit (loop 2) is configured to generate a second control voltage (Vctrl2). In some embodiments, a first delay element group (N, M1) of the second plurality of delay elements (N, M1, M2) exhibits a first delay time (τ1) based at least in part on a first control voltage (Vctrl1), and a second delay element group (M2) of the second plurality of delay elements (N, M1, M2) exhibits a second delay time (τ2) based at least in part on a second control voltage (Vctrl2). In some embodiments, the example control circuit may further include a multiplexer configured to receive the first control voltage and the second control voltage at an input, and to generate a first command signal based at least in part on the first control voltage, and to generate a second command signal based at least in part on the second control voltage. In some embodiments, each additional delay element may be configured to receive a respective first command signal and a second command signal, and each additional delay element exhibits a first delay time when receiving the first command signal, and exhibits a second delay time when receiving the second command signal.

[0019] In some embodiments, the delay resolution can be proportional to the period of a reference clock (Tref), and the proportionality constant between the delay resolution and the reference clock (Tref) can be based at least in part on the number of delay elements in the first plurality of delay elements (N), the number of delay elements in the second delay element subgroup (M1), and the number of delay elements in the second delay element group (M2).

[0020] An example method for delaying an electronic signal is also provided. In some embodiments, the method may include receiving a reference clock at a control circuit. The method may further include generating a first control voltage (Vctrl1) at a first delay circuit (loop 1) based at least in part on the reference clock, wherein the first delay circuit (loop 1) includes a first plurality of delay elements (N) at least partially electrically connected in series, and wherein the first plurality of delay elements (N) exhibit a first delay time (τ1) based at least in part on the first control voltage (Vctrl1). In some embodiments, the method may further include generating a second control voltage (Vctrl2) at a second delay circuit (loop 2) based at least in part on a reference clock, wherein the second delay circuit (loop 2) includes a second plurality of delay elements (N, M1, M2) electrically connected in series, wherein a first delay element group (N, M1) of the second plurality of delay elements (N, M1, M2) exhibits a first delay time (τ1) based at least in part on the first control voltage (Vctrl1), and wherein a second delay element group (M2) of the second plurality of delay elements (N, M1, M2) exhibits a second delay time (τ2) based at least in part on the second control voltage (Vctrl2). In some embodiments, the example method may further include delaying the electronic signal based on the first control voltage and the second control voltage.

[0021] In some embodiments, the second delay circuit (loop 2) may further include a first channel, the first channel includes a first delay element subset (N), the delay elements of the first subset belong to the first delay element group (N, M1), and the first channel further includes a second delay element group (M2). The second delay circuit may further include a second channel, the second channel includes a second delay element subset (M1), the second delay element subset (M1) belongs to the first delay element group, the first delay element subset and the second delay element subset form a first delay element group.

[0022] In some embodiments, the method may further include receiving a first control voltage and a second control voltage at a multiplexer, and generating a first command signal based at least in part on the first control voltage and generating a second command signal based at least in part on the second control voltage.

[0023] In some embodiments, the method may further include receiving a corresponding first command signal and a second command signal at each additional delay element at an additional delay line including a plurality of additional delay elements, wherein each additional delay element exhibits a first delay time when receiving the first command signal and exhibits a second delay time when receiving the second command signal.

[0024] An example time-to-digital converter is further provided. In some embodiments, the example time-to-digital converter may include a first input signal, a second input signal, an electronic circuit for generating a delayed second input signal based at least in part on the second input signal, and a phase detector configured to determine a signal offset between the first input signal and the delayed second input signal. In some embodiments, the electronic circuit may include an additional delay line, the additional delay line including a plurality of additional delay elements and a plurality of control circuits. In some embodiments, the example control circuit may include a first delay circuit (loop 1), the first delay circuit (N) including a first plurality of delay elements (N) electrically connected in series, wherein the first delay circuit (loop 1) is configured to generate a first control voltage (Vctrl1), and wherein the first plurality of delay elements (N) exhibit a first delay time (τ1) based at least in part on the first control voltage (Vctrl1). The example control circuit may further include a second delay circuit (loop 2), the second delay circuit including a second plurality of delay elements (N, M1, M2) electrically connected in series at least in part, wherein the second delay circuit (loop 2) is configured to generate a second control voltage (Vctrl2). In some embodiments, a first delay element group (N, M1) of the second plurality of delay elements (N, M1, M2) exhibits a first delay time (τ1) based at least in part on a first control voltage (Vctrl1), and a second delay element group (M2) of the second plurality of delay elements exhibits a second delay time (τ2) based at least in part on a second control voltage (Vctrl2). In some embodiments, the example control circuit may further include a multiplexer configured to receive the first control voltage and the second control voltage at an input, and to generate a first command signal based at least in part on the first control voltage, and to generate a second command signal based at least in part on the second control voltage. In some embodiments, each additional delay element may be configured to receive a respective first command signal and a second command signal, and each additional delay element exhibits a first delay time when receiving the first command signal, and exhibits a second delay time when receiving the second command signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Reference will now be made to the drawings. The components illustrated in the drawings may or may not be present in certain embodiments described herein. Some embodiments may include fewer (or more) components than those shown in the drawings according to example embodiments of the present disclosure.

[0026] Figure 1 A system diagram of an example control circuit configured to generate a control voltage according to one or more embodiments of the present disclosure is illustrated.

[0027] Figure 2A block diagram of an example control circuit configured to generate a first control voltage and a second control voltage according to one or more embodiments of the present disclosure is illustrated.

[0028] Figure 3 An example schematic diagram of an example variable delay circuit according to one or more embodiments of the present disclosure is shown.

[0029] Figure 4 An example schematic diagram of an example control circuit according to one or more embodiments of the present disclosure is shown.

[0030] Figure 5 An example schematic diagram of an example control circuit according to one or more embodiments of the present disclosure is shown.

[0031] Figure 6 An example variable delay circuit with sub-gate delay resolution according to one or more embodiments of the present disclosure is shown, and an example schematic diagram of an example control circuit is shown.

[0032] Figure 7 An example flow chart of a method for generating sub-gate delays with process, voltage, and temperature invariance according to one or more embodiments of the present disclosure is shown.

[0033] Figure 8 An example block diagram of an example time-to-digital converter including a sub-gate delay line with process, voltage, and temperature invariance is shown in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] Example embodiments will be described more fully below with reference to the accompanying drawings, in which some but not all embodiments of the disclosed invention are shown. Indeed, embodiments of the disclosed invention may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0035] Various example embodiments solve technical problems associated with generating a delay signal with sub-gate resolution and invariance to process, voltage, and temperature variations. As understood by those skilled in the art to which the present disclosure pertains, there are many example scenarios in which a user may need to delay a signal with high precision so that the performance of the delay does not change with process, voltage, and temperature variations (reconfiguration or programming is required if changes occur).

[0036] For example, many electronic devices utilize a series of simple logic delay elements to delay electronic signals. The delay of electronic signals can have a variety of purposes, for example, delay lines can be used to synchronize electronic signals, generate electronic pulses with precise pulse widths, create effects in audio applications, introduce phase shifts, filter unwanted frequencies, and many other similar applications. In addition, delay lines can be used in time-to-digital converters (TDCs) for accurately measuring the time difference between two events in one or more electronic signals. In some embodiments, the delay element can be a voltage-controlled delay element. The delay of the voltage-controlled delay element can be changed based on the reception of a control voltage.

[0037] There are many problems with existing delay line electronics. First, delay line devices may be susceptible to changes in production process, voltage and temperature (PVT). In other words, changes in process, supply voltage and / or temperature in the electronic device may produce changes in delay, and the delay produced by the electronic delay line may change. Secondly, the resolution of the delay may be limited by the minimum gate delay of the technology used to manufacture the logic gate. Resolution refers to the step or change between successive available delays of the delay line. For example, a CMOS gate developed using 130 nanometer technology may have a minimum gate delay of 200 picoseconds. Therefore, in some schemes, only delays of multiples of 200 picoseconds can be obtained. For example, possible delays may include 1.2 nanoseconds, 1.4 nanoseconds, 1.6 nanoseconds, 1.8 nanoseconds, etc. However, a delay of 1.3 nanoseconds may not be available. Sub-gate resolution refers to the step or change between successive available delays that is less than the minimum gate delay of a particular technology.

[0038] One approach has utilized two separate signals (fast delay and slow delay) to achieve a delay with sub-gate delay. The difference between the fast delay and the slow delay can be used to produce a gate delay with a resolution less than the gate delay of the related art. However, these approaches change as the device changes in production process, power supply voltage, and operating temperature. In order to overcome such changes due to process, voltage, and temperature, in some approaches, changes due to temperature can be recorded and stored in a table so that the device can be reconfigured based on measurements of temperature and / or voltage. This approach can be complex, slow, and inaccurate.

[0039] Various example embodiments described herein utilize a variety of techniques to obtain sub-gate resolution delays while maintaining invariance to changes in temperature and supply voltage. For example, in some embodiments, a first delay circuit including a plurality of delay elements and a feedback loop can generate a first control voltage associated with a particular delay based on a reference clock for PVT invariance. The first control voltage can be transmitted to a second delay circuit. The second delay circuit may include a second plurality of delay elements, including at least a portion of the delay elements whose delays are controlled by the first control voltage. Other delay elements may be controlled by a second control voltage based on a feedback voltage of the second delay circuit. The first control voltage of the first delay circuit associated with the first delay time and the second control voltage of the second delay circuit associated with the second delay time can be used to generate a sub-gate delay for PVT invariance.

[0040] As a result of the example embodiments described herein, and in some examples, the resolution of the delay line can be substantially improved. Furthermore, the delay line described herein can be invariant to variations in process, voltage, and temperature.

[0041] Reference now Figure 1 , an example control circuit 100 is provided. Figure 1 As shown, the example control circuit 100 receives a reference clock 102 and generates two inputs to a phase detector 106, namely a delayed signal 114 and a non-delayed signal 112. As the non-delayed signal 112, the reference clock 102 is transmitted directly to the phase detector 106 without delay. The delayed signal 114 is generated by transmitting the reference clock 102 through a series of voltage-controlled delay elements 104. Therefore, the delayed signal 114 arriving at the phase detector 106 is a delayed copy of the non-delayed signal 112. Figure 1 As further shown in FIG. 1 , the output of the phase detector 106 is electrically connected to an integrator circuit 108. The integrator circuit 108 generates a control voltage 116 based on the output of the phase detector 106. The control voltage 116 is fed back to each of the voltage controlled delay elements 104 as a control voltage.

[0042] Generally speaking, Figure 1 The control circuit 100 determines the error between the delayed signal 114 and the non-delayed signal 112, and generates a corrective feedback voltage (e.g., a control voltage 116) to the voltage-controlled delay elements 104. Thus, each of the voltage-controlled delay elements 104 receives a control voltage 116 such that the total delay is equal to a multiple of the period of the reference clock 102, and each voltage-controlled delay element 104 provides an equal fraction of the total delay. In this way, the control voltage 116 can be associated with a specific time delay when applied to similar voltage-controlled delay elements 104.

[0043] like Figure 1 As shown, the control circuit 100 receives a reference clock 102 as an input. The reference clock 102 (e.g., Tref) can be any electronic signal that provides a consistent and stable time base for the electronic device. The reference clock 102 can further be invariant to changes in temperature and power supply voltage. Therefore, the delay determined based on the reference clock 102 can also be invariant to changes in temperature and power supply voltage. In some embodiments, the reference clock 102 can be generated by a crystal oscillator or other stable frequency source.

[0044] like Figure 1 As shown, the example control circuit 100 includes a plurality of voltage-controlled delay elements 104. The voltage-controlled delay element 104 can be any electrical component configured to receive an input signal (e.g., a reference clock 102) and a control voltage (e.g., a control voltage 116) and delay the input signal by a variable amount based at least in part on the control voltage. In some embodiments, the voltage-controlled delay element 104 can include a CMOS logic gate whose gate delay varies based on the control voltage 116 provided. In some embodiments, the higher the control voltage 116 provided to the voltage-controlled delay element 104, the shorter the delay through the gate. In some embodiments, one or more voltage-controlled delay elements 104 can be electrically connected in series to generate a delayed signal 114 based on the reference clock 102.

[0045] like Figure 1 As shown, the example control circuit 100 includes a phase detector 106. The phase detector 106 can be any electronic device that is configured to compare the phases of two input signals and output a signal indicating the difference between the two signals, or output two signals, one of which is "charged" in the case of a positive offset and the other is "discharged" in the case of a negative offset. For example, the phase detector 106 can output a charge signal, wherein the duration, voltage, and / or current of the signal is proportional to the phase difference between the two input signals. In some embodiments, the phase detector 106 can receive the non-delayed signal 112 and the delayed signal 114 and generate a voltage representing the phase offset between the two signals.

[0046] like Figure 1As further shown, the example control circuit 100 includes an integrator circuit 108. The integrator circuit 108 can be any electronic device configured to convert a time difference between input signals into a voltage / current output. For example, a constant current generator charges (or discharges) a capacitor during the duration of the charging (discharging) input signal. In some embodiments, the integrator circuit 108 can receive an output signal of the phase detector 106 representing a phase difference between the delayed signal 114 and the non-delayed signal 112, and generate a DC control voltage 116. In some embodiments, the integrator circuit 108 can include a charge pump.

[0047] Reference now Figure 2 , an example control circuit 200 configured to produce a sub-gate delay for PVT invariance is provided. Figure 2 As shown, the example control circuit 200 includes a first delay circuit 220 and a second delay circuit 222. The first delay circuit 220 receives the reference clock 202 and generates a first control voltage 224. As further shown, the second delay circuit 222 receives the reference clock 202 and the first control voltage 224 and generates a second control voltage 226.

[0048] like Figure 2 As shown, the example control circuit 200 includes a first delay circuit 220 (e.g., loop 1). The first delay circuit 220 can be any electronic circuit that includes one or more voltage-controlled delay elements (e.g., voltage-controlled delay element 104) connected in series and is configured to generate an output voltage (e.g., first control voltage 224) associated with a time delay (τ1) of the one or more voltage-controlled delay elements. In some embodiments, the first delay circuit 220 can include a first control voltage 224 in combination with a first control voltage 224. Figure 1 The control circuit 100 described above is similar to the delay circuit. Figure 4-Figure 5 Further example embodiments of the first delay circuit 220 are described. In some embodiments, the first control voltage 224 (e.g., Vctrl1) generated by the first delay circuit 220, when applied to voltage-controlled delay elements similar to those comprising the first delay circuit, can cause the voltage-controlled delay elements to exhibit similar delays (e.g., τ1).

[0049] like Figure 2As further shown, the example control circuit 200 includes a second delay circuit 222 (e.g., loop 2). The second delay circuit 222 can be any electronic circuit that includes one or more voltage-controlled delay elements (e.g., voltage-controlled delay elements 104) connected in series, wherein a portion of the delay elements are configured to receive a first control voltage 224 and exhibit a time delay (τ1), and a second portion of the delay elements are configured to receive a second control voltage (e.g., second control voltage 226) and exhibit a time delay (τ2). The second delay circuit 222 is further configured to output a second control voltage 226 (e.g., Vctrl2) associated with a feedback control voltage of the second delay circuit 222. In some embodiments, when the second control voltage 226 is applied to voltage-controlled delay elements similar to those that include the second delay circuit 222, the voltage-controlled delay elements exhibit similar delays (e.g., τ2). In combination Figure 4-Figure 5 Further example embodiments of the first delay circuit 220 are described.

[0050] Reference now Figure 3 , an example variable delay circuit 300 is provided. Figure 3 As shown, the example variable delay circuit 300 includes a control voltage multiplexer 330 configured to receive a first control voltage 324, a second control voltage 326, and a control voltage selection signal 332. The control voltage multiplexer (mux) 330 is further configured to output a selected control voltage 338. Figure 3 As shown, the output of the control voltage multiplexer 330 (selected control voltage 338) is electrically connected to the voltage control input of the delay element 304. The delay element 304 is configured to delay the delay element input 334 based on the selected control voltage 338 to generate a delay element output 336.

[0051] like Figure 3 As shown, the example variable delay circuit 300 includes a control voltage multiplexer 330. The control voltage multiplexer 330 (mux) can be any electronic component configured to receive two signal inputs (e.g., first control voltage 324, second control voltage 326) and output one of the provided inputs (e.g., selected control voltage 338) based on the value of a control signal (e.g., control voltage selection signal 332). Although in Figure 3330 is shown as a two-to-one mux, but the control voltage multiplexer 330 can receive any number of inputs, for example, a four-to-one mux, an eight-to-one mux, or other similar configurations can be used. The control voltage mux 330 is configured to select a first control voltage 324 (e.g., a first command signal) or a second control voltage 326 (e.g., a second command signal) based on the value of the control voltage selection signal 332. For example, in some embodiments, the first control voltage 324 is selected in an instance where the control voltage selection signal 332 is zero, and the second control voltage 326 is selected in an instance where the control voltage selection signal 332 is one. The selected input can then be transmitted to the output as a selected control voltage 338.

[0052] like Figure 3 As further shown in FIG. 1 , the example variable delay circuit 300 includes a delay element 304. Figure 1 As further described, the delay element 304 can be any electrical component that is configured to receive an input signal (e.g., a delay element input 334) and a control voltage (e.g., a selected control voltage 338), and delay the input signal by a variable amount based at least in part on the control voltage to produce a delayed delay element output 336. As described herein, the delay element 304 can exhibit different delay times based on the selected control voltage 338. Thus, when the control voltage selection signal 332 is configured to select the first control voltage 324, the delay element 304 will delay the delay element input 334 by the delay time (e.g., τ1) associated with the first control voltage 324. However, when the control voltage selection signal 332 is configured to select the second control voltage 326, the delay element 304 will delay the delay element input 334 by the delay time (e.g., τ2) associated with the second control voltage 326. Thus, the delay of a single delay element 304 can be varied based on the value of the control voltage selection signal 332.

[0053] Reference now Figure 4 , an example control circuit 400 is provided. Figure 4 As shown in , the control circuit 400 includes a first delay circuit 420 (loop 1) and a second delay circuit 422 (loop 2). The first delay circuit 420 is configured to receive the reference clock 402 and generate a first control voltage 424 based at least in part on a feedback voltage of the first delay circuit 420. The first delay circuit 420 further includes a first phase detector 406a, which is configured to receive a first delayed signal 414 and the reference clock 402. The output of the first phase detector 406a is electrically connected to a first integrator circuit 408a, which is configured to output a first control voltage 424 based at least in part on a phase difference between the first delayed signal 414 and the reference clock 402. Figure 4 As further shown in , the first delayed signal 414 is generated by transmitting the reference clock 402 through a first plurality of delay elements 440 , wherein each delay element 404 of the plurality of delay elements 440 exhibits a delay time τ1 based on a first control voltage 424 .

[0054] like Figure 4 As further shown in FIG. 4 , the second delay circuit 422 (loop 2) includes a first channel 444 and a second channel 445. The first channel 444 includes a first delay element subset 441 connected in series, each delay element being configured to receive a first control voltage 424 and exhibiting a first delay time τ1. The first delay element subset 441 is electrically connected in series with a second delay element group 443. Each delay element in the second delay element group 443 is connected in series, and each delay element is configured to receive a second control voltage 426, thereby exhibiting a second delay time τ2. As shown, the first channel 444 receives the reference clock 402 as an input and generates a second delayed signal 446 as an input to the second phase detector 406b.

[0055] like Figure 4 As further shown in FIG. 4 , the second channel 445 includes a second delay element subset 442 connected in series, each delay element being configured to receive the first control voltage 424 and exhibiting a first delay time τ1. As shown, the second channel 445 receives the reference clock 402 as an input and generates an additional signal 447 as a second input of the second phase detector 406b. The output of the second phase detector 406b is electrically connected to a second integrator circuit 408b, which is configured to output a second control voltage 426 based at least in part on a phase difference between the second delayed signal 446 and the additional signal 447.

[0056] like Figure 4 As shown, the control circuit 400 includes a first delay element group, the first delay element group includes all delay elements that receive a first control voltage 424 as a control voltage and exhibit a first delay time τ1. The delay elements comprising the first delay element group include the first plurality of delay elements 440 of the first delay circuit 420, a first delay element subgroup 441 of a first channel 444 of a second delay circuit 422, and a second delay element subgroup 442 of a second channel 445 of the second delay circuit 422. In addition, the control circuit 400 includes a second delay element group, the second delay element group includes all delay elements that receive a second control voltage 426 as a control voltage and exhibit a second delay time τ2.

[0057] like Figure 4As shown, the control circuit 400 includes a first delay circuit 420 (loop 1). The first delay circuit 420 includes a first plurality of delay elements 440, which are configured to generate a first delayed signal 414. The first plurality of delay elements 440 may include any number (as represented by the label N) of one or more delay elements 404. The number (N) of delay elements in the first plurality of delay elements 440 may change the first delay time τ1 and the associated first control voltage 424. For example, in some embodiments, the first delay time τ1 may be determined by the following equation:

[0058]

[0059] Where T ref is the period of the reference clock 402 , and N is the number of delay elements in the first plurality of delay elements 440 .

[0060] like Figure 4 As shown in , the delay time τ1 is invariant to variations in process, voltage, and temperature (PVT). In other words, τ1 remains stable when subjected to variations in the production process, variations in the device power supply voltage, and variations in the component operating temperature. The delay time τ1 corresponds to the feedback control voltage (e.g., the first control voltage 424) of the first delay circuit 420. The first control voltage 424 is determined based on a stable, PVT-invariant reference clock 402. The delay time τ1 is also dynamic, meaning that it is continuously updated. Therefore, based on the PVT-invariant reference clock 402, changes in the performance of the electronic component over time are compensated in the first control voltage 424, and the delay time τ1 remains constant.

[0061] like Figure 4 As further described in , the control circuit 400 includes a second delay circuit 422. Figure 4 As shown in , the second delay circuit 422 includes a second plurality of delay elements, the second plurality of delay elements including a first delay element subset 441, a second delay element subset 442, and a second delay element group 443. A first channel 444 of a series of delay elements is configured to generate a second delayed signal 446, the first channel 444 including the first delay element subset 441 electrically connected in series with the second delay element group 443. The first delay element subset 441 may include any number (as indicated by the label N) of one or more delay elements 404. In some embodiments, as Figure 4As shown in , the number (N) of delay elements in the first plurality of delay elements 440 may be equal to the number (N) of delay elements in the first delay element subset 441. In some embodiments, the number (N) of delay elements in the first plurality of delay elements 440 may be different from the number (N) of delay elements in the first delay element subset 441. Figure 5 As described, in such an embodiment, the second subset of delay elements 442 may not be required.

[0062] like Figure 4 As further described in the example control circuit 400, the first channel 444 of the second delay circuit 422 further includes a second delay element group 443. The second delay element group 443 may include any number (as represented by the label M2) of one or more delay elements 404. Each delay element of the second delay element group 443 is electrically connected to the feedback control voltage (e.g., the second control voltage 426) of the second delay circuit 422. Therefore, each of the delay elements of the second delay element group 443 exhibits a second delay time τ2.

[0063] like Figure 4 As further shown in FIG. 4 , the second delay circuit 422 includes a second channel 445 of a series of delay elements configured to generate an additional signal 447. The second channel 445 includes a second delay element subset 442 electrically connected in series. Each delay element 404 of the second delay element subset 442 is electrically connected to the first control voltage 424 of the first delay circuit 420. Therefore, each delay element 404 of the second delay element subset 442 exhibits a first delay time τ1. The second delay element subset 442 may include any number (as represented by the label M1) of one or more delay elements 404.

[0064] The number of delay elements in the first delay element subset 441 is equal to the number of delay elements in the first plurality of delay elements 440 (eg Figure 4 In the example shown in ), the second delay time τ2 associated with the second control voltage 426 can depend on the first delay time τ1, as well as the number of delay elements (M1) in the second delay element subgroup 442 and the number of delay elements (M2) in the second delay element group 443. Variations in the number of delay elements in each of these groups can change the second delay time τ2 and the associated second control voltage 426. For example, in some embodiments, the second delay time τ2 can be determined by the following equation:

[0065]

[0066] Where τ1 is the delay time associated with the first control voltage 424 , M1 is the number of delay elements in the second delay element subgroup 442 , and M2 is the number of delay elements in the second delay element group 443 .

[0067] like Figure 4 As shown in , the delay time τ2 is invariant to changes in process, voltage and temperature (PVT) because the second delay circuit 422 generates a feedback voltage (second control voltage 426) based on the reference clock 402 (which is PVT invariant). In other words, τ2 remains stable when subjected to changes in production process, device power supply voltage and operating temperature. The delay time τ2 corresponds to the feedback control voltage (e.g., second control voltage 426) of the second delay circuit 422. The second control voltage 426 is determined based on the stable, PVT invariant reference clock 402. The delay time τ2 is also dynamic, which means that it is continuously updated. Therefore, based on the PVT invariant reference clock 402, changes in electronic component performance over time are compensated in the second control voltage 426, and the delay time τ2 remains constant.

[0068] Reference now Figure 5 , an example control circuit 500 is provided. Figure 5 As shown in , the control circuit 500 includes a first delay circuit 520 (loop 1) and a second delay circuit 522 (loop 2). The first delay circuit 520 is configured to receive a reference clock 502 and generate a first control voltage 524 based at least in part on a feedback voltage of the first delay circuit 520. The first delay circuit 520 further includes a first phase detector 506a, which is configured to receive a first delayed signal 514 and the reference clock 502. The output of the first phase detector 506a is electrically connected to a first integrator circuit 508a, which is configured to output a first control voltage 524 based at least in part on a phase difference between the first delayed signal 514 and the reference clock 502. As shown in FIG. Figure 5 As further shown in , the first delayed signal 514 is generated by transmitting the reference clock 502 through a first plurality of delay elements 540 , wherein each delay element 504 of the plurality of delay elements 540 exhibits a delay time τ1 based on a first control voltage 524 .

[0069] like Figure 5As further shown in FIG. 5 , the second delay circuit 522 (loop 2) includes a first channel 544 and a second channel 545. The first channel 544 includes a first delay element subset 541 connected in series, each delay element being configured to receive a first control voltage 524 and exhibiting a first delay time τ1. The first delay element subset 541 is electrically connected in series with a second delay element group 543. Each delay element in the second delay element group 543 is connected in series, and each delay element is configured to receive a second control voltage 526 and exhibit a second delay time τ2. As shown, the first channel 544 receives the reference clock 502 as an input and generates a second delayed signal 546 as an input to the second phase detector 506b.

[0070] like Figure 5 As shown in , in some embodiments, the number of delay elements (N1) in the first plurality of delay elements 540 may be different from the number of delay elements (N2) in the first delay element subset 541. In such an embodiment, the second channel 545 no longer includes any delay elements, and the additional signal 547 is generated by transmitting the reference clock 502 directly to the phase detector 506b. Since the number of delay elements exhibiting the first delay time τ1 on the first channel 544 is different, no delay elements on the second channel 545 are required. The second delay time τ2 can now be calculated by the following equation:

[0071]

[0072] Wherein, τ1 is the delay time associated with the first control voltage 524, N1 is the number of delay elements in the first plurality of delay elements 540, and N2 is the number of delay elements in the first delay element subgroup 541, and M2 is the number of delay elements in the second delay element group 543.

[0073] Reference now Figure 6 , an example PVT-invariant variable delay circuit 660 with sub-gate delay is provided. Figure 6 As shown in , the example variable delay circuit 660 includes a plurality of control voltage multiplexers (mux) 630a-630n, each multiplexer having two signal inputs, a control input, and a single signal output. Each control voltage mux 630a-630n is configured to receive a first control voltage 624 at one signal input and a second control voltage 626 at another signal input. In addition, each control voltage mux 630a-630n is configured to receive a control voltage select bit 632a-632n at the control input. Figure 6As further shown in FIG. 1 , the selected control voltage 638a-638n is transmitted to the corresponding delay element 604a-604n as the control voltage for the delay element 604a-604n. The first delay element 604a receives the input signal 634. The input signal 634 is transmitted through each of the delay elements 604a-604n that are electrically connected in series. The output of the last delay element 604n is the delayed output signal 636.

[0074] like Figure 6 As shown in FIG. 6 , the example variable delay circuit 660 includes a plurality of control voltage multiplexers 630 a-630 n. Figure 3 As described above (e.g., control voltage multiplexer 330), control voltage multiplexers 630a-630n may be any electronic component configured to receive two signal inputs (e.g., first control voltage 624, second control voltage 626) and output one of the provided inputs (e.g., selected control voltage 638a-638n) based on the value of a control signal (e.g., control voltage select bits 632a-632n). Variable delay circuit 660 may include one or more control voltage multiplexers 630a-630n as needed to generate a desired delayed output signal 636. Figure 6 As shown in FIG. 1 , each of the control voltage multiplexers 630a-630n receives a first control voltage 624 (Vctrl1) and a second control voltage 626 (Vtrl2). The first control voltage 624 may be a control voltage output of a first delay circuit (loop 1), for example, Figure 4-Figure 5 As shown in , the first control voltage 624 corresponds to the first delay time (τ1). The second control voltage 626 can be the control voltage output of the second delay circuit (loop 2), for example, Figure 4-Figure 5 As shown in , where the second control voltage 626 corresponds to the second delay time (τ2).

[0075] like Figure 6 As further shown in FIG. 1 , each control voltage multiplexer 630a-630n is configured to receive a control voltage select bit 632a-632n at a control input. Figure 3 As described above (e.g., control voltage select signal 332), control voltage select bits 632a-632n may be any signal, group of signals, or series of signals that instruct a signal input (e.g., first control voltage 624, second control voltage 626) to be output on a signal output (e.g., selected control voltages 638a-638n). For example, Figure 6As shown in , in the instance where the control voltage select bit 632a is low (set to 0), the first control voltage 624 is transmitted as the selected control voltage 638a (e.g., the first command signal) on the control voltage mux 630a output, and in the instance where the control voltage select bit 632a is high (set to 1), the second control voltage 626 is transmitted as the selected control voltage 638a (e.g., the second command signal) on the control voltage mux 630a output. In some embodiments, the multiple control voltage select bits 632a-632n may include a digital data signal having multiple bits. For example, in some embodiments, the control voltage select bits may include a four-bit digital data signal (e.g., 4b'0110). In such an embodiment, the least significant bit may be used as the control voltage select bit at the control voltage mux 630a, the second bit may be used as the control voltage select bit at the control voltage mux 630b, and so on, until the most significant bit may be used as the control voltage select bit at the control voltage mux 630n. Thus, the delay of the delayed output signal 636 of the variable delay circuit 660 may be programmed or updated based on the received control voltage select bits 632a-632n.

[0076] like Figure 6 As further shown in FIG. 6 , the variable delay circuit 660 includes a plurality of delay elements 604a-604n (eg, additional delay elements). The delay elements 604a-604n are combined with Figure 1-Figure 5 Those similar voltage controlled delay devices described herein. As described herein, based on the control voltage transmitted to the delay elements 604a-604n, the delay elements 604a-604n can exhibit different delay times (τ1, τ2). In other words, in an instance where the first control voltage 624 is selected by the control voltage mux 630a-630n and transmitted to the control voltage input of the corresponding delay element 604a-604n, the corresponding delay element 604a-604n can delay the input received at the input of the delay element 604a-604n by a certain delay time τ1. However, in an instance where the second control voltage 626 is selected by the control voltage mux 630a-630n and transmitted to the control voltage input of the corresponding delay element 604a-604n, the corresponding delay element 604a-604n can delay the input received at the input of the delay element 604a-604n by a certain delay time τ2, which delay time τ2 can be different from τ1.

[0077] By using multiple delay elements 604a-604n connected in series (e.g., additional delay lines), sub-gate delay resolution can be achieved. As used herein, sub-gate resolution refers to the step size or change between successive achievable delays that is less than the minimum gate delay for a particular technology. Figure 6As shown, the delay resolution (Δτ) of the variable delay circuit 660 can be defined as:

[0078] Δτ=τ2-τ1.

[0079] Thus, by carefully selecting the number of delay elements in the first plurality of delay elements (e.g., first plurality of delay elements 440, 540), the number of delay elements in the first delay element subset (e.g., first delay element subset 441, 541), the number of delay elements in the second delay element group (e.g., second delay element group 443, 543), and the number of delay elements in the second delay element subset (e.g., second delay element subset 442), sub-gate delay resolution may be achieved. For example, consider Figure 4 , where the number of delay elements in the first plurality of delay elements is N, the number of delay elements in the first delay element subset is also N, the number of delay elements in the second delay element group is M2, and the number of delay elements in the second delay element subset is M1, the delay resolution of the delay line (e.g., variable delay circuit 300, 660) may be determined by the following equation:

[0080]

[0081] like Figure 6 As shown in FIG. 1 , the variable delay circuit 660 receives an input signal 634 at a first delay element 604a, transmits the input signal 634 through each of the electrically connected delay elements 604a-604n, and generates a delayed output signal 636, which is delayed according to each of the programmed delay times (τ1, τ2) of each of the delay elements 604a-604n. By adjusting the number of delay elements 604a-604n in the variable delay circuit 660 and adjusting the control voltage select bits 632a-632n of each control voltage mux 630a-630n, a delayed output signal 636 with precise, PVT-invariant sub-gate resolution delay can be generated.

[0082] Reference now Figure 7 , a flow chart showing an example process 700 for generating a PVT invariant sub-gate delay is provided. At block 702, an electronic circuit including a variable delay circuit (e.g., variable delay circuit 300, 600) and a control circuit (e.g., control circuit 200, 400, 500) receives a reference clock (e.g., reference clock 102, 202, 402, 502). As described herein, a reference clock can be any PVT invariant electronic signal that provides a consistent and stable time basis for an electronic device.

[0083] At block 704, the electronic circuit generates a first control voltage (e.g., first control voltage 224, 324, 424, 524, 624) at a first delay circuit (e.g., first delay circuit 220, 420, 520) based at least in part on a reference clock, wherein the first delay circuit includes a first plurality of delay elements (e.g., first plurality of delay elements 440, 540) electrically connected in series, and wherein the first plurality of delay elements exhibit a first delay time (τ1) based at least in part on the first control voltage. As described herein, the control circuit may include a first delay circuit or loop that utilizes a first control loop to generate a stable first control voltage. The generated first control voltage may be associated with a first delay time (τ1). Having the first control voltage based at least in part on the reference clock ensures that the first delay time (τ1) is invariant to variations in process, voltage, temperature, and even aging of the electronic component.

[0084] At block 706, the electronic circuit generates a second control voltage (e.g., second control voltage 226, 326, 426, 526, 626) at a second delay circuit (e.g., second delay circuit 222, 422, 522) based at least in part on a reference clock, wherein the second delay circuit includes a second plurality of delay elements (e.g., first delay element subset 441, 541; second delay element subset 443, 543; second delay element subset 442) electrically connected in series, wherein a first delay element group of the second plurality of delay elements (first delay element subset 441, 541; second delay element subset 442) exhibits a first delay time (τ1) based at least in part on the first control voltage, and wherein a second delay element group of the second plurality of delay elements (e.g., second delay element subset 443, 543) exhibits a second delay time (τ2) based at least in part on the second control voltage. As described herein, the control circuit can include a second delay circuit or loop that utilizes a second control loop to generate a stable second control voltage. A portion of the delay element in the second control loop may receive a first control voltage from the first delay circuit, thereby exhibiting a first delay time (τ1). A second portion of the delay element may receive a second control voltage, thereby exhibiting a second delay time (τ2). Having the second control voltage at least partially based on the reference clock ensures that the second delay time (τ2) is invariant to variations in process, voltage, temperature, and even aging of the electronic components.

[0085] At block 708, the electronic circuit delays the electronic signal (eg, delay element input 334, input signal 634) based on the first control voltage and the second control voltage. Figure 6As described, the variable delay circuit 660 is configured to receive a first control voltage, a second control voltage, and a control voltage selection signal (e.g., control voltage selection bits 632a-632n), and the electronic circuit including the variable delay circuit 660 can be configured to output a delayed output signal 636 with a sub-gate delay resolution. For example, in an example embodiment, the variable delay circuit can include two delay elements. In addition, assuming that the minimum gate delay of a particular logic gate technology is 200 picoseconds, the first delay time τ1 is 200 picoseconds, and the second delay time τ2 is 250 picoseconds. The example electronic circuit can be configured to generate delays of 400 picoseconds (e.g., the control voltage selection bit is 2'b00), 450 picoseconds (e.g., the control voltage selection bit is 2'b01 or 2'b10), and 500 picoseconds (e.g., the control voltage selection bit is 2'b11), and thus, a sub-gate delay resolution of 50 picoseconds can be achieved.

[0086] Reference now Figure 8 , an example time-to-digital converter 880 including an electronic circuit 886 configured to generate sub-gate delays for PVT invariance is provided. Figure 8 As shown in , the example time-to-digital converter 880 includes a phase detector 888 configured to generate a signal offset 884 based on a phase difference between a reference signal 882 and a delayed output signal 836. Figure 8 As further shown in FIG. 8 , the example time-to-digital converter 880 further includes an electronic circuit 886 configured to receive an input signal 834 and generate a delayed output signal 836 based on the value of a control voltage selection signal 832. As shown, the example electronic circuit 886 further includes: a control circuit 800 configured to receive a reference clock 802 and generate a first control voltage 824 and a second control voltage 826; and a variable delay circuit 860 configured to generate a delayed output signal based on the received input signal 834 and the first control voltage 824, the second control voltage 826, and the control voltage selection signal 832.

[0087] like Figure 8 As shown in , a time to digital converter (TDC) 880 can be any hardware, firmware, software, or combination thereof configured to receive one or more signals (e.g., a reference signal 882, an input signal 834) and convert the phase offset between the signals into digital time. In some embodiments, the signal and the target pulse width can be provided to the TDC to determine whether the signal exhibits the expected pulse width. In some embodiments, the digital time and / or signal offset 884 generated by the TDC 880 can be used to synchronize the phases of the two input signals.

[0088] In general, TDC 880 can be configured with a precise target delay. For example, TDC 880 can receive two signals with a desired offset, and can provide the desired offset between the two signals via control voltage selection signal 832. In another example, TDC 880 can receive a signal and a desired pulse width of the signal. In such an example, a signal can be provided to two inputs of TDC 880, and the desired pulse width can be provided via control voltage selection signal 832. TDC 880 is configured to transmit a reference signal 882 input to phase detector 888 without delay. At the same time, TDC 880 transmits input signal 834 to electronic circuit 886, which can be configured by control voltage selection signal 832 to delay input signal 834 by a target delay and output a delayed output signal 836. Afterwards, phase detector 888 can output a signal offset 884 representing the phase difference between reference signal 882 and delayed output signal 836. Signal offset 884 can be monitored by an electronic device for adjusting one or both of the input signals, or can be used in other ways.

[0089] like Figure 8 As further shown in FIG. 8 , the electronic circuit 886 receives a reference clock 802 and a control voltage selection signal 832. As further described herein, the reference clock 802 enables the electronic circuit to generate a time delay that is PVT invariant. Also as described herein, the control voltage selection signal 832 enables the electronic circuit 886 to delay an input signal 834 with a sub-gate delay resolution. As described herein, the control circuit 800 generates a first control voltage 824 associated with a first delay time τ1 and a second control voltage 826 associated with a second delay time τ2. The variable delay circuit 860 configures the internal delay element using the first control voltage 824 and the second control voltage 826 according to the control voltage selection signal 832 to generate a PVT invariant delay with a sub-gate delay resolution.

[0090] Although this detailed description describes some embodiments of the invention, the appended claims cover other embodiments of the invention that differ from the described embodiments according to various modifications and improvements. For example, those skilled in the art will recognize that these principles can be applied to any electronic device that requires a high resolution delay line that is invariant to PVT variations. For example, time-to-digital controllers, light detection and ranging (LIDAR) systems, oscilloscopes, digital signal processors, audio equipment, phase-locked loops, delay-locked loops, and the like.

[0091] In the following claims, unless the specific terms "means for" or "step for" are used in a given claim, it is not intended that the claim be interpreted under 35 USC 112, paragraph 6.

[0092] The use of broader terms such as "comprising," "including," and "having" should be understood to provide support for narrower terms such as "consisting of," "consisting substantially of," and "consisting essentially of." Use of the terms "optionally," "may," "might," "possibly," and the like with respect to any element of an embodiment means that the element is not required, or, alternatively, the element is required, both alternatives being within the scope of the embodiment. Furthermore, references to examples are provided for illustrative purposes only and are not intended to be exclusive.

Claims

1. A control circuit, comprising: a first delay circuit comprising a first plurality of delay elements electrically connected in series, wherein the first delay circuit is configured to generate a first control voltage, and wherein the first plurality of delay elements exhibit a first delay time based at least in part on a first control voltage; as well as a second delay circuit comprising a second plurality of delay elements at least partially electrically connected in series, wherein the second delay circuit is configured to generate a second control voltage, wherein a first delay element group of the second plurality of delay elements exhibits a first delay time based at least in part on a first control voltage, and Wherein a second group of delay elements of the second plurality of delay elements exhibits a second delay time based at least in part on a second control voltage. 2 . The control circuit according to claim 1 , wherein the control circuit is configured to receive a reference clock, wherein the first delay time and the second delay time are at least partially based on the reference clock.

3. The control circuit of claim 2, wherein the reference clock is invariant to variations in process, voltage and / or temperature.

4. The control circuit according to claim 2, wherein the first delay circuit further comprises a first phase detector: wherein the first plurality of delay elements generates a first delayed signal, and Wherein the first control voltage is based at least in part on a phase difference between the first delayed signal and a reference clock.

5. The control circuit according to claim 2, wherein the second delay circuit further comprises: a first channel comprising a first subset of delay elements, the delay elements of the first subset belonging to a first delay element group, and the first channel further comprising a second delay element group; as well as Second channel. The control circuit of claim 5 , wherein the second channel does not include a delay element. 7 . The control circuit of claim 5 , wherein the number of delay elements of the first subset of delay elements is different from the number of delay elements of the first plurality of delay elements.

8. The control circuit of claim 5, wherein the number of delay elements of the first subset of delay elements is equal to the number of delay elements of the first plurality of delay elements.

9. The control circuit of claim 5, wherein the second channel comprises a second delay element subset, the second delay element subset belongs to the first delay element group, and the first delay element subset and the second delay element subset form the first delay element group.

10. The control circuit of claim 5 , wherein the second delay circuit further comprises a second phase detector configured to receive at an input the second delayed signal on the first channel and an additional signal on the second channel, wherein the second control voltage is based at least in part on a phase difference between the second delayed signal and the additional signal.

11. The control circuit of claim 1 , further comprising a multiplexer configured to receive the first control voltage and the second control voltage at inputs and to generate a first command signal based at least in part on the first control voltage and a second command signal based at least in part on the second control voltage. 12 . The control circuit according to claim 1 , wherein the second delay time is greater than the first delay time. 13 . The control circuit according to claim 1 , wherein a difference between the second delay time and the first delay time is smaller in absolute value than each of the second delay time and the first delay time.

14. An electronic circuit comprising: an additional delay line comprising a plurality of additional delay elements; as well as a plurality of control circuits according to claim 11, each control circuit being connected to a corresponding additional delay element, wherein each additional delay element is configured to receive a corresponding first command signal and a second command signal, and Each additional delay element exhibits a first delay time when receiving a first command signal, and exhibits a second delay time when receiving a second command signal.

15. The electronic circuit of claim 14 , wherein the delay resolution is proportional to a period of a reference clock, and a proportionality constant between the delay resolution and the reference clock is based at least in part on the number of delay elements in the first plurality of delay elements, the number of delay elements in the second delay element subset, and the number of delay elements in the second delay element group.

16. A method for delaying an electronic signal, the method comprising: receiving a reference clock at a control circuit; generating a first control voltage at a first delay circuit based at least in part on a reference clock, wherein the first delay circuit comprises a first plurality of delay elements at least partially electrically connected in series, and wherein the first plurality of delay elements exhibit a first delay time based at least in part on a first control voltage; generating a second control voltage at a second delay circuit based at least in part on a reference clock, wherein the second delay circuit comprises a second plurality of delay elements electrically connected in series, wherein a first group of delay elements in the second plurality of delay elements exhibits a first delay time based at least in part on a first control voltage, and wherein a second group of delay elements of the second plurality of delay elements exhibits a second delay time based at least in part on a second control voltage; and The electronic signal is delayed based on the first control voltage and the second control voltage.

17. The method of claim 16, wherein the second delay circuit further comprises: a first channel comprising a first subset of delay elements, the delay elements of the first subset belonging to a first delay element group, and the first channel further comprising a second delay element group; as well as The second channel includes a second delay element subgroup, the second delay element subgroup belongs to the first delay element group, and the first delay element subgroup and the second delay element subgroup form the first delay element group.

18. The method according to claim 17, further comprising: receiving a first control voltage and a second control voltage at a multiplexer; as well as A first command signal is generated based at least in part on the first control voltage and a second command signal is generated based at least in part on the second control voltage.

19. The method according to claim 18, further comprising: At an additional delay line including a plurality of additional delay elements, receiving a respective first command signal and a second command signal at each additional delay element, Each additional delay element exhibits a first delay time when receiving the first command signal, and exhibits a second delay time when receiving the second command signal.

20. A time-to-digital converter comprising: A first input signal; A second input signal; The electronic circuit of claim 14, configured to generate a delayed second input signal based at least in part on the second input signal; as well as A phase detector is configured to determine a signal offset between a first input signal and a delayed second input signal.

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