Transceiver circuit and control method thereof

Abstract

The invention discloses a transceiver circuit and a control method thereof, the transceiver circuit comprises a receiving circuit and a digital circuit, and the receiving circuit comprises a first mixer, a second mixer, a bias circuit, a composite filter and an analog-to-digital converter. In operation of the transceiver circuit, the digital circuit controls the bias circuit to sequentially switch the first bias to a plurality of first bias values, and the receiving circuit generates a plurality of first digital signals corresponding to the plurality of first bias values respectively and calculates a plurality of first quality parameters corresponding to the plurality of first bias values respectively according to the plurality of first digital signals; and the digital circuit controls the bias circuit so that the first bias has a bias value corresponding to an optimal quality parameter, wherein the optimal quality parameter is determined at least by the plurality of first quality parameters.

Description

Technical Field

[0001] The invention relates to a transceiver circuit and a control method thereof. Background Art

[0002] Low-IF receivers (low-IF receivers) have been widely used in many electronic devices. In order to achieve a better image rejection ratio (IMRR), low-IF receivers generally include two channels, in-phase and quadrature, and a complex filter (complex filter). In addition, in order to calibrate the gain and phase in the receiver and the corresponding impedance matching, multiple adjustable resistors are required in the complex filter, but this will increase the complexity of the resistor network and also increase the chip area. Summary of the invention

[0003] Therefore, one of the objects of the present invention is to provide a transceiver circuit, which can adjust the bias voltage of the mixer so that the transceiver circuit can still maintain a better image rejection ratio under a low current design, so that there is no need to use a complex resistor network in the composite filter, thereby solving the problems described in the prior art.

[0004] In one embodiment of the present invention, a transceiver circuit is disclosed, which includes a receiving circuit and a digital circuit, and the receiving circuit includes a first mixer, a second mixer, a bias circuit, a composite filter and an analog-to-digital converter. The first mixer is used to use a first oscillating signal to perform a mixing operation on an input signal to generate a first mixed signal. The second mixer is used to use a second oscillating signal to perform a mixing operation on the input signal to generate a second mixed signal. The bias circuit is used to generate a first bias to the first mixer and a second bias to the second mixer. The composite filter is used to generate a first intermediate frequency signal and a second intermediate frequency signal according to the first mixed signal and the second mixed signal. The analog-to-digital converter is used to perform an analog-to-digital conversion operation on an output intermediate frequency signal to generate a digital signal, wherein the output intermediate frequency signal is one of the first intermediate frequency signal and the second intermediate frequency signal. The digital circuit is coupled to the receiving circuit, wherein the digital circuit controls the bias circuit to sequentially switch the first bias voltage to a plurality of first bias values, and the receiving circuit generates a plurality of first digital signals respectively corresponding to the plurality of first bias values, and calculates a plurality of first quality parameters respectively corresponding to the plurality of first bias values ​​based on the first digital signals; and the digital circuit controls the bias circuit so that the first bias voltage has a bias value corresponding to an optimal quality parameter, wherein the optimal quality parameter is at least determined by the plurality of first quality parameters.

[0005] In one embodiment of the present invention, a transceiver circuit control method is disclosed, wherein the transceiver circuit includes a receiving circuit and a digital circuit, and the receiving circuit includes a first mixer, a second mixer, a bias circuit, a composite filter and an analog-to-digital converter. The first mixer is used to use a first oscillating signal to perform a mixing operation on an input signal to generate a first mixed signal. The second mixer is used to use a second oscillating signal to perform a mixing operation on the input signal to generate a second mixed signal. The bias circuit is used to generate a first bias to the first mixer and a second bias to the second mixer. The composite filter is used to generate a first intermediate frequency signal and a second intermediate frequency signal according to the first mixed signal and the second mixed signal. The analog-to-digital converter is used to perform an analog-to-digital conversion operation on an output intermediate frequency signal to generate a digital signal, wherein the output intermediate frequency signal is one of the first intermediate frequency signal and the second intermediate frequency signal. The control method comprises the following steps: controlling the bias circuit to sequentially switch the first bias voltage to a plurality of first bias voltage values ​​so that the receiving circuit generates a plurality of first digital signals respectively corresponding to the plurality of first bias voltage values; calculating a plurality of first quality parameters respectively corresponding to the plurality of first bias voltage values ​​according to the plurality of first digital signals; and controlling the bias circuit so that the first bias voltage has a bias voltage value corresponding to an optimal quality parameter, wherein the optimal quality parameter is at least determined by the plurality of first quality parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 4 is a schematic diagram of a transceiver circuit according to an embodiment of the present invention.

[0007] Figure 2 FIG. 4 is a flow chart of a control method of a transceiver circuit according to an embodiment of the present invention.

[0008] Figure 3 Schematic diagram of the desired signal after being processed by the mixer and the complex filter.

[0009] Figure 4 This is a schematic diagram of the image signal after being processed by the mixer and the composite filter.

[0010] Figure 5 FIG. 4 is a schematic diagram of a mixer according to an embodiment of the present invention.

[0011] Figure 6 FIG. 4 is a schematic diagram of a bias circuit according to an embodiment of the present invention.

[0012] Figure 7 FIG. 4 is a schematic diagram of a transceiver circuit according to an embodiment of the present invention.

[0013] Explanation of symbols

[0014] 100: Transceiver circuit

[0015] 102: Antenna

[0016] 104: Matching Circuit

[0017] 110: Receiving circuit

[0018] 111: Low Noise Amplifier

[0019] 112,113: Mixer

[0020] 114: Composite filter

[0021] 115: Switch module

[0022] 116: Programmable Gain Amplifier

[0023] 117: Analog-to-digital converter

[0024] 118: Bias circuit

[0025] 120: Transmission circuit

[0026] 121: Power Amplifier

[0027] 122,123: Mixer

[0028] 124,125: Filter

[0029] 126,127: Digital-to-analog converter

[0030] 130: Digital Circuits

[0031] 202-212: Steps

[0032] 500: Mixer

[0033] 600: Bias circuit

[0034] 610: Operational Amplifier

[0035] 700: Transceiver circuit

[0036] IF_I, IF_Q: intermediate frequency signal

[0037] RXLO_I, RXLO_Q: oscillation signal

[0038] TXLO_I,TXLO_Q: oscillation signal

[0039] SW1, SW2: switch

[0040] VB_I, VB_Q: Bias voltage

[0041] Vc: control signal

[0042] Vin_I, Vin_Q: signal after mixing

[0043] DC: Direct current

[0044] IF: Frequency

[0045] RXLO: Frequency of RXLO_I / RXLO_Q

[0046] TXLO: Frequency of TXLO_I / TXLO_Q

[0047] C1, C2, C3: capacitors

[0048] R1, R2, R3: resistors

[0049] INL input signal

[0050] M1, M2: transistors

[0051] Vin+, Vin-: signal after mixing

[0052] N1: First endpoint

[0053] N2: Second endpoint

[0054] Vref: reference voltage

[0055] VB1, VB2: Bias voltage

[0056] CT, Control Signal DETAILED DESCRIPTION

[0057] Figure 1 FIG. 1 is a schematic diagram of a transceiver circuit 100 according to an embodiment of the present invention. Figure 1 As shown, the transceiver circuit 100 includes a receiving circuit 110, a transmitting circuit 120 and a digital circuit 130, wherein the receiving circuit 110 includes a low noise amplifier 111, two mixers 112, 113, a composite filter 114, a switch module 115, a programmable gain amplifier (PGA) 116, an analog-to-digital converter 117 and a bias circuit 118, and the switch module 115 includes two switches SW1, SW2. The transmitting circuit 120 includes a power amplifier 121, two mixers 122, 123, two filters 124, 125, and two digital-to-analog converters 126, 127. In this embodiment, the receiving circuit 110 and the transmitting circuit 120 are connected to an antenna 102 through a matching circuit 104 to receive and transmit signals. In addition, in this embodiment, the receiving circuit 110 is a low intermediate frequency receiving circuit.

[0058] In the operation of the receiving circuit 110, the low noise amplifier 111 receives a receiving signal from the antenna 102 through the matching circuit 104, and processes the receiving signal to generate an input signal. Then, the mixer 112 uses an oscillating signal RXLO_I to mix the input signal to generate a mixed signal Vin_I, and the mixer 114 uses an oscillating signal RXLO_Q to mix the input signal to generate a mixed signal Vin_Q, wherein the oscillating signal RXLO_Q and the oscillating signal RXLO_I have the same frequency and a phase difference of 90 degrees, that is, the mixed signal Vin_I corresponds to an in-phase channel, and the mixed signal Vin_Q corresponds to a quadrature channel. Then, the composite filter 114 receives the mixed signals Vin_I and Vin_Q to generate intermediate frequency signals IF_I and IF_Q, wherein the intermediate frequency signal IF_I corresponds to the in-phase channel, and the intermediate frequency signal IF_Q corresponds to the quadrature channel. In addition, since the operation of the composite filter 114 requires the use of the signals of the in-phase channel and the quadrature channel at the same time, the composite filter 114 generates the intermediate frequency signal IF_I according to the mixed signals Vin_I and Vin_Q, and generates the intermediate frequency signal IF_Q according to the mixed signals Vin_I and Vin_Q. Since the composite filter 114 is well known to those skilled in the art, its detailed circuit architecture is not described in detail here. Next, the switch module 115 receives the intermediate frequency signals IF_I and IF_Q, and selects one of the intermediate frequency signals IF_I and IF_Q as an output intermediate frequency signal according to a control signal Vc. Specifically, when the control signal Vc indicates that the intermediate frequency signal IF_I is to be output, the switch module 115 turns on the switch SW1 and turns off the switch SW2 to output the intermediate frequency signal IF_I; and when the control signal Vc indicates that the intermediate frequency signal IF_Q is to be output, the switch module 115 turns on the switch SW2 and turns off the switch SW1 to output the intermediate frequency signal IF_Q. Next, the programmable gain amplifier 116 amplifies the output intermediate frequency signal to generate an amplified intermediate frequency signal, and the analog-to-digital converter 117 performs an analog-to-digital conversion operation on the amplified intermediate frequency signal to generate a digital signal to the digital circuit 130 for subsequent processing.

[0059] In the operation of the receiving circuit 110, since the switch module 115 only selects one of the intermediate frequency signals IF_I and IF_Q as the output intermediate frequency signal, the receiving circuit 110 only needs to set up a programmable gain amplifier 116 and an analog-to-digital converter 117 to process the intermediate frequency signal IF_I or the intermediate frequency signal IF_Q, instead of setting up two sets of circuits to process the intermediate frequency signals IF_I and IF_Q at the same time as in the prior art. Therefore, the receiving circuit 110 of this embodiment can effectively reduce the chip area and power consumption.

[0060] However, since the circuits and signals in the in-phase channel and the quadrature channel of the receiving circuit 110 are not completely matched, for example, the phase difference of the oscillation signals RXLO_I and RXLO_Q is not exactly 90 degrees, and the gains of the paths are not exactly the same, the responses of the composite filter 114 in the in-phase channel and the quadrature channel are inconsistent, which in turn causes the intermediate frequency signals IF_I and IF_Q to have different signal qualities. As described above, in order to allow the receiving circuit 110 to generate a better digital signal to the digital circuit 130 and reduce the complexity of the design of the composite filter 114, the present embodiment further proposes a method for adjusting the bias voltage of the mixers 112 and 113 and automatically determining which of the intermediate frequency signals IF_I and IF_Q has a better signal quality, and controlling the switch module 115 to select the intermediate frequency signal with a better signal quality from the intermediate frequency signals IF_I and IF_Q.

[0061] Figure 2 Flow chart of a control method of the transceiver circuit 100 according to an embodiment of the present invention. In step 200, the process starts, and the transceiver circuit 100 is powered on and starts running. In step 202, the bias circuit 118 is controlled to sequentially generate a plurality of bias voltages VB_I with different values ​​to the mixer 112, and generate a bias voltage VB_Q with a preset value to the mixer 113, and for any bias voltage among the plurality of bias voltages VB_I, the digital circuit 130 determines the image suppression ratio (IMRR) (i.e., corresponding to a quality parameter) of the intermediate frequency signal IF_I of the in-phase channel and the intermediate frequency signal IF_Q of the quadrature channel. In detail, for any bias voltage among the plurality of bias voltages VB_I, refer to Figure 1 and Figure 3 , Figure 4First, the digital circuit 130 generates two digital test signals to the digital-to-analog converters 126 and 127 to generate two analog signals. Then, the two analog signals are processed by the filters 124 and 125 to generate a first filtered signal and a second filtered signal, respectively, and the mixer 122 uses an oscillation signal TXLO_I to mix the first filtered signal to generate a first mixed signal, and the mixer 123 uses an oscillation signal TXLO_Q to mix the second filtered signal to generate a second mixed signal, wherein the oscillation signal TXLO_Q and the oscillation signal TXLO_I have the same frequency and a phase difference of 90 degrees. Then, the first mixed signal and the second mixed signal are combined and processed by the power amplifier 121 to generate a first test signal to the matching circuit 104. In this embodiment, the first test signal is used to represent a desired signal, and the frequency difference between the oscillation signal TXLO_I / TXLO_Q and the oscillation signal RXLO_I / RXLO_Q is Figure 3 The "IF" shown, where Figure 3 The frequency of the oscillation signal TXLO_I / TXLO_Q is denoted by “TXLO”, and the frequency of the oscillation signal RXLO_I / RXLO_Q is denoted by “RXLO.” In addition, the frequency of the desired signal is within the in-band frequency band of the composite filter 114 .

[0062] Next, the receiving circuit 110 receives the first test signal generated by the transmitting circuit 120 through the matching circuit 104, and processes the first test signal as a receiving signal. At this time, the digital circuit 130 can first generate a control signal Vc to control the switch module 115 to select the intermediate frequency signal IF_I. Figure 3 As shown, after being processed by the mixers 112 / 113 and the composite filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "IF", wherein the intermediate frequency signals IF_I and IF_Q are close to direct current "DC". It should be noted that Figure 3 The response of the composite filter 114 shown is an ideal state, and in actual state, due to the mismatch between the in-phase channel and the quadrature channel, the response of the composite filter 114 is not completely symmetrical. Next, since the switch module 115 has been controlled to output the intermediate frequency signal IF_I, the programmable gain amplifier 116 and the analog-to-digital converter 117 process the intermediate frequency signal IF_I to generate a digital signal to the digital circuit 130, so that the digital circuit 130 can determine the strength of the intermediate frequency signal IF_I having the desired signal.

[0063] Next, the digital circuit 130 generates two digital test signals to the transmitting circuit 120 again, and the transmitting circuit 120 performs similar operations to generate a second test signal to the matching circuit 104. Figure 4 In this embodiment, the second test signal is used to indicate the Figure 4 The frequency difference between the oscillation signal TXLO_I / TXLO_Q and the oscillation signal RXLO_I / RXLO_Q is Figure 4 The "IF" shown, that is, if Figure 3 The frequency TXLO of the first test signal shown is "RXLO+IF", then Figure 4 The frequency TXLO of the second test signal is shown as "RXLO-IF".

[0064] Next, the receiving circuit 110 receives the second test signal generated by the transmitting circuit 120 through the matching circuit 104 and processes the second test signal as a receiving signal. At this time, the digital circuit 130 has generated a control signal Vc to control the switch module 115 to select the intermediate frequency signal IF_I. Figure 3 As shown, after being processed by the mixers 112 / 113 and the composite filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "-IF". Next, since the switch module 115 has been controlled to output the intermediate frequency signal IF_I, the programmable gain amplifier 116 and the analog-to-digital converter 117 process the intermediate frequency signal IF_I to generate a digital signal to the digital circuit 130, so that the digital circuit 130 can determine the strength of the intermediate frequency signal IF_I with the mirror signal.

[0065] As described above, since the digital circuit 130 determines the strength of the desired signal and the strength of the image signal, the image suppression ratio of the intermediate frequency signal IF_I can be calculated. The calculation of the image suppression ratio can refer to Figure 4 As shown, that is, the degree of attenuation of the image signal after passing through the response of the composite filter 114, for example Figure 4 The image rejection ratio IMRR is indicated in the figure.

[0066] It should be noted that in Figure 3 , Figure 4 In the embodiment of the present invention, the frequency of the desired signal is "RXLO+IF", and the frequency of the image signal is "RXLO-IF", but the present invention is not limited thereto. In other embodiments, the frequency of the desired signal may be "RXLO-IF", the frequency of the image signal may be "RXLO+IF", and the center frequency of the composite filter 114 may be located near "RXLO-IF", and these design changes should fall within the scope of the present invention.

[0067] Then, similarly, the digital circuit 130 generates two digital test signals to the transmission circuit 120 again, and the transmission circuit 120 performs similar operations to generate a third test signal to the matching circuit 104. In this embodiment, the third test signal is used to indicate Figure 3 The desired signal is shown in FIG. 1 , and the frequency difference between the oscillation signal TXLO_I / TXLO_Q and the oscillation signal RXLO_I / RXLO_Q is Figure 3 The "IF" shown.

[0068] Next, the receiving circuit 110 receives the third test signal generated by the transmitting circuit 120 through the matching circuit 104, and processes the third test signal as a receiving signal. At this time, the digital circuit 130 can first generate a control signal Vc to control the switch module 115 to select the intermediate frequency signal IF_Q. Figure 3 As shown, after being processed by the mixers 112 / 113 and the composite filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "IF". Since the switch module 115 has been controlled to output the intermediate frequency signal IF_Q, the programmable gain amplifier 116 and the analog-to-digital converter 117 process the intermediate frequency signal IF_Q to generate a digital signal to the digital circuit 130, so that the digital circuit 130 can determine the strength of the intermediate frequency signal IF_Q having the desired signal.

[0069] Next, the digital circuit 130 generates two digital test signals to the transmission circuit 120 again, and the transmission circuit 120 performs similar operations to generate a fourth test signal to the matching circuit 104. In this embodiment, the fourth test signal is used to represent the corresponding Figure 4 The frequency difference between the oscillation signal TXLO_I / TXLO_Q and the oscillation signal RXLO_I / RXLO_Q is Figure 4 The "IF" shown, that is, if Figure 3 The frequency TXLO of the third test signal shown is "RXLO+IF", then Figure 4 The frequency TXLO of the fourth test signal is shown as "RXLO-IF".

[0070] Next, the receiving circuit 110 receives the fourth test signal generated by the transmitting circuit 120 through the matching circuit 104 and processes the fourth test signal as a receiving signal. At this time, the digital circuit 130 has generated a control signal Vc to control the switch module 115 to select the intermediate frequency signal IF_Q. Figure 4As shown, after being processed by the mixers 112 / 113 and the composite filter 114, the intermediate frequency signals IF_I and IF_Q contain components corresponding to the frequency "-IF". Next, since the switch module 115 has been controlled to output the intermediate frequency signal IF_Q, the programmable gain amplifier 116 and the analog-to-digital converter 117 process the intermediate frequency signal IF_Q to generate a digital signal to the digital circuit 130, so that the digital circuit 130 can determine the strength of the intermediate frequency signal IF_Q with the mirror signal.

[0071] As described above, since the digital circuit 130 determines the strength of the desired signal and the strength of the image signal, the image rejection ratio of the intermediate frequency signal IF_Q can be calculated.

[0072] It should be noted that the order of generating and processing the above-mentioned first test signal, second test signal, third test signal and fourth test signal is not a limitation of the present invention, that is, the order in which the digital circuit 130 determines the strength of the intermediate frequency signal IF_I having the desired signal, the strength of the intermediate frequency signal IF_I having the mirror signal, the strength of the intermediate frequency signal IF_Q having the desired signal, and the strength of the intermediate frequency signal IF_Q having the mirror signal can be changed arbitrarily without affecting the concept of the present invention.

[0073] It should be noted that the above calculation of the image rejection ratio of the intermediate frequency signals IF_Q, IF_Q is only used as an example and is not a limitation of the present invention. In the embodiment of the present invention, the image rejection ratio can be replaced by any quality parameter that can reflect the attenuation degree of the image signal of the intermediate frequency signals IF_Q, IF_Q.

[0074] As described above, in step 202, if the bias circuit 118 can switch the bias voltage VB_I to N bias values ​​(where N is a positive integer greater than or equal to 2), then in step 202, image suppression ratios of N intermediate frequency signals IF_I corresponding to the N bias voltages VB_I, and image suppression ratios of N intermediate frequency signals IF_Q corresponding to the N bias voltages, will be generated.

[0075] In step 204, the digital circuit 130 selects an optimal value from among the image rejection ratios of the intermediate frequency signals IF_I and the image rejection ratios of the intermediate frequency signals IF_Q generated in step 202 as a first value, and the digital circuit 130 records the first value and the corresponding bias voltage VB_I and channel (i.e., in-phase channel or quadrature channel).

[0076] In step 206, the bias circuit 118 is controlled to sequentially generate a plurality of bias voltages VB_Q having different values ​​to the mixer 113, and to generate a bias voltage VB_I having a preset value to the mixer 112, and for any bias voltage among the plurality of bias voltages VB_Q, the digital circuit 130 determines the image rejection ratio of the intermediate frequency signal IF_I of the in-phase channel and the intermediate frequency signal IF_Q of the quadrature channel. That is, if the bias circuit 118 can switch the bias voltage VB_Q to M bias values ​​(where M is a positive integer greater than or equal to 2), then in step 206, the image rejection ratios of the M intermediate frequency signals IF_I corresponding to the M bias values, and the image rejection ratios of the M intermediate frequency signals IF_Q corresponding to the M bias values, will be generated. Since the detailed operation of step 206 can refer to the contents of the embodiment of step 202 above, the detailed operation will not be repeated here.

[0077] In step 208, the digital circuit 130 selects an optimal value from among the image rejection ratios of the intermediate frequency signals IF_I and the image rejection ratios of the intermediate frequency signals IF_Q generated in step 206 as a second value, and the digital circuit 130 records the second value and the corresponding bias voltage VB_Q and channel (i.e., the in-phase channel or the quadrature channel).

[0078] In step 210 , the digital circuit 130 selects a value having a better image rejection ratio between the first value and the second value.

[0079] It should be noted that the above steps 204, 208, and 210 can be integrated to directly determine the best image rejection ratio and the corresponding bias voltages VB_I, VB_Q, and channels, without having to first determine the first value and the second value. In other words, the digital circuit 130 can directly determine an best image rejection ratio (i.e., best quality parameter) based on the image rejection ratios (i.e., first quality parameters) of the plurality of intermediate frequency signals IF_I and the plurality of intermediate frequency signals IF_Q corresponding to different bias voltages VB_I generated in step 202, and the image rejection ratios (i.e., second quality parameters) of the plurality of intermediate frequency signals IF_I and the plurality of intermediate frequency signals IF_Q corresponding to different bias voltages VB_Q generated in step 206.

[0080] In step 212, after determining the best image rejection ratio, in the subsequent operation of the transceiver circuit 100, the digital circuit 130 can control the bias circuit 118 to generate bias voltages VB_I and VB_Q corresponding to the best image rejection ratio to the mixers 112 and 113, and can also generate a control signal Vc to control the switch module 115 to select the intermediate frequency signal corresponding to the best image rejection ratio as the output intermediate frequency signal for subsequent processing by the programmable gain amplifier 116 and the analog-to-digital converter 117.

[0081] Figure 5 FIG. 5 is a schematic diagram of a mixer 500 according to an embodiment of the present invention, wherein the mixer 500 can be used to implement Figure 1 The mixers 112 and 113 are shown. Figure 5 As shown, the mixer 500 includes capacitors C1, C2, C3, two resistors R1, R2 and two transistors M1, M2. In the operation of the mixer 500, the bias voltage VB is input to the gates of the transistors M1, M2 through the resistors R1, R2, and the transistors M1, M2 are respectively controlled by the oscillation signals LO+, LO- to perform a mixing operation (down-conversion operation) on an input signal IN to generate a differential mixed signal Vin+, Vin-. Figure 5 In the embodiment, LO+ and LO- correspond to Figure 1 RXLO_I or RXLO_Q, VB corresponds to Figure 1 VB_I or VB_Q, and Vin+, Vin- correspond to Figure 1 Vin_I or Vin_Q.

[0082] It should be noted that Figure 5 The mixer 500 shown is only used as an example and is not intended to limit the present invention. In other embodiments, as long as the bias voltages VB_I and VB_Q generated by the bias circuit 118 are input to the mixer as the gate bias voltages of the transistors, Figure 1 The mixers 112 and 113 may be implemented by using other single balanced mixers or double balanced mixers.

[0083] Figure 6 FIG. 6 is a schematic diagram of a bias circuit 600 according to an embodiment of the present invention, wherein the bias circuit 600 can be used to implement Figure 1 The bias circuit 118 is shown. Figure 6 As shown, the bias circuit 600 includes an operational amplifier 610, a resistor R3 and four switch current sources, wherein an input terminal of the operational amplifier 610 is connected to a reference voltage Vref, and an output terminal of the operational amplifier 610 is connected to the first terminal N1. The resistor R3 is coupled between the first terminal N1 and the second terminal N2. The first switch current source is coupled between the supply voltage VDD and the first terminal N1; the second switch current source is coupled between the supply voltage VDD and the second terminal N2; the third switch current source is coupled between the ground voltage and the first terminal N1; and the fourth switch current source is coupled between the ground voltage and the second terminal N2. The four switch current sources are respectively controlled by the control signal CT and In the operation of the bias circuit 600, the operational amplifier 610 receives the reference voltage Vref and controls the bias circuit 600 by changing the control signals CT, The level of the bias voltages VB1 and VB2 can be changed by changing the level of the bias voltages VB1 and VB2, where the bias voltage VB1 shown in the figure can be Figure 1 The bias voltage VB_I and VB_Q are one of them, and the bias voltage VB2 can be Figure 1 For example, if the bias voltage VB1 is used as Figure 1 The bias voltage VB_I and the bias voltage VB2 are used as Figure 1 If the bias voltage VB_Q is VB2, when the control signal CT enables the corresponding switch (for example, CT=1), the bias voltage VB2 will be lower than the bias voltage VB1, making the bias voltage VB_Q lower than the bias voltage VB_I, thereby reducing the gain of the orthogonal channel. Figure 1 The bias voltage VB_Q, and the bias voltage VB2 as Figure 1 If the bias voltage VB_I is VB2, when the control signal CT enables the corresponding switch, the bias voltage VB2 will be lower than the bias voltage VB1, making the bias voltage VB_I lower than the bias voltage VB_Q, thereby reducing the gain of the in-phase channel. Figure 1 The bias voltage VB_I and the bias voltage VB2 are used as Figure 1 The bias voltage VB_Q, then the control signal When the corresponding switch is enabled (e.g., CT=0), the bias voltage VB2 will be higher than the bias voltage VB1, thereby increasing the gain of the quadrature channel. Figure 1 The bias voltage VB_Q, and the bias voltage VB2 as Figure 1 The bias voltage VB_I, then the control signal When the corresponding switch is enabled, the bias voltage VB2 will be higher than the bias voltage VB1, thereby increasing the gain of the in-phase channel. Figure 6 The bias circuit 600 shown is provided for illustrative purposes only and is not intended to be limiting of the present invention.

[0084] In another embodiment of the present invention, Figure 1 The transceiver circuit 100 shown is modified to disconnect the path from the in-phase channel or the quadrature channel to the programmable gain amplifier 116, which can further reduce the chip area and thus reduce the manufacturing cost. Figure 7 , which is a schematic diagram of a transceiver circuit 700 according to an embodiment of the present invention, wherein the transceiver circuit 700 and Figure 1 The difference between the transceiver circuit shown is that the transceiver circuit 700 does not have the switch module 115, and the programmable gain amplifier 116 only receives the intermediate frequency signal IF_I generated by the in-phase channel. In the operation of the transceiver circuit 700, it is similar to Figure 2However, since the programmable gain amplifier 116 only receives the intermediate frequency signal IF_I generated by the in-phase channel, only the image suppression ratios of the intermediate frequency signals IF_I corresponding to the multiple bias voltages VB_I are generated in step 202, and only the image suppression ratios of the intermediate frequency signals IF_I corresponding to the multiple bias voltages VB_Q are generated in step 206. Figure 1 to Figure 4 The operation of the transceiver circuit 700 should be understood after reading the embodiments, so other details are not repeated here.

[0085] In another embodiment of the present invention, the programmable gain amplifier 116 of the transceiver circuit 700 only receives the intermediate frequency signal IF_Q generated by the orthogonal channel, that is, only the image rejection ratios of the intermediate frequency signals IF_Q corresponding to the multiple bias voltages VB_I are generated in step 202, and only the image rejection ratios of the intermediate frequency signals IF_Q corresponding to the multiple bias voltages VB_Q are generated in step 206. These design changes should belong to the scope of the present invention.

[0086] In one embodiment of the present invention, the bias voltage VB_I or the bias voltage VB_Q generated by the bias circuit 118 of the transceiver circuit 700 may be a fixed value, and need not be switchable to a plurality of different bias values. For example, the bias voltage VB_Q generated by the bias circuit 118 may be a fixed value, and at this time Figure 2 Steps 206, 208, and 210 in step 204 can be removed, that is, the digital circuit 130 in step 204 directly selects the best image rejection ratio (that is, the best quality parameter) from the image rejection ratios (that is, the first quality parameters) of the intermediate frequency signal IF_I for use in step 212.

[0087] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A transceiver circuit, comprising: A receiving circuit, wherein the receiving circuit comprises: A first mixer, configured to use a first oscillating signal to perform a mixing operation on an input signal to generate a first mixed signal; a second mixer for mixing the input signal with a second oscillating signal to generate a second mixed signal; a bias circuit for generating a first bias voltage to the first mixer and generating a second bias voltage to the second mixer; a composite filter, for generating a first intermediate frequency signal and a second intermediate frequency signal according to the first mixed signal and the second mixed signal; and an analog-to-digital converter for performing an analog-to-digital conversion operation on an output intermediate frequency signal to generate a digital signal, wherein the output intermediate frequency signal is one of the first intermediate frequency signal and the second intermediate frequency signal; and a digital circuit coupled to the receiving circuit, wherein the digital circuit controls the bias circuit to sequentially switch the first bias voltage to a plurality of first bias voltage values, and the receiving circuit generates a plurality of first digital signals respectively corresponding to the plurality of first bias voltage values, and calculates a plurality of first quality parameters respectively corresponding to the plurality of first bias voltage values ​​based on the first digital signals; and the digital circuit controls the bias circuit so that the first bias voltage has a bias voltage value corresponding to an optimal quality parameter, wherein the optimal quality parameter is at least determined by the plurality of first quality parameters.

2. The transceiver circuit as claimed in claim 1 , wherein the digital circuit further controls the bias circuit to sequentially switch the second bias to a plurality of second bias values, and the receiving circuit generates a plurality of second digital signals respectively corresponding to the plurality of second bias values, and calculates a plurality of second quality parameters respectively corresponding to the plurality of second bias values ​​based on the second digital signals; and the digital circuit selects the best quality parameter from the first quality parameter and the plurality of second quality parameters.

3. The transceiver circuit as claimed in claim 1, wherein the receiving circuit further comprises: a switch module, for receiving the first intermediate frequency signal and the second intermediate frequency signal, and selecting one of the first intermediate frequency signal and the second intermediate frequency signal according to a control signal to generate the output intermediate frequency signal; The digital circuit generates the control signal to sequentially select one of the first intermediate frequency signal and the second intermediate frequency signal as the output intermediate frequency signal, and in response to using the first intermediate frequency signal and the second intermediate frequency signal as the output intermediate frequency signal, the digital circuit controls the bias circuit to sequentially switch the first bias to the plurality of first bias values, so that the plurality of first quality parameters include a quality parameter corresponding to the first intermediate frequency signal and a quality parameter corresponding to the second intermediate frequency signal.

4. The transceiver circuit as claimed in claim 3, wherein the digital circuit further controls the bias circuit to sequentially switch the second bias to a plurality of second bias values, and the receiving circuit generates a plurality of second digital signals respectively corresponding to the plurality of second bias values, and calculates a plurality of second quality parameters respectively corresponding to the plurality of second bias values ​​based on the second digital signals; and the digital circuit selects the best quality parameter from the first quality parameter and the plurality of second quality parameters.

5. The transceiver circuit as claimed in claim 4, wherein for using the first intermediate frequency signal and the second intermediate frequency signal as the output intermediate frequency signal, the digital circuit controls the bias circuit to sequentially switch the second bias to the plurality of second bias values, so that the plurality of second quality parameters include a quality parameter corresponding to the first intermediate frequency signal and a quality parameter corresponding to the second intermediate frequency signal. 6 . The transceiver circuit as claimed in claim 1 , wherein each of the plurality of first quality parameters is an image rejection ratio. 7 . The transceiver circuit as claimed in claim 1 , wherein the first mixer comprises at least one transistor, and the bias circuit generates the first bias voltage to a gate of the at least one transistor in the first mixer.

8. The transceiver circuit as claimed in claim 1, wherein the bias circuit comprises: an operational amplifier, wherein an input terminal of the operational amplifier is connected to a reference voltage, and an output terminal of the operational amplifier is connected to a first terminal; A resistor coupled between the first terminal and a second terminal; A first switch current source is coupled between a supply voltage and the first terminal; A second switch current source is coupled between the supply voltage and the second terminal; A third switch current source is coupled between a ground voltage and the first terminal; as well as a fourth switch current source, coupled between the ground voltage and the second terminal; The first end point or the second end point is used to generate the first bias voltage.

9. A method for controlling a transceiver circuit, wherein the transceiver circuit comprises: A receiving circuit, wherein the receiving circuit comprises: A first mixer, configured to use a first oscillating signal to perform a mixing operation on an input signal to generate a first mixed signal; a second mixer for mixing the input signal with a second oscillating signal to generate a second mixed signal; a bias circuit for generating a first bias voltage to the first mixer and generating a second bias voltage to the second mixer; a composite filter for generating a first intermediate frequency signal and a second intermediate frequency signal according to the first mixed signal and the second mixed signal; and an analog-to-digital converter for performing an analog-to-digital conversion operation on an output intermediate frequency signal to generate a digital signal, wherein the output intermediate frequency signal is one of the first intermediate frequency signal and the second intermediate frequency signal; and The control method includes: Controlling the bias circuit to sequentially switch the first bias to a plurality of first bias values, so that the receiving circuit generates a plurality of first digital signals respectively corresponding to the plurality of first bias values; Calculating a plurality of first quality parameters respectively corresponding to the plurality of first bias values ​​according to the plurality of first digital signals; as well as The bias circuit is controlled so that the first bias has a bias value corresponding to a best quality parameter, wherein the best quality parameter is at least determined by the plurality of first quality parameters.

10. The control method according to claim 9, further comprising: Controlling the bias circuit to sequentially switch the second bias to a plurality of second bias values, so that the receiving circuit generates a plurality of second digital signals respectively corresponding to the plurality of second bias values; Calculating a plurality of second quality parameters respectively corresponding to the plurality of second bias values ​​according to the plurality of second digital signals; as well as The best quality parameter is selected from the first quality parameter and the plurality of second quality parameters.

Images