Data processing method, encryption and decryption algorithm module, chip and electronic equipment

Abstract

The embodiment of the invention provides a data processing method, an encryption and decryption algorithm module, a chip and electronic equipment, and relates to the technical field of computers, the data processing method is applied to the encryption and decryption algorithm module, and the encryption and decryption algorithm module comprises a transposition distribution sub-module, a transposition reading sub-module, an unpacking and packaging sub-module and a plurality of operation sub-modules. The method comprises the following steps: receiving a plurality of to-be-processed data packets through a transpose distribution sub-module, extracting data from each to-be-processed data packet in sequence, combining the data into one data packet, and sending a plurality of first transpose data packets to an unpacking and grouping sub-module in sequence; splitting the first transposed data packet into a plurality of first sub-data packets through an unpacking and grouping sub-module, and respectively sending the plurality of first sub-data packets to respective corresponding operation sub-modules; performing encryption or decryption processing on the data through the operation sub-module to obtain a processing result corresponding to the to-be-processed data packet; and reading the processing result through the transposition reading sub-module, and generating a processed data packet.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of computer technology, and in particular to a data processing method, an encryption and decryption algorithm module, a chip, and an electronic device. Background Art

[0002] With the development of computer technology and network technology, illegal intrusion or system attacks seriously threaten the security of computer systems, especially attacks on computer memory data will cause great harm. The general protection method for memory data is: use the encryption and decryption algorithm module to encrypt the memory data when writing the memory data to the memory, and use the encryption and decryption algorithm module to decrypt the data when reading the memory data from the memory.

[0003] In the prior art, the SM4 algorithm is a commonly used encryption and decryption algorithm in the encryption and decryption algorithm module. The algorithm core of the encryption and decryption algorithm module is an operation submodule, to which the encryption and decryption algorithm module sends a received data packet, and the operation submodule performs encryption and decryption operations on the data of the data packet. The operation process requires the use of a round function to perform 32 rounds of iterative operations and one reverse transformation, and then the encryption and decryption algorithm module obtains and outputs the processing result from the operation submodule.

[0004] However, since the operation submodule can only encrypt and decrypt one data packet at a time, and the operation process of the operation submodule takes a long time and has a low operation speed, the existing method of encrypting and decrypting data has the problem of low operation efficiency. Summary of the invention

[0005] The embodiments of the present invention provide a data processing method, an encryption and decryption algorithm module, a chip and an electronic device, which can solve the problem of low computational efficiency in the prior art methods for encrypting and decrypting data.

[0006] In order to solve the above problem, an embodiment of the present invention discloses a data processing method, which is applied to an encryption and decryption algorithm module, wherein the encryption and decryption algorithm module includes a transposition distribution submodule, a transposition reading submodule, an unpacking and packaging submodule, and a plurality of operation submodules, wherein the interface bit width of the transposition distribution submodule is greater than the interface bit width of the operation submodule, and the method includes:

[0007] The transposition distribution submodule receives a plurality of data packets to be processed, extracts data from each of the data packets to be processed in turn and merges them into one data packet to obtain a plurality of first transposed data packets, and sends the plurality of first transposed data packets to the unpacking and packaging submodule in turn; the number of the plurality of data packets to be processed is consistent with the number of the plurality of operation submodules, and each data packet to be processed is processed by one operation submodule;

[0008] For any of the first transposed data packets, the first transposed data packet is split into a plurality of first sub-data packets by the unpacking and packing sub-module, and the plurality of first sub-data packets are respectively sent to the corresponding operation sub-modules; the data length of the first sub-data packet matches the interface bit width of the operation sub-module;

[0009] For any of the operation submodules, the operation submodule combines the received first sub-data packets into a data packet to be processed corresponding to the operation submodule, and encrypts or decrypts the data in the data packet to be processed to obtain a processing result corresponding to the data packet to be processed;

[0010] The processing results corresponding to each of the data packets to be processed are read from the multiple operation submodules through the transposition reading submodule, and processed data packets corresponding to each of the data packets to be processed are generated according to the processing results corresponding to each of the data packets to be processed.

[0011] On the other hand, an embodiment of the present invention discloses an encryption and decryption algorithm module for executing the data processing method as described above; the encryption and decryption algorithm module includes a transposition distribution submodule, a transposition reading submodule, an unpacking and packaging submodule and a plurality of operation submodules;

[0012] The transposition distribution submodule is used to receive a plurality of data packets to be processed, and extract data from each of the data packets to be processed in turn and merge them into one data packet to obtain a plurality of first transposed data packets, and send the plurality of first transposed data packets to the unpacking and packaging submodule in turn; the number of the plurality of data packets to be processed is consistent with the number of the plurality of operation submodules, and each data packet to be processed is processed by one operation submodule;

[0013] For any of the first transposed data packets, the first transposed data packet is split into a plurality of first sub-data packets by the unpacking and packing sub-module, and the plurality of first sub-data packets are respectively sent to the corresponding operation sub-modules; the data length of the first sub-data packet matches the interface bit width of the operation sub-module;

[0014] The operation submodule is used to merge the received first sub-data packets into a data packet to be processed corresponding to the operation submodule, and perform encryption or decryption processing on the data in the data packet to be processed to obtain a processing result corresponding to the data packet to be processed;

[0015] The transposition reading submodule is used to read the processing results corresponding to each of the data packets to be processed from the multiple operation submodules, and generate processed data packets corresponding to each of the data packets to be processed according to the processing results corresponding to each of the data packets to be processed.

[0016] On the other hand, an embodiment of the present invention discloses a chip, which includes the encryption and decryption algorithm module as described above, and is used to execute the data processing method as described above.

[0017] On the other hand, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the data processing method described above.

[0018] An embodiment of the present invention further discloses a readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned data processing method.

[0019] The embodiment of the present invention includes the following advantages: the encryption and decryption algorithm module can receive multiple data packets to be processed at one time, which are the same number as the number of operation submodules, through the transposition distribution submodule, and the multiple data packets to be processed are processed by multiple operation submodules respectively. The data are extracted from each data packet to be processed in turn through the transposition distribution submodule and merged into one data packet, so that the first transposed data packet obtained by each extraction and merging operation includes data from each data packet to be processed, and then the multiple first transposed data packets are sent to the unpacking and packet grouping submodule in turn through the transposition distribution submodule, so that each data packet to be processed can be sent to the unpacking and packet grouping submodule in parallel, and then each first transposed data packet is split into multiple first sub-data packets whose data length matches the interface bit width of the operation submodule through the unpacking and packet grouping submodule, and then sent to the corresponding operation subdevices respectively, so that the operation submodule can successfully receive the first sub-data packet, and the received first sub-data packet is the data from the data packet to be processed corresponding to the operation submodule, so that each data packet to be processed can be sent to the corresponding operation submodule in parallel, thereby improving the parallelism of the encryption and decryption algorithm module. Furthermore, the data packets to be processed are encrypted or decrypted through the operation submodule to obtain corresponding processing results, and the processing results corresponding to each data packet to be processed are read out through the transposition reading submodule to generate processed data packets corresponding to each data packet to be processed, thereby completing the encryption or decryption processing of multiple data packets to be processed. This can increase the amount of data received and encrypted and decrypted at a single time, so that more data can be processed in the same time, and the overall operation speed can be correspondingly improved, which can improve the operation efficiency of encryption and decryption of data to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0021] Figure 1 is a flow chart of steps of a data processing method provided by an embodiment of the present invention;

[0022] Figure 2 It is a transposition distribution logic diagram of a data processing method provided by an embodiment of the present invention;

[0023] Figure 3 is a state diagram of a third state machine provided by an embodiment of the present invention;

[0024] Figure 4 is a state diagram of a data reading state machine provided by an embodiment of the present invention;

[0025] Figure 5 is a state diagram of a data writing state machine provided by an embodiment of the present invention;

[0026] Figure 6 It is a structural diagram of an encryption and decryption algorithm module provided by an embodiment of the present invention;

[0027] Figure 7 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] Reference Figure 1 , shows a flow chart of the steps of a data processing method provided by an embodiment of the present invention, the data processing method is applied to an encryption and decryption algorithm module, the encryption and decryption algorithm module includes a transposition distribution submodule, a transposition reading submodule, an unpacking and packaging submodule and a plurality of operation submodules, such as Figure 1 As shown, the data processing method specifically includes the following steps:

[0030] Step 101, receiving a plurality of data packets to be processed through the transposition distribution submodule, and extracting data from each of the data packets to be processed in turn and merging them into one data packet to obtain a plurality of first transposed data packets, and sending the plurality of first transposed data packets to the unpacking and packaging submodule in turn; the number of the plurality of data packets to be processed is consistent with the number of the plurality of operation submodules, and each data packet to be processed is processed by an operation submodule.

[0031] In an embodiment of the present invention, the encryption and decryption algorithm module can be used to encrypt data before writing the data into the memory, and to decrypt the encrypted data when reading the data from the memory. The encryption and decryption algorithm module can protect the reading and writing process of the memory data through the encryption and decryption algorithm to prevent illegal intrusion or system attack on the memory data. Among them, the encryption and decryption algorithm can adopt a common cryptographic standard, and the embodiment of the present invention does not limit this. For example, the SM4 encryption and decryption algorithm can be used. The SM4 encryption and decryption algorithm is a grouping algorithm. The data group length is 128 bits and the key length is also 128 bits. Among them, the encryption algorithm and the key expansion algorithm both adopt a 32-round nonlinear iterative structure. The decryption algorithm has the same structure as the encryption algorithm, except that the order of using the round keys is reversed. The round keys of the decryption algorithm are the reverse order of the round keys of the encryption algorithm.

[0032] In an embodiment of the present invention, the encryption and decryption algorithm module includes a transposition distribution submodule, a transposition reading submodule, a package unpacking and assembly submodule, and a plurality of operation submodules. Specifically, the number of the operation submodules is N, and N can be a positive integer greater than or equal to 2. A plurality of data packets to be processed are received by the transposition distribution submodule, and the number of received data packets to be processed is equal to N, that is, the number of the plurality of data packets to be processed is consistent with the number of the plurality of operation submodules, so that one operation submodule corresponds to one data packet to be processed, and each data packet to be processed is processed by one operation submodule. Specifically, the transposition distribution submodule may include a data receiving port, and the transposition distribution submodule sequentially receives the plurality of data packets to be processed sent to the encryption and decryption algorithm module through the data receiving port.

[0033] For example, the encryption and decryption algorithm module can adopt the SM4 encryption and decryption algorithm, and adopt the electronic codebook (ECB) packet encryption mode, the data receiving port of the transposition distribution submodule can be a slave port of the 128-bit advanced extensible interface bus (AXI), and the transposition distribution submodule sequentially receives N 128-bit data packets to be processed from the AXI slave port in an outstanding manner. Among them, the AXI bus supports outstanding transmission access, which means that the AXI bus can continue to send data without waiting for the receiver to respond, which can reduce data transmission delay and improve data transmission efficiency.

[0034] Optionally, the transposition distribution submodule may include a first register, which is used to store received data packets to be processed. When the transposition distribution submodule receives a data packet to be processed, the data packet to be processed may be temporarily stored in the first register until multiple data packets to be processed are received.

[0035] In the embodiment of the present invention, the corresponding relationship between the data packets to be processed and the operation submodules can be determined according to the size order of the module identifiers of the plurality of operation submodules and the data packet receiving order of the transposition distribution submodule receiving the data packets to be processed. For example, the encryption and decryption algorithm module includes 4 operation submodules, the transposition distribution submodule can sequentially receive 4 data packets to be processed and temporarily store them in the first register, and the operation submodules whose module identifier order is the same as the data packet receiving order and the data packets to be processed can be determined to have a corresponding relationship, that is, the data in the corresponding data packets to be processed are processed by the operation submodule.

[0036] In an embodiment of the present invention, the data length of the data packet to be processed received by the transposition distribution submodule matches the interface width of the transposition distribution submodule. For example, if the interface width of the transposition distribution submodule is 128 bits, the transposition distribution submodule can receive 128 bits of data packet to be processed at one time. In the case where the interface width of the transposition distribution submodule is greater than the interface width of the operation submodule, the data in a data packet to be processed requires multiple write operations before the data can be sent to the operation submodule. In the prior art, if the interface width of the SM4 algorithm module is 128 bits, and the interface width of the SM4 algorithm core is 32 bits, the data in a 128-bit data packet received by the SM4 algorithm module requires 4 write operations before the data can be sent to the SM4 algorithm core.

[0037] In an embodiment of the present invention, the interface width of the transposition distribution submodule may be P times the interface width of the operation submodule, where P is an integer greater than 1. The unpacking and packaging submodule is connected to the transposition distribution submodule and each operation submodule respectively. Among them, the interface width corresponding to the first interface connected between the unpacking and packaging submodule and the transposition distribution submodule is consistent with the interface width of the transposition distribution submodule, and the interface width corresponding to the second interface connected between the unpacking and packaging submodule and the operation submodule is consistent with the interface width of the operation submodule.

[0038] In an embodiment of the present invention, the data in each data packet to be processed can be divided according to the interface width of the operation submodule by the transposition distribution submodule to obtain multiple sub-data packets, and the data length of each sub-data packet matches the interface width of the operation submodule. For example, if the data packet to be processed is a 128-bit data packet and the interface width of the operation submodule is 32 bits, the data packet to be processed can be divided into 4 sub-data packets, and the data length of each sub-data packet is 32 bits. Then, the sub-data packets that need to be written into the corresponding operation submodules for the first time in each data packet to be processed are extracted and merged into one data packet to obtain the first first transposed data packet, and so on, data is extracted from each data packet to be processed in turn and merged into one data packet to obtain multiple first transposed data packets. Wherein, the data contained in any first transposed data packet comes from each data packet to be processed.

[0039] In the embodiment of the present invention, the multiple first transposed data packets can be sequentially sent to the unpacking and assembling submodule according to the order in which the first transposed data packets are generated by the transposition distribution submodule. Since any first transposed data packet contains a portion of data in each data packet to be processed, the multiple first transposed data packets are sequentially sent to the unpacking and assembling submodule by the transposition distribution submodule, so that each data packet to be processed can be sent to the unpacking and assembling submodule in parallel, thereby improving the parallelism of the encryption and decryption algorithm module.

[0040] Step 102: for any of the first transposed data packets, split the first transposed data packet into multiple first sub-data packets through the unpacking and packing sub-module, and send the multiple first sub-data packets to their respective corresponding operation sub-modules; the data length of the first sub-data packet matches the interface bit width of the operation sub-module.

[0041] In the embodiment of the present invention, for any first transposed data packet, the first transposed data packet can be split according to the target data length by the unpacking function of the unpacking and packing submodule, so that the first transposed data packet is split into a plurality of first sub-data packets. Wherein, the data length of any first sub-data packet is the target data length, and the target data length matches the interface width of the operation submodule. Specifically, the target data length can be determined according to the interface width of the operation submodule. For example, if the interface width of the operation submodule is 32 bits, the target data length can be 32 bits. This is only an example, and the embodiment of the present invention does not limit this.

[0042] In the embodiment of the present invention, for any first transposed data packet, since the first transposed data packet is obtained by dividing the data in each data packet to be processed according to the interface bit width of the operation submodule, and then extracting the divided sub-data packets from each data packet to be processed and then recombining them, the first transposed data packet is split according to the target data length by the unpacking and packing submodule, and the obtained multiple first sub-data packets belong to each data packet to be processed respectively.

[0043] In an embodiment of the present invention, for a first sub-data packet, the first sub-data packet can be sent to a corresponding operation sub-module through an unpacking and packaging sub-module. Specifically, the operation sub-module corresponding to the first sub-data packet can be determined according to the data packet to be processed to which the first sub-data packet belongs, and the operation sub-module corresponding to the data packet to be processed can be determined as the operation sub-module corresponding to the first sub-data packet. Among them, the operation sub-module corresponding to the data packet to be processed can refer to the size order of the module identifiers of the aforementioned operation sub-modules, and the relevant description of the data packet receiving order of the transposed distribution sub-module receiving the data packet to be processed, which will not be repeated here.

[0044] Step 103: For any of the operation submodules, the operation submodule merges the received first sub-data packet into a data packet to be processed corresponding to the operation submodule, and encrypts or decrypts the data in the data packet to be processed to obtain a processing result corresponding to the data packet to be processed.

[0045] In an embodiment of the present invention, the operation submodule may include a key register and a command register. Before the operation submodule performs encryption or decryption processing on the data in the data packet to be processed, the key register and the command register need to be configured. Specifically, the key and command corresponding to the encryption or decryption processing operation can be received by the transposition distribution submodule, and the key and command can be sent to each operation submodule by the unpacking and packaging submodule, and then the register values ​​in the respective key registers and command registers are configured by each operation submodule, so that each operation submodule uses the key to encrypt or decrypt the data in the received data packet to be processed according to the processing method indicated by the command.

[0046] For example, Table 1 is a configuration table of the command register of the operation submodule. Referring to Table 1, 0 or 1 is written to the first bit of the command register. If the register value is 0, it indicates that the operation submodule encrypts the data in the data packet to be processed. If the register value is 1, it indicates that the operation submodule decrypts the data in the data packet to be processed.

[0047] Table 1 Operation submodule command register configuration table

[0048]

[0049] In an embodiment of the present invention, when an operation sub-module receives a first sub-data packet, the first sub-data packet can be stored. When all first sub-data packets are received, the data in each received first sub-data packet can be merged into one data packet according to the receiving order of each first sub-data packet. The merged data packet is the data packet to be processed corresponding to the operation sub-module.

[0050] In the embodiment of the present invention, for any operation submodule, the operation submodule performs encryption processing or decryption processing on the data in the data packet to be processed using the encryption and decryption algorithm corresponding to the processing method to obtain encrypted data or decrypted data, and the encrypted data or decrypted data is used as the processing result corresponding to the data packet to be processed. The encrypted data is obtained after the operation submodule performs encryption processing on the data in the data packet to be processed, and the decrypted data is obtained after the operation submodule performs decryption processing on the data in the data packet to be processed.

[0051] For example, the encryption and decryption algorithm module adopts the SM4 encryption and decryption algorithm, and the operation submodule performs 32 rounds of iterative calculations on the data in the received 128-bit data packet to be processed according to the key in the key register and the command in the command register, and obtains encrypted data or decrypted data as the processing result corresponding to the data packet to be processed. Among them, the calculation process of the SM4 encryption and decryption algorithm can refer to the calculation method of the SM4 encryption and decryption algorithm in the prior art, which is only an example here, and the embodiment of the present invention does not limit this.

[0052] It should be noted that, according to the SM4 encryption and decryption algorithm standard, the data in a 128-bit data packet to be processed must complete 32 rounds of iterative calculations in the same operation submodule. In the embodiment of the present invention, the received multiple data packets to be processed can be sent to the corresponding operation submodules. Since the number of the multiple data packets to be processed is consistent with the number of the multiple operation submodules, one operation submodule can encrypt or decrypt one data packet to be processed to obtain a processing result corresponding to the data packet to be processed.

[0053] Step 104: read the processing results corresponding to each of the data packets to be processed from the multiple operation submodules through the transposition reading submodule, and generate processed data packets corresponding to each of the data packets to be processed according to the processing results corresponding to each of the data packets to be processed.

[0054] In an embodiment of the present invention, the processing results corresponding to each data packet to be processed are read from multiple operation submodules through a transposed reading submodule. For the processing results corresponding to any data packet to be processed, the processing results corresponding to the data packet to be processed can be packaged to obtain a data packet, and the obtained data packet is used as the processed data packet corresponding to the data packet to be processed.

[0055] Optionally, the transposition reading submodule includes a second register, and after generating processed data packets corresponding to each of the to-be-processed data packets according to the processing results corresponding to each of the to-be-processed data packets, each of the processed data packets can be stored in the second register of the transposition reading submodule. When the encryption and decryption algorithm module receives a read data instruction, in response to the data read instruction, each to-be-processed data packet stored in the second register can be returned to the device or storage address specified by the data read instruction through the transposition reading submodule.

[0056] In an embodiment of the present invention, the encryption and decryption algorithm module can receive multiple data packets to be processed at one time, which is the same number as the number of operation submodules, through the transposition distribution submodule. The multiple data packets to be processed are processed by multiple operation submodules respectively. The data are extracted from each data packet to be processed in turn through the transposition distribution submodule and merged into one data packet, so that the first transposed data packet obtained by each extraction and merging operation includes data from each data packet to be processed, and then the multiple first transposed data packets are sent to the unpacking and packaging submodule in turn through the transposition distribution submodule, so that each data packet to be processed can be sent to the unpacking and packaging submodule in parallel, and then each first transposed data packet is split into multiple first sub-data packets whose data length matches the interface bit width of the operation submodule through the unpacking and packaging submodule, and then sent to the corresponding operation subdevices respectively, so that the operation submodule can successfully receive the first sub-data packet, and the received first sub-data packet is the data of the data packet to be processed corresponding to the operation submodule, thereby realizing the sending of each data packet to be processed in parallel to the corresponding operation submodule, thereby improving the parallelism of the encryption and decryption algorithm module. Furthermore, the data packets to be processed are encrypted or decrypted through the operation submodule to obtain corresponding processing results, and the processing results corresponding to each data packet to be processed are read out through the transposition reading submodule to generate processed data packets corresponding to each data packet to be processed, thereby completing the encryption or decryption processing of multiple data packets to be processed. This can increase the amount of data received and encrypted and decrypted at a single time, so that more data can be processed in the same time, and the overall operation speed can be correspondingly improved, which can improve the operation efficiency of encryption and decryption of data to a certain extent.

[0057] Optionally, step 101 may include the following steps:

[0058] Step 1011: For any of the data packets to be processed, the transposition distribution submodule divides the data in the data packet to be processed into a plurality of first sub-data packets according to the data sequence.

[0059] In the embodiment of the present invention, for any data packet to be processed, the data in the data packet to be processed can be divided according to the data sequence according to the interface bit width of the operation submodule by the transposition distribution submodule to obtain multiple first sub-data packets, and the data length of each first sub-data packet is the target data length, and the target data length matches the interface bit width of the operation submodule. Wherein, each first sub-data packet is sorted according to the data sequence in the data packet to be processed to obtain multiple ordered first sub-data packets.

[0060] For example, if the interface bit width of the operation submodule is 32 bits, and the data packet to be processed is a 128-bit data packet, the data in the data packet to be processed can be divided into four 32-bit sub-data packets in sequence according to the data order, and four ordered first sub-data packets are obtained. This is only an example, and the embodiment of the present invention does not limit this.

[0061] Step 1012: extracting first sub-data packets of the same order from each of the to-be-processed data packets in sequence through the transposition distribution submodule, and merging the first sub-data packets of the same order extracted each time to obtain the multiple first transposed data packets.

[0062] In an embodiment of the present invention, the first first sub-data packet can be extracted from each data packet to be processed by the transposition distribution submodule, and the number of the extracted first sub-data packets is consistent with the total number of data packets to be processed. Then, the extracted first first sub-data packets are merged, that is, combined into one data packet according to the order in which the data packets are received, to obtain the first first transposed data packet. The order in which the data packets are received is the order in which the transposition distribution submodule receives each data packet to be processed. By analogy, the first sub-data packets of the same order are extracted from each data packet to be processed in turn, and the first sub-data packets of the same order extracted each time are merged to obtain multiple first transposed data packets.

[0063] In the embodiment of the present invention, for any of the data packets to be processed, the data in the data packet to be processed is divided into a plurality of first sub-data packets according to the data sequence by the transposition distribution submodule; the first sub-data packets of the same sequence are sequentially extracted from each of the data packets to be processed by the transposition distribution submodule, and the first sub-data packets of the same sequence extracted each time are merged to obtain the plurality of first transposed data packets. In this way, by dividing the data packet to be processed into a plurality of first sub-data packets, and then extracting and merging the first sub-data packets of the same sequence from each of the data packets to be processed, each data packet to be processed can be conveniently transposed into a plurality of first transposed data packets, thereby improving the efficiency of obtaining the first transposed data packets.

[0064] Optionally, the encryption and decryption algorithm module further includes a first bus, the transposition distribution submodule includes a first state machine corresponding to the first bus, and the transposition distribution submodule is connected to the unpacking and packaging submodule through the first bus; before the plurality of first transposed data packets are sequentially sent to the unpacking and packaging submodule, the method further includes:

[0065] Step 201: In any case where a first transposed data packet is obtained through the transposition distribution submodule, the first transposed data packet is stored in the first state machine through the transposition distribution submodule, and a write data signal corresponding to the first transposed data packet is generated through the first state machine.

[0066] Optionally, step 101 may further include the following steps:

[0067] Step 1013: Send the first transposed data packet and the write data signal to the depacketizing and assembling submodule through the first bus by using the first state machine.

[0068] In an embodiment of the present invention, the bus width of the first bus matches the interface width of the transposition and distribution submodule, the unpacking and packaging submodule includes a first bus master interface and a slave interface, the interface width of the first bus master interface is consistent with the interface width of the transposition and distribution submodule, and the interface width of the slave interface is consistent with the interface width of the operation submodule.

[0069] In the embodiment of the present invention, in any case where a first transposed data packet is obtained through the transposition distribution submodule, the first transposed data packet is directly stored in the first state machine. The first state machine generates a write data signal corresponding to the first transposed data packet according to the bus protocol standard corresponding to the first bus. Then, the first transposed data packet and the write data signal are sent to the unpacking and assembling submodule through the first bus by the first state machine.

[0070] For example, the first bus is an AXI bus, the first state machine is an AXI state machine, the first transposed data packet enters the AXI state machine, the AXI state machine generates an AXI bus signal for writing data, i.e., a write data signal, according to the AXI protocol standard, and then the AXI state machine sends the first transposed data packet and the write data signal to the unpacking and assembly sub-module via the AXI bus.

[0071] The method further comprises:

[0072] Step 301: Send the write data signal to the multiple operation submodules through the unpacking and packaging submodule; the write data signal is used to instruct the operation submodule to receive the first sub-data packet sent by the unpacking and packaging submodule, and store the data in the first sub-data packet to a specified location.

[0073] In an embodiment of the present invention, a first transposed data packet corresponds to a write data signal, and a first transposed data packet can be split into multiple first sub-data packets. Before the multiple first sub-data packets are sent to their corresponding operation sub-modules through the unpacking and packaging sub-module, the write data signal can be sent to each operation sub-module respectively through the unpacking and packaging sub-module to instruct each operation sub-module to receive the first sub-data packet sent by the unpacking and packaging sub-module, and store the data in the first sub-data packet to a designated location inside each operation sub-module.

[0074] For example, the four data packets to be processed received by the transposition distribution submodule are transposed to obtain the first first transposed sub-data packet, and then the multiple first sub-data packets in the first first transposed sub-data packet are sent to the corresponding operation submodules. Then, the second first sub-data packet in the four data packets to be processed is extracted by the transposition distribution submodule, and merged into the second first transposed data packet. The second first transposed data packet is stored in the first state machine by the transposition distribution submodule, and the write data signal corresponding to the second first transposed data packet is generated by the first state machine. The second first transposed data packet and the write data signal are sent to the unpacking and assembling submodule through the first bus by the first state machine, and the multiple first sub-data packets and the write data signal are sent to multiple operation submodules by the unpacking and assembling submodule. Each operation submodule receives the first sub-data packet corresponding to the second transposed sub-data packet in response to the write data signal corresponding to the second first transposed data packet, and then stores the first sub-data packet corresponding to the second transposed sub-data packet received this time behind the first sub-data packet corresponding to the first first transposed sub-data packet received last time in an address incrementing manner. Next, a third first transposed data packet is obtained, and the same data transmission process is performed until a plurality of first sub-data packets divided from each first transposed data packet and a write data signal are sent to each operation submodule.

[0075] In an embodiment of the present invention, when a first transposed data packet is obtained through the transposition distribution submodule at any time, the first transposed data packet is stored in the first state machine through the transposition distribution submodule, and a write data signal corresponding to the first transposed data packet is generated through the first state machine; the first transposed data packet and the write data signal are sent to the unpacking and assembling submodule through the first bus through the first state machine; the write data signal is sent to the multiple operation submodules through the unpacking and assembling submodule; the write data signal is used to instruct the operation submodule to receive the first sub-data packet sent by the unpacking and assembling submodule, and store the data in the first sub-data packet to a specified location. In this way, the signal action of the data write operation to the operation submodule can be coordinated through the first state machine, and the write data signal generated by the first state machine instructs the operation submodule to receive and store data, thereby improving the rationality of the data write operation to the operation submodule, and to a certain extent, the data transmission efficiency between the transposition distribution submodule and each operation submodule can be improved.

[0076] Optionally, step 301 may include the following steps:

[0077] Step 3011: split the write data signal into multiple write data sub-signals through the unpacking and packaging sub-module, and send the multiple write data sub-signals to their corresponding operation sub-modules; the number of the multiple write data sub-signals is consistent with the number of the multiple operation sub-modules, and the write data sub-signals are used to instruct the corresponding operation sub-module to receive the first sub-data packet sent by the unpacking and packaging sub-module, and store the data in the first sub-data packet to a specified location.

[0078] In the embodiment of the present invention, the unpacking and packaging submodule and each operation submodule can be connected through a third bus, and the unpacking and packaging submodule can generate multiple identical write data sub-signals according to the write data signal, wherein the write data sub-signals match the third bus. Then, the unpacking and packaging submodule distributes the multiple write data sub-signals to the multiple operation submodules through the third bus.

[0079] In the embodiment of the present invention, the write data signal is split into multiple write data sub-signals by the unpacking and packaging sub-module, and the multiple write data sub-signals are sent to the corresponding operation sub-modules; the number of the multiple write data sub-signals is consistent with the number of the multiple operation sub-modules, and the write data sub-signals are used to instruct the corresponding operation sub-module to receive the first sub-data packet sent by the unpacking and packaging sub-module, and store the data in the first sub-data packet to the specified location. In this way, the write data sub-signals corresponding to each operation sub-module can be easily obtained, and the write data sub-signals are sent to the corresponding operation sub-module, thereby improving the acquisition efficiency of the write data sub-signals and the data receiving efficiency of the operation sub-module.

[0080] Figure 2 is a schematic diagram of the transposition distribution logic of the data processing method provided by the embodiment of the present invention, such as Figure 2 As shown, the transposition distribution submodule receives four data packets AD to be processed, and divides each data packet to be processed into four first sub-data packets, then extracts the first first sub-data packet from the four data packets to be processed, and merges the extracted four first sub-data packets according to the order of data packet reception to obtain the first first transposed data packet. The first first transposed data packet is sent to the unpacking and packaging submodule through the transposition distribution submodule, and the unpacking and packaging submodule then splits the first first transposed data packet to obtain four first sub-data packets.

[0081] Optionally, the transposition reading submodule is connected to the unpacking and packaging submodule, and before step 104, the method further includes:

[0082] Step 401: For any of the operation submodules, the operation submodule divides the data in the processing result into a plurality of second sub-data packets according to the data sequence; the data length of the second sub-data packet matches the interface bit width of the operation submodule.

[0083] In an embodiment of the present invention, the length of data read by the transposition reading submodule from an operation submodule at one time matches the interface bit width of the operation submodule. For example, a processing result corresponding to a 128-bit data packet to be processed is 128 bits. If the interface bit width of the operation submodule is 32 bits, the transposition reading submodule can read 32 bits of data from the operation submodule at a time. A 128-bit processing result requires 4 read operations to be spliced ​​into a complete processing result.

[0084] In the embodiment of the present invention, the interface width of the transposition reading submodule may be Q times the interface width of the operation submodule, where Q is an integer greater than 1. The transposition reading submodule may be connected to the unpacking and packaging submodule, and the unpacking and packaging submodule is respectively connected to each operation submodule. The interface width corresponding to the third interface connected between the unpacking and packaging submodule and the transposition reading submodule is consistent with the interface width of the transposition reading submodule.

[0085] Optionally, the interface width of the transposition reading submodule and the interface width of the transposition distribution submodule can be equal, then P=Q, and further, the interface widths of the first interface and the third interface of the unpacking and assembling submodule are also consistent. For example, the interface width of the transposition reading submodule and the interface width of the transposition distribution submodule are both 128 bits, and the interface width of the operation submodule is 32 bits, P=Q=4, then the interface widths of the first interface and the third interface of the unpacking and assembling submodule are both 128 bits, and the interface width of the second interface of the unpacking and assembling submodule is 32 bits. This is only an example, and the embodiments of the present application are not limited to this.

[0086] In the embodiment of the present invention, for any operation submodule, the data in the obtained processing result is divided according to the data sequence and the interface bit width of the operation submodule by the operation submodule, and the processing result is divided into a plurality of second sub-data packets, and the data length of each second sub-data packet is the target data length, and the target data length matches the interface bit width of the operation submodule. Wherein, each second sub-data packet is sorted according to the data sequence in the processing result to obtain a plurality of ordered second sub-data packets.

[0087] For example, if the interface bit width of the operation submodule is 32 bits, a processing result corresponding to a 128-bit data packet to be processed is 128 bits, and the data in the processing result can be divided into four 32-bit sub-data packets in sequence according to the data order to obtain four ordered second sub-data packets. This is only an example, and the embodiment of the present invention does not limit this.

[0088] Optionally, step 104 may include the following steps:

[0089] Step 1041, read the second sub-data packets of the same order from each of the operation sub-modules in sequence through the unpacking and packing sub-module, merge the second sub-data packets of the same order read out each time to obtain multiple second transposed data packets, and send the multiple second transposed data packets to the transposition reading sub-module in sequence.

[0090] In the embodiment of the present invention, the first second sub-data packet can be extracted from each operation sub-module through the unpacking and packing sub-module, and the number of the extracted second sub-data packets is consistent with the total number of the operation sub-modules. Then, the extracted first second sub-data packets are merged, that is, combined into a data packet according to the module identification order to obtain the first second transposed data packet. Among them, the module identification order is the size order of the module identification of each operation sub-module. By analogy, the second sub-data packets of the same order are read from each operation sub-module in turn through the unpacking and packing sub-module, and the second sub-data packets of the same order read each time are merged to obtain multiple second transposed data packets.

[0091] In the embodiment of the present invention, the unpacking and grouping submodule can sequentially send the plurality of second transposed data packets to the transposition reading submodule in the order in which the second transposed data packets are generated. Since any second transposed data packet contains a part of the processing results in each operation submodule, the unpacking and grouping submodule sequentially sends the plurality of first transposed data packets to the transposition reading submodule, and the unpacking and grouping submodule can read the processing results corresponding to the data packets to be processed in parallel and forward them to the transposition reading submodule, thereby improving the parallelism of the encryption and decryption algorithm module.

[0092] Step 1042: Generate processed data packets corresponding to each of the to-be-processed data packets according to the data in the plurality of second transposed data packets through the transposition reading submodule.

[0093] In the embodiment of the present invention, the processing result corresponding to any operation submodule, that is, the multiple second sub-data packets corresponding to the operation submodule are scattered in each second transposed data packet, and the second sub-data packets belonging to the first operation submodule can be extracted from each second transposed data packet by the transposition reading submodule, and the multiple second sub-data packets belonging to the first operation submodule extracted are merged into one data packet according to the data sequence in the first operation submodule to obtain the processed data packet corresponding to the first operation submodule, and the processed data packet is used as the processed data packet corresponding to the data packet to be processed received by the operation submodule. By analogy, the second sub-data packets belonging to the same operation submodule are extracted from each second transposed data packet in sequence by the transposition reading submodule, and the multiple second sub-data packets belonging to the same operation submodule extracted each time are merged to obtain the processed data packets corresponding to each operation submodule, and according to the corresponding relationship between the operation submodule and the received data packet to be processed, the processed data packets corresponding to each operation submodule are used as the processed data packets corresponding to each data packet to be processed.

[0094] In an embodiment of the present invention, when the interface width of the transposition reading submodule is greater than the interface width of the operation submodule, the transposition reading submodule is connected to the unpacking and packing submodule, and for any of the operation submodules, the operation submodule divides the data in the processing result into a plurality of second sub-data packets according to the data sequence; the data length of the second sub-data packet matches the interface width of the operation submodule; the unpacking and packing submodule sequentially reads the second sub-data packets of the same order from each of the operation submodules, and merges the second sub-data packets of the same order read out each time to obtain a plurality of second transposition data packets, and sends the plurality of second transposition data packets to the transposition reading submodule; the transposition reading submodule generates the processed data packets corresponding to each of the to-be-processed data packets according to the data in the plurality of second transposition data packets. In this way, when the interface width of the transposition reading submodule is greater than the interface width of the operation submodule, the unpacking and packing submodule connected to the transposition reading submodule and each of the operation submodules can read the data in each of the operation submodules and forward them to the transposition reading submodule, thereby improving the practicality of the data processing method of the present invention. And because the data contained in the second transposed data packet comes from each operation sub-module, by sending multiple second transposed data packets to the transposed reading sub-module in sequence through the unpacking and packing sub-module, the processing results in each operation sub-module can be read in parallel and forwarded to the transposed reading sub-module, thereby improving the parallelism of the encryption and decryption algorithm module, and to a certain extent, the data transmission efficiency between the transposed reading sub-module and each operation sub-module can be improved.

[0095] Optionally, step 1042 may include the following steps:

[0096] Step 1042a, extracting second sub-data packets belonging to the same operation sub-module from each of the second transposed data packets in turn through the transposition reading sub-module, and merging the second sub-data packets belonging to the same operation sub-module extracted each time to obtain processed data packets corresponding to each of the data packets to be processed.

[0097] In the embodiment of the present invention, the second transposed data packet is obtained by combining the second sub-data packets of the same order in each operation sub-module according to the module identification order, and the second sub-data packets of the same module identification order can be sequentially extracted from each second transposed data packet by the transposition reading sub-module, that is, the second sub-data packets belonging to the same operation sub-module, and the extracted second sub-data packets of the same module identification order are merged into one data packet according to the data order in the operation sub-module corresponding to the module identification, so as to obtain a processed data packet corresponding to the operation sub-module, and the processed data packet is used as the processed data packet corresponding to the data packet to be processed received by the operation sub-module. By analogy, the second sub-data packets of the same module identification order can be sequentially extracted from each second transposed data packet by the transposition reading sub-module, that is, the second sub-data packets belonging to the same operation sub-module, and the second sub-data packets belonging to the same operation sub-module extracted each time are merged to obtain the processed data packets corresponding to each data packet to be processed.

[0098] In the embodiment of the present invention, the second sub-data packets belonging to the same operation sub-module are sequentially extracted from each of the second transposed data packets by the transposition reading sub-module, and the second sub-data packets belonging to the same operation sub-module extracted each time are merged to obtain the processed data packets corresponding to each of the data packets to be processed. In this way, by merging the second sub-data packets belonging to the same operation sub-module extracted each time, the processed data packets corresponding to each of the operation sub-modules can be obtained, and then the processed data packets corresponding to each of the data packets to be processed can be determined according to the data packets to be processed received by each of the operation sub-modules, which can improve the acquisition efficiency of the processed data packets corresponding to each of the data packets to be processed to a certain extent.

[0099] Optionally, the encryption and decryption algorithm module further includes a second bus, the transposition reading submodule includes a second state machine corresponding to the second bus, and the transposition reading submodule is connected to the unpacking and packaging submodule through the second bus; when the transposition reading submodule receives a read data instruction, the method further includes:

[0100] Step 501: Before any second sub-data packet of the same order is read from each of the operation sub-modules through the unpacking and packaging sub-module, a first read data signal corresponding to the current reading operation of the unpacking and packaging sub-module is generated through the second state machine, and the first read data signal is sent to the unpacking and packaging sub-module through the second bus.

[0101] Step 502: Send the first read data signal to each of the operation submodules through the unpacking and packaging submodule.

[0102] In an embodiment of the present invention, the bus width of the second bus matches the interface width of the transposition reading submodule, and the unpacking and packaging submodule also includes a second bus master interface, and the interface width of the second bus master interface is consistent with the interface width of the transposition reading submodule.

[0103] In the embodiment of the present invention, the processed data packets corresponding to each data packet to be processed are read and forwarded in parallel by the unpacking and packing submodule. Therefore, when the transposition reading submodule receives the first read data instruction for the processed data packet, it is necessary to use a pre-reading method to read all the processed data packets corresponding to each data packet to be processed from each operation module and temporarily store them in the register inside the transposition reading submodule. Among them, the read data instruction can be sent to the encryption and decryption algorithm module in the direction of sending the data packet to be processed, or it can be sent to the encryption and decryption algorithm module by other devices or modules, and the embodiment of the present invention does not limit this.

[0104] In an embodiment of the present invention, when the transposition reading submodule receives a read data instruction, before the unpacking and assembling submodule reads the second sub-data packets of the same order from each operation submodule for the first time, a first read data signal corresponding to the first read operation of the unpacking and assembling submodule is generated by the second state machine, and the first read data signal is used to instruct each operation submodule to return the first second sub-data packet. Then, the first read data signal is sent to the unpacking and assembling submodule via the second bus through the second state machine. By analogy, before any second sub-data packets of the same order are read from each operation submodule by the unpacking and assembling submodule, a first read data signal corresponding to the current read operation of the unpacking and assembling submodule is generated by the second state machine, and the first read data signal is sent to the unpacking and assembling submodule via the second bus. Then, the first read data signal is sent to each operation submodule by the unpacking and assembling submodule.

[0105] For example, the second bus is an AXI bus, and the second state machine is an AXI state machine. When the transposed read sub-module receives a read data instruction, the AXI state machine generates an AXI bus signal for reading data according to the AXI protocol standard, that is, the first read data signal corresponding to the current read operation of the unpacking and packaging sub-module, and then the AXI state machine sends the first read data signal to the unpacking and packaging sub-module via the AXI bus.

[0106] Optionally, step 1041 may include the following steps:

[0107] Step 1041a. In any case where the unpacking and packing submodule reads a second sub-data packet of the same order from each of the operation submodules, each of the operation submodules responds to the first read data signal to return the second sub-data packet corresponding to the current read operation of the unpacking and packing submodule to the unpacking and packing submodule.

[0108] In the embodiment of the present invention, the first read data signal is used to instruct each operation submodule to return the second sub-data packet corresponding to the current read operation of the unpacking and packaging submodule. For any operation submodule, each time the first read data signal is received, in response to the first read data signal, the second sub-data packet corresponding to the current read operation of the unpacking and packaging submodule indicated by the first read data signal is returned to the unpacking and packaging submodule.

[0109] In an embodiment of the present invention, before the unpacking and assembling submodule reads the second sub-data packets of the same order from each of the operation submodules at any time, the second state machine generates a first read data signal corresponding to the current read operation of the unpacking and assembling submodule, and sends the first read data signal to the unpacking and assembling submodule through the second bus; the unpacking and assembling submodule sends the first read data signal to each of the operation submodules; in the case of reading the second sub-data packets of the same order from each of the operation submodules at any time through the unpacking and assembling submodule, each of the operation submodules responds to the first read data signal and returns the second sub-data packet corresponding to the current read operation of the unpacking and assembling submodule to the unpacking and assembling submodule. In this way, the signal action of the data reading operation on the operation submodule can be coordinated by the second state machine, and the first read data signal generated by the second state machine indicates that the operation submodule returns the second sub-data packet corresponding to the current read operation to the unpacking and assembling submodule, thereby improving the rationality of the data reading operation on the operation submodule, and to a certain extent, the data transmission efficiency between the transposition distribution submodule and each of the operation submodules can be improved.

[0110] Optionally, before step 502, the method further includes:

[0111] Step 601: Split the first read data signal into a plurality of read data sub-signals by the unpacking and packing sub-module.

[0112] Optionally, step 502 may include the following steps:

[0113] Step 5021: Send the multiple read data sub-signals to the corresponding operation sub-modules through the unpacking and packing sub-module.

[0114] Optionally, step 1041a may include the following steps:

[0115] Step 1041a1: For any of the operation submodules, in response to the corresponding read data subsignal, return the second subdata packet corresponding to the current read operation of the unpacking and packing submodule to the unpacking and packing submodule.

[0116] In the embodiment of the present invention, the unpacking and packaging submodule and each operation submodule can be connected through a third bus, and the unpacking and packaging submodule can generate multiple identical read data sub-signals according to the first read data signal, wherein the read data sub-signals match the third bus. Then, the unpacking and packaging submodule distributes the multiple read data sub-signals to the multiple operation submodules through the third bus.

[0117] In the embodiment of the present invention, the read data sub-signal is used to instruct the corresponding operation sub-module to return the second sub-data packet corresponding to the current read operation of the unpacking and packaging sub-module. For any operation sub-module, each time the read data sub-signal is received, in response to the read data sub-signal, the second sub-data packet corresponding to the current read operation of the unpacking and packaging sub-module indicated by the read data sub-signal is returned to the unpacking and packaging sub-module.

[0118] For example, when the transposition reading submodule receives the read data instruction, the AXI bus signal of the read data corresponding to the first read operation of the unpacking and packaging submodule, i.e., the first read data signal, is generated through the second state machine, such as the AXI state machine, and the first read data signal is sent to the unpacking and packaging submodule through the second bus, such as the AXI bus. The first read data signal is split into 4 read data sub-signals by the unpacking and packaging submodule, and the 4 read data sub-signals are sent to the 4 operation submodules. The 4 operation submodules respond to the read data sub-signals and return the 32-bit second sub-data packet corresponding to the current read operation of the unpacking and packaging submodule to the unpacking and packaging submodule. Then, the unpacking and packet assembly submodule is used to merge the four 32-bit second sub-packets read this time to obtain a 128-bit second transposed data packet, and the second state machine, such as the AXI state machine, writes the four 32-bit second sub-packets in the 128-bit second transposed data packet into the storage addresses corresponding to each of the four processed data packets, and then the second state machine, such as the AXI state machine, generates a first read data signal corresponding to the second read operation of the unpacking and packet assembly submodule. The above process is repeated four times to obtain the processed data packets corresponding to each of the four operation submodules as the processed data packets corresponding to each of the four data packets to be processed.

[0119] Optionally, each operation submodule may return a response subsignal each time it returns the second sub-data packet to the unpacking and packaging submodule, and the unpacking and packaging submodule merges the response subsignals into a response signal and then sends it to the second state machine, which receives and temporarily stores the response signal for reading and viewing by other devices or modules. The response signal is related to the bus protocol and is used to indicate the communication status.

[0120] In an embodiment of the present invention, the first read data signal is split into a plurality of read data sub-signals by the unpacking and packaging sub-module; the plurality of read data sub-signals are sent to the corresponding operation sub-modules by the unpacking and packaging sub-module; for any of the operation sub-modules, in response to the corresponding read data sub-signal, the second sub-data packet corresponding to the current read operation of the unpacking and packaging sub-module is returned to the unpacking and packaging sub-module. In this way, the first read data signal can be split into a plurality of read data sub-signals by the unpacking and packaging sub-module, each operation sub-module corresponds to a read data sub-signal, and the plurality of read data sub-signals are sent to the corresponding operation sub-modules by the unpacking and packaging sub-module, so as to instruct each operation sub-module to return the second sub-data packet corresponding to the current read operation of the unpacking and packaging sub-module to the unpacking and packaging sub-module in response to the corresponding read data sub-signal, which can improve the response speed of each operation sub-module and improve the reading efficiency of the unpacking and packaging sub-module to a certain extent.

[0121] Optionally, the encryption and decryption algorithm module further includes a plurality of third buses, the unpacking and packaging submodule is connected to the operation submodule via the third bus, and the third bus includes a write channel and a read channel; step 102 may include the following steps:

[0122] Step 1021: For any of the operation submodules, the unpacking and packaging submodule sends a first sub-data packet corresponding to the operation submodule to the operation submodule through a write channel corresponding to the operation submodule.

[0123] Optionally, step 3011 may include the following steps:

[0124] Step 3011a: For any of the operation sub-modules, the unpacking and packaging sub-module sends the write data sub-signal corresponding to the operation sub-module to the operation sub-module through the write channel corresponding to the operation sub-module.

[0125] Optionally, step 5021 may include the following steps:

[0126] Step 5021a: For any of the operation sub-modules, the unpacking and packaging sub-module sends the read data sub-signal corresponding to the operation sub-module to the operation sub-module through the write channel corresponding to the operation sub-module.

[0127] Optionally, step 1041 may include the following steps:

[0128] Step 1041a: In any case where the second sub-data packets of the same order are read from each of the operation sub-modules by the unpacking and packing sub-module, the second sub-data packets of the same order are read from each of the operation sub-modules by the unpacking and packing sub-module through the read channels corresponding to each of the operation sub-modules.

[0129] In the embodiment of the present invention, the unpacking and packaging submodule is connected to the operation submodule through a third bus, and the read and write channels of the third bus are separated, that is, the third bus includes a write channel and a read channel. For example, the interface bit width of the operation submodule is 32 bits, and the third bus can use a 32-bit peripheral bus (Advanced Peripheral Bus, APB), the interface bit width of the slave interface of the unpacking and packaging submodule matches the interface bit width of the operation submodule and is also 32 bits, and the unpacking and packaging submodule is connected to the operation submodule through a 32-bit APB bus.

[0130] Optionally, if the first bus and the second bus are both AXI buses, the APB bus may include an AXI to APB bridge and a data selector (Multiplexer, MUX). The read signals of the AXI bus, such as AR and R signals, are sent to the read channel, and the write signals of the AXI bus, such as AW, W, and B signals, are sent to the write channel. The read and write channels generate corresponding APB bus signals through the AXI to APB bridge, and the data selector selects an APB bus signal and sends it to the operation sub-module.

[0131] In the embodiment of the present invention, for any operation submodule, the first sub-data packet, the write data sub-signal, and the read data sub-signal sent to the operation submodule can be sent to the operation submodule through the write channel on the third bus corresponding to the operation submodule. When reading the second sub-data packet from the operation submodule, the second sub-data packet can be read through the read channel on the third bus corresponding to the operation submodule.

[0132] In an embodiment of the present invention, for any of the operation sub-modules, the first sub-data packet corresponding to the operation sub-module is sent to the operation sub-module through the write channel corresponding to the operation sub-module by the unpacking and packing sub-module; for any of the operation sub-modules, the write data sub-signal corresponding to the operation sub-module is sent to the operation sub-module through the write channel corresponding to the operation sub-module by the unpacking and packing sub-module; for any of the operation sub-modules, the read data sub-signal corresponding to the operation sub-module is sent to the operation sub-module through the write channel corresponding to the operation sub-module by the unpacking and packing sub-module; in the case of any time in which the second sub-data packet of the same order is read from each of the operation sub-modules by the unpacking and packing sub-module, the second sub-data packet of the same order is read from each of the operation sub-modules by the unpacking and packing sub-module through the read channel corresponding to each of the operation sub-modules. In this way, the read and write channels of the third bus can be separated, and bidirectional transmission can be performed simultaneously through the read channel and the write channel. After the operation sub-module obtains the processing result, the processing result can be read through the read channel, and at the same time, a new write data sub-signal and a first sub-data packet are sent to the operation sub-module through the write channel. This can improve the data transmission efficiency between the unpacking and packaging sub-module and the operation sub-module to a certain extent.

[0133] Optionally, the read channel includes a storage submodule, and the storage submodule includes a first memory; before step 1041a, the method further includes:

[0134] Step 701: When a preset storage condition is met, the storage submodule reads the plurality of second sub-data packets in the operation submodule corresponding to the storage submodule, and stores the plurality of second sub-data packets in the first memory.

[0135] Optionally, step 1041a may include the following steps:

[0136] Step 1041a1: read the second sub-data packets of the same order from each of the first memories through the unpacking and packing sub-module.

[0137] In an embodiment of the present invention, the storage submodule can directly access the operation submodule and read the operation status of the operation submodule, and determine whether the preset storage condition is met according to the operation status of the operation submodule. The preset storage condition can be that the operation status of the operation submodule is that the operation has been completed. For example, referring to Table 1, the third bit in the register of the operation submodule stores the operation status of the operation submodule, and the storage submodule determines the operation status of the operation submodule according to the register value, and the register value is 1 when the operation is completed.

[0138] In the embodiment of the present invention, when the preset storage conditions are met, that is, when the operation submodule has completed the encryption or decryption processing of the data in a data packet to be processed, the operation submodule connected to the third bus where the storage submodule is located is accessed through the storage submodule, and multiple second sub-data packets in the operation submodule are read, and the multiple second sub-data packets are temporarily stored in the first memory inside the storage submodule. Among them, the first memory can be a first-in first-out memory (First In / First Out, FIFO). After the storage submodule reads the processing result from the operation submodule, the operation submodule can receive the data in the next round of data packets to be processed, thereby realizing data streaming processing. This is only an example, and the embodiment of the present invention does not limit this.

[0139] In the embodiment of the present invention, the second sub-data packets of the same order can be read from the first memory on the read channel of each third bus by the unpacking and packing sub-module, and the number of the second sub-data packets read out is consistent with the total number of the operation sub-modules. The unpacking and packing sub-module can combine the second sub-data packets of the same order read from each first memory to obtain a second transposed data packet.

[0140] In an embodiment of the present invention, by reading the plurality of second sub-data packets in the operation sub-module corresponding to the storage sub-module through the storage sub-module under the condition of meeting the preset storage conditions, and storing the plurality of second sub-data packets in the first memory; and reading the second sub-data packets of the same order from each of the first memories through the unpacking and packing sub-module. In this way, the second sub-data packets of the operation sub-module can be temporarily stored through the storage sub-module, which facilitates the operation sub-module to receive data in a new data packet to be processed, and the unpacking and packing sub-module can directly read the second sub-data packet from the storage sub-module, which can reduce the time delay of the operation sub-module receiving data, and can improve the data transmission efficiency between the unpacking and packing sub-module and the operation sub-module to a certain extent.

[0141] Optionally, before step 701, the method further includes:

[0142] Step 801: Send a second read data signal to the operation submodule corresponding to the storage submodule through the third state machine.

[0143] Optionally, step 701 may include the following steps:

[0144] Step 7011: In response to the second read data signal, the operation submodule returns the plurality of second sub-data packets to the storage submodule.

[0145] In the embodiment of the present invention, when the preset storage condition is met, the storage submodule automatically starts the third state machine, generates a second read data signal through the third state machine, and sends the second read data signal to the operation submodule corresponding to the storage submodule. The second read data signal is used to instruct the operation submodule to return multiple second sub-data packets to the storage submodule.

[0146] In the embodiment of the present invention, for any operation submodule, in response to the second read data signal, multiple second sub-data packets in the operation submodule are returned to the storage submodule, so that the storage submodule stores the multiple second sub-data packets in the first memory.

[0147] Figure 3 : is a state diagram of the third state machine provided in an embodiment of the present invention, the third bus is an APB bus, and the storage submodule is a read_fifo module, such as Figure 3 As shown, the third state machine starts in an idle state (IDLE). When the read_fifo module detects that the operation submodule completes the SM4 encryption and decryption algorithm operation, the third state machine enters the request state (PREQ) and pulls up the PREQ signal, then enters the enable state (PSEL), pulls up the PSEL signal, and then enters the judgment state (PEN), and pulls up the PEN signal. In the PEN state, it is necessary to judge whether the internal fifo of the read_fifo module, that is, the first memory, is full. If it is full, stop reading until the internal fifo is free, then enter the write data state (PDATA), and write the read multiple second sub-data packets into the internal fifo in the PDATA state. Optionally, a counter is set inside the read_fifo, and the counter is used to record the second sub-data packet currently read in the 128-bit processing result. If count=3 indicates that the 4 second sub-data packets corresponding to a 128-bit processing result have all been read, then return to the IDLE state, and clear count to 0. If count<3, return to the PSEL state to continue reading the second sub-data packet from the operation submodule.

[0148] In the embodiment of the present invention, the third state machine sends a second read data signal to the operation submodule corresponding to the storage submodule; the operation submodule responds to the second read data signal and returns the multiple second sub-data packets to the storage submodule. In this way, the third state machine can coordinate the signal action of the data reading operation on the operation submodule, and the second read data signal generated by the second state machine instructs the operation submodule to return multiple second sub-data packets to the storage submodule, thereby improving the rationality of the data reading operation on the operation submodule, further reducing the time delay of the operation submodule receiving data, and improving the data transmission efficiency between the unpacking and packaging submodule and the operation submodule to a certain extent.

[0149] Optionally, the encryption and decryption algorithm module is set in a target device, and the target device includes a processor; the method further includes:

[0150] Step 901, receiving a data processing instruction sent by the processor through the transposition distribution submodule; the data processing instruction is used to instruct the encryption and decryption algorithm module to encrypt or decrypt the multiple data packets to be processed; the multiple data packets to be processed are data packets sent by the processor to the transposition distribution submodule.

[0151] In an embodiment of the present invention, the target device may be a computer device, such as a personal computer or a server. The target device includes a processor, such as a central processing unit (CPU). A plurality of data packets to be processed are initially stored in a continuous memory address space in the target device, and the processor sends the plurality of data packets to be processed to the transposition distribution submodule from the continuous memory address space, and then receives the plurality of data packets to be processed sent by the processor through the transposition distribution submodule.

[0152] For example, the encryption and decryption algorithm module adopts the SM4 encryption and decryption algorithm, and four 128-bit data packets to be processed are stored in the continuous memory address space of the target device. The transposition distribution submodule includes an AXI slave port of the 128-bit AXI bus. The CPU sends the four data packets to be processed from the continuous memory address space to the transposition distribution submodule in sequence through the AXI slave port. One 128-bit data packet to be processed is transmitted in one beat, and the transmission of the four data packets to be processed is completed in 4 beats.

[0153] In the embodiment of the present invention, the target processor generates keys and commands corresponding to the multiple data packets to be processed this time, generates data processing instructions according to the keys and commands, and sends the data processing instructions to the transposition distribution submodule. Then the transposition distribution submodule receives the data processing instructions sent by the processor, and determines the keys and commands according to the data processing instructions, and the commands include encrypting or decrypting the multiple data packets to be processed. Among them, the keys and commands can refer to the relevant description in step 102, which will not be repeated here.

[0154] In an embodiment of the present invention, the data processing instruction sent by the processor is received by the transposition distribution submodule; the data processing instruction is used to instruct the encryption and decryption algorithm module to encrypt or decrypt the multiple data packets to be processed; the multiple data packets to be processed are data packets sent by the processor to the transposition distribution submodule. In this way, the multiple data packets to be processed sent by the processor of the target device can be encrypted or decrypted according to the processing method indicated by the data processing instruction sent by the processor of the target device, and the encryption and decryption algorithm module can be used to improve the computing efficiency of the encryption and decryption processing of the data packets to be processed in the target device.

[0155] Optionally, the encryption and decryption algorithm module further includes a data write-back submodule, and the data write-back submodule is connected to the transposition reading submodule; the method further includes:

[0156] Step 1001: read the processed data packets corresponding to each of the data packets to be processed from the transposition reading submodule through the data write-back submodule, and write each of the processed data packets to a designated memory address in the target device.

[0157] It should be noted that when the encryption and decryption algorithm module in the prior art is set in the target device, it is used as a device. After each encryption or decryption of multiple pending data packets sent by the processor, the processor needs to be interrupted by an interrupt, and the processor actively reads the encrypted data or decrypted data, or reads the data by configuring direct memory access (DMA) and then writes it into the memory of the target device. Among them, DMA transmission can copy data from one address space to another address space, providing high-speed data transmission between peripherals and memories or between memories and memories. When a large amount of data needs to be encrypted and decrypted, the interrupt method will cause the processor to be judged frequently, resulting in a decrease in the overall performance of the system.

[0158] In the embodiment of the present invention, the encryption and decryption algorithm module further includes a data write-back submodule, which is connected to the transposition reading submodule, and can directly read multiple processed data packets from the transposition reading submodule through the data write-back submodule, and then write the multiple processed data packets to a specified memory address in the target device. The specified memory address can be determined by a processor of the target device, and the specified memory address is sent to the data write-back submodule.

[0159] In the embodiment of the present invention, the data write-back submodule reads the processed data packets corresponding to each of the data packets to be processed from the transposition reading submodule, and writes each of the processed data packets to a specified memory address in the target device. In this way, the data transmission efficiency after the encryption and decryption processing of the data can be improved without interrupting the processor of the target device, and the influence of the encryption and decryption algorithm module on the processor can be reduced, thereby improving the overall system performance of the target device.

[0160] Optionally, the data write-back submodule includes a data read state machine; before step 1001, the method further includes:

[0161] Step 1101: When a preset data reading condition is met, a third read data signal is generated by the read data state machine, and the third read data signal is sent to the transposition read submodule;

[0162] Optionally, step 1001 may include the following steps:

[0163] Step 1001a: In response to the third read data signal, the transposition reading submodule returns the processed data packets corresponding to each of the to-be-processed data packets to the data write-back submodule.

[0164] In an embodiment of the present invention, the data write-back submodule may include a configuration register. Before the processor sends a data packet to be processed to the transposition distribution submodule, it is necessary to first configure the parameters of the configuration register of the data write-back submodule. For example, Table 2 is a configuration table of the configuration register of the data write-back submodule, see Table 2:

[0165] Table 2 Data write back submodule configuration register configuration table

[0166] Bit illustrate 31：0 Write back to the base address base 57：32 Write back data length 61：58 reserve 62 Write back module reset resetn 63 Write back completed done

[0167] The specific configuration process of the CPU / DMA configuration register for the data write back submodule includes:

[0168] 1. Determine the status of the data write-back submodule and wait for the last write-back operation to be completed;

[0169] 2. Write the reset data back to the submodule and set resetn to 0;

[0170] 3. Configure the write-back address and write-back data length of the data write-back submodule;

[0171] 4. Release the data write back submodule reset and set resetn to 1;

[0172] 5. Write the data packet to be processed into the transposition reading submodule through CPU / DMA;

[0173] 6. Determine the status of the data write-back submodule and wait for the current write-back operation to be completed.

[0174] In the embodiment of the present invention, a read_count counter may be set inside the data write-back submodule, and the read_count counter is used to record the length of the data read by the data write-back submodule from the transposition read submodule. The preset data reading condition may be that the length read_count of the read data recorded by the read_count counter is less than the write-back data length length configured in the register of the data write-back submodule, that is, read_count <length。

[0175] In an embodiment of the present invention, the data write-back submodule and the transposition read submodule may be connected via a fourth bus, and the read data state machine may be a state machine corresponding to the fourth bus. When a preset data read condition is met, a third read data signal corresponding to the fourth bus is generated by the read data state machine, and the third read data signal is sent to the transposition read submodule via the fourth bus. The third read data signal is used to instruct the transposition read submodule to return the processed data packets corresponding to each of the to-be-processed data packets to the data write-back submodule.

[0176] In an embodiment of the present invention, the third read data instruction sent by the data write back submodule can serve as the read data instruction received by the transpose read submodule. When the transpose read submodule receives the third read data instruction, the transpose read submodule responds to the third read data instruction and returns the processed data packets corresponding to each data packet to be processed to the data write back submodule.

[0177] Specifically, when the transposition reading submodule receives the third read data instruction, in response to the third read data instruction, the first read data signal corresponding to each read operation of the unpacking and assembling submodule is generated in sequence through the second state machine, and the first read data signal is sent to the unpacking and assembling submodule through the second bus. Then, the first read data signal is split into multiple read data sub-signals by the unpacking and assembling submodule, and the multiple read data sub-signals are sent to the storage submodule corresponding to each operation submodule, so as to instruct each storage submodule to return the second sub-data packet corresponding to the current read operation of the unpacking and assembling submodule in the first memory to the unpacking and assembling submodule. The second sub-data packets of the same order read out each time are merged by the unpacking and assembling subdevice to obtain multiple second transposed data packets, and the multiple second transposed data packets are sent to the transposition reading submodule. Furthermore, the transposition reading submodule generates the processed data packets corresponding to each to-be-processed data packet according to the data in the multiple second transposed data packets, and the processed data packets corresponding to each to-be-processed data packet are returned to the data write-back submodule.

[0178] In an embodiment of the present invention, when the preset data reading condition is met, the third read data signal is generated by the read data state machine, and the third read data signal is sent to the transposition read submodule; the transposition read submodule responds to the third read data signal and returns the processed data packets corresponding to each of the to-be-processed data packets to the data write-back submodule. In this way, the read data state machine can coordinate the signal action of the data read operation on the transposition read submodule, and the third read data signal generated by the read data state machine instructs the transposition read submodule to return the processed data packet to the data write-back submodule, thereby improving the rationality of the data read operation on the transposition read submodule, and to a certain extent, the data transmission efficiency between the data write-back submodule and the transposition read submodule can be improved.

[0179] Optionally, the data write-back submodule further includes a second memory; and the method further includes:

[0180] Step 1201: Store the processed data packets corresponding to each of the data packets to be processed into the second memory through the data write-back submodule.

[0181] Optionally, step 1001 may include the following steps:

[0182] Step 1001b: When a preset data writing condition is met, each of the processed data packets is read from the second memory through the data write-back submodule, and each of the processed data packets is written to the designated memory address in the target device.

[0183] In the embodiment of the present invention, the second memory is used to temporarily store the processed data packets read by the data write-back sub-module from the transpose read sub-module. For example, the second memory can be a FIFO memory. The preset data writing condition can be that the second memory is not empty, that is, when there are processed data packets stored in the second memory, the data write-back sub-module automatically reads the processed data packets from the second memory and writes the processed data packets to the specified memory address in the target device.

[0184] Figure 4 is a state diagram of the read data state machine provided by the embodiment of the present invention. As Figure 4 shown, the fourth bus connecting the data write-back sub-module and the transpose read sub-module can be an AXI bus, and the read data state machine is the state machine corresponding to the AXI bus. When the read data state machine is reset, it is in the IDLE state. After the read data state machine releases the reset, if it judges that read_count < length, it enters the READ_A state, generates the third read data signal, that is, the AXI bus signal, and sends the third read data signal to the transpose read sub-module. Pull up the arready bit to enter the READ_R state and wait for the transpose read sub-module to return the processed data packet. When rvalid is valid, it enters the READ_D state, stores the read processed data packet into the second memory, such as an internal fifo. If the internal fifo is not full, it returns to the IDLE state to prepare for the next round of reading operations.

[0185] In the embodiment of the present invention, each processed data packet corresponding to each to-be-processed data packet is stored in the second memory through the data write-back sub-module; when the preset data writing condition is met, each processed data packet is read from the second memory through the data write-back sub-module and written to the specified memory address in the target device. In this way, the second memory can be used to temporarily store the to-be-processed data packets read from the transpose read sub-module, relieve the data transmission pressure between the data write-back sub-module and the transpose read sub-module, and correspondingly improve the data transmission efficiency between the data write-back sub-module and the transpose read sub-module.

[0186] Optionally, the data write-back sub-module further includes a write data state machine; step 1001b may include the following steps:

[0187] Step 1001b1, through the write data state machine, sequentially write each processed data packet in the second memory to the specified memory address in the target device in the increasing order of the memory address of the target device.

[0188] In an embodiment of the present invention, the data write back submodule and the memory of the target device can be connected through a fifth bus, and the data write state machine can be a state machine corresponding to the fifth bus. The data write state machine is used to read the processed data packet from the second memory, and write the processed data packet to the specified memory address in the memory of the target device through the fifth bus. Specifically, the data write state machine reads the first processed data packet from the second memory, and writes the first processed data packet to the write back base address in the configuration register of the data write back submodule, and then performs an address increment operation according to the data length of a processed data packet to obtain the write back address corresponding to the next processed data packet, and then reads the second processed data packet from the second memory and writes it to the write back address in the target device. By analogy, in accordance with the memory address increment method of the target device, each processed data packet in the second memory is sequentially written to the specified memory address in the target device.

[0189] Figure 5 is a state diagram of a data writing state machine provided in an embodiment of the present invention, such as Figure 5 As shown, the fifth bus connecting the data write-back submodule and the memory of the target device can be an AXI bus, and the data write state machine is a state machine corresponding to the AXI bus. A write_count counter is set inside the data write-back submodule, and the write_count counter is used to record the data length written back to the specified memory address. The unit of write_count can be the sum of the data lengths of N data packets to be processed. When the write data state machine system is reset, it is in the IDLE state. After the write data state machine releases the reset, it determines whether the second memory, such as the internal fifo, is empty. If it is not empty, it enters the WRITE_A state, issues a write-back base address, and increments the write-back base address base, pulls up the arready bit to enter the WRTITE_D state, and writes the data of the internal fifo to the specified memory address in the target device through the AXI bus. If wready=1, it enters the WRITE_B state, waits for bvalid to be valid, and then returns to the IDLE state to prepare for the next round of write operations.

[0190] In the embodiment of the present invention, the data write state machine sequentially writes the processed data packets in the second memory to the designated memory address in the target device in an increasing manner according to the memory address of the target device. In this way, the signal action of the write operation can be coordinated by the data write state machine to improve the efficiency of the write operation.

[0191] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0192] The embodiment of the present invention provides an encryption and decryption algorithm module for executing the data processing method as described in the above embodiment; the encryption and decryption algorithm module includes a transposition distribution submodule, a transposition reading submodule, an unpacking and packaging submodule and a plurality of operation submodules;

[0193] The transposition distribution submodule is used to receive a plurality of data packets to be processed, and extract data from each of the data packets to be processed in turn and merge them into one data packet to obtain a plurality of first transposed data packets, and send the plurality of first transposed data packets to the unpacking and packaging submodule in turn; the number of the plurality of data packets to be processed is consistent with the number of the plurality of operation submodules, and each data packet to be processed is processed by one operation submodule;

[0194] For any of the first transposed data packets, the first transposed data packet is split into a plurality of first sub-data packets by the unpacking and packing sub-module, and the plurality of first sub-data packets are respectively sent to the corresponding operation sub-modules; the data length of the first sub-data packet matches the interface bit width of the operation sub-module;

[0195] The operation submodule is used to merge the received first sub-data packets into a data packet to be processed corresponding to the operation submodule, and perform encryption or decryption processing on the data in the data packet to be processed to obtain a processing result corresponding to the data packet to be processed;

[0196] The transposition reading submodule is used to read the processing results corresponding to each of the data packets to be processed from the multiple operation submodules, and generate processed data packets corresponding to each of the data packets to be processed according to the processing results corresponding to each of the data packets to be processed.

[0197] Optionally, the transposition distribution submodule is further used for:

[0198] For any of the data packets to be processed, dividing the data in the data packet to be processed into a plurality of first sub-data packets according to the data sequence;

[0199] The first sub-data packets of the same order are sequentially extracted from each of the data packets to be processed, and the first sub-data packets of the same order extracted each time are merged to obtain the multiple first transposed data packets.

[0200] Optionally, the encryption and decryption algorithm module further includes a first bus, the transposition distribution submodule includes a first state machine corresponding to the first bus, and the transposition distribution submodule is connected to the unpacking and packaging submodule via the first bus;

[0201] The transposition distribution submodule is further specifically configured to: in any case where a first transposed data packet is obtained through the transposition distribution submodule, store the first transposed data packet in the first state machine;

[0202] The first state machine is used to: generate a write data signal corresponding to the first transposed data packet when the first transposed data packet is obtained through the transposition distribution submodule at any time, and send the first transposed data packet and the write data signal to the unpacking and assembling submodule through the first bus;

[0203] The unpacking and packaging submodule is specifically used to: send the write data signal to the multiple operation submodules; the write data signal is used to instruct the operation submodule to receive the first sub-data packet sent by the unpacking and packaging submodule, and store the data in the first sub-data packet to a specified location.

[0204] Optionally, the unpacking and packaging submodule is further used for:

[0205] The write data signal is split into multiple write data sub-signals, and the multiple write data sub-signals are sent to their respective corresponding operation sub-modules; the number of the multiple write data sub-signals is consistent with the number of the multiple operation sub-modules, and the write data sub-signals are used to instruct the corresponding operation sub-module to receive the first sub-data packet sent by the unpacking and packaging sub-module, and store the data in the first sub-data packet to a specified location.

[0206] Optionally, in the case where the interface bit width of the transposition reading submodule is greater than the interface bit width of the operation submodule, the transposition reading submodule is connected to the unpacking and packaging submodule;

[0207] The operation submodule is specifically used to: divide the data in the obtained processing result into a plurality of second sub-data packets according to the data sequence; the data length of the second sub-data packet matches the interface bit width of the operation submodule;

[0208] The unpacking and packing submodule is further specifically used for: sequentially reading the second sub-data packets of the same order from each of the operation submodules, merging the second sub-data packets of the same order read out each time to obtain a plurality of second transposed data packets, and sequentially sending the plurality of second transposed data packets to the transposition reading submodule;

[0209] The transposed reading submodule is specifically used to generate processed data packets corresponding to each of the to-be-processed data packets according to the data in the plurality of second transposed data packets.

[0210] Optionally, the transposition reading submodule is further used for:

[0211] The second sub-data packets belonging to the same operation submodule are extracted from each of the second transposed data packets in sequence, and the second sub-data packets belonging to the same operation submodule extracted each time are merged to obtain processed data packets corresponding to each of the to-be-processed data packets.

[0212] Optionally, the encryption and decryption algorithm module further includes a second bus, the transposition reading submodule includes a second state machine corresponding to the second bus, and the transposition reading submodule is connected to the unpacking and packaging submodule via the second bus;

[0213] The second state machine is used to: when the transposition reading submodule receives a read data instruction, before the unpacking and assembling submodule reads the second sub-data packets of the same order from each of the operation submodules, generate a first read data signal corresponding to the current read operation of the unpacking and assembling submodule, and send the first read data signal to the unpacking and assembling submodule through the second bus;

[0214] The unpacking and packing submodule is further configured to: send the first read data signal to each of the operation submodules;

[0215] The operation submodule is also specifically used to: in any case where the second sub-data packet of the same order is read from each of the operation submodules through the unpacking and packing submodule, in response to the first read data signal, return the second sub-data packet corresponding to the current read operation of the unpacking and packing submodule to the unpacking and packing submodule.

[0216] Optionally, the unpacking and packaging submodule is further used for:

[0217] Splitting the first read data signal into a plurality of read data sub-signals, and sending the plurality of read data sub-signals to the respective corresponding operation sub-modules;

[0218] The operation submodule is further specifically used for returning, to the unpacking and packing submodule, a second subdata packet corresponding to the current read operation of the unpacking and packing submodule in response to the corresponding read data subsignal.

[0219] Optionally, the encryption and decryption algorithm module further includes a plurality of third buses, the unpacking and packaging submodule and the operation submodule are connected via the third buses, and the third bus includes a write channel and a read channel;

[0220] The unpacking and packaging submodule is further specifically used to: for any operation submodule, send the first sub-data packet corresponding to the operation submodule to the operation submodule through the write channel corresponding to the operation submodule;

[0221] The unpacking and packaging submodule is further specifically used to: for any operation submodule, send the write data sub-signal corresponding to the operation submodule to the operation submodule through the write channel corresponding to the operation submodule;

[0222] The unpacking and packaging submodule is further specifically used to: for any operation submodule, send the read data sub-signal corresponding to the operation submodule to the operation submodule through the read channel corresponding to the operation submodule;

[0223] The unpacking and packaging submodule is also specifically used for: in any case where the second sub-packets of the same order are read from each of the operation submodules through the unpacking and packaging submodule, the second sub-packets of the same order are read from each of the operation submodules through the read channels corresponding to each of the operation submodules.

[0224] Optionally, the read channel includes a storage submodule, and the storage submodule includes a first memory;

[0225] The storage submodule is used to: read the multiple second sub-data packets in the operation submodule corresponding to the storage submodule under the condition of meeting the preset storage condition, and store the multiple second sub-data packets in the first memory;

[0226] The unpacking and packing submodule is further specifically used for reading the second sub-data packets of the same order from each of the first memories.

[0227] Optionally, the storage submodule further includes a third state machine corresponding to the third bus;

[0228] The third state machine is used to: before the storage submodule reads the plurality of second sub-data packets in the operation submodule corresponding to the storage submodule, send a second read data signal to the operation submodule corresponding to the storage submodule;

[0229] The operation submodule is further specifically configured to return the plurality of second sub-data packets to the storage submodule in response to the second read data signal.

[0230] Optionally, the encryption and decryption algorithm module is set in a target device, and the target device includes a processor;

[0231] The transposition distribution submodule is also specifically used to: receive data processing instructions sent by the processor; the data processing instructions are used to instruct the encryption and decryption algorithm module to encrypt or decrypt the multiple data packets to be processed; the multiple data packets to be processed are data packets sent by the processor to the transposition distribution submodule.

[0232] Optionally, the encryption and decryption algorithm module further includes a data write-back submodule, and the data write-back submodule is connected to the transposition reading submodule;

[0233] The data write-back submodule is used to read the processed data packets corresponding to each of the data packets to be processed from the transposition reading submodule, and write each of the processed data packets to a designated memory address in the target device.

[0234] Optionally, the data write-back submodule includes a data read state machine;

[0235] The data read state machine is used to: before the data write-back submodule reads the processed data packets corresponding to each of the to-be-processed data packets from the transposition read submodule, if a preset data read condition is met, generate a third read data signal and send the third read data signal to the transposition read submodule;

[0236] The transposition reading submodule is further specifically configured to: in response to the third read data signal, return the processed data packets corresponding to each of the to-be-processed data packets to the data write-back submodule.

[0237] Optionally, the data write-back submodule further includes a second memory;

[0238] The data write-back submodule is specifically used to: store the processed data packets corresponding to each of the data packets to be processed in the second memory, and, when the preset data writing conditions are met, read each of the processed data packets from the second memory and write each of the processed data packets to the designated memory address in the target device.

[0239] Optionally, the data write-back submodule further includes a data write state machine;

[0240] The data writing state machine is used to write the processed data packets in the second memory to the designated memory address in the target device in sequence according to the increasing memory address of the target device.

[0241] Figure 6 is a schematic diagram of the structure of an encryption and decryption algorithm module provided by an embodiment of the present invention, such as Figure 6As shown, the encryption and decryption algorithm module includes a data write-back submodule, a transposition distribution submodule, a transposition reading submodule, an unpacking and packaging submodule, and multiple operation submodules, wherein the data write-back submodule is connected to the transposition reading submodule, the transposition distribution submodule is connected to the unpacking and packaging submodule through a first bus, the transposition reading submodule is connected to the unpacking and packaging submodule through a second bus, and the unpacking and packaging submodule is connected to each operation submodule through a third bus, the third bus includes a write channel and a read channel, and the read channel includes a storage submodule. The encryption and decryption algorithm module is configured to execute the data processing method as described in the above embodiment.

[0242] An embodiment of the present invention provides a chip, which includes the encryption and decryption algorithm module as described in the above embodiment, and is used to execute the data processing method as described in the above embodiment.

[0243] Reference Figure 7 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 7 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the data processing method of the aforementioned embodiment.

[0244] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or processor of a terminal, the terminal is enabled to execute the data processing method of the aforementioned embodiment.

[0245] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0246] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0247] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0248] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0249] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0250] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0251] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0252] The data processing method, encryption and decryption algorithm module, chip and electronic device provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A data processing method, characterized in that: Applied to an encryption and decryption algorithm module, the encryption and decryption algorithm module includes a transposition distribution submodule, a transposition reading submodule, an unpacking and packaging submodule, and a plurality of operation submodules, the interface width of the transposition distribution submodule is greater than the interface width of the operation submodule, and the method includes: The transposition distribution submodule receives a plurality of data packets to be processed, extracts data from each of the data packets to be processed in turn and merges them into one data packet to obtain a plurality of first transposed data packets, and sends the plurality of first transposed data packets to the unpacking and packaging submodule in turn; the number of the plurality of data packets to be processed is consistent with the number of the plurality of operation submodules, and each data packet to be processed is processed by one operation submodule; For any of the first transposed data packets, the first transposed data packet is split into a plurality of first sub-data packets by the unpacking and packing sub-module, and the plurality of first sub-data packets are respectively sent to the corresponding operation sub-modules; the data length of the first sub-data packet matches the interface bit width of the operation sub-module; For any of the operation submodules, the operation submodule combines the received first sub-data packets into a data packet to be processed corresponding to the operation submodule, and encrypts or decrypts the data in the data packet to be processed to obtain a processing result corresponding to the data packet to be processed; The processing results corresponding to each of the data packets to be processed are read from the multiple operation submodules through the transposition reading submodule, and processed data packets corresponding to each of the data packets to be processed are generated according to the processing results corresponding to each of the data packets to be processed.

2. The method according to claim 1, characterized in that The step of extracting data from each of the to-be-processed data packets in turn and merging them into one data packet to obtain a plurality of first transposed data packets comprises: For any of the data packets to be processed, the data in the data packet to be processed is divided into a plurality of first sub-data packets according to the data sequence by the transposition distribution submodule; The transposition distribution submodule sequentially extracts first sub-data packets of the same order from each of the to-be-processed data packets, and merges the first sub-data packets of the same order extracted each time to obtain the multiple first transposed data packets.

3. The method according to claim 2, characterized in that The encryption and decryption algorithm module further includes a first bus, the transposition distribution submodule includes a first state machine corresponding to the first bus, and the transposition distribution submodule is connected to the unpacking and packaging submodule via the first bus; Before sending the plurality of first transposed data packets sequentially to the packet disassembling and packet assembly submodule, the method further includes: In any case where a first transposed data packet is obtained by the transposition distribution submodule, the first transposed data packet is stored in the first state machine by the transposition distribution submodule, and a write data signal corresponding to the first transposed data packet is generated by the first state machine; The sending of the plurality of first transposed data packets to the unpacking and packaging submodule in sequence through the transposition distribution submodule comprises: Sending the first transposed data packet and the write data signal to the unpacking and assembling submodule through the first bus by means of the first state machine; The method further comprises: The write data signal is sent to the multiple operation submodules through the unpacking and packaging submodule; the write data signal is used to instruct the operation submodule to receive the first sub-data packet sent by the unpacking and packaging submodule, and store the data in the first sub-data packet to a specified location.

4. The method according to claim 3, characterized in that The sending the write data signal to the multiple operation submodules through the unpacking and packaging submodule includes: The write data signal is split into multiple write data sub-signals by the unpacking and packaging sub-module, and the multiple write data sub-signals are sent to their corresponding operation sub-modules; the number of the multiple write data sub-signals is consistent with the number of the multiple operation sub-modules, and the write data sub-signals are used to instruct the corresponding operation sub-module to receive the first sub-data packet sent by the unpacking and packaging sub-module, and store the data in the first sub-data packet to a designated location.

5. The method according to any one of claims 1 to 4, characterized in that: Before reading the processing results corresponding to each of the data packets to be processed from the multiple operation submodules through the transposition reading submodule, and generating processed data packets corresponding to each of the data packets to be processed according to the processing results corresponding to each of the data packets to be processed, the method further includes: For any of the operation submodules, the data in the obtained processing result is divided into a plurality of second sub-data packets according to the data sequence by the operation submodule; the data length of the second sub-data packet matches the interface bit width of the operation submodule; The method of reading the processing results corresponding to each of the data packets to be processed from the multiple operation submodules through the transposition reading submodule, and generating processed data packets corresponding to each of the data packets to be processed according to the processing results corresponding to each of the data packets to be processed, includes: The unpacking and packing submodule sequentially reads the second sub-data packets of the same order from each of the operation submodules, and merges the second sub-data packets of the same order read out each time to obtain a plurality of second transposed data packets, and sequentially sends the plurality of second transposed data packets to the transposition reading submodule; The transposed reading submodule generates processed data packets corresponding to each of the to-be-processed data packets according to the data in the plurality of second transposed data packets.

6. The method according to claim 5, characterized in that Generating processed data packets corresponding to each of the data packets to be processed according to the data in the plurality of second transposed data packets comprises: The transposed reading submodule sequentially extracts second sub-data packets belonging to the same operation submodule from each of the second transposed data packets, and merges the second sub-data packets belonging to the same operation submodule extracted each time to obtain processed data packets corresponding to each of the data packets to be processed.

7. The method according to claim 6, characterized in that The encryption and decryption algorithm module further includes a second bus, the transposition reading submodule includes a second state machine corresponding to the second bus, and the transposition reading submodule is connected to the unpacking and packaging submodule via the second bus; In the case where the transposition reading submodule receives a read data instruction, the method further includes: Before reading the second sub-data packets of the same order from each of the operation sub-modules by the unpacking and assembling sub-module at any time, generating a first read data signal corresponding to the current read operation of the unpacking and assembling sub-module by the second state machine, and sending the first read data signal to the unpacking and assembling sub-module via the second bus; Sending the first read data signal to each of the operation submodules through the unpacking and packaging submodule; The step of sequentially reading the second sub-data packets of the same order from each of the operation sub-modules through the unpacking and packing sub-module includes: In any case where the unpacking and packing submodule reads the second sub-data packet of the same order from each of the operation submodules, each of the operation submodules responds to the first read data signal to return the second sub-data packet corresponding to the current read operation of the unpacking and packing submodule to the unpacking and packing submodule.

8. The method according to claim 7, characterized in that Before sending the first read data signal to each of the operation submodules through the unpacking and packaging submodule, the method further includes: Splitting the first read data signal into a plurality of read data sub-signals by the unpacking and packaging sub-module; The sending the first read data signal to each of the operation submodules through the unpacking and packaging submodule includes: Sending the plurality of read data sub-signals to the respective corresponding operation sub-modules through the unpacking and packing sub-module; The returning, by each of the operation submodules in response to the first read data signal, to the unpacking and packaging submodule a second subdata packet corresponding to the current read operation of the unpacking and packaging submodule, comprises: For any of the operation submodules, in response to the corresponding read data sub-signal, a second sub-data packet corresponding to the current read operation of the unpacking and packing submodule is returned to the unpacking and packing submodule.

9. The method according to any one of claims 6 to 8, characterized in that: The encryption and decryption algorithm module further includes a plurality of third buses, the unpacking and packaging submodule and the operation submodule are connected via the third buses, and the third bus includes a write channel and a read channel; The sending of the plurality of first sub-data packets to the respective corresponding operation sub-modules comprises: For any of the operation submodules, the first sub-data packet corresponding to the operation submodule is sent to the operation submodule through the unpacking and packing submodule via the write channel corresponding to the operation submodule; The sending of the plurality of write data sub-signals to the respective corresponding operation sub-modules comprises: For any of the operation submodules, the unpacking and packaging submodule sends the write data subsignal corresponding to the operation submodule to the operation submodule through the write channel corresponding to the operation submodule; The sending of the plurality of read data sub-signals to the respective corresponding operation sub-modules through the unpacking and packing sub-module comprises: For any of the operation submodules, the unpacking and packaging submodule sends the read data sub-signal corresponding to the operation submodule to the operation submodule through the read channel corresponding to the operation submodule; The step of sequentially reading the second sub-data packets of the same order from each of the operation sub-modules through the unpacking and packing sub-module includes: In any case where the second sub-data packets of the same order are read from each of the operation sub-modules by the unpacking and packing sub-module, the second sub-data packets of the same order are read from each of the operation sub-modules by the unpacking and packing sub-module through the read channels corresponding to each of the operation sub-modules.

10. The method according to claim 9, characterized in that The read channel includes a storage submodule, and the storage submodule includes a first memory; before the second sub-data packets of the same order are read from each of the operation submodules through the read channels corresponding to the operation submodules through the unpacking and packing submodules, the method further includes: In the case where a preset storage condition is met, the plurality of second sub-data packets in the operation sub-module corresponding to the storage sub-module are read by the storage sub-module, and the plurality of second sub-data packets are stored in the first memory; The step of reading the second sub-data packets of the same order from each of the operation sub-modules through the read channels corresponding to each of the operation sub-modules by the unpacking and packing sub-module includes: The second sub-data packets of the same sequence are read from each of the first memories through the depacketizing and packing sub-module.

11. The method according to claim 10, characterized in that The storage submodule further includes a third state machine corresponding to the third bus; before reading the plurality of second sub-data packets in the operation submodule corresponding to the storage submodule through the storage submodule, the method further includes: Sending a second read data signal to the operation submodule corresponding to the storage submodule through the third state machine; The step of reading the plurality of second sub-data packets in the operation sub-module through the storage sub-module comprises: The operation submodule returns the plurality of second sub-data packets to the storage submodule in response to the second read data signal.

12. The method according to claim 10 or 11, characterized in that: The encryption and decryption algorithm module is set in the target device, and the target device includes a processor; the method also includes: The data processing instructions sent by the processor are received through the transposition distribution submodule; the data processing instructions are used to instruct the encryption and decryption algorithm module to encrypt or decrypt the multiple data packets to be processed; the multiple data packets to be processed are data packets sent by the processor to the transposition distribution submodule.

13. The method according to claim 12, characterized in that The encryption and decryption algorithm module further includes a data write-back submodule, and the data write-back submodule is connected to the transposition reading submodule; the method further includes: The data write-back submodule reads the processed data packets corresponding to each of the data packets to be processed from the transposition reading submodule, and writes each of the processed data packets to a designated memory address in the target device.

14. The method according to claim 13, characterized in that The data write-back submodule includes a data read state machine; before the data write-back submodule reads the processed data packets corresponding to each of the to-be-processed data packets from the transposition read submodule, the method further includes: In the case of meeting the preset data reading condition, generating a third read data signal through the read data state machine, and sending the third read data signal to the transposition read submodule; The step of reading the processed data packets corresponding to the data packets to be processed from the transposition reading submodule through the data write-back submodule comprises: The transposed reading submodule responds to the third read data signal to return the processed data packets corresponding to each of the to-be-processed data packets to the data write-back submodule.

15. The method according to claim 14, characterized in that The data write-back submodule further includes a second memory; and the method further includes: The data write-back submodule stores the processed data packets corresponding to the data packets to be processed in the second memory; Writing each of the processed data packets to a specified memory address in the target device includes: When the preset data writing condition is met, each of the processed data packets is read from the second memory through the data write-back submodule, and each of the processed data packets is written to the designated memory address in the target device.

16. The method according to claim 15, characterized in that The data write-back submodule further includes a data write state machine; the step of writing each of the processed data packets to the designated memory address in the target device includes: The data write state machine writes the processed data packets in the second memory to the designated memory address in the target device in sequence in an increasing manner according to the memory address of the target device.

17. An encryption and decryption algorithm module, characterized in that: Used to execute the data processing method according to claim 1; the encryption and decryption algorithm module includes a transposition distribution submodule, a transposition reading submodule, an unpacking and packaging submodule and a plurality of operation submodules; The transposition distribution submodule is used to receive a plurality of data packets to be processed, and extract data from each of the data packets to be processed in turn and merge them into one data packet to obtain a plurality of first transposed data packets, and send the plurality of first transposed data packets to the unpacking and packaging submodule in turn; the number of the plurality of data packets to be processed is consistent with the number of the plurality of operation submodules, and each data packet to be processed is processed by one operation submodule; For any of the first transposed data packets, the first transposed data packet is split into a plurality of first sub-data packets by the unpacking and packing sub-module, and the plurality of first sub-data packets are respectively sent to the corresponding operation sub-modules; the data length of the first sub-data packet matches the interface bit width of the operation sub-module; The operation submodule is used to merge the received first sub-data packets into a data packet to be processed corresponding to the operation submodule, and perform encryption or decryption processing on the data in the data packet to be processed to obtain a processing result corresponding to the data packet to be processed; The transposition reading submodule is used to read the processing results corresponding to each of the data packets to be processed from the multiple operation submodules, and generate processed data packets corresponding to each of the data packets to be processed according to the processing results corresponding to each of the data packets to be processed.

18. A chip, characterized in that: The chip includes the encryption and decryption algorithm module as described in claim 17, which is used to execute the data processing method as described in any one of claims 1 to 16.

19. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store executable instructions, and the executable instructions enable the processor to execute the data processing method according to any one of claims 1 to 16.

Images