Resistive random access memory structure and forming method thereof

Abstract

The invention discloses a resistive random access memory structure and a forming method thereof. The forming method comprises the following steps: providing a substrate; a conductive material layer is formed on the substrate, the conductive material layer comprises a first region and a second region located on the first region, and the first region is used as a first electrode layer; performing oxidation treatment on the second region to form an insulating oxide layer; and forming a second electrode layer on the insulating oxide layer. The insulating oxide layer is formed by oxidizing the second region of the conductive material layer, and the thickness of the insulating oxide layer and the distribution of oxygen vacancies in the insulating oxide layer can be accurately controlled by controlling technological parameters (such as gas proportion, sputtering power and sputtering time) in the oxidation treatment process. In addition, the first electrode layer and the insulating oxide layer are of an integral structure formed based on the conductive material layer, and an air layer cannot be formed on a contact interface between the first electrode layer and the insulating oxide layer, so that the stability and the performance of the resistive random access memory structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a resistive memory structure and a forming method thereof. Background Art

[0002] Resistive Random Access Memory (RRAM) uses certain thin film materials to exhibit two or more different resistance states under the action of an external electric field to achieve data storage. It is a new type of non-volatile memory that has attracted widespread attention from academia and industry in the past decade. Its typical structure is metal electrode-oxide-metal electrode.

[0003] Under the stimulation of an external electric field, the device can undergo a reversible change between high and low resistance states, and its high and low resistance states can still be maintained after the electric field is removed. Resistive random access memory has many advantages such as fast erase and write speed, high storage density, high number of repeated erase and write times, multi-value storage and three-dimensional storage. Under the stimulation of an external electric field, the device can undergo a reversible change between high and low positive states, and its high and low resistance states can still be maintained after the electric field is removed.

[0004] The forming process refers to the process in which the RRAM jumps from the initial high-resistance state to the low-resistance state for the first time. Conversely, the RRAM in the low-resistance state can be converted to the high-resistance state after a certain voltage is applied. The process of the low-resistance state jumping to the high-resistance state is called Reset. The RRAM that enters the high-resistance state after the Reset process can also be converted to the low-resistance state by applying voltage stimulation. This process is different from the first high-resistance state jumping to the low-resistance state, which is called the Set process.

[0005] However, the resistive memory structure in the prior art still has many problems. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a resistive memory structure and a method for forming the same, so as to improve the stability and performance of the resistive memory.

[0007] To solve the above problems, the present invention provides a resistive memory structure, comprising: a substrate; a first electrode layer located on the substrate; an insulating oxide layer located on the first electrode layer, the first electrode layer and the insulating oxide layer are an integral structure; and a second electrode layer formed on the insulating oxide layer.

[0008] Optionally, the thickness of the insulating oxide layer is 10 nanometers to 50 nanometers.

[0009] Optionally, it further includes: a passivation layer located on the first electrode layer, wherein the passivation layer surrounds the insulating oxide layer.

[0010] Optionally, the material of the passivation layer includes: silicon nitride or silicon oxide.

[0011] Optionally, the material of the first electrode layer includes: tantalum nitride.

[0012] Optionally, the material of the insulating oxide layer includes: tantalum oxynitride.

[0013] Optionally, the material of the second electrode layer includes: titanium nitride, tungsten or an inert electrode material; the inert electrode material includes: platinum, gold, palladium, iridium, rhodium, silver or lead.

[0014] Correspondingly, the technical solution of the present invention also provides a method for forming a resistive memory structure, comprising: providing a substrate; forming a conductive material layer on the substrate, the conductive material layer comprising a first region and a second region located on the first region, the first region being used as a first electrode layer; oxidizing the second region to form an insulating oxide layer; and forming a second electrode layer on the insulating oxide layer.

[0015] Optionally, the process parameters of the oxidation treatment include: the sputtering ions include oxygen ions and argon ions; the gas flow ratio of oxygen ions to argon ions is 1:4 to 1:1; the sputtering power is 100 watts to 300 watts; the sputtering time is 5 minutes to 30 minutes; the target material applied voltage is -400 volts to -600 volts; the substrate applied voltage is 200 volts to 400 volts.

[0016] Optionally, the thickness of the insulating oxide layer is 10 nanometers to 50 nanometers.

[0017] Optionally, after forming the conductive material layer and before performing the oxidation treatment, the method further includes: etching the conductive material layer to form an isolation opening in the conductive material layer; and forming a passivation layer in the isolation opening.

[0018] Optionally, the material of the passivation layer includes: silicon nitride or silicon oxide.

[0019] Optionally, the material of the conductive material layer includes: tantalum nitride.

[0020] Optionally, the material of the insulating oxide layer includes: tantalum oxynitride.

[0021] Optionally, the process for forming the conductive material layer includes: a chemical vapor deposition process.

[0022] Optionally, the second electrode layer is formed by a process including a physical vapor deposition process or a magnetron sputtering process.

[0023] Optionally, the material of the second electrode layer includes: titanium nitride, tungsten or an inert electrode material; the inert electrode material includes: platinum, gold, palladium, iridium, rhodium, silver or lead.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the resistive memory structure of the technical solution of the present invention, the first electrode layer and the insulating oxide layer are an integral structure, and no air layer is formed at the contact interface between the two, thereby improving the stability and performance of the resistive memory structure.

[0026] In the method for forming a resistive memory structure of the technical solution of the present invention, the insulating oxide layer is formed by oxidizing the second region of the conductive material layer, and the thickness of the insulating oxide layer and the distribution of oxygen vacancies in the insulating oxide layer can be accurately controlled by controlling the process parameters (such as gas ratio, sputtering power and sputtering time, etc.) during the oxidation process. In addition, the first electrode layer and the insulating oxide layer are an integral structure formed based on the conductive material layer, and the contact interface between the two does not form an air layer, thereby improving the stability and performance of the resistive memory structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figures 1 to 5 It is a schematic structural diagram of each step of a method for forming a resistive memory structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] As described in the background art, the resistive random access memory structure in the prior art still has many problems, which will be described in detail below.

[0029] At present, in the process of preparing resistive random access memory (RRAM), the insulating oxide layer (or dielectric layer) usually needs to be formed by complex chemical or physical deposition. The deposition process not only has a high production cost, but also the thickness of the insulating oxide layer formed by deposition is difficult to control, resulting in uneven film quality. The generation and distribution of oxygen vacancies in the insulating oxide layer formed by the deposition process are also difficult to accurately control. In addition, the insulating oxide layer and the electrode layer formed are discrete structures, and an air layer is easily formed between the two, which in turn affects the stability and performance of the resistive random access memory.

[0030] On this basis, the present invention provides a resistive memory structure and a method for forming the same, wherein the insulating oxide layer is formed by oxidizing the second region of the conductive material layer, and the thickness of the insulating oxide layer and the distribution of oxygen vacancies in the insulating oxide layer can be accurately controlled by controlling process parameters (such as gas ratio, sputtering power and sputtering time, etc.) during the oxidation process. In addition, the first electrode layer and the insulating oxide layer are an integral structure formed based on the conductive material layer, and an air layer will not be formed at the contact interface between the two, thereby improving the stability and performance of the resistive memory structure.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 5 It is a schematic structural diagram of each step of a method for forming a resistive memory structure according to an embodiment of the present invention.

[0033] Please refer to Figure 1 , providing a substrate 100.

[0034] In this embodiment, the material of the substrate 100 is silicon.

[0035] In other embodiments, the material of the substrate may also be germanium, silicon germanium or silicon carbide.

[0036] Please refer to Figure 2 , a conductive material layer is formed on the substrate 100 , the conductive material layer includes a first region I and a second region II located on the first region I, and the first region I is used as a first electrode layer 101 .

[0037] It should be noted that, in this embodiment, the first region I in the conductive material layer is used as the first electrode layer 101, so the conductive material layer needs to have conductivity. In the subsequent process, the second region II of the conductive material layer needs to be oxidized to form an insulating oxide layer in the resistive memory, so the conductive material layer also needs to have the property of insulation after oxidation.

[0038] In this embodiment, the conductive material layer is made of tantalum nitride.

[0039] In this embodiment, the conductive material layer is formed by a chemical vapor deposition process.

[0040] Please refer to Figure 3 After the conductive material layer is formed, the conductive material layer is etched to form an isolation opening (not shown) in the conductive material layer; and a passivation layer 102 is formed in the isolation opening.

[0041] In this embodiment, the passivation layer 102 is used for electrical isolation between device structures. The passivation layer 102 is an insulating material, and the material of the passivation layer 102 is silicon oxide.

[0042] In other embodiments, the material of the passivation layer may also be silicon nitride.

[0043] In this embodiment, the method for forming the passivation layer 102 includes: forming a passivation material layer (not shown) in the isolation opening and on the conductive material layer; and planarizing the passivation material layer until the top surface of the conductive material layer is exposed to form the passivation layer 102.

[0044] Please refer to Figure 4 , the second region II is oxidized to form an insulating oxide layer 103.

[0045] The insulating oxide layer 103 is formed by performing oxidation treatment on the second region II of the conductive material layer, and by controlling process parameters (such as gas ratio, sputtering power and sputtering time, etc.) during the oxidation treatment, the thickness of the insulating oxide layer 103 and the distribution of oxygen vacancies in the insulating oxide layer 103 can be accurately controlled. In addition, the first electrode layer 101 and the insulating oxide layer 103 are an integral structure formed based on the conductive material layer, and no air layer is formed at the contact interface between the two, thereby improving the stability and performance of the resistive random access memory structure.

[0046] It should be noted that, in the present embodiment, the point resistance of the insulating oxide layer 103 is variable. When a high voltage is applied to the insulating oxide layer 103, the oxygen ions in the insulating oxide layer 103 are rearranged in a regular manner to form conductive filaments, thereby making the insulating oxide layer 103 present a low-resistance state; when the applied high voltage is removed, the conductive filaments formed by the oxygen ions are broken, and the insulating oxide layer 103 presents a high-resistance state.

[0047] In this embodiment, since the conductive material layer is made of tantalum nitride, the corresponding material of the insulating oxide layer 103 is tantalum oxynitride.

[0048] In this embodiment, the process parameters of the oxidation treatment include: the sputtering ions include oxygen ions and argon ions; the gas flow ratio of oxygen ions and argon ions is 1:4 to 1:1; the sputtering power is 100 watts to 300 watts; the sputtering time is 5 minutes to 30 minutes; the target material applied voltage is -400 volts to -600 volts; the substrate 100 applied voltage is 200 volts to 400 volts.

[0049] It should be noted that, during the sputtering process, by applying a negative bias to the target material and a positive bias to the substrate 100, argon ions will move toward the target material, while oxygen ions will move toward the substrate 100 and penetrate into the conductive material layer of the tantalum nitride material, thereby forming the insulating oxide layer 103 of the tantalum oxynitride material. The gas flow ratio of oxygen ions to argon ions is between 1:4 and 1:1, and a higher gas ratio of oxygen ions tends to produce a thicker insulating oxide layer 103. The sputtering power is between 100 watts and 300 watts, and a higher power can accelerate the oxidation process, thereby forming the insulating oxide layer 103 of the desired thickness in a shorter time. The sputtering time is between 5 minutes and 30 minutes, and a longer sputtering time will result in the formation of a thicker insulating oxide layer 103, while a shorter sputtering time will form a thinner insulating oxide layer 103.

[0050] In this embodiment, the thickness of the insulating oxide layer 103 is 10 nanometers to 50 nanometers. The thickness of the insulating oxide layer 103 is consistent with the thickness of the second region II of the conductive material layer. The thickness setting of the insulating oxide layer 103 can be flexibly adjusted according to the needs of the actual device, and the thickness of the insulating oxide layer 103 formed can be controlled by adjusting parameters such as sputtering power and sputtering time during the oxidation process.

[0051] Please refer to Figure 5 , a second electrode layer 104 is formed on the insulating oxide layer 103 .

[0052] In this embodiment, the second electrode layer 104 is formed by a physical vapor deposition process.

[0053] In other embodiments, the second electrode layer may be formed by a magnetron sputtering process.

[0054] In this embodiment, the second electrode layer 104 is made of tungsten.

[0055] In other embodiments, the material of the second electrode layer may also be titanium nitride or an inert electrode material; the inert electrode material includes: platinum, gold, palladium, iridium, rhodium, silver or lead.

[0056] Correspondingly, the embodiment of the present invention further provides a resistive memory structure, please continue to refer to Figure 5 , comprising: a substrate 100; a first electrode layer 101 located on the substrate 100; an insulating oxide layer 103 located on the first electrode layer 101, wherein the first electrode layer 101 and the insulating oxide layer 103 are an integral structure; and a second electrode layer 104 formed on the insulating oxide layer 103.

[0057] The first electrode layer 101 and the insulating oxide layer 103 are an integral structure, and no air layer is formed at the contact interface between the two, thereby improving the stability and performance of the resistive random access memory structure.

[0058] In this embodiment, the thickness of the insulating oxide layer 103 is 10 nanometers to 50 nanometers.

[0059] In this embodiment, the present invention further includes: a passivation layer 102 located on the first electrode layer 101 , and the passivation layer 102 surrounds the insulating oxide layer 103 .

[0060] In this embodiment, the material of the passivation layer 102 is silicon oxide.

[0061] In other embodiments, the material of the passivation layer may also be silicon nitride.

[0062] In this embodiment, the material of the first electrode layer 101 is tantalum nitride.

[0063] In this embodiment, the material of the insulating oxide layer 103 is tantalum oxynitride.

[0064] In this embodiment, the second electrode layer 104 is made of tungsten.

[0065] In other embodiments, the material of the second electrode layer may also be titanium nitride or an inert electrode material; the inert electrode material includes: platinum, gold, palladium, iridium, rhodium, silver or lead.

[0066] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A resistive memory structure, characterized in that: include: substrate; a first electrode layer located on the substrate; an insulating oxide layer located on the first electrode layer, wherein the first electrode layer and the insulating oxide layer are an integral structure; A second electrode layer is formed on the insulating oxide layer.

2. The resistive memory structure according to claim 1, wherein: The thickness of the insulating oxide layer is 10 nanometers to 50 nanometers.

3. The resistive memory structure according to claim 1, wherein: Also includes: A passivation layer is located on the first electrode layer, and the passivation layer surrounds the insulating oxide layer.

4. The resistive memory structure according to claim 3, wherein: The material of the passivation layer includes silicon nitride or silicon oxide.

5. The resistive memory structure according to claim 1, wherein: The material of the first electrode layer includes: tantalum nitride.

6. The resistive memory structure according to claim 1, wherein: The material of the insulating oxide layer includes: tantalum oxynitride.

7. The resistive memory structure according to claim 1, wherein: The material of the second electrode layer includes: titanium nitride, tungsten or an inert electrode material; the inert electrode material includes: platinum, gold, palladium, iridium, rhodium, silver or lead.

8. A method for forming a resistive memory structure, characterized in that: include: providing a substrate; forming a conductive material layer on the substrate, wherein the conductive material layer comprises a first region and a second region located on the first region, wherein the first region is used as a first electrode layer; performing oxidation treatment on the second region to form an insulating oxide layer; A second electrode layer is formed on the insulating oxide layer.

9. The method for forming a resistive memory structure according to claim 8, wherein: The process parameters of the oxidation treatment include: sputtering ions include oxygen ions and argon ions; the gas flow ratio of oxygen ions to argon ions is 1:4 to 1:1; the sputtering power is 100 watts to 300 watts; the sputtering time is 5 minutes to 30 minutes; the target material applied voltage is -400 volts to -600 volts; the substrate applied voltage is 200 volts to 400 volts.

10. The method for forming a resistive memory structure according to claim 8, wherein: The thickness of the insulating oxide layer is 10 nanometers to 50 nanometers.

11. The method for forming a resistive memory structure according to claim 8, wherein: After forming the conductive material layer and before performing the oxidation treatment, the method further includes: etching the conductive material layer to form an isolation opening in the conductive material layer; and forming a passivation layer in the isolation opening.

12. The method for forming a resistive memory structure according to claim 11, wherein: The material of the passivation layer includes silicon nitride or silicon oxide.

13. The method for forming a resistive memory structure according to claim 8, wherein: The material of the conductive material layer includes: tantalum nitride.

14. The method for forming a resistive memory structure according to claim 8, wherein: The material of the insulating oxide layer includes: tantalum oxynitride.

15. The method for forming a resistive memory structure according to claim 8, wherein: The process for forming the conductive material layer includes: a chemical vapor deposition process.

16. The method for forming a resistive memory structure according to claim 8, wherein: The formation process of the second electrode layer includes: a physical vapor deposition process or a magnetron sputtering process.

17. The method for forming a resistive memory structure according to claim 8, wherein: The material of the second electrode layer includes: titanium nitride, tungsten or an inert electrode material; the inert electrode material includes: platinum, gold, palladium, iridium, rhodium, silver or lead.

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