Kerr inversion traveling wave parameter amplifier and preparation method thereof

Abstract

The invention provides a Kerr inversion traveling wave parameter amplifier and a preparation method thereof. The method comprises the following steps: depositing a first layer of superconducting material film on a substrate; exposing and etching the first layer of superconducting material film by using laser direct writing, wherein a superconducting material film serving as a bonding welding pad and forming lower polar plates of capacitors in all repetitive units in the Kerr inversion traveling wave parameter amplifier is reserved; preparing Josephson junctions of aluminum in the repetitive units to obtain a conducted superconducting circuit; growing an aluminum oxide dielectric layer; and growing a top conductor layer and etching a pattern.

Description

Technical Field

[0001] This invention relates to the field of superconducting quantum mechanics, and more particularly to a Kerr-inverted traveling-wave parametric amplifier and its fabrication method. Background Technology

[0002] The statements in this section are merely to provide background information in relation to the present invention to aid in understanding the invention, and such background information does not necessarily constitute prior art.

[0003] Currently, Josephson traveling-wave parametric amplifiers (TWAPAs) have become a research hotspot worldwide due to their near-quantum-limit noise, high gain, large bandwidth, and high saturation power. The main challenges in designing and fabricating a TWAPA include: achieving phase matching between the pump microwave, signal microwave, and idle microwave; achieving impedance matching between the TWAPA and the external environment; and meeting stringent fabrication requirements, resulting in significant fabrication difficulties.

[0004] Of these challenges, achieving phase matching between the pump microwave, signal microwave, and idle microwave is the most critical. If the phase matching problem cannot be solved, the gain of the Josephson traveling-wave parametric amplifier will be significantly limited.

[0005] Current methods for achieving phase matching include periodic insertion of resonant cavities (Kevin O'Brien et al, Phys. Rev. Lett. 113, 157001), periodic load modes (Byeong Ho Eom et al, Nature Phys 8, 623–627 (2012)), and modulation of periodic Josephson junctions (Luca Planat et al, Phys. Rev. X 10, 021021).

[0006] However, these methods have the following drawbacks: the gain curve at the signal frequency exhibits an extremely steep dip due to gaps in the dispersion relation, resulting in large fluctuations in the gain distribution; and the amplification bandwidth is fixed. Therefore, it is necessary to manufacture a traveling-wave parametric amplifier with high gain, relatively small gain curve fluctuations, large bandwidth, and dynamically adjustable frequency band tuning range. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides a method for fabricating a Kerr-inverted traveling-wave parametric amplifier, comprising:

[0008] Step 1: Deposit the first layer of superconducting material on the substrate;

[0009] Step 2: Use laser direct writing exposure and etching to expose and etch the first layer of superconducting material film, in which the superconducting material film that serves as a bonding pad and the lower plate of the capacitor in all repeating units of the Kerr inverted traveling wave parametric amplifier is retained;

[0010] Step 3: Prepare the aluminum Josephson junction in the repeating unit to obtain a conductive superconducting circuit;

[0011] Step 4: Growing the alumina dielectric layer; and

[0012] Step 5: Grow the top conductor layer and etch the pattern.

[0013] In one embodiment, step 3 further includes designing the layout positions of the first Josephson knot, the second Josephson knot, the third Josephson knot, and the Josephson small knot in the repeating unit, such that the first Josephson knot, the second Josephson knot, and the third Josephson knot are connected in series, and the three series-connected Josephson knots and the Josephson small knot are connected in parallel; wherein the first Josephson knot, the third Josephson knot, and the Josephson small knot are prepared as a cross knot structure, and the second Josephson knot is prepared as a parallel knot structure.

[0014] In one embodiment, the second Josephson knot is located between the first Josephson knot and the third Josephson knot, and the center of the third Josephson knot is not on the line connecting the center of the first Josephson knot and the center of the second Josephson knot.

[0015] In one embodiment, the top conductor is gold, and step 5 further includes the following steps:

[0016] A gold thin film was prepared on the surface of the sample obtained in step 4 by electron beam evaporation;

[0017] Spin-coating photoresist, followed by hot plate baking;

[0018] After exposure, the sample is developed and fixed. After fixing, the substrate is purged with nitrogen gas.

[0019] Etching is performed on the developed and fixed sample; and

[0020] Remove glue.

[0021] In one embodiment, a gold etching solution is prepared using potassium iodide, elemental iodine, and water to etch the developed and fixed sample.

[0022] In one embodiment, a gold etching solution is prepared using 20 grams of potassium iodide, 4 grams of elemental iodine, and 200 milliliters of water.

[0023] In one embodiment, step 2 further includes:

[0024] Photoresist was spin-coated onto the surface of the sample obtained in step 1, and then baked on a hot plate.

[0025] The sample with spin-coated photoresist is laser-written to expose the designed pattern;

[0026] After exposure, the sample is developed and fixed. After fixing, the substrate is purged with nitrogen gas.

[0027] Etching is performed on the developed and fixed sample; and

[0028] Remove glue.

[0029] In one embodiment, step 3 further includes:

[0030] Gold growth markers are used in high-voltage electron beam lithography systems to determine the exposure location;

[0031] MAA photoresist and PMMA photoresist are spin-coated sequentially. Depending on the electron beam exposure equipment, conductive adhesive is applied or an aluminum film is grown by electron beam deposition.

[0032] Electron beam exposure of Josephson junction patterns;

[0033] Develop and fix the substrate; after fixing, the substrate is purged with nitrogen gas.

[0034] Electron beam deposition for Josephson junction fabrication; and

[0035] Remove adhesive and peel off.

[0036] In one embodiment, the first layer of superconducting material is aluminum or niobium.

[0037] The present invention also provides a Kerr inverted traveling wave parametric amplifier prepared using the above-described method for preparing a Kerr inverted traveling wave parametric amplifier.

[0038] The Kerr-inverted traveling-wave parametric amplifier of this invention features high gain, relatively small ripple, large bandwidth, and a dynamically adjustable gain curve with a frequency band tuning range, making it easier to design and fabricate. The method for fabricating the Kerr-inverted traveling-wave parametric amplifier of this invention effectively combines laser direct-write etching and electron beam exposure techniques, reducing the overall electron beam exposure area and significantly shortening the exposure time. This avoids erroneous exposure caused by excessive electron accumulation due to an excessively large exposure area in the electron beam resist, and also avoids the problem of short-circuiting the Josephson junction. Attached Figure Description

[0039] Figure 1 A circuit diagram of a Kerr inverted traveling wave parametric amplifier is shown.

[0040] Figure 2A A schematic diagram is shown after the first aluminum film has been deposited on the substrate.

[0041] Figure 2B A schematic diagram is shown after etching the first layer of aluminum film.

[0042] Figure 2C A schematic diagram of the preparation of an aluminum Josephson junction is shown.

[0043] Figure 2D A schematic diagram of atomic layer deposition for preparing dielectric layers is shown.

[0044] Figure 3 An electron microscope image of the chip after the Josephson junction chain structure of aluminum was fabricated is shown.

[0045] Figure 4 The measured gain of the Kerr inverted traveling wave parametric amplifier is shown.

[0046] Figure 5 The saturation power of the Kerr inverted traveling wave parametric amplifier at different signal frequencies is shown.

[0047] Figure 6 A schematic diagram of the structure of a Kerr inverted traveling wave parametric amplifier is shown.

[0048] Figure 7 This shows a complete diagram of the Kerr inverted traveling wave parametric amplifier. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the embodiments given in this invention are for illustrative purposes only and do not limit the scope of protection of this invention.

[0050] Figure 1 A circuit diagram of a Kerr inverted traveling-wave parametric amplifier is shown. Figure 1 As shown, the Kerr-inverting traveling-wave parametric amplifier is a chain structure comprising multiple repetitive units 101. Each repetitive unit 101 includes three Josephson large junctions 101a, 101b, and 101c and one Josephson small junction 101d, wherein the three series-connected Josephson large junctions and the one Josephson small junction are connected in parallel. Capacitor C 101 One end is connected to the node between Josephson large junction 101b and Josephson small junction 101d, and the other end is bonded to ground, communicating with the outer conductor of the SMA adapter. The node between Josephson large junction 101c and Josephson small junction 101d is coupled to the center conductor of the SMA adapter. Multiple repeating units such as Figure 1 The series connections shown form a chain structure. Repeating units with Josephson small knots above and Josephson large knots below are spaced apart from repeating units with Josephson large knots above and Josephson small knots below. Figure 1The Kerr-inverted traveling-wave parametric amplifier shown is based on the principle of Kerr inversion to cancel overall phase mismatch. It uses a superconducting non-linear asymmetric element (SNAIL) and a capacitor as the basic repeating unit of the transmission chain. The simulation results show that this principle can guarantee the device's high gain, relatively small fluctuation, large bandwidth, and dynamically adjustable gain curve of the frequency band tuning range.

[0051] When fabricating this Kerr-inverted traveling-wave parametric amplifier using conventional methods, some Josephson junctions become short-circuited. Through theoretical analysis and experimental verification, the inventors discovered that the conventional fabrication method uses electron beam exposure and development to prepare almost all parts of the chain structure. Because this method exposes a large area, it easily leads to excessive electron accumulation on the electron beam resist, causing incorrect exposure of the resist. This results in some Josephson junctions becoming short-circuited during subsequent development and coating. This invention proposes a new method for fabricating a Kerr-inverted traveling-wave parametric amplifier. This method includes: depositing a first superconducting material film on a substrate; using laser direct writing exposure and etching of the first superconducting material film, retaining the superconducting material film that acts as bonding pads and the lower electrode of the capacitors in all repeating units of the Kerr-inverted traveling-wave parametric amplifier; fabricating aluminum Josephson junctions in the repeating units to obtain a conductive superconducting circuit; growing an alumina dielectric layer; and growing a top conductor layer and etching a pattern.

[0052] Figures 2A-2D A schematic diagram illustrating the fabrication process of a method for fabricating a Kerr-inverted traveling-wave parametric amplifier according to an embodiment of the present invention is shown below. Figures 2A-2D The present invention specifically describes a method for preparing a Kerr-inverted traveling-wave parametric amplifier, the method comprising:

[0053] Step 101: Deposit the first layer of superconducting material film on the substrate.

[0054] In one embodiment, the first superconducting material is aluminum or niobium. For clarity, aluminum will be used as an example below.

[0055] Figure 2A This diagram shows the result after the first aluminum film has been deposited on the substrate. The substrate 201 is sapphire, and the first superconducting material film 202 is an aluminum film.

[0056] In one embodiment, a multi-chamber ultra-high vacuum electron beam deposition system is used to deposit an aluminum film with a thickness of 100 nm on a 500 μm polished sapphire wafer.

[0057] In one embodiment, the thickness of the first aluminum film is 50-200 nm, preferably 80-150 nm, and most preferably 100 nm. In one embodiment, the method for depositing and growing the first aluminum film is electron beam evaporation. In one embodiment, the substrate is sapphire, high-resistivity silicon, or amorphous silicon; and preferably sapphire.

[0058] Step 102: Use laser direct writing exposure to etch the first layer of superconducting material film, in which the superconducting material film that serves as a bonding pad and the lower plate of the capacitor C in all the repeating units of the Kerr inverted traveling wave parametric amplifier is retained.

[0059] Figure 2B A schematic diagram is shown after etching the first aluminum film. As shown in Figure 2, 202a and 202d are aluminum layers between the repeating unit and the chip edge, used as bonding pads to bond to the center conductor of the SMA adapter. 202b and 202c are aluminum layers forming the lower electrode of the capacitor in the repeating unit.

[0060] Figure 3 An electron microscope image of a chip after the fabrication of an aluminum Josephson junction chain structure is shown. It more clearly shows the retained superconducting material. Figure 3 As shown, the aluminum 304 (i.e., 202a) between the repeating unit 301 and the chip edge is not etched, the aluminum 305 constituting the lower electrode of the capacitor in the repeating unit 301 is not etched, and the aluminum 306 constituting the lower electrode of the capacitor in the repeating unit 302 is not etched.

[0061] In traditional processes, the entire first aluminum layer, except for bonding pads 202a and 202d, is etched. Subsequent electron beam exposure (EBET) deposition and growth then form all the transport chain structures. This invention rationally designs the exposure pattern, effectively combining laser direct-write etching and EBET techniques. This allows the first aluminum layer, excluding the bonding pads, to be partially etched during the laser direct-write etching process, leaving a portion intact. This eliminates the need for subsequent EBET deposition and growth of this portion of the aluminum layer, effectively reducing the EBET exposure area and preventing errors caused by excessive electron accumulation due to an overly large exposure area, which could lead to short circuits in the Josephson junction. It also significantly reduces exposure time and improves fabrication efficiency. After creating a suitable exposure pattern, thousands of highly uniform and well-morphologically sound aluminum-alumina-alumina Josephson junctions were successfully fabricated.

[0062] In one embodiment, step 102 further includes the following steps:

[0063] Step 102a: Spin-coat photoresist onto the surface of the sample obtained in step 101 and bake it on a hot plate.

[0064] In one embodiment, photoresist SPR 955 is spin-coated onto the first aluminum film 202. A disposable dropper is used to pick up the photoresist and drop it onto the center of the chip to cover the entire chip. Then, the chip is first rotated at an angular velocity of 500 revolutions per second for 5 seconds, and then rotated at an angular velocity of 4000 revolutions per second for 40 seconds. After spin coating is completed, the sample is placed on a hot plate and baked at 90°C for 90 seconds. After baking is completed, the sample is removed from the hot plate and cooled at room temperature for 3 minutes.

[0065] In one embodiment, the thickness of the photoresist is 0.5-3 micrometers, preferably 0.6 micrometers.

[0066] In one embodiment, the photoresist is selected from one of the following: SPR955 photoresist, S1813 photoresist, preferably SPR955 photoresist.

[0067] Step 102b: Perform laser direct writing on the sample with spin-coated photoresist to expose the designed pattern.

[0068] In one embodiment, the sample is exposed using a DWL66+ laser direct writing system according to a pre-drawn pattern (when drawing the development pattern, care is taken to remove a portion that would otherwise require electron beam exposure for development and coating, so that no development or etching is performed). The exposure parameters are: intensity 90%, power 60mW, and filter 25%. After exposure, the sample is baked at 120°C for 90 seconds using a hot plate. After baking, the sample is removed from the hot plate and allowed to cool at room temperature for 3 minutes.

[0069] Step 102c: Develop and fix the exposed sample, and after fixing, blow nitrogen gas through the substrate.

[0070] In one embodiment, the photoresist was developed using ZX-238 positive photoresist developer (tetramethylammonium hydroxide 2.38%) for 60 seconds. Afterwards, the sample was fixed by immersion in deionized water for 30 seconds and then dried using a nitrogen gun.

[0071] Step 102d: Etch the developed and fixed sample.

[0072] In one embodiment, after confirming that the sample development is normal under a microscope, the aluminum pattern is etched using ZX-238 positive photoresist developer heated to 45°C in a water bath for 66 seconds.

[0073] In one embodiment, the etching method is selected from one or more of the following: chemical etching, reactive ion etching; preferably chemical etching.

[0074] Step 102e: Remove adhesive.

[0075] In one embodiment, the sample is finally removed and placed in NMP stripping solution, heated and soaked at 80°C for 4 hours to complete the stripping process. To remove residual adhesive, the sample is removed from the NMP stripping solution again, placed in acetone solution and sonicated at low power for 3 minutes, then soaked for 4 minutes, and finally soaked in isopropanol solution for 7 minutes. Finally, the sample is removed, rinsed again with a wash bottle containing isopropanol, and the sample surface is dried with a nitrogen gun.

[0076] In one embodiment, the adhesive stripping solution is selected from one or more of the following: NMP solution, PG solution, preferably NMP solution.

[0077] Step 103: Prepare an aluminum Josephson junction in a repeating structure to obtain a conductive superconducting circuit.

[0078] Figure 2C A schematic diagram of the preparation of an aluminum Josephson junction is shown.

[0079] Figure 3 An electron microscope image of the chip after the fabrication of an aluminum Josephson junction chain structure is shown. Figure 3 As shown, for clarity, the positions of the first Josephson junction 301a, the second Josephson junction 301b, and the third Josephson junction 301c are indicated by black boxes. In the SNAIL structure of this invention, only the second Josephson junction 301b is a parallel junction structure, meaning the current flow directions in the upper and lower conductors of the Josephson junction are parallel to each other. The first Josephson junction 301a, the third Josephson junction 301c, and the Josephson junction 301d are all cross junction structures, meaning the current flow directions in the upper and lower layers of the Josephson junction are not parallel but intersect. This intersection angle can be 90 degrees or other degrees. This cross junction structure allows for precise control of the junction area because, during tilted evaporation, an angle greater than a certain value is sufficient to produce a Josephson junction with the required dimensions, and it is not sensitive to angle changes. It is only necessary to ensure that the size of the parallel junction is equal to the size of the cross junction, making design and fabrication easier.

[0080] The aluminum Josephson junction in the repeating structure can be fabricated using existing methods. In one embodiment, step 103 further includes the following steps:

[0081] Step 103a: Gold markers are grown for use in a high-voltage electron beam exposure system to determine the exposure location.

[0082] In one embodiment, based on step 102, a small amount of SPR 955 photoresist is taken and applied only to the superconducting circuit etched on the chip, excluding the etched markings around the wafer. The sample is then baked again at 120°C for 90 seconds. After baking, the sample is removed from the hot plate and cooled to room temperature for 3 minutes. Using an electron beam evaporation system, 5nm titanium and 60nm gold are deposited sequentially at a speed of 0.05nm / s. Depositing 5nm titanium helps the gold layer better adhere to the aluminum film. The sample is placed in NMP stripper and heated and immersed at 80°C for 4 hours. The gold layer is then blown off in a beaker using a dropper to complete the stripping process. The sample is removed from the NMP stripper, placed in acetone solution, sonicated at low power for 3 minutes, then immersed for 4 minutes, and finally immersed in isopropanol solution for 7 minutes. The sample is then rinsed again with a wash bottle containing isopropanol, and the sample surface is dried with a nitrogen gun. Successful gold markings are observed under an optical microscope.

[0083] In one embodiment, the thickness of the gold marker is 40-200 nm, preferably 60 nm, and a 5 nm titanium layer can be pre-plated before gold plating to increase the adhesion of the gold marker.

[0084] Step 103b: Spin-coat MAA photoresist and PMMA photoresist in sequence, and select conductive adhesive or electron beam deposition to grow aluminum film depending on the electron beam exposure equipment.

[0085] In one embodiment, electron beam photoresist MAA and electron beam photoresist PMMA are spin-coated onto the sample sequentially. For both, a disposable dropper is used to apply the photoresist to the center of the wafer, ensuring complete coverage. The spin-coating parameters for the electron beam photoresist MAA are: first, spin at an angular velocity of 500 revolutions per second for 5 seconds, then at an angular velocity of 1600 revolutions per second for 50 seconds. After spin-coating, the sample is placed on a hot plate and baked at 160°C for 10 minutes. After baking, it is removed from the hot plate and cooled to room temperature for 3 minutes. After cooling, the spin-coating parameters for the electron beam photoresist PMMA are: first, spin at an angular velocity of 500 revolutions per second for 5 seconds, then at an angular velocity of 2000 revolutions per second for 60 seconds. After spin-coating, the sample is placed on a hot plate and baked at 160°C for 10 minutes. After baking, it is removed from the hot plate and cooled to room temperature for 3 minutes. After spin coating the electron beam resist, in order to facilitate the high voltage electron beam exposure system to measure the sample and conduct electrons away, an aluminum film with a thickness of 10nm needs to be deposited on the surface of the electron beam resist using an electron beam evaporation system.

[0086] In one embodiment, the thickness of the PMMA photoresist is 100-400 nm, preferably 150-250 nm, and most preferably 200 nm; the thickness of the MAA photoresist is 80-400 nm, preferably 150-250 nm, and most preferably 200 nm. The conductive adhesive is preferably SX AR-PC with a thickness of 40-60 nm, and most preferably 50 nm. The thickness of the aluminum film is preferably 10 nm.

[0087] Step 103c: Electron beam exposure of Josephson junction pattern.

[0088] In one embodiment, a high-voltage electron beam exposure system is used to expose the sample.

[0089] Step 103d: Development and fixing. After fixing, the substrate is purged with nitrogen gas.

[0090] In one embodiment, after exposure, a 10 nm aluminum film was etched at room temperature using ZX-238 positive photoresist developer for 60 s, followed by rinsing with deionized water for 30 s, and then drying the sample surface with a nitrogen gun. Subsequently, the sample was developed using a mixed developing solution of methyl isobutyl ketone (MIBK) and isopropanol (IPA) at a volume ratio of 1:3. The sample was immersed in the developing solution for 35 s, rinsed with isopropanol for 20 s, and then dried with a nitrogen gun.

[0091] Step 103e: Electron beam deposition to prepare Josephson junctions.

[0092] In one embodiment, a multi-chamber ultra-high vacuum electron beam deposition system is used to first bombard the sample with ions to ensure that the subsequently grown aluminum film can achieve superconducting contact with the existing aluminum film. Then, an aluminum film with a thickness of 65 nm is deposited at an angle of -64°. Next, a static oxidation procedure is used to make the pressure in the oxidation chamber reach 1.1 Torr with a pure oxygen flow of 2 sccm and maintain it for 1 s. Then, a vacuum is drawn. Immediately afterwards, an aluminum film with a thickness of 100 nm is vertically deposited.

[0093] In one embodiment, electron beam deposition is either single-angle oblique-vertical evaporation or double-angle oblique evaporation, preferably single-angle oblique-vertical evaporation.

[0094] Step 103f: Remove adhesive and peel off.

[0095] In one embodiment, the sample is finally removed and placed in NMP stripping solution, heated and soaked at 80°C for 4 hours, and the aluminum film is blown off in a beaker using a dropper to complete the peeling process. The sample is then removed from the NMP stripping solution, placed in acetone solution, sonicated at low power for 3 minutes, soaked for 4 minutes, and finally soaked in isopropanol solution for 7 minutes. Afterward, the sample is rinsed again with a wash bottle containing isopropanol and the sample surface is dried with a nitrogen gun.

[0096] In one embodiment, the adhesive stripping solution is selected from one or more of the following: NMP solution, PG solution, preferably NMP solution.

[0097] In one embodiment, step 103 further includes designing the layout positions of the first Josephson large junction 301a, the second Josephson large junction 301b, the third Josephson large junction 301c, and the Josephson small junction 301d in the repeating unit, such that the first Josephson large junction 301a, the second Josephson large junction 301b, and the third Josephson small junction 301c are connected in series, and the three series-connected Josephson large junctions and the Josephson small junction 301d are connected in parallel. In one embodiment, the first Josephson large junction 301a, the third Josephson large junction 301c, and the Josephson small junction 301d in the repeating unit are fabricated as a cross-junction structure, and the second Josephson large junction 301b in the repeating unit is fabricated as a parallel junction structure.

[0098] In one embodiment, the second Josephson knot 301b is located between the first Josephson knot 301a and the third Josephson knot 301c, and the center of the third Josephson knot 301c is not on the line connecting the center of the first Josephson knot 301a and the center of the second Josephson knot 301b, so as to facilitate the implementation of cross knot and parallel knot structures.

[0099] Step 104: Grow the alumina dielectric layer.

[0100] Figure 2D A schematic diagram of atomic layer deposition for preparing dielectric layers is shown.

[0101] In one embodiment, an atomic layer deposition (ALD) system is used to grow a 30 nm alumina intermediate layer at 110 °C, with deionized water as the reactant and trimethylaluminum (TMA) as the precursor. During ALD, one alumina growth cycle consists of a 0.015 s TMA pulse, a 20 s nitrogen purging, followed by a 0.015 s deionized water pulse and a 20 s nitrogen purging, for a total of 300 cycles.

[0102] In one embodiment, the dielectric layer is an alumina thin film with a thickness of 15-80 nm, preferably 25-50 nm. The alumina thin film is deposited and grown by atomic layer deposition.

[0103] Step 105: Grow the top conductor layer and etch the pattern.

[0104] In one embodiment, the top conductor is gold or copper.

[0105] In one embodiment, step 105 includes the following steps:

[0106] Step 105a: Prepare a gold film on the surface of the sample obtained in step 104.

[0107] In one embodiment, the thickness of the gold film is 60-200 nm, preferably 80-150 nm; the method for depositing and growing the gold film is electron beam evaporation.

[0108] In one embodiment, an electron beam evaporation system is used to deposit a 100 nm gold film at a rate of 0.05 nm / s.

[0109] Step 105b: Spin-coat photoresist and bake on a hot plate.

[0110] In one embodiment, SPR 955 photoresist is spin-coated onto a gold layer. A disposable dropper is used to apply the photoresist to the center of the wafer, covering the entire wafer. The wafer is then rotated at an angular velocity of 500 revolutions per second for 5 seconds, followed by a rotation at an angular velocity of 4000 revolutions per second for 40 seconds. After spin-coating, the sample is placed on a hot plate and baked at 90°C for 90 seconds. After baking, the sample is removed from the hot plate and allowed to cool at room temperature for 3 minutes. Subsequently, the sample is exposed using a DWL66+ laser direct writing system with the following exposure parameters: focus -5, intensity 80%, power 60mW, and filter 25%. After exposure, the sample is baked again at 120°C for 90 seconds. After baking, the sample is removed from the hot plate and allowed to cool at room temperature for 3 minutes.

[0111] In one embodiment, the thickness of the photoresist on the gold film is 0.5-3 micrometers, preferably 0.6 micrometers; the photoresist is selected from one or more of the following: SPR955 photoresist, S1813 photoresist; preferably SPR955 photoresist.

[0112] Step 105c: Develop and fix the exposed sample, and after fixing, blow nitrogen gas through the substrate.

[0113] In one embodiment, the photoresist was developed using ZX-238 positive photoresist developer (tetramethylammonium hydroxide 2.38%) for 60 seconds. Afterwards, the sample was fixed by immersion in deionized water for 30 seconds and then dried using a nitrogen gun.

[0114] Step 105d: Etch the developed and fixed sample.

[0115] In one embodiment, the etching method is chemical etching.

[0116] In one embodiment, after confirming normal sample development under a microscope, gold is etched using a KI / I2 solution for 130 seconds. Afterward, the sample is immersed in deionized water for 30 seconds and dried with a nitrogen gun. The sample is then placed in NMP stripper and heated at 80°C for 4 hours. After removing the sample from the NMP stripper, it is immersed in isopropanol solution for 15 minutes. Finally, the sample is rinsed again with a wash bottle containing isopropanol and dried with a nitrogen gun.

[0117] In one embodiment, a gold etching solution is prepared using potassium iodide, elemental iodine, and water. This solution not only rapidly etches gold chemically but also avoids reacting with the intermediate alumina dielectric layer. Simultaneously, the dense alumina dielectric layer protects the first aluminum film of the chip from being etched by the gold etching solution. In one embodiment, the gold etching solution is prepared using a ratio of 20 grams of potassium iodide, 4 grams of elemental iodine, and 200 milliliters of water.

[0118] In this invention, the gold layer is prepared by first performing electron beam deposition and then developing and etching. This is because when using a conventional lift-off method, the alkaline developer of the photoresist will etch the aluminum oxide dielectric layer, which reduces the thickness of the dielectric layer and causes a change in capacitance.

[0119] Step 105e: Remove adhesive.

[0120] In one embodiment, the sample is finally removed and placed in NMP stripping solution, heated and soaked at 80°C for 4 hours to complete the stripping process. To remove residual adhesive, the sample is removed from the NMP stripping solution again, placed in acetone solution and sonicated at low power for 3 minutes, then soaked for 4 minutes, and finally soaked in isopropanol solution for 7 minutes. Finally, the sample is removed, rinsed again with a wash bottle containing isopropanol, and the sample surface is dried with a nitrogen gun.

[0121] In one embodiment, the adhesive stripping solution is selected from one or more of the following: NMP solution, PG solution, preferably NMP solution.

[0122] Step 106: Slice.

[0123] In one embodiment, SPR 220 photoresist is spin-coated onto the sample to protect the sample surface during slicing. Using a disposable dropper, the photoresist is applied to the center of the chip, covering the entire chip. The chip is then rotated at an angular velocity of 500 revolutions per second for 5 seconds, followed by a rotation at an angular velocity of 2000 revolutions per second for 60 seconds. After spin-coating, the sample is placed on a hot plate at 115°C and baked for 2 minutes. After baking, it is removed from the hot plate and cooled to room temperature for 3 minutes. After cooling, the sample is sliced ​​using a microtome. The sliced ​​sample is then immersed in NMP stripper at 80°C for 4 hours. After removing the sample from the NMP stripper, it is immersed in isopropanol solution for 15 minutes. Finally, the sample is rinsed again with a wash bottle containing isopropanol and dried with a nitrogen gun to obtain the Kerr inverted traveling-wave parametric amplifier chip.

[0124] Step 107: Ozone and Bonding.

[0125] In one embodiment, a microwave plasma de-adhesion program is run for 100 minutes to minimize residual adhesive on the surface of the Kerr inverted traveling-wave parametric amplifier chip. After the program finishes, the Kerr inverted traveling-wave parametric amplifier chip is bonded to the sample box of the Kerr inverted traveling-wave parametric amplifier. A magnetic flux coil with 400 turns of NbTi / Cu superconducting wire is wound and placed at the bottom of the sample box, and then uniformly placed in a designed magnetic shielding box to obtain a Kerr inverted traveling-wave parametric amplifier.

[0126] The gain and saturation power of the Kerr inverted traveling wave parametric amplifier prepared by the method described above were measured. Figure 4 The measurement results of the gain of the Kerr inverted traveling-wave parametric amplifier are shown. When the pump frequency is 7.1 GHz and the current on the flux bias line used to apply global flux to the Kerr inverted traveling-wave parametric amplifier chip is 0.2 mA, the amplifier has a gain of more than 10 dB in the 6.21-6.91 GHz and 7.3-8.33 GHz ranges, and the bandwidth of more than 10 dB is 1.73 GHz. Figure 5 The diagram shows the saturation power of a Kerr inverted traveling-wave parametric amplifier at a pump frequency of 8.3 GHz for different signal frequencies. The saturation power represents the 1 dB compression point of the gain. Figure 5 It can be seen that the saturation power is -96.75dBm when the signal frequency is 9.15GHz and -98.7dBm when the signal frequency is 7.7GHz.

[0127] The present invention also provides a Kerr inverted traveling wave parametric amplifier manufactured using the above method. Figure 6 A schematic diagram of a Kerr inverted traveling-wave parametric amplifier is shown. Figure 6 As shown, the Kerr-inverted traveling-wave parametric amplifier includes a substrate 601, a first aluminum film 602 disposed on the substrate 601, a dielectric layer 603 disposed on the first aluminum film 602, and a top gold film 604 deposited on the dielectric layer 603. The surface of the first aluminum film 602 is etched with superconducting circuitry, forming hundreds, thousands, or tens of thousands of aluminum-alumina-alumina Josephson junctions. The chip as a whole constitutes a periodically arranged long-chain structure. The basic repeating unit of the long-chain structure includes a superconducting nonlinear asymmetric inductor and a capacitor. The superconducting nonlinear asymmetric inductor consists of three identical Josephson junctions (using a parallel structure that is easier to design) and a smaller Josephson junction (a cross-junction structure that is easier to control as the junction area is less sensitive to the evaporation angle). The capacitor is composed of a lower electrode plate of the patterned aluminum film, an intermediate dielectric layer, and an upper electrode plate of the gold layer. The top gold film is etched with a pattern.

[0128] Figure 7 A full view of the Kerr inverted traveling wave parametric amplifier is shown. It shows the bonding pads 701 and 702.

[0129] The Kerr-inverted traveling-wave parametric amplifier of this invention features high gain, relatively small fluctuations, large bandwidth, and a dynamically adjustable gain curve with a frequency band tuning range, making it easier to design and fabricate. The method for fabricating the Kerr-inverted traveling-wave parametric amplifier of this invention effectively combines laser direct-write etching and electron beam exposure techniques. A portion of the area requiring electron beam exposure for coating growth in traditional quantum chip fabrication is subtracted from the initial laser direct-write etching pattern, thus avoiding etching of this portion and eliminating the need for further electron beam exposure coating growth. This effectively reduces the overall electron beam exposure area, significantly shortening exposure time and preventing erroneous exposure caused by excessive electron accumulation due to an excessively large exposure area, which could lead to short circuits in the fabricated Josephson junction. After drawing a suitable exposure pattern, thousands of highly uniform and well-morphologically sound aluminum-alumina-alumina Josephson junctions were successfully fabricated. In the method for fabricating a Kerr-inverted traveling-wave parametric amplifier of the present invention, the gold layer is prepared by first performing electron beam deposition followed by development and etching. This is because, using a conventional lift-off method, the alkaline developer of the photoresist will etch the alumina dielectric layer, reducing the thickness of the dielectric layer and causing a change in capacitance. However, by preparing a gold etching solution using 20 grams of potassium iodide, 4 grams of elemental iodine, and 200 ml of water, not only can the gold be chemically etched quickly, but it will also not react with the intermediate alumina dielectric layer. At the same time, the dense alumina dielectric layer can also protect the first aluminum film of the chip from being etched by the gold etching solution.

[0130] While the present invention has been described through preferred embodiments, it is not limited to the embodiments described herein, and various changes and modifications are made without departing from the scope of the invention.

Claims

1. A method for preparing a Kerr inversion traveling wave parametric amplifier, comprising: Step 1: depositing a first layer of superconducting material film on a substrate; Step 2: using laser direct writing to expose and etch the first layer of superconducting material film, wherein the superconducting material film serving as a bonding pad and constituting the lower plate of the capacitor in all repeating units of the Kerr inversion traveling wave parametric amplifier is retained; Step 3: Prepare the aluminum Josephson junction in the repeating unit to obtain a conducting superconducting circuit; Step 4: growing an aluminum oxide dielectric layer; and Step 5: Grow the top conductor layer and etch out the pattern.

2. The method for preparing a Kerr inversion traveling wave parametric amplifier according to claim 1, wherein: The step 3 also includes designing the layout positions of the first Josephson big knot, the second Josephson big knot, the third Josephson big knot and the Josephson small knot in the repeating unit, so that the first Josephson big knot, the second Josephson big knot and the third Josephson big knot are connected in series, and the three serially connected Josephson big knots and the Josephson small knot are connected in parallel; wherein the first Josephson big knot, the third Josephson big knot and the Josephson knot are prepared as a cross-junction structure, and the second Josephson big knot is prepared as a parallel junction structure.

3. The method for preparing a Kerr inversion traveling wave parametric amplifier according to claim 2, wherein: The second Josephson knot is located between the first Josephson knot and the third Josephson knot, and the center of the third Josephson knot is not on the connecting line between the center of the first Josephson knot and the center of the second Josephson knot.

4. The method for preparing a Kerr inversion traveling wave parametric amplifier according to claim 1, wherein: The top conductor is gold, and step 5 further comprises the following steps: Prepare a gold thin film on the surface of the sample obtained in step 4 by electron beam evaporation; Spin-coat photoresist and hot plate bake; Developing and fixing the sample after exposure, and after fixing, blowing nitrogen gas on the substrate; etching the developed and fixed sample; and Remove glue.

5. The method for preparing a Kerr inversion traveling wave parametric amplifier according to claim 4, wherein: A gold etching solution is prepared using potassium iodide, elemental iodine and water to etch the developed and fixed samples.

6. The method for preparing a Kerr inversion traveling wave parametric amplifier according to claim 5, wherein: A gold etching solution is prepared by mixing 20 grams of potassium iodide, 4 grams of elemental iodine and 200 milliliters of water.

7. The method for preparing a Kerr inversion traveling wave parametric amplifier according to claim 1, wherein: The step 2 also includes: Spin-coat photoresist on the surface of the sample obtained in step 1, and bake on a hot plate; Perform laser direct writing on the sample with spin-coated photoresist to expose the designed pattern; Developing and fixing the sample after exposure, and after fixing, blowing nitrogen gas on the substrate; etching the developed and fixed sample; and Remove glue.

8. The method for preparing a Kerr inversion traveling wave parametric amplifier according to claim 1, wherein: The step 3 also includes: The grown gold markers are used in high voltage electron beam exposure systems to determine the exposure position; Spin-coat MAA photoresist and PMMA photoresist in sequence, and choose to apply conductive glue or electron beam deposition to grow aluminum film according to different electron beam exposure equipment; Electron beam exposure of Josephson junction patterns; developing and fixing, and after fixing, showering the substrate with nitrogen; Josephson junctions fabricated by electron beam deposition; and Glue removal and stripping.

9. The method for preparing a Kerr inversion traveling wave parametric amplifier according to any one of claims 1 to 8, wherein: The first layer of superconducting material is aluminum or niobium.

10. A Kerr inversion traveling-wave parametric amplifier prepared by using the method for preparing a Kerr inversion traveling-wave parametric amplifier according to any one of claims 1 to 9.

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